Fault-considered spacecraft integrated chip interface circuit potential path analysis method, storage medium and equipment

Abstract

The invention discloses a fault-considered spacecraft integrated chip interface circuit potential path analysis method, a storage medium and equipment, and belongs to the technical field of integrated circuit design and fault analysis. The method aims at solving the problem that an analysis method for a path under a failure mechanism under different environmental stresses is lacked. The method comprises the following steps: constructing an interface circuit simulation model of an integrated device based on a common interface circuit and a potential path structure in a spacecraft electronic system, then supplementing degradation mechanisms in various task stress environments, and determining a fault mode table of the interface circuit of the integrated device; a circuit simulation method is adopted to carry out potential path analysis considering fault factors on an interface circuit under a typical task profile, a fault path response feature library of the interface circuit under the task profile is obtained, then a constraint clue table for interface circuit design is formed, an interface circuit failure associated fault tree model is constructed, and the interface circuit failure associated fault tree model is constructed. And calibrating a relation path between various potential paths and device degradation or local failure for failure positioning and path checking.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design and fault analysis technology, specifically relating to a method for analyzing potential pathways in spacecraft integrated chip interface circuits. Background Technology

[0002] The electronic systems onboard spacecraft undertake various complex functions, and integrated device interface circuits play a crucial role in this process. To ensure the reliability of these interface circuits in the extreme operating environment of spacecraft, potential path analysis has become a critical issue in the design and maintenance phases. Currently, existing potential path analyses mostly focus on the topology of board-level circuits and the failure analysis of discrete components, with less attention paid to potential path problems within integrated device interface circuits. Due to the complex structure of integrated device interface circuits and incomplete design documentation, signal transmission and component failures are difficult to identify, thus affecting fault diagnosis and system reliability. The high integration and low power consumption characteristics of integrated circuits have led to their widespread application in spacecraft. However, integrated device interface circuits are prone to degradation and failure under prolonged exposure to extreme environmental stresses such as space radiation and temperature changes, further leading to potential path problems. Currently, research on potential paths in integrated device interface circuits is insufficient both domestically and internationally, especially regarding failure mechanisms under different environmental stresses. The lack of effective degradation models and failure analysis methods makes it difficult to accurately identify and locate potential paths, affecting the robustness of integrated circuit design. Summary of the Invention

[0003] This invention aims to address the lack of analytical methods for failure mechanisms under different environmental stresses.

[0004] A method for analyzing potential pathways in spacecraft integrated chip interface circuits considering faults, comprising:

[0005] Based on common interface circuits and potential path structures in spacecraft electronic systems, an interface circuit simulation model of integrated devices is constructed. Based on the circuit simulation model, degradation mechanisms under various mission stress environments are supplemented to determine the fault mode table of interface circuits of integrated devices. Based on the fault mode table, circuit simulation methods are used to perform potential path analysis on interface circuits under typical mission profiles, considering fault factors, to obtain a fault path response feature library of interface circuits under mission profiles.

[0006] By combining the fault path response feature library of interface circuits under the mission profile, the triggering conditions and fault manifestations of potential paths are summarized to form a constraint clue table for interface circuit design. Based on the clue table, an interface circuit failure association fault tree model is constructed to identify the relationship paths between various potential paths and device degradation or local failure, which is used for failure location and path investigation in the process of integrated device design and verification.

[0007] Furthermore, the types of interface circuits include power and ground interface circuits, I / O interface circuits, level conversion circuits, and protection circuits.

[0008] Furthermore, based on the circuit simulation model, the process of supplementing the degradation mechanisms under various task stress environments and determining the fault mode table of the integrated device interface circuit includes:

[0009] Step S21: Based on various stress sources in the spacecraft operating environment, determine the stress types that the integrated device suffers in the mission environment. Use simulation software to perform thermal and vibration simulations on the integrated device, analyze the stress level of the interface circuit of the integrated device under a typical mission profile, and determine the specific location where the stress is applied.

[0010] Step S22: Based on the thermal and vibration simulation results in step S21, analyze the impact of different stress types on the interface circuit of the integrated device, and establish a fault mode table for the interface circuit of the integrated device.

[0011] Furthermore, the process of using circuit simulation to perform potential path analysis on interface circuits under typical mission profiles, considering fault factors, and obtaining a fault path response feature library for interface circuits under mission profiles includes:

[0012] Step S31: Based on the fault mode table, by modifying the parameters of the component model or changing the internal connection method of the component interface, the fault is injected into the constructed interface circuit simulation model to construct an interface circuit failure simulation model containing fault factors.

[0013] Step S32: Set the stress excitation signal for a typical task profile, apply electrical excitation, drive the interface circuit failure simulation model, and run the simulation under various working conditions.

[0014] Step S33: Monitor the voltage and current waveforms of key nodes in the interface circuit during the simulation process, and extract the typical potential path formation process and conditions;

[0015] Step S34: Based on the triggering conditions, stable state, and degree of impact on system function of potential paths, classify the potential paths identified in step S33 to form a fault path response feature library of interface circuits under the task profile.

[0016] Furthermore, the electrical excitation applied in step S32 includes ESD pulses, power-on surges, and level input interference.

[0017] Furthermore, step S33 extracts typical potential pathways including source-to-ground short circuit, I / O interference, pull-up failure, and protection diode breakdown.

[0018] Furthermore, by combining the fault path response feature library of the interface circuit under the mission profile, the process of summarizing the potential path activation conditions and fault manifestations, and forming a constraint thread table for interface circuit design includes:

[0019] Step S41: Based on the established fault path response feature library, extract the excitation conditions of various potential paths under different task profiles, and classify them into a set of excitation conditions with input level, power timing, pull-up / pull-down structure, and level clamping method as key factors.

[0020] Step S42: Combining the excitation conditions identified in step S41, summarize the typical fault manifestations of various potential paths and clarify the electrical abnormality characteristics that each type of path may cause.

[0021] Step S43: Based on the excitation conditions and fault manifestations summarized in step S42, establish a design constraint clue table for interface circuit design, form circuit structure review items corresponding to interface topology, level relationship, protection structure, and power connection method, and cover common potential path triggering paths to obtain a constraint clue table for interface circuit design.

[0022] Furthermore, the typical fault manifestations described in step S42 include source-to-ground short circuit, interface open circuit, signal reverse conduction, and protection diode breakdown.

[0023] A computer storage medium, characterized in that the storage medium stores at least one instruction, which is loaded and executed by a processor to implement the aforementioned method for potential path analysis of spacecraft integrated chip interface circuits considering faults.

[0024] A potential path analysis device for spacecraft integrated chip interface circuits considering faults, characterized in that the device includes a processor and a memory, the memory storing at least one instruction, the at least one instruction being loaded and executed by the processor to implement the aforementioned potential path analysis method for spacecraft integrated chip interface circuits considering faults.

[0025] The present invention has the following advantages:

[0026] This invention constructs a typical integrated device interface circuit model and, by combining fault modes and degradation mechanisms under multiphysics stress conditions, conducts potential path analysis, effectively identifying potential path faults that may be triggered in real-world mission environments. This method improves the accuracy of interface circuit fault identification and provides strong support for robust design and fault diagnosis of spacecraft electronic systems. Attached Figure Description

[0027] Figure 1 This is a flowchart of a method for analyzing potential pathways in spacecraft integrated chip interface circuits that consider faults.

[0028] Figure 2 This is a simulation diagram of the external circuit of the 54AC245 bus transceiver in the embodiment;

[0029] Figure 3 This is a simulation circuit diagram of the interface and peripheral circuit of the 54AC245 bus transceiver in the embodiment;

[0030] Figure 4 This is a waveform diagram showing the potential path simulation characteristics of the 54AC245 bus transceiver in the embodiment;

[0031] Figure 5 This is a fault tree showing potential pathway problems for the integrated devices in the embodiment. Detailed Implementation

[0032] To address the problems existing in the background technology, constructing a model library of integrated device interface circuits, studying typical potential path modes, and conducting quantitative analysis based on a simulation platform have become urgent technical issues to be solved. The following detailed explanation is provided in conjunction with specific implementation methods.

[0033] Specific implementation method one: Combining Figure 1 This implementation method is described below.

[0034] This embodiment is a method for analyzing potential pathways in spacecraft integrated chip interface circuits that consider faults, including the following steps:

[0035] Step S1: Based on common interface circuits and potential path structures in spacecraft electronic systems, construct simulation models of interface circuits for typical integrated devices. The specific steps are as follows:

[0036] Step S11: Based on the module composition and signal transmission relationship of the spacecraft electronic system, identify the category of integrated device interface circuit. In this embodiment, the categories of interface circuits include four major categories: power supply and grounding interface circuits, I / O interface circuits, level conversion circuits, and protection circuits.

[0037] Step S12: Based on the interface categories identified in step S11, construct simulation models for various interface circuits:

[0038] For power supply and grounding interface circuits, establish power supply simulation models and grounding simulation models;

[0039] A bidirectional diode protection circuit model is established for the I / O interface circuit;

[0040] For level conversion circuits, a TTL to CMOS level conversion model is constructed;

[0041] For the protection circuit, a circuit model including TVS and Zener diodes is designed.

[0042] Step S13: Based on the simulation model in step S12, perform Monte Carlo simulation to analyze the potential paths of various interface circuits under different excitation signals. In this embodiment, different types of excitation signals such as electrostatic discharge (ESD) and voltage surges are used to analyze the low-impedance path, pull-up / pull-down path, and voltage spike path of the port.

[0043] Step S2: Based on the circuit simulation model established in Step S1, supplement the common degradation mechanisms under various task stress environments, and analyze and determine the fault mode table of the interface circuit for integrated devices. The specific steps are as follows:

[0044] Step S21: Based on various stress sources in the spacecraft operating environment, determine the stress types that typical integrated devices may suffer in the mission environment. Use ANSYS Mechanical simulation software to perform thermal and vibration simulations on the integrated devices, analyze the stress level of the interface circuit of the integrated devices under typical mission profiles, and determine the specific location where stress is applied.

[0045] Step S22: Combining the thermal and vibration simulation results from step S21, analyze the impact of different stress types on the interface circuit of integrated devices, identify possible failure mechanisms, establish a failure mode table for the interface circuit of integrated devices, and clarify the failure modes caused by various stress sources.

[0046] Step S3: Based on the fault mode table determined in Step S2, the potential path analysis considering fault factors is performed on the interface circuit under typical task profiles using circuit simulation methods to obtain the fault path response feature library of the interface circuit under the task profiles. The specific steps are as follows:

[0047] Step S31: Based on the fault mode table established in step S2, by modifying the parameters of the component model or changing the internal connection method of the component interface, the fault is injected into the interface circuit simulation model constructed in step S1, and an interface circuit failure simulation model containing fault factors is constructed.

[0048] Step S32: Set the stress excitation signal for a typical task profile, load electrical excitations such as ESD pulses, power-on surges, and level input interference, drive the interface circuit failure simulation model, and run the simulation under various working conditions;

[0049] Step S33: Monitor the voltage and current waveforms of key nodes in the interface circuit during the simulation process, and extract the formation process and conditions of typical potential paths such as source-to-ground short circuit, I / O mutual interference, pull-up failure, and protection diode breakdown;

[0050] Step S34: Based on the triggering conditions, stable state, and degree of impact on system function of potential paths, classify the potential paths identified in step S33 to form a fault path response feature library of interface circuits under the task profile.

[0051] Step S4: Combining the fault path response feature library of the interface circuit under the task profile obtained in Step S3, summarize the potential path activation conditions and fault manifestations, and form a constraint clue table for interface circuit design. The specific steps are as follows:

[0052] Step S41: Based on the fault path response feature library established in step S3, extract the excitation conditions of various potential paths under different task profiles, and classify them into a set of excitation conditions with input level, power timing, pull-up / pull-down structure, and level clamping method as key factors.

[0053] Step S42: Combining the excitation conditions identified in step S41, summarize the typical fault manifestations of various potential paths, including source-to-ground short circuit, interface open circuit, signal reverse conduction, protection diode breakdown, etc., and clarify the electrical abnormality characteristics that may be caused by each type of path.

[0054] Step S43: Based on the excitation conditions and fault manifestations summarized in step S42, establish a design constraint clue table for interface circuit design, form circuit structure review items corresponding to interface topology, level relationship, protection structure, power connection method, etc., and cover common potential path triggering paths, to obtain a constraint clue table for interface circuit design.

[0055] Step S5: Based on the clue table established in step S4, construct the interface circuit failure association fault tree model, and mark the relationship path between various potential paths and device degradation or local failure, which is used for failure location and path investigation in the process of integrated device design and verification.

[0056] Example:

[0057] This embodiment uses historical potential path problems as background, selects two typical cases, reproduces their potential paths through simulation, and performs diagnostic analysis of the potential paths in faulty circuits. Furthermore, this embodiment, based on circuit design data, builds a circuit simulation model of a typical FPGA peripheral circuit and identifies potential paths based on a forward design flow. The specific implementation steps are as follows:

[0058] First, determine the key interface type and potential path structure. The 54AC245 eight-channel bus transceiver is designed for asynchronous bidirectional communication between data buses, and its control functions minimize external timing requirements. Depending on the logic level on the direction control input, this type of device sends data from bus A to bus B, or vice versa. The output enable input can be used to disable the device, thus achieving effective bus isolation. The external circuit simulation diagram for this fault case is shown below. Figure 2 As shown, there are three 54AC245 devices that implement three-to-one redundancy cold backup, and their first I / O channels are named I / O1, I / O2, and I / O3, respectively.

[0059] Secondly, the typical failure modes of the internal components of the interface circuit were determined, and a failure mode table for the integrated device interface circuit was established. According to historical reports, when the fault occurred, the second and third transceivers were in a power-off state, and their I / O ports were all closed. At this time, the command control I / O1 output a high level, but the receiving bus Wire received a low level signal, and a high-level signal could not be received. Preliminary investigation determined that the diode at I / O3 had short-circuited and failed. Then, based on the fault description, a corresponding circuit simulation model was established. For example... Figure 3 As shown, in addition to the external circuits, it includes 6 integrated device interface circuits, including 3 identical ESD protection dual unidirectional diode circuits and 3 identical dual-terminal control interface circuits, corresponding to I / O1, I / O2, and I / O3 respectively.

[0060] Then, circuit simulation was used to analyze the potential path of the interface circuit under a typical task profile, considering fault factors. By setting different input forms for the interface circuit, simulation analysis was performed on the output I / O port. It was found that when the input form was defined as "54AC245 I / O in default pull-down low impedance state", the fault waveform corresponding to the potential path was as follows: Figure 4 As shown, the voltage at Wire point ②, which should have been the same as the input voltage ① (3.8V), is 1.55V, consistent with the fault description. Therefore, it can be determined that the cause of this problem is that the internal I / O interface circuit of the integrated device uses a power-off pull-down low-resistance mode. When the diode at I / O3 fails due to a short circuit, its unidirectional conduction is disrupted, and I / O3 pulls the level of the Wire port low, causing the high-level output of IO1 to also be pulled low, thus preventing the output of a high level. The solution to this fault is to use a more reliable reverse current protection circuit.

[0061] Finally, the triggering conditions and fault manifestations of potential paths are summarized, forming a constraint clue table for interface circuit design. Potential path analysis is essentially topology pattern recognition and the application of potential clues related to each topology. If a potential path is identified, further analysis is required to verify or refute it. Based on the above qualitative and quantitative analysis, and the analysis results of the circuit simulation model, a self-check table of design constraint clues considering integrated circuit interface circuits was established, as shown in Table 1. This table can serve as a supplement to the potential path analysis of spacecraft electronic systems, allowing for the investigation of potential paths in circuit parts related to integrated devices.

[0062] Table 1

[0063] 1. According to the manual, determine whether the integrated device interface has ESD protection circuitry, and if so, whether it is a bidirectional diode protection circuit. If so, does it have multiple ground ports to ensure the overcurrent capability of the electrostatic discharge path to ground? 2. According to the manual, determine whether the integrated device interface has ESD protection circuitry, and if so, whether it is a dual unidirectional diode protection circuit. If so, does it have multiple ground ports to ensure the overcurrent capability of the grounding path? Does it have multiple power supply ports to ensure the overcurrent capability of the electrostatic discharge path between the device and the power source? 3. According to the manual, determine whether the integrated device interface has ESD protection circuitry and power clamping circuitry. If so, can the overcurrent capability of the source-to-ground path be guaranteed? 4. Does the integrated device interface have a low-impedance pull-down circuit? If so, does it have a reverse current protection circuit? 5. Does the integrated device interface have a low-impedance pull-up circuit? If so, does it have a reverse current protection circuit? 6. Does the integrated device have multiple power supplies? Are there any requirements for the power-on and power-off timing? If so, are the timing control signals robust enough to prevent signal mistransmission? 7. Does the I / O port input level exceed the source and ground level range? If so, is there a corresponding reverse current protection circuit?

[0064] Based on this self-checklist, a fault tree approach is used to analyze the possible component failure modes in the integrated device interface circuit, and to locate the faulty circuits that may result from each type of failure. The specific fault tree is as follows: Figure 5 As shown, this serves as a supplement to the potential component failure scenario during the potential path analysis process. Using this method, given the location of the faulty circuit in advance, the specific internal components of the integrated device with the potential for intermittent failure can be deduced. Simulations can then be used to verify hypotheses about the failure of these components, eliminating the possibility that a failure caused by a specific component is mistakenly identified as a potential path problem, or determining that the potential path failure is caused by the combined effect of component failure and other phenomena. Specific Implementation Method Two:

[0066] This embodiment is a computer storage medium that stores at least one instruction, which is loaded and executed by a processor to implement the aforementioned method for potential path analysis of spacecraft integrated chip interface circuits considering faults.

[0067] It should be understood that the instructions include computer program products, software, or computerized methods corresponding to any method described in this invention; the instructions can be used to program computer systems or other electronic devices. Computer storage media may include readable media on which instructions are stored, and may include, but are not limited to, magnetic storage media, optical storage media; magneto-optical storage media include read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), and flash memory layers, or other types of media suitable for storing electronic instructions. Specific implementation method three:

[0069] This embodiment is a potential path analysis device for spacecraft integrated chip interface circuit considering faults. The device includes a processor and a memory. It should be understood that it includes any device including a processor and a memory described in this invention. The device may also include other units or modules that perform display, interaction, processing, control, and other functions through signals or instructions.

[0070] The memory stores at least one instruction, which is loaded and executed by a processor to implement the aforementioned method for analyzing potential pathways in spacecraft integrated chip interface circuits that consider faults.

[0071] Those skilled in the art will understand that at least one stored instruction constitutes a computer program product corresponding to a method or system. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0072] This application is described with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of this application, and can also be used with corresponding devices. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0073] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0074] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0075] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

[0076] The above examples of the present invention are merely illustrative of the computational model and process of the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is impossible to exhaustively list all possible implementations here. Any obvious variations or modifications derived from the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A method for analyzing potential pathways in spacecraft integrated chip interface circuits considering faults, characterized in that, include: Based on common interface circuits and potential path structures in spacecraft electronic systems, a simulation model of the interface circuit of integrated devices is constructed. Based on the circuit simulation model, the degradation mechanisms under various task stress environments are supplemented, and the fault mode table of the integrated device interface circuit is determined. Based on the fault mode table, circuit simulation is used to perform potential path analysis on interface circuits under typical task profiles, considering fault factors, and obtain a fault path response feature library of interface circuits under task profiles. By combining the fault path response feature library of interface circuits under the mission profile, the triggering conditions and fault manifestations of potential paths are summarized to form a constraint clue table for interface circuit design. Based on the clue table, an interface circuit failure association fault tree model is constructed to identify the relationship paths between various potential paths and device degradation or local failure, which is used for failure location and path investigation in the process of integrated device design and verification.

2. The method for potential path analysis of spacecraft integrated chip interface circuits considering faults according to claim 1, characterized in that, The types of interface circuits include power and ground interface circuits, I / O interface circuits, level conversion circuits, and protection circuits.

3. A method for analyzing potential pathways in spacecraft integrated chip interface circuits considering faults, as described in claim 1 or 2, characterized in that, The process of determining the fault mode table of integrated device interface circuits by supplementing degradation mechanisms under various task stress environments based on circuit simulation models includes: Step S21: Based on various stress sources in the spacecraft operating environment, determine the stress types that the integrated device suffers in the mission environment. Use simulation software to perform thermal and vibration simulations on the integrated device, analyze the stress level of the interface circuit of the integrated device under a typical mission profile, and determine the specific location where the stress is applied. Step S22: Based on the thermal and vibration simulation results in step S21, analyze the impact of different stress types on the interface circuit of the integrated device, and establish a fault mode table for the interface circuit of the integrated device.

4. The method for potential path analysis of spacecraft integrated chip interface circuits considering faults, as described in claim 3, is characterized in that... The process of using circuit simulation to perform potential path analysis on interface circuits under typical mission profiles, considering fault factors, and obtaining a fault path response feature library for interface circuits under mission profiles includes: Step S31: Based on the fault mode table, by modifying the parameters of the component model or changing the internal connection method of the component interface, the fault is injected into the constructed interface circuit simulation model to construct an interface circuit failure simulation model containing fault factors. Step S32: Set the stress excitation signal for a typical task profile, apply electrical excitation, drive the interface circuit failure simulation model, and run the simulation under various working conditions. Step S33: Monitor the voltage and current waveforms of key nodes in the interface circuit during the simulation process, and extract the typical potential path formation process and conditions; Step S34: Based on the triggering conditions, stable state, and degree of impact on system function of potential paths, classify the potential paths identified in step S33 to form a fault path response feature library of interface circuits under the task profile.

5. The method for potential path analysis of spacecraft integrated chip interface circuits considering faults, as described in claim 4, is characterized in that... The electrical excitation applied in step S32 includes ESD pulses, power-on surges, and level input interference.

6. The method for potential path analysis of spacecraft integrated chip interface circuits considering faults, as described in claim 5, is characterized in that... Step S33 extracts typical potential pathways, including source-to-ground short circuit, I / O interference, pull-up failure, and protection diode breakdown.

7. The method for potential path analysis of spacecraft integrated chip interface circuits considering faults, as described in claim 4, is characterized in that... The process of summarizing the potential path activation conditions and fault manifestations by combining the fault path response feature library of the interface circuit under the mission profile, and forming a constraint thread table for interface circuit design includes: Step S41: Based on the established fault path response feature library, extract the excitation conditions of various potential paths under different task profiles, and classify them into a set of excitation conditions with input level, power timing, pull-up / pull-down structure, and level clamping method as key factors. Step S42: Combining the excitation conditions identified in step S41, summarize the typical fault manifestations of various potential paths and clarify the electrical abnormality characteristics that each type of path may cause. Step S43: Based on the excitation conditions and fault manifestations summarized in step S42, establish a design constraint clue table for interface circuit design, form circuit structure review items corresponding to interface topology, level relationship, protection structure, and power connection method, and cover common potential path triggering paths to obtain a constraint clue table for interface circuit design.

8. The method for potential path analysis of spacecraft integrated chip interface circuits considering faults, as described in claim 7, is characterized in that, The typical fault manifestations described in step S42 include source-to-ground short circuit, interface open circuit, signal reverse conduction, and protection diode breakdown.

9. A computer storage medium, characterized in that, The storage medium stores at least one instruction, which is loaded and executed by a processor to implement the potential path analysis method for spacecraft integrated chip interface circuits considering faults, as described in any one of claims 1 to 8.

10. A potential path analysis device for spacecraft integrated chip interface circuits considering faults, characterized in that, The device includes a processor and a memory, the memory storing at least one instruction, which is loaded and executed by the processor to implement the potential path analysis method for spacecraft integrated chip interface circuits considering faults, as described in any one of claims 1 to 8.

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