Data processing apparatus, method, chip, electronic device, and storage medium

Abstract

The application discloses a data processing device, method, chip, electronic equipment and storage medium. The device comprises: a cache module for caching data; a cache monitoring module for determining the highest priority of the data in the cache module; determining the preset data consumption speed of the cache module according to the data variation in the first preset time length in the cache module; determining the adjustment value of the second data quantity threshold of the cache module according to the first time length when the data quantity in the cache module is greater than the first data quantity threshold; when the data quantity in the cache module is in the first state greater than the second data quantity threshold and the continuous time length is less than the first time length threshold, the highest priority is output; otherwise, the highest priority, the preset data consumption speed and the adjustment value are output; an arbitration module for executing data processing according to the output result. In this way, the flexibility and stability of the data processing of the buffer of the network on chip can be improved, and the processing efficiency of the upstream and downstream data can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a data processing device, method, chip, electronic equipment and storage medium. BACKGROUND

[0002] In a network-on-chip system, due to the dynamic characteristics of data flow, the load of each channel changes constantly. As a temporary storage unit for data transmission, the reasonable use of a buffer has a crucial impact on the performance of a network-on-chip channel. Unreasonable buffer regulation and use may lead to waste of storage resources, congestion concentration, and thus increase data transmission delay and reduce throughput.

[0003] In related technologies, monitoring the use of a buffer in a network-on-chip channel and optimizing the channel based on the monitoring results can effectively improve the overall performance of the network-on-chip system and meet the demand for high-speed and efficient data transmission of modern chips. However, fixed priority regulation methods may cause a large number of low-priority data packets to be directed to other congested areas, causing high-priority transactions in other channels to be blocked, increasing latency, and reducing bandwidth for high-bandwidth demand channels. In the face of the dynamic characteristics of traffic, frequent regulation intervention, insufficient use of cache, and waste of local cache resources may occur.

[0004] In related technologies, there is no good way to improve the data processing method of the buffer of the network-on-chip to improve the processing efficiency of upstream and downstream data. SUMMARY

[0005] The present application provides a data processing device, method, chip, electronic equipment and computer storage medium, which can improve the flexibility and stability of data processing of the buffer of the network-on-chip to improve the processing efficiency of upstream and downstream data.

[0006] To achieve the above-mentioned purpose, the technical scheme of the present application is as follows:

[0007] The present application provides a data processing device, which comprises a cache module, a cache monitoring module and an arbitration module, wherein,

[0008] The cache module is configured to cache data.

[0009] The cache monitoring module is configured to determine the highest priority of data of different events in the cache module, wherein the highest priority is the priority of data processing.

[0010] The cache monitoring module is further configured to determine a preset data consumption speed of the cache module according to a data variation amount in a first preset time length in the cache module, wherein the first preset time length is a total time length of a plurality of clock cycles before a current time;

[0011] The cache monitoring module is further configured to determine an adjustment value of a second data amount threshold of the cache module according to a first time length during which a data amount in the cache module is greater than a first data amount threshold, wherein the first data amount threshold is equal to an initial second data amount threshold, and the initial second data amount threshold is one half of a total data storage amount of the cache module;

[0012] The cache monitoring module is further configured to take the highest priority as an output result when the data amount in the cache module is in a first state greater than a second data amount threshold, and a continuous time length of the first state is less than a first time length threshold, wherein the first time length threshold is less than the first preset time length;

[0013] The cache monitoring module is further configured to take the highest priority, the preset data consumption speed, and the adjustment value as the output result when the data amount in the cache module is in the first state greater than the second data amount threshold, and the continuous time length of the first state is greater than the first time length threshold;

[0014] The arbitration module is configured to perform data processing according to the output result.

[0015] Embodiments of the present application provide a data processing method, which is implemented based on the data processing device described in the embodiments of the present application. The method comprises:

[0016] Caching data by using the cache module;

[0017] Determining a highest priority of data of different events in the cache module;

[0018] Determining a preset data consumption speed of the cache module according to a data variation amount in a first preset time length in the cache module, wherein the first preset time length is a total time length of a plurality of clock cycles before a current time;

[0019] Determining an adjustment value of a second data amount threshold of the cache module according to a first time length during which a data amount in the cache module is greater than a first data amount threshold, wherein the first data amount threshold is equal to an initial second data amount threshold, and the initial second data amount threshold is one half of a total data storage amount of the cache module;

[0020] when the data amount in the cache module is in a first state greater than a second data amount threshold and a continuous time length of the first state is less than a first time length threshold, taking the highest priority as the output result, wherein the first time length threshold is less than the first preset time length;

[0021] when the data amount in the cache module is in a first state greater than a second data amount threshold and a continuous time length of the first state is greater than a first time length threshold, taking the highest priority, the preset data consumption speed and the adjustment value as the output result;

[0022] performing data processing according to the output result.

[0023] In some embodiments, the embodiments of the present application further provide a chip, comprising the data processing apparatus as described in the embodiments of the present application.

[0024] In some embodiments, the embodiments of the present application further provide an electronic device, comprising a processor, wherein the processor comprises the data processing apparatus as described in the embodiments of the present application.

[0025] or a memory for storing computer executable instructions or computer programs; and a processor for executing the computer executable instructions or computer programs stored in the memory to implement the data processing method as described in the embodiments of the present application.

[0026] In some embodiments, the embodiments of the present application further provide a computer readable storage medium storing computer executable instructions or computer programs, which are executed by a processor to implement the data processing method as described in the embodiments of the present application.

[0027] The embodiments of the present application have the following beneficial effects:

[0028] The cache monitoring module monitors different parameters of the cache module respectively, and generates corresponding parameters for adjusting the cache module according to the monitored parameters, including but not limited to the highest priority of data processing, the preset data consumption speed, and the adjustment value of the data volume threshold. At the same time, the cache monitoring module is also used to determine that the data volume in the cache module is in a first state greater than a second data volume threshold. The first state can represent whether the cache module is in a state of storing more resources for a long time. According to whether the duration of the first state is greater than a preset duration threshold, it is judged whether the highest priority of data processing, the preset data consumption speed, and the adjustment value of the data volume threshold are applied to data processing to relieve the data congestion of the upstream and downstream of the cache module. The highest priority is output to the downstream in each case, which can optimize local congestion without damaging the global priority strategy. Whether to adjust the preset data consumption speed and the adjustment value of the data volume threshold does not depend on the instantaneous value, and is judged according to the continuous duration of the first state, which can filter out temporary fluctuations and avoid misjudgment. It can improve the data processing efficiency of the upstream and downstream of the cache module, control the data volume in the cache module appropriately, avoid the overflow of the cache module, the data congestion of the upstream of the cache module, or the lack of data to be processed in the downstream of the cache module, and improve the adaptability of the network on chip. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a structure schematic diagram of a data processing device provided by an embodiment of the present application Figure 1 ;

[0030] Figure 2 is a structure schematic diagram of a data processing device provided by an embodiment of the present application Figure 2 ;

[0031] Figure 3 is a structure schematic diagram of a data processing device provided by an embodiment of the present application Figure 3 ;

[0032] Figure 4 is a flowchart of a data processing method provided by an embodiment of the present application.

[0033] It should be pointed out that the "first" and "second" above are only used to distinguish different schemes, and do not represent the degree of superiority or priority in the implementation process. DETAILED DESCRIPTION

[0034] In order to be able to understand the characteristics and technical content of the embodiments of the present application more thoroughly, the implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present application.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0036] In the following description, reference is made to the "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or a different subset of all possible embodiments and can be combined with each other, without conflict.

[0037] It should also be noted that the terms "first\second\third" in the embodiments of the present application are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that the "first\second\third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program with a predetermined function, and works together with other related parts to achieve a predetermined target, and can be implemented entirely or partially by using software, hardware (such as processing circuit or memory) or combination thereof. Similarly, one processor (or multiple processors or memory) can be used to implement one or more modules or units. In addition, each module or unit can be a part of an overall module or unit that includes the functions of the module or unit.

[0038] It should be noted that the relevant data collection and processing in the present application should strictly comply with the requirements of relevant laws and regulations, obtain the informed consent or separate consent of the personal information subject, and within the scope of authorization of laws and regulations and the personal information subject, carry out subsequent data use and processing behavior.

[0039] In order to facilitate the understanding of the technical solutions of the embodiments of the present application, the related terms and related technologies of the embodiments of the present application are described as follows, which can be combined with the technical solutions of the embodiments of the present application in any way as optional solutions, and all belong to the protection scope of the embodiments of the present application.

[0040] 1) Multiprocessor system: a parallel computing system composed of multiple processors interconnected by shared memory or distributed memory, combining very large scale integrated circuit (VLSI) technology and parallel processing technology, which can not only improve system throughput and running reliability, but also realize high-performance computing through parallel processing. The traditional narrow definition refers to the architecture system that uses multiple central processing units (CPUs) to execute user programs in parallel to improve system throughput or perform redundant operations.

[0041] 2) Network-on-chip (NOC): A new communication method for system-on-chip (SoC), as a major component of multi-core technology, it realizes concurrent communication through distributed routing nodes and time-multiplexed links, replacing the traditional bus architecture to solve the scalability and performance bottleneck problem. Its architecture is divided into electronic network-on-chip (ENoC) based on electronic technology and optical network-on-chip (ONoC) based on optical technology, using a global asynchronous and local synchronous clock mechanism to reduce power consumption. The bandwidth of network-on-chip is higher than that of bus architecture, the dynamic power consumption is not high, and it supports multi-core processor and artificial intelligence (AI) accelerator scenarios.

[0042] 3) Multi-Processor System on Chip (MPSOC): A combination of system-on-chip (SoC) and multi-processor system, referring to a system that integrates multiple processor cores on a single chip.

[0043] 4) Buffer: The buffer of network-on-chip is a storage area used for temporary storage of network data exchange, its main function is to balance the data transmission rate difference between different devices and reduce the risk of congestion.

[0044] 5) Flow control unit (flit): The basic packet structure used for data transmission in network-on-chip. When a message is injected into the network-on-chip, the message is divided into packets (referred to as packets), and then divided into fixed-length flow control units (referred to as flits). For example, a 128-byte cache line is sent from a sharer to a requester, which will be sent as a message, if the maximum packet size is greater than 128 bytes, the entire message will be encoded as a single packet. This packet will include a head flit containing the target address, body flits, and a tail flit indicating the end of the packet. Flits can be further divided into physical units (phits) corresponding to the physical channel width.

[0045] 6) Channel: The channel of network-on-chip (NoC) is mainly composed of communication links and routers.

[0046] 7) Depth: The depth of the buffer in the embodiments of the present application refers to its storage capacity, including the maximum amount of data that can be stored and the amount of data currently stored. The maximum amount of data that can be stored can be in bits, and the amount of data currently stored can be expressed in bits, or the percentage of the ratio of the bit value of the amount of data currently stored to the bit value of the maximum amount of data stored.

[0047] 8) Clock cycle: The clock cycle of a chip is the minimum unit of time in which a central processing unit (CPU) performs an operation, referring to the complete cycle of a clock signal, determined by the inverse of the frequency.

[0048] In the related art, in a network-on-chip system, due to the dynamic characteristics of data flow, the load of each channel changes constantly. The traditional fixed priority channel scheduling method is difficult to adapt to such dynamic changes, which easily leads to long-term resource occupation of high-priority channels, and low-priority channels cannot obtain sufficient resource allocation even when the load is light, thereby reducing the overall system efficiency. As a temporary storage unit for data transmission, the reasonable use of the buffer has a crucial impact on the performance of the network-on-chip channel. Unreasonable buffer regulation and use may lead to waste of storage resources, congestion concentration, and thus increase the delay of high-priority data transmission and reduce the throughput. Therefore, monitoring the buffer usage in the network-on-chip channel and optimizing the channel regulation based on the monitoring results can effectively improve the overall performance of the network-on-chip system and meet the demand for high-speed and efficient data transmission of modern chips. In the related art, the fixed priority regulation method for the buffer may lead to a large number of low-priority data packets being directed to other congested areas, causing high-priority transactions in other channels to be blocked, increasing the delay, and reducing the bandwidth obtained by high-bandwidth demand channels. In the face of the dynamic characteristics of the flow, the regulation intervention is prone to be frequent, the cache usage is insufficient, and the local cache resources are wasted.

[0049] Therefore, the embodiments of the present application provide a data processing apparatus, a data processing method, a chip, an electronic device and a computer storage medium, which respectively monitor different parameters of the cache module, and determine that the data amount in the cache module is in a first state greater than a second data amount threshold. The first state can represent whether the cache module is in a state of storing more resources for a long time. According to whether the duration of the first state is greater than a preset duration threshold, it is judged whether to apply the adjustment value of the highest priority of data processing, the preset data consumption speed and the data amount threshold to the data processing to relieve the data congestion of the upstream and downstream of the cache module. According to the sustained parameters, the adjustment of the cache module can filter out temporary fluctuations and avoid misjudgment. The data amount in the cache module is appropriately controlled to avoid the overflow of the cache module, the congestion of the data upstream of the cache module, or the lack of data to be processed downstream of the cache module, thereby improving the adaptability of the network-on-chip.

[0050] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0051] Figure 1 is a structure diagram of a data processing apparatus provided by the embodiments of the present application Figure 1 The data processing apparatus 100 includes a cache module 102, a cache monitoring module 101 and an arbitration module 103.

[0052] The cache module 102 is configured to cache data.

[0053] The cache monitoring module 101 is configured to determine the highest priority of data of different events in the cache module, wherein the highest priority is the priority of data processing.

[0054] In an example, the preset priorities of different types of events are different, and in an actual application scenario, the preset priorities of different events can be set according to requirements. The priorities of different events in the cache module can be updated according to the data amounts of different events, and the highest priority data is determined based on the updated priorities.

[0055] In some embodiments, the cache monitoring module is further configured to determine the highest priority of data of different events in the cache module by: counting the amounts of data of different events stored in the cache module; determining priority adjustment values of different events according to the amounts of data of each event, wherein the priority adjustment values are positively correlated with the amounts of data of the events; adding the priority adjustment values and the preset priorities of the corresponding events to obtain actual priorities of each event, and selecting the highest priority among the actual priorities.

[0056] For example, there are event A, event B and event C, the preset priority of event A is 3, the preset priority of event B is 4, and the preset priority of event C is 5, the greater the value of the priority is, the higher the priority is, the cache module stores 3 copies of data of event A, 1 copy of data of event B, and 0 copy of data of event C. The priority of data of event A is adjusted to 6 (3+3), and the priority of data of event B is adjusted to 5 (4+1), so the priority of data of event A is the highest, and the output result of the priority of data of event A is 6.

[0057] The cache monitoring module 101 is further configured to determine a preset data consumption speed of the cache module according to a data variation amount in a first preset time length in the cache module.

[0058] In an example, the first preset time length is the total time length of a plurality of clock periods before the current time. For example, 8 clock periods. The data variation amount can be used to measure the possibility of data mutation in the cache module in the first preset time length, and if there is a possibility of sudden rise or fall of data in the cache module, the data consumption speed in the cache module needs to be adjusted to avoid data overflow in the cache module. The preset data consumption speed can be represented by data amount / time, for example, 2 kilobits / second.

[0059] In some embodiments, the cache monitoring module is further configured to obtain a first data amount at each of a plurality of first time points within the first preset time period before the current time point, wherein adjacent first time points are separated by at least one clock cycle; when the current data amount at the current time point is greater than a third data amount threshold, the data variation is a difference between the current data amount and a smallest first data amount; and when the data variation is greater than a data variation threshold, a preset data consumption speed is determined according to a preset mapping relationship between the third data amount threshold and the consumption speed.

[0060] For example, the data variation threshold is less than a difference between the third data amount threshold and the first data amount threshold. For example, the third data amount threshold is set to 80% of the total cache data amount (32 KB), i.e., 24 KB, the difference between the third data amount threshold and the first data amount threshold (16 KB) is 8 KB, and the data variation threshold can be 4 KB. When the current data amount at the current time point is greater than the third data amount threshold, it indicates that the current data amount is large, and if the data amount increases rapidly, the cache module may overflow, triggering the operation of predicting the data variation. The data amount threshold or the preset mapping relationship between the third data amount threshold and the consumption speed can be set according to the actual application scenario. For example, the third data amount threshold is 80% of the total cache data amount of the cache module, and the preset data consumption speed is V0, the unit of V0 is kilobit per second (KB / s). The data amount threshold is 90% of the total cache data amount of the cache module, and the preset data consumption speed is V1. V1 is greater than V0. Assuming that the total size of the cache space of the cache module is 32 KB, the preset data consumption speed can be 0.5 KB per clock cycle (cycle). The length of the clock cycle is set according to the requirements of the actual application scenario. The clock cycle of the chip is the minimum time unit for the central processing unit (CPU) to execute an operation, which refers to the complete period of the clock signal and is determined by the reciprocal of the frequency.

[0061] In some embodiments, the cache monitoring module further includes a plurality of counters, wherein one of the counters is configured to store a first data amount at one of the first time points; and when the number of stored first data amounts is equal to the number of the counters, the latest obtained first data amount is used to replace the first data amount stored in a target counter, wherein the target counter is the earliest counter corresponding to the first time point of the stored first data amount among the plurality of counters.

[0062] For example, there are a counter 1 to a counter N, N is a positive integer, the first data quantity obtained is stored in the corresponding counter in sequence from the counter 1 to the counter N, in the case that the counter 1 to the counter N all store a first data quantity, the first data quantity of the latest first time obtained is stored in the counter 1, and the first data quantity stored in the counter 1 is overwritten.

[0063] The cache monitoring module 101 is further configured to determine an adjustment value of the second data quantity threshold of the cache module according to a first time length during which the data quantity in the cache module is greater than a first data quantity threshold.

[0064] For example, the first data quantity threshold is equal to the initial second data quantity threshold, and the initial second data quantity threshold is half of the total data storage quantity of the cache module. For example, the total data storage quantity of the cache module is 32 KB, the initial second data quantity threshold is 16 KB, and the first data quantity threshold is also 16 KB.

[0065] The state in which the data quantity is greater than the first data quantity threshold is regarded as a second state, a first time length during which the second state accumulates within a preset time length before the current time is counted, and an adjustment value of the second data quantity threshold of the cache module is determined according to whether the first time length exceeds a threshold value.

[0066] In some embodiments, the cache monitoring module is further configured to determine the adjustment value of the second data quantity threshold of the cache module according to a first time length during which the data quantity in the cache module is greater than a first data quantity threshold by: obtaining a first data quantity of the cache module within a second preset time length before the current time; determining a first time length of a second state within the second preset time length, wherein the second state is a state in which the first data quantity is greater than the first data quantity threshold; when the first time length is greater than a third time length threshold, taking a first preset value as the adjustment value; and when the first time length is less than the third time length threshold, taking a second preset value as the adjustment value, wherein the second preset value is less than the first preset value.

[0067] For example, a basic value and a dynamic adjustment value are set in advance according to the needs of the cache module, when the first time length is greater than the third time length threshold, the sum of the basic value and the dynamic adjustment value is taken as the first preset value, and the dynamic adjustment value can be 1 (unit: KB), when the first time length is less than the third time length threshold, the difference obtained by subtracting the dynamic adjustment value from the basic value is taken as the second preset value. Continue to take the above as an example, when the adjustment value is equal to 1 as the output result, based on the adjustment to the second data quantity threshold, 16 KB is added by 1 KB, and the updated second data quantity threshold is 17 KB.

[0068] In some embodiments, the cache monitoring module is further configured to determine the first time length by: taking a second time point as a start time point in response to the first data amount being less than the first data amount threshold before the second time point and the first data amount being greater than the first data amount threshold after the second time point; taking a third time point as an end time point in response to the first data amount being greater than the first data amount threshold before the third time point and the first data amount being less than the first data amount threshold after the third time point, wherein the third time point is after the second time point; taking a time length between the start time point and the end time point as a statistical time length of the second state; and adding each statistical time length corresponding to the second preset time length to obtain the first time length.

[0069] The cache monitoring module 101 is further configured to take the highest priority as the output result when the data amount in the cache module is in the first state greater than the second data amount threshold and a continuous time length of the first state is less than a first time length threshold.

[0070] For example, the first time length threshold is less than the first preset time length. For example, the first time length threshold is 4 clock cycles and the first preset time length is 8 clock cycles. The cache monitoring module is provided with a data selector. When the data amount in the cache module is in the first state greater than the second data amount threshold and the continuous time length of the first state is less than the first time length threshold, the data selector outputs a selection value 1, indicating that the highest priority is taken as the output result.

[0071] The cache monitoring module 101 is further configured to take the highest priority, the preset data consumption speed and the adjustment value as the output result when the data amount in the cache module is in the first state greater than the second data amount threshold and the continuous time length of the first state is greater than the first time length threshold.

[0072] For example, the cache monitoring module is provided with a data selector. When the data amount in the cache module is in the first state greater than the second data amount threshold and the continuous time length of the first state is greater than the first time length threshold, the data selector outputs a selection value 0, indicating that the highest priority, the preset data consumption speed and the adjustment value are taken as the output result.

[0073] The arbitration module 103 is configured to perform data processing according to the output result.

[0074] For example, when the output result is the highest priority, the arbitration module outputs the data of the highest priority to a downstream data processing unit, and the data processing unit processes the data of the highest priority in priority according to the highest priority to relieve the storage pressure of the cache module. When the output result is the highest priority, the preset data consumption speed, and the adjustment value, the arbitration module outputs the highest priority, the preset data consumption speed, and the adjustment value to the downstream data processing unit, and the data processing unit processes the data of the highest priority in priority according to the highest priority to relieve the storage pressure of the cache module; the data processing unit increases the data processing speed according to the preset data consumption speed and increases the data quantity threshold of the cache module according to the adjustment value.

[0075] In some embodiments, when the cache modules are multiple, the arbitration module is further configured to determine a target cache module according to the output results respectively corresponding to the different cache modules, wherein the stored data of the target cache module is output to a downstream data processing unit.

[0076] For example, when the output result is the priority, the arbitration module outputs the maximum priority corresponding to the multiple cache modules to a downstream data processing unit, so that the downstream data processing unit processes the data of the maximum priority in priority. For example, the traffic control units (basic packet structures for data transmission) with the highest priority in the multiple cache modules are traffic control unit A, traffic control unit B, and traffic control unit C, respectively, the multiple cache modules belong to different channels, and share one downstream processing unit, and the traffic control unit with the highest priority among the traffic control unit A, the traffic control unit B, and the traffic control unit C is selected for processing. The above setting can ensure the global priority and process the data of the global highest priority in priority in the case of multiple channels and multiple cache modules.

[0077] In some embodiments, the cache monitoring module is further configured to determine a first priority of data to be stored in the cache module when the cached data quantity of the cache module is equal to the total cache data quantity of the cache module; and in response to the first priority being greater than a second priority of the stored data of the cache module, the second priority is taken as the output result.

[0078] For example, when the depth of data in the cache module reaches 100%, data upstream of the cache module accumulates, and therefore it should be considered whether to output the upstream data (data to be stored in the cache module) directly to the downstream without passing through the cache module. The first priority of the data to be stored in the cache module and the second priority of the stored data are compared, and the greater priority is output to the arbitration module, so that the arbitration module controls the downstream circuit to preferentially process the corresponding data according to the maximum priority. The above process can be represented as max (value4, value5), where max() is a function for selecting the maximum value, value4 is the second priority of the stored data, and value5 is the first priority of the data to be stored in the cache module.

[0079] In some embodiments, the application also provides a data processing method, which is implemented based on the data processing device provided by the application, Figure 4 is a flowchart of the data processing method provided by the application.

[0080] In step 401, data is cached by the cache module.

[0081] In step 402, the highest priority of the data of different events in the cache module is determined.

[0082] In some embodiments, step 402 can be implemented in the following manner: the number of data of different events stored in the cache module is counted; the priority adjustment value of each event is determined according to the number of the event, wherein the priority adjustment value is positively correlated with the number of the event; the actual priority of each event is obtained by adding the priority adjustment value and the preset priority of the corresponding event, and the highest priority in the actual priority is selected.

[0083] In step 403, the preset data consumption speed of the cache module is determined according to the data variation within the first preset time length in the cache module.

[0084] In some embodiments, the first preset time length is a total time length of a plurality of clock cycles before a current time. Step 403 can be implemented by: obtaining a first data amount of a plurality of first times in the cache module within the first preset time length before the current time, wherein adjacent first times are separated by a clock cycle; when a current data amount of the current time is greater than a third data amount threshold, the third data amount threshold being greater than the first data amount threshold and the second data amount threshold, taking a difference between the current data amount and a smallest first data amount as the data variation amount; when the data variation amount is greater than a data variation amount threshold, determining a preset data consumption speed according to a preset mapping relationship between the third data amount threshold and the consumption speed. Wherein, a plurality of counters are set, wherein one of the counters is used to store a first data amount of one of the first times; when the number of stored first data amounts is equal to the number of the counters, the latest obtained first data amount is used to replace the first data amount stored in a target counter, wherein the target counter is the counter with the earliest first time corresponding to the stored first data amount among the plurality of counters.

[0085] In step 404, an adjustment value of the second data amount threshold of the cache module is determined according to a first time length during which the data amount in the cache module is greater than the first data amount threshold.

[0086] In some embodiments, the first data amount threshold is equal to an initial second data amount threshold, and the initial second data amount threshold is half of the total data storage amount of the cache module. Step 404 can be implemented by: obtaining a first data amount of the cache module within a second preset time length before a current time; determining a first time length during which the first data amount is in a second state greater than a first data amount threshold, the second state being a state in which the first data amount is greater than the first data amount threshold; when the first time length is greater than a third time length threshold, taking a first preset value as the adjustment value; when the first time length is less than the third time length threshold, taking a second preset value as the adjustment value, wherein the second preset value is less than the first preset value.

[0087] In some embodiments, determining the first duration of the first data amount being in the second state greater than the first data amount threshold can be achieved by: in response to the first data amount being less than the first data amount threshold before a second time and the first data amount being greater than the first data amount threshold after the second time, taking the second time as a starting time; in response to the first data amount being greater than the first data amount threshold before a third time and the first data amount being less than the first data amount threshold after the third time, taking the third time as an ending time, wherein the third time is after the second time; taking the duration between the starting time and the ending time as a statistical duration of the second state; and adding each corresponding statistical duration within the second preset duration to obtain the first duration.

[0088] In step 405, when the amount of data in the cache module is in the first state greater than the second data amount threshold and the continuous duration of the first state is less than the first duration threshold, the highest priority is taken as the output result.

[0089] In step 406, when the amount of data in the cache module is in the first state greater than the second data amount threshold and the continuous duration of the first state is greater than the first duration threshold, the highest priority, the preset data consumption speed and the adjustment value are taken as the output result.

[0090] In step 407, data processing is performed according to the output result.

[0091] In some embodiments, step 407 can be achieved by: when the cache module is multiple, determining a target cache module according to the output results respectively corresponding to the different cache modules, wherein the stored data of the target cache module is output to a downstream data processing unit.

[0092] In some embodiments, the following processing is also performed: when the amount of cached data of the cache module is equal to the total amount of cached data of the cache module, determining the first priority of the data to be stored in the cache module; in response to the first priority being greater than the second priority of the data already stored in the cache module, taking the second priority as the output result.

[0093] In the embodiments of the present application, the cache monitoring module monitors different parameters of the cache module, and generates corresponding parameters for adjusting the cache module according to the monitored parameters, including but not limited to the highest priority of data processing, the preset data consumption speed, and the adjustment value of the data volume threshold. At the same time, the cache monitoring module determines that the data volume in the cache module is in a first state greater than a second data volume threshold. The first state can represent whether the cache module is in a state of storing more resources for a long time. According to whether the duration of the first state is greater than a preset duration threshold, it is judged whether the highest priority of data processing, the preset data consumption speed, and the adjustment value of the data volume threshold are applied to data processing to relieve the data congestion of the upstream and downstream of the cache module. The highest priority is output to the downstream in each case, which can optimize local congestion without damaging the global priority strategy. Whether to adjust the preset data consumption speed and the adjustment value of the data volume threshold does not depend on the instantaneous value, but is judged according to the continuous duration of the first state, which can filter out temporary fluctuations and avoid misjudgment. It can improve the data processing efficiency of the upstream and downstream of the cache module, and control the data volume in the cache module appropriately to avoid the overflow of the cache module, the data congestion of the upstream of the cache module, or the lack of data to be processed in the downstream of the cache module, and improve the adaptability of the network on chip.

[0094] In the following, an exemplary application of the data processing device in an actual application scenario will be described.

[0095] In a network-on-chip system, due to the dynamic characteristics of data traffic, the load of each channel is constantly changing. The traditional fixed priority channel scheduling method is difficult to adapt to such dynamic changes, which easily leads to long-term occupation of resources by high-priority channels, and low-priority channels cannot get enough resource allocation even when the load is light, thereby reducing the overall system efficiency. As a temporary storage unit for data transmission, the reasonable use of the buffer has a crucial impact on the performance of the network-on-chip channel. In the related technology, the buffer usage depth is monitored to improve the channel priority, multiple high thresholds (High Threshold) TH0, TH1 and multiple low thresholds (Low Threshold) TL0, TL1 are set, and preset priorities Q0 and Q1 are set. When the depth does not exceed TH0, the original priority v0 of the channel is used as the priority of the channel to participate in downstream arbitration; when the depth usage exceeds TH0, v0+Q0 is used to participate in arbitration; when the depth usage exceeds TH1, v0+Q1 is used to participate in arbitration; when the depth usage is less than TL1, v0+Q0 is used to participate in arbitration; when the depth usage is less than TL0, the original priority v0 is used to participate in arbitration. The related technology has the following problems: (1) Only the local congestion state is considered, and the global priority scheme is not considered. The fixed priority control method of the related technology may cause a large number of low-priority data packets to be output to other congested areas, causing high-priority transactions of other channels to be blocked, increasing the delay, and reducing the bandwidth allocated to high-bandwidth demand channels. For example, the transactions of channel A are all low-priority, the transactions of channel B are all high-priority, channel A and channel B share a downstream processing unit, and channel A and channel B have their own buffers. When a large number of low-priority transactions are cached in channel A, the control method of the related technology may determine to process the data in channel A first according to the data amount, which may cause a large number of transactions in channel A to be transmitted to the downstream, causing the high-priority transactions of channel B to be blocked by the low-priority transactions of channel A for a long time. (2) The parameter representing the instantaneous state is used to determine whether to control, and the "instantaneous depth" of the buffer is used as the only judgment standard, which may misjudge "temporary congestion" as "continuous congestion". In the face of the dynamic characteristics of traffic, the control may be frequently intervened, the buffer usage may be insufficient, and local cache resources may be wasted. When the buffer depth temporarily exceeds the threshold due to sudden traffic, the priority may be adjusted. However, such fluctuations may recover in a short time, and the adjustment at this time wastes computing resources and does not play a corresponding role. For example, when the threshold is set to 50%, the buffer depth may frequently fluctuate around 50% (such as 49%→51%→48%), causing the priority to be repeatedly adjusted, the hardware logic to frequently switch the priority, and the circuit power consumption to increase; frequent triggering of priority promotion may also cause temporary occupation of downstream resources, affecting the normal scheduling of other channels. (3) Lack of adaptive adjustment means, which cannot adapt to complex multi-task scenarios.Over-regulation in light congestion, waste high priority resources, such as the priority of low load path is promoted, critical business bandwidth is squeezed; serious congestion, lack of strength, can not effectively alleviate the bottleneck; for example, the threshold is sustained but the regulation intensity is fixed, and the buffer is eventually overflowed.

[0096] The embodiment of the present application provides a data processing device, which optimizes data processing of an on-chip network channel according to parameters of a cache region, considers a global quality of service (QoS) priority scheme, and does not damage the global priority strategy when optimizing local congestion. When optimizing local congestion, the global priority strategy is not damaged; the judgment is made according to data of continuous n periods and a preset condition without depending on instantaneous values, a time threshold is added on the basis of a data quantity threshold, and adjustment is only performed when the buffer is continuously at a high water level, so that short-term fluctuations can be filtered out, and misjudgment can be avoided. For a multi-task scene, corresponding adaptive adjustment means are set, the current regulation intensity is judged according to past situations and a set adjustment expectation when congestion occurs, the hardware adaptively adjusts the regulation scheme for the multi-task scene, software intervention is not needed, sudden transactions of additional monitored data quantity increase or decrease are regulated, and both regular transaction scenes and sudden transaction scenes can be handled.

[0097] The data processing device provided by the embodiment of the present application is explained and described below with reference to the accompanying drawings. Figure 2 , Figure 2 is a structure diagram of the data processing device provided by the embodiment of the present application. Figure 2 The data processing device 200 includes a cache module 201, a cache monitoring module 202 and an arbitration module 203. The upstream refers to other modules that input data to the data processing device, and the downstream refers to a calculation unit that performs other processing on output data of the data processing device. When the flow control unit flitB of channel B and the flow control unit flitC of channel C arrive at the input end of the arbitration module at the same time, priority judgment is performed, if the flow control unit flitC obtains authorization, the data is transmitted to the downstream, the flow control unit flitA writes the cache module, and the cache module depth is increased by 1; according to the set expectation, the cache monitoring module 202 decides whether to improve the priority of the flow control unit flitB participating in the next arbitration.

[0098] Reference Figure 3 , Figure 3 is a structure diagram of the data processing device provided by the embodiment of the present application. Figure 3 ; Figure 3 The cache monitoring module 300 in Figure 2Figure 3 illustrates one embodiment of the cache monitoring module 202 in Figure 2. The cache monitoring module 300 includes a configurable register module 301, a priority statistics comparison module 302, a burst monitoring comparison module 303, a depth statistics comparison module 304, a summation module 306, a depth monitoring comparison module 305, a selection module 307, and a maximum module 308.

[0099] In some embodiments, the configurable register module 301 provides configurable input ports to publish configuration schemes to each sub-module in the cache monitoring module 300. That is, the configurable register module 301 assigns different configuration conditions to the depth statistics comparison module, the burst monitoring comparison module, and the depth statistics comparison module, respectively. The preconfigured conditions in the configurable register module 301 are input through a configuration input interface, which can be set according to requirements in actual applications. Assuming that the buffer depth is 32, and continuing to refer to Figure 2 , the following settings are made: configuration 0: depth threshold TH0= 16 (the second data amount threshold in the foregoing), time tolerance = 4 (the first time length threshold in the foregoing); configuration 1: depth = 24 (the third data amount threshold in the foregoing), time window = 8 (the first preset time length in the foregoing), and burst intensity value = 4 (the data amount change threshold in the foregoing); and configuration 2: depth = 16 (the first data amount threshold in the foregoing), time window = 32 (the second preset time length in the foregoing), and regulation result threshold = 16 (namely 50%).

[0100] In some embodiments, the priority statistics comparison module 302 is configured to count the priority of cache transactions in the buffer and record the number of cache transactions of each priority. The preset priority is adjusted according to the number of events stored in the cache module, for example: when transaction A is written into the buffer, the priority counter corresponding to transaction A is incremented by 1, and when transaction B is read out from the buffer, the priority counter corresponding to transaction B is decremented by 1. According to the priority counter values, the highest priority of all transactions in the buffer can be inferred, and the inferred highest priority is taken as the output (value0) of the priority statistics comparison module 302. The output value of the priority statistics comparison module 302 is input to the selection module 307 or the summation module 306.

[0101] For example, 8 priority levels are designed in advance, and a sideband channel of urgency is set in addition to the QoS state carried by the transaction itself; when back pressure occurs downstream, for example, back pressure generated by the arbitration module failing to obtain authorization, the buffer monitoring module makes a prediction according to the buffer usage, and the result is transmitted to the downstream through the urgency channel, and the arbitration module determines the highest priority through the formula max (transaction priority, urgency value), and participates in the next arbitration based on the highest priority. For example: the priority statistical comparison module statistically compares the priority of the transaction in the buffer, when the transaction enters the buffer, input1 will increase the counter value corresponding to the priority of the transaction by 1, there are 7 counters in total, corresponding to priority 1, 2, …, 7 (priority = 0 does not need to be counted). According to the non-zero state of each counter, the maximum priority of the cached transaction is selected as the output value (value0) of this module.

[0102] In the embodiment of the application, the highest priority of the cached transaction in the buffer is counted, and additional control is made based on the highest priority. The priority statistical comparison module counts and outputs the highest priority of the transaction in the buffer, and ensures that when back pressure occurs downstream, the priority of the transaction in the buffer is used as a reference for adjustment, without affecting the global priority strategy. At different times, the priority of the transaction in the same buffer may be different, and corresponding adjustment is performed to effectively avoid the destruction of the global QoS strategy.

[0103] In some embodiments, the burst monitoring comparison module 303 is configured to monitor the traffic burst of the buffer module, and output a preset data consumption rate to avoid data overflow of the buffer module. When a traffic burst is detected, the preset data consumption rate is output to the downstream to ensure that the burst scenario does not exceed the tolerance upper limit of traffic variation (the tolerance upper limit of traffic variation depends on the sensitivity of the upstream to back pressure). This can be achieved by the following method: based on the total depth of the buffer module, a preset number of counters cnt_n is configured. The depth value of cnt_n cycles is monitored, and the depth value is recorded once per cycle. The depth values at times 0 to cnt_n are recorded in the counters cnt_0, cnt_1 to cnt_n in turn. The depth value at time cnt_n+1 is recorded in cnt_0, i.e. the value at time 0 is overwritten, and the depth values of the last cnt_n cycles are recorded in this way through a sliding window. The data threshold TH0 is configured; when the current buffer depth usage is equal to D0, the minimum value (the minimum first data amount) is selected from the counters cnt_0, cnt_1 and cnt_n, and the minimum value is assumed to be D1. The burst strength = (D0-D1) is calculated, and compared with the data threshold TH0. For example, in 10 clock cycles, D0-D1=8, and the threshold is set to 5, so the burst strength is greater than the tolerance upper limit of traffic variation, and the burst monitoring comparison module outputs a preset data consumption rate v0 (preconfigured through a register). The burst monitoring module can compare the burst according to multiple waterline thresholds, for example: 80% depth waterline outputs v0, and 90% waterline outputs v1.

[0104] For example, continue to illustrate based on the above configuration, for example: when the depth usage of the buffer module reaches 24, if the minimum depth value of the previous 8 cycles is less than or equal to 20 (i.e. the difference from 24 is 4), the burst monitoring comparison module outputs a preset data consumption rate (to control the depth consumption of the downstream to be 0.5 KB per cycle for a short time), and further improves the priority of the channel B in arbitration. In the case of mild regulation, the burst traffic may cause the free space of the buffer to be depleted for a short time, and the back pressure of the upstream may occur. The output of the burst monitoring comparison module can avoid the occurrence of the above condition.

[0105] In some embodiments, the depth statistics comparison module 304 is configured to output a tolerance control value, which is used to adjust the threshold value for triggering the adjustment means for the cache module. The observation depth of the depth statistics comparison module is configured as TH1, the monitoring time window is T0, the tolerance threshold value is V0 (the third time length threshold value described above), and the basic output value is A1. The cache usage is monitored every T0 time period, and the total time length V1 (the first time length described above) of the depth usage exceeding TH1 in the T0 time period is obtained. The depth usage exceeding TH1 is also the second state described above. The monitoring result V1 and the time length tolerance threshold value V0 are compared. If the comparison result is that V1 is greater than V0, the tolerance control value is increased by 1. In the initial state, the tolerance control value = 0. If the comparison result is that V1 is less than V0 and the tolerance control value is not 0, the tolerance control value is decreased by 1. The minimum tolerance control value = 0. The output value (value2) of the depth statistics comparison module 304 is the sum of the basic output value A1 and the tolerance control value.

[0106] For example, based on the above configuration, it is further illustrated that, for example, when the proportion of the depth exceeding 16 is greater than or equal to 50% in 32 periods, the trigger condition of the cache depth statistics comparison module is reached, and the priority of the channel B participating in arbitration is further improved. The setting condition here is based on the bandwidth demand and the preset upper limit of the delay. When the proportion of the depth exceeding 16 is greater than 50%, it is determined that the channel continuously undertakes a high-load task, and the original control intensity is not enough. At this time, the control intensity needs to be increased, and more bandwidth is obtained for the channel.

[0107] In the embodiments of the present application, based on the monitoring result of the last period and the set tolerance, it is determined whether the original control intensity can meet the design expectation. The simple monitoring logic and the tolerance comparison mechanism are used to realize the dynamic adaptive control of the channel behavior with small logic resources.

[0108] In some embodiments, a cache depth high threshold value TH2 and a preset time upper limit of N periods are set for the depth monitoring comparison module 305. When the cache usage depth is greater than TH2 for continuous N periods, the sum of the output values of the above three modules is selected. When the cache usage depth is less than TH2 for continuous N periods, the output value of the priority statistics comparison module (the highest priority) is selected.

[0109] For example, based on the above configuration, continue to illustrate, for example: when the depth usage is greater than or equal to the data amount threshold 16 for 4 consecutive periods (preset time threshold), the buffer monitoring module triggers the regulation condition, and starts to improve the priority of channel B participating in arbitration; that is, when the depth usage continuously reaches 16, it is necessary to improve the downstream priority to effectively alleviate the congestion. When the depth of the buffer does not reach 16 for 4 consecutive periods, the depth monitoring comparison module 305 determines that the current congestion is not serious, and outputs the select value = 0. The buffer monitoring module 300 selects the maximum priority value0 in the output value of the buffer transaction of the output priority statistical comparison module 302; when the depth of the buffer reaches 16 for 4 consecutive periods, the depth monitoring comparison module 305 determines that the current congestion is serious, and outputs the select value = 1. The selection module 307 outputs the value3 output by the summation module 306.

[0110] The judgment of the embodiment of the application does not depend on the state at a moment, but is based on the state of N consecutive period periods, and the advantage is that it is more smooth to intervene in dynamic flow, and it will not frequently intervene, and the buffer space can be fully utilized. The regulation means of the embodiment of the application is based on the existing transaction priority in the buffer area as a benchmark to adjust, which is more matched with the priority strategy of the whole system, and will not affect the priority strategy of the whole system because of local regulation. For example: the priority strategy of the whole system is: 0-2 is low priority, 3-5 is medium priority, and 6-7 is high priority; at a moment, three channels are competing, the highest priority of the channel A buffer transaction is 2, the priority of the channel B buffer transaction is 3, and the priority of the channel C buffer transaction is 6, when the channel A buffer usage depth exceeds the set tolerance threshold, the channel QoS is adjusted to 3 to participate in the competition. At this time, the highest priority transaction of channel C = 6 still enjoys the absolute bandwidth allocation right, and channel A can share the remaining bandwidth allocation with channel B after adjustment, if the priority of the transaction of channel B is 4, the above adjustment still ensures that the priority = 4 transaction of channel B can be more easily obtained than channel A.

[0111] In some embodiments, when the cache amount of the cache module reaches 100%, the upstream circuit inputs value5 to the maximum value module 308, the maximum value module 308 is used to compare value4 output by the selection module 307 and value5 input by the upstream circuit, and the maximum of the two is output as the result (urgency out). When there is no value5 input by the upstream circuit, the maximum value module 308 outputs value4 output by the selection module 307. For example: if the depth of the cache module reaches 100%, that is, there is back pressure on the upstream, the high priority information of the upstream is input to the maximum value module through the urgency_in interface, the maximum value module compares the high priority information of the upstream and the output value (value4 can be value0 or value3) of the selection module, which is expressed as formula max(value5, value4). The above processing can consider that there may be higher priority transactions of the upstream being back-pressed, and also consider the regulation output of the cache module, so as to improve the data processing efficiency.

[0112] In the embodiments of the application, without relying on the instantaneous state, it can be judged whether the buffer depth exceeds the threshold due to continuous pressure or temporary fluctuation through the preset time, so as to effectively avoid frequent priority adjustment; in essence, a data flow anti-jitter mechanism is added in the priority adjustment, so that it is more suitable for processing data flow scenarios with fluctuation. The embodiments of the application evaluate whether the original means is reasonable based on the statistical results of the last period, adaptively and dynamically adjust the intervention intensity, and are more suitable for complex dynamic flow of multi-channel systems; the depth of the buffer is fully utilized to avoid that a single adjustment scheme spreads the congestion to other units in the network on chip. Based on the burst characteristics of the channel flow and the tolerance of the upstream to back pressure, the regulation intensity is timely and in advance, so that the priority can be quickly adjusted in real time according to the change rate of the buffer depth of each channel, the dynamic change of the data flow is adapted, and the response ability of the system to dynamic flow load is improved.

[0113] In still another embodiment of the application, the application provides a chip, which can include the data processing apparatus in any one of the foregoing embodiments, or the data processing method as described in any one of the foregoing embodiments.

[0114] In still another embodiment of the application, the application provides an electronic device, which includes a processor, wherein the processor includes the data processing apparatus in any one of the foregoing embodiments, or the data processing method as described in any one of the foregoing embodiments.

[0115] In summary, the foregoing embodiments are described in detail through the foregoing embodiments, and it can be seen that, through the technical solutions of the foregoing embodiments, the cache monitoring module monitors different parameters of the cache module respectively, and generates corresponding parameters for adjusting the cache module according to the monitored parameters, including but not limited to the highest priority of data processing, the preset data consumption speed, and the adjustment value of the data volume threshold. At the same time, the cache monitoring module is also used to determine that the data volume in the cache module is in a first state greater than a second data volume threshold. The first state can represent whether the cache module is in a state of storing more resources for a long time. According to whether the duration of the first state is greater than a preset duration threshold, it is determined whether to apply the highest priority of data processing, the preset data consumption speed, and the adjustment value of the data volume threshold to data processing to relieve data congestion of the cache module upstream and downstream. The highest priority is output to the downstream in each case, which can optimize local congestion without damaging the global priority strategy. Whether to adjust the preset data consumption speed and the adjustment value of the data volume threshold does not depend on the instantaneous value, but is judged according to the continuous duration of the first state, which can filter out temporary fluctuations and avoid misjudgment. It can improve the data processing efficiency of the cache module upstream and downstream, while properly controlling the data volume in the cache module, avoiding overflow of the cache module, data congestion upstream of the cache module, or lack of data to be processed downstream of the cache module, and improving the adaptability of the network on a chip.

[0116] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed in the present application can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solutions. Professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0117] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the apparatus and unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0118] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other manners. For example, the described apparatus embodiments are merely schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, can be indirect couplings or communication connections through some interfaces, and can be in electrical, mechanical or other forms.

[0119] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0120] In addition, each functional unit in the various embodiments of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium.

[0121] It should be noted that in the present application, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or further include elements inherent in such processes, methods, articles or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0122] The serial numbers of the above embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0123] The methods disclosed in several method embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments.

[0124] The features disclosed in several product embodiments provided by the present application can be combined arbitrarily without conflict to obtain new product embodiments.

[0125] The features disclosed in several method or device embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method or device embodiments.

[0126] The above descriptions are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

Claims

1. A data processing apparatus, characterized by, The device comprises a cache module, a cache monitoring module and an arbitration module, wherein, the cache module is configured to cache data; the cache monitoring module is configured to determine the highest priority of data of different events in the cache module, wherein the highest priority is the priority of data processing; the cache monitoring module is further configured to determine a preset data consumption speed of the cache module according to a data variation amount in a first preset time period in the cache module, wherein the first preset time period is the total time period of a plurality of clock periods before the current time; the cache monitoring module is further configured to determine an adjustment value of a second data amount threshold of the cache module according to a first time period during which the data amount in the cache module is greater than a first data amount threshold, wherein the first data amount threshold is equal to an initial second data amount threshold, and the initial second data amount threshold is half of the total data storage amount of the cache module; the cache monitoring module is further configured to take the highest priority as an output result when the data amount in the cache module is in a first state greater than a second data amount threshold and the continuous time period of the first state is less than a first time period threshold, wherein the first time period threshold is less than the first preset time period; the cache monitoring module is further configured to take the highest priority, the preset data consumption speed and the adjustment value as the output result when the data amount in the cache module is in a first state greater than a second data amount threshold and the continuous time period of the first state is greater than a first time period threshold; the arbitration module is configured to perform data processing according to the output result.

2. The apparatus of claim 1, wherein, The cache monitoring module is further configured to count the number of data of different events stored in the cache module; determine a priority adjustment value of different events according to the number of each event, wherein the priority adjustment value is positively correlated with the number of the event; add the priority adjustment value and the preset priority of the corresponding event to obtain the actual priority of each event, and select the highest priority in the actual priority.

3. The apparatus of claim 1, wherein, The cache monitoring module is further configured to obtain a first data amount at a plurality of first time periods in the first preset time period before the current time, wherein adjacent first time periods are separated by at least one clock period; when the current data amount at the current time is greater than a third data amount threshold, take the difference between the current data amount and the smallest first data amount as the data variation amount, wherein the third data amount threshold is greater than the first data amount threshold and the second data amount threshold; when the data variation amount is greater than a data variation amount threshold, determine a preset data consumption speed according to a preset mapping relationship between the third data amount threshold and the consumption speed, wherein the data variation amount threshold is less than the difference between the third data amount threshold and the first data amount threshold.

4. The apparatus of claim 3, wherein, The cache monitoring module further comprises a plurality of counters, wherein one counter is configured to store a first data amount at one first time period; When the number of the stored first data amounts equals the number of the counters, the first data amount newly acquired is used to replace the first data amount stored in a target counter, wherein the target counter is the counter with the earliest first time corresponding to the stored first data amount in the plurality of counters.

5. The apparatus of claim 1, wherein, The cache monitoring module is further configured to acquire a first data amount of the cache module within a second preset time period before a current time, wherein the second preset time period is longer than the first preset time period. The first time period of the second state within the second preset time period is determined, wherein the second state is a state in which the first data amount is greater than the first data amount threshold. When the first time period is greater than a third time period threshold, a first preset value is used as the adjustment value. When the first time period is less than the third time period threshold, a second preset value is used as the adjustment value, wherein the second preset value is less than the first preset value.

6. The apparatus of claim 5, wherein, The cache monitoring module is further configured to, in response to the first data amount being less than the first data amount threshold before a second time and the first data amount being greater than the first data amount threshold after the second time, use the second time as a starting time. In response to the first data amount being greater than the first data amount threshold before a third time and the first data amount being less than the first data amount threshold after the third time, the third time is used as an ending time, wherein the third time is after the second time. The time period between the starting time and the ending time is used as the statistical time period of the second state. Each statistical time period corresponding to the second preset time period is added to obtain the first time period.

7. The device of any one of claims 1 to 6, wherein, When there are a plurality of cache modules, the arbitration module is further configured to determine a target cache module according to output results respectively corresponding to different cache modules, wherein the data stored in the target cache module is output to a downstream data processing unit.

8. The device of any one of claims 1 to 6, wherein, The cache monitoring module is further configured to determine a first priority of data to be stored in the cache module when the amount of data cached in the cache module equals the total amount of data cached in the cache module. In response to the first priority being greater than a second priority of data stored in the cache module, the second priority is used as an output result.

9. A data processing method, characterized by, The data processing method is implemented based on the data processing device of any one of claims 1 to 8, and the method comprises: caching data by a cache module; determining a highest priority of data of different events in the cache module; determining a preset data consumption speed of the cache module according to a data variation amount within a first preset time period in the cache module, wherein the first preset time period is a total time period of a plurality of clock periods before a current time; determining an adjustment value of a second data amount threshold of the cache module according to a first time period in which a data amount in the cache module is greater than a first data amount threshold, wherein the first data amount threshold is equal to an initial second data amount threshold, and the initial second data amount threshold is half of a total data storage amount of the cache module; and determining an adjustment value of a second data amount threshold of the cache module according to a first time period in which a data amount in the cache module is greater than a first data amount threshold, wherein the first data amount threshold is equal to an initial second data amount threshold, and the initial second data amount threshold is half of a total data storage amount of the cache module. when the data amount in the cache module is in a first state greater than a second data amount threshold, and a continuous time length of the first state is less than a first time length threshold, taking the highest priority as the output result, wherein the first time length threshold is less than the first preset time length; when the data amount in the cache module is in a first state greater than a second data amount threshold, and a continuous time length of the first state is greater than a first time length threshold, taking the highest priority, the preset data consumption speed and the adjustment value as the output result; performing data processing according to the output result.

10. A chip, characterized by The chip comprises the data processing device according to any one of claims 1 to 8.

11. An electronic device, comprising: The electronic device comprises a processor, wherein the processor comprises the data processing device according to any one of claims 1 to 8. Or a memory for storing computer executable instructions or computer programs; a processor for implementing the data processing method of claim 9 when executing the computer executable instructions or computer programs stored in the memory.

12. A computer-readable storage medium storing computer-executable instructions or a computer program, characterized in that, The computer executable instructions or computer programs are executed by the processor to implement the data processing method of claim 9.

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