Layout design method for low parasitic inductance structure in SiC power module

Abstract

The invention discloses a low parasitic inductance structure layout design method in a SiC power module, and relates to the technical field of electronic structure design, and the method comprises the steps: S11, constructing an initial power loop structure and a gate driving loop structure of a plurality of parallel power devices in the SiC power module, the power loop structure is a parallel symmetric path structure from a power pin to a busbar, and the gate driving loop structure is a gate driving loop structure; the gate pole driving loop structure is an independent path structure with the same length from a gate pole pin to a driving board terminal, and the power loop structure and the gate pole driving loop structure are both arranged in a double-layer copper bar structure which is symmetrical up and down; s12, on the basis of the geometric arrangement relation between the power loop structure and the gate drive loop structure, calculating parasitic inductance values and mutual inductance coupling values between loops, and constructing a mutual inductance coupling matrix; according to the invention, by constructing the symmetrical power loop structure and the gate drive loop structure, the structure level balance of the parasitic inductance and the synchronous suppression of the peak voltage in the SiC power module are realized.

Description

Technical Field

[0001] This invention relates to the field of electronic structure design technology, specifically to a method for designing a low parasitic inductance structure layout in a SiC power module. Background Technology

[0002] In power electronic conversion equipment, SiC power modules are widely used in new energy, rail transportation, power electronics, and other fields due to their ability to operate at high voltage, high frequency, and high temperature. SiC power modules typically employ a topology of multiple parallel power devices working together in their packaging structure, and current conduction and gate control are accomplished through physical structures such as upper and lower copper busbars, busbars, and power terminals. Internally, the power loop structure from the power pins to the busbar, and the gate drive loop structure from the gate pins to the driver board terminals, are the critical paths affecting the device's operational stability and switching losses.

[0003] In existing design methods, some power module packaging schemes have begun to adopt a top-to-bottom symmetrical copper busbar structure and symmetrical path arrangement, which can reduce the overall parasitic inductance to a certain extent. In addition, some gate drive paths also adopt equal length matching and independent wiring methods to reduce gate signal misalignment caused by path differences.

[0004] However, due to the lack of a joint assessment of the magnetic coupling behavior between the power circuit structure and the gate drive circuit structure, local magnetic flux abrupt changes and coupling strength anomalies may still occur in some paths, resulting in uneven current distribution among parallel power devices.

[0005] Meanwhile, the peak voltage in the gate path cannot be effectively suppressed during the structural design stage, and it relies solely on the absorption of the back-end circuit devices, resulting in problems such as response lag and residual path coupling. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a method for designing a low parasitic inductance structure layout in a SiC power module, the method comprising:

[0007] S11, Construct the initial power circuit structure and gate drive circuit structure of multiple parallel power devices in the SiC power module. The power circuit structure is a parallel symmetrical path structure from the power pin to the busbar, and the gate drive circuit structure is an independent path structure of the same length from the gate pin to the driver board terminal. Both the power circuit structure and the gate drive circuit structure are set in a double-layer copper busbar structure with upper and lower symmetry.

[0008] S12, based on the geometric arrangement relationship between the power circuit structure and the gate drive circuit structure, calculate the parasitic inductance value and mutual inductance coupling value between each circuit, and construct a mutual inductance coupling matrix. Each element of the mutual inductance coupling matrix corresponds to the magnetic coupling strength between any two circuit paths.

[0009] S13. Based on the maximum mutual inductance difference in each row of the mutual inductance coupling matrix, identify the structural location where there is abrupt boundary between the circuits. Use the abrupt boundary location as the target area for local inductance structure adjustment. Construct a longitudinal magnetic flux guiding groove structure and insert it into the gap layer between the upper and lower copper busbars. The longitudinal magnetic flux guiding groove structure is used to locally suppress the magnetic coupling strength at the abrupt location.

[0010] Furthermore, the steps for constructing the power circuit structure and the gate drive circuit structure are as follows:

[0011] S111 arranges the parallel path between the power pin and the busbar according to the symmetrical geometric position, and forms a symmetrical path of equivalent length in the upper and lower copper busbars;

[0012] S112, arrange the lead-out paths between the gate pins and the driver board terminals of equal length independently, and maintain equivalent geometric positions within the upper and lower copper busbars;

[0013] S113, a gap layer is set between the upper and lower copper busbars to separate the power circuit structure from the gate drive circuit structure.

[0014] Furthermore, the steps for calculating the parasitic inductance and mutual inductance coupling values ​​between each loop, and constructing the mutual inductance coupling matrix are as follows:

[0015] S121, based on the geometric parameters of the power circuit structure and the gate drive circuit structure, extract the equivalent self-inductance value of each path;

[0016] S122, Calculate the mutual inductance value between two paths based on the spatial distribution relationship between paths;

[0017] S123 combines the self-inductance value with the mutual inductance value to generate a mutual inductance coupling matrix.

[0018] Furthermore, the steps for identifying the structural locations where abrupt boundary changes exist between circuits are as follows:

[0019] S131, extract the mutual inductance value corresponding to each row in the mutual inductance coupling matrix;

[0020] S132, perform a difference operation on adjacent mutual inductance values ​​in the same row, and select the value with the largest difference as the maximum mutual inductance difference of the row.

[0021] S133, based on the distribution results of the maximum mutual inductance difference, locates the structural locations where abrupt change boundaries exist.

[0022] Furthermore, the method also includes:

[0023] S14. Based on the three-dimensional power circuit model and gate drive circuit model after inserting the flux guide slot structure, perform transient current distribution simulation and gate flyback peak voltage simulation. The transient current distribution simulation is used to determine whether the current difference of each parallel device is less than the current balancing threshold value. The gate flyback peak voltage simulation is used to determine whether the gate flyback voltage is less than the set voltage protection threshold.

[0024] S15, when the transient current difference is less than the current balancing threshold and the gate flyback voltage is less than the voltage protection threshold, a symmetrical bleed resistor structure is inserted in each gate lead-out path. The bleed resistor structure forms a symmetrical connection between the gate output terminals of the upper and lower copper busbars to suppress the remaining reverse induction spikes in the gate path and solidify the final low parasitic inductance structure layout.

[0025] Furthermore, the steps for performing gate flyback spike voltage simulation are as follows:

[0026] S144, Establish a three-dimensional gate drive circuit model including a longitudinal flux guide slot structure;

[0027] S142, perform time-domain simulation of the current distribution of each parallel device;

[0028] S143, calculate the current difference between parallel devices and compare it with the current balance threshold.

[0029] Furthermore, the steps for performing gate flyback spike voltage simulation are as follows:

[0030] S144, Establish a three-dimensional gate drive circuit model including a longitudinal flux guide slot structure;

[0031] S145 performs transient voltage simulation of the gate turn-on and turn-off processes;

[0032] S146: Extract the gate flyback voltage value and compare it with the voltage protection threshold.

[0033] Furthermore, the step of inserting a symmetrical bleeder resistor structure in each gate lead-out path is as follows:

[0034] S151, discharge resistors are arranged between the gate output terminals of the upper and lower copper busbars respectively;

[0035] S152, the bleeder resistors are connected in parallel in a symmetrical manner to insert a symmetrical bleeder resistor path structure.

[0036] Furthermore, the suppression logic of the symmetrical bleeder resistor structure is as follows:

[0037] S153, when there is a residual reverse induced spike in the gate path, the bleeder resistor structure absorbs the spike voltage.

[0038] S154, after the peak voltage is discharged to the set attenuation range, maintains the voltage stability of the gate lead-out path;

[0039] S155 incorporates the bleed resistor structure as part of the final fixed layout to form a low parasitic inductance structure layout.

[0040] Furthermore, the steps for solidifying the final low parasitic inductance structure layout are as follows:

[0041] S157 preserves the three-dimensional layout including the power circuit structure, the gate drive circuit structure, the longitudinal flux guide slot structure and the symmetrical discharge resistor structure.

[0042] S158 uses the solidified layout diagram as the basis for power module production, so as to realize the final implementation of the low parasitic inductance structure.

[0043] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0044] This invention constructs a symmetrical layout of upper and lower copper busbars in the power circuit structure and the gate drive circuit structure, identifies the location of abrupt boundary structures based on the mutual inductance coupling matrix, and inserts a longitudinal magnetic flux guiding slot structure to weaken the local magnetic coupling strength, thereby balancing the magnetic flux distribution of each parallel power device in the current transmission path; thus, it achieves consistency in the current change trend of each path in terms of transient current distribution values, thereby improving the parallel current balancing capability and path stability during switching; thus, it enhances the current shunting control effect of the power module under high-frequency operating conditions.

[0045] Furthermore, this invention also detects the difference between the gate flyback voltage and the voltage protection threshold in the gate drive circuit structure, inserts a symmetrical bleeder resistor structure to absorb the residual reverse induction spikes in the gate path, and constructs an electrically symmetrical voltage attenuation path structure. This achieves rapid suppression of abnormal voltage in gate signal transmission, thereby improving the stability of the gate signal and the anti-interference reliability of the gate driver, and thus improving the voltage fluctuation control capability in the switching device control process.

[0046] Furthermore, this invention integrates the power circuit structure, gate drive circuit structure, longitudinal flux guide slot structure, and symmetrical discharge resistor structure into a unified three-dimensional layout, and solidifies it into a low parasitic inductance structure layout diagram, which serves as the production layout basis for the mass production process. This achieves integrated control of electrical structure, electromagnetic distribution, and manufacturing implementation while ensuring processing consistency.

[0047] In summary, this invention achieves structural-level equalization of parasitic inductance and synchronous suppression of peak voltage in SiC power modules by constructing a symmetrical power circuit structure and a gate drive circuit structure, and by introducing magnetic coupling suppression and voltage absorption mechanisms. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0049] Figure 1 The first flowchart of a low parasitic inductance structure layout design method in a SiC power module provided by the present invention;

[0050] Figure 2 This is a second flowchart of a low parasitic inductance structure layout design method for a SiC power module provided by the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] Please see Figure 1 As shown in the figure, this embodiment discloses a method for designing a low parasitic inductance structure layout in a SiC power module, the method comprising:

[0053] S11, Construct the initial power circuit structure and gate drive circuit structure of multiple parallel power devices in the SiC power module. The power circuit structure is a parallel symmetrical path structure from the power pin to the busbar, and the gate drive circuit structure is an independent path structure of the same length from the gate pin to the driver board terminal. Both the power circuit structure and the gate drive circuit structure are set in a double-layer copper busbar structure with upper and lower symmetry.

[0054] Specifically, the steps for constructing the power circuit structure and the gate drive circuit structure are as follows:

[0055] S111 arranges the parallel path between the power pin and the busbar according to the symmetrical geometric position, and forms a symmetrical path of equivalent length in the upper and lower copper busbars;

[0056] It should be noted that the paths between the power pins and the busbar are arranged in parallel, and each path is mirror-symmetrical with respect to the central reference axis in both the horizontal and vertical directions. By keeping the path length and width consistent, the inductance difference between each path is reduced, and uneven current distribution of parallel devices is avoided.

[0057] S112, arrange the lead-out paths between the gate pins and the driver board terminals of equal length independently, and maintain equivalent geometric positions within the upper and lower copper busbars;

[0058] Specifically, each path from the gate pin to the driver board terminal is kept to be of strictly equal length to eliminate signal transmission delay; independent physical spacing is maintained between paths to reduce unnecessary electromagnetic coupling; this equal-length independent arrangement ensures that the parallel power devices are synchronously triggered at the moment of switching, thereby suppressing voltage spikes and oscillations caused by time offset.

[0059] S113, a gap layer is set between the upper and lower copper busbars to separate the power circuit structure from the gate drive circuit structure.

[0060] It should be noted that the gap layer is an insulating medium, and its thickness is determined according to the electrical safety clearance and machining tolerances. This gap layer not only achieves electrical isolation between the power circuit and the gate circuit, but also weakens the magnetic coupling between the two through the physical height difference. In implementation, epoxy resin, polyimide film or other high dielectric strength materials can be used as the filler layer.

[0061] S12, based on the geometric arrangement relationship between the power circuit structure and the gate drive circuit structure, calculate the parasitic inductance value and mutual inductance coupling value between each circuit, and construct a mutual inductance coupling matrix. Each element of the mutual inductance coupling matrix corresponds to the magnetic coupling strength between any two circuit paths.

[0062] It should be noted that the "geometric arrangement relationship" mentioned in this step includes parameters such as the length, width, thickness, number and position of corners, inter-layer height difference, horizontal spacing, overlap length, and current direction calibration of each loop path. To ensure engineering consistency in the calculation, a reference return path must first be determined for each path (e.g., the power loop forms a closed loop with the positive / negative terminals of the DC bus, and the gate loop forms a closed loop with the gate / source terminals to the driver board terminals), and then the path parameters are extracted under this closed definition. To ensure the symmetry of self / mutual inductance, after the path numbering is fixed, the mutual inductance calculation satisfies the commutative law.

[0063] Specifically, the steps for calculating the parasitic inductance and mutual inductance coupling values ​​between each loop, and constructing the mutual inductance coupling matrix are as follows:

[0064] S121, based on the geometric parameters of the power circuit structure and the gate drive circuit structure, extract the equivalent self-inductance value of each path;

[0065] Specifically, the equivalent self-inductance value of each path is estimated based on the path length, equivalent conductor width and thickness, and the height relationship between the layer it is in and the adjacent reference plane.

[0066] For flat copper strip paths that are mainly composed of straight segments, the strip approximation or equivalent partial element method can be used to discretize and sum the paths to obtain the equivalent self-inductance value.

[0067] This can be understood as follows: when the geometric dimensions of the path (length is significantly greater than width and thickness) satisfy the strip approximation, the self-inductance value mainly increases with the increase of the effective path length and decreases with the increase of the equivalent width and thickness; when the path crosses layers or is close to the reference plane, the equivalent height relationship will further affect the self-inductance.

[0068] When a formulaic expression is required, the strip approximation formula can be used:

[0069]

[0070] In the formula, For the first The self-inductance value of the path, For path length, For equivalent width, For thickness, The air permeability constant, These are empirical coefficients related to the cross-sectional shape and the conditions of the adjacent reference surface;

[0071] It should be noted that: In engineering applications, the equivalent inductance can be determined by simulation or fitting of a calibration prototype. When the path needs to be divided into multiple segments, the equivalent inductance of the entire path is obtained by summing the self-inductance of each segment and considering corner corrections. The input parameters extracted from the inductance are derived from the geometric arrangement that has been solidified in step S11. If there are structures such as holes, corners, or local widening / thickening, they are calculated and superimposed separately in a discrete segment manner.

[0072] S122, Calculate the mutual inductance value between two paths based on the spatial distribution relationship between paths;

[0073] The mutual inductance is calculated by considering the horizontal spacing between the two paths, the overlap length, the height difference between the layers, and the current direction. When the paths are parallel and on the same layer, the mutual inductance is greater. When the paths cross layers or the spacing increases, the mutual inductance decreases. When the current directions are opposite, the mutual inductance is negative.

[0074] The formula for calculating mutual inductance is as follows:

[0075]

[0076] In the formula, For the first The path and the first The mutual inductance value of the path, , For the first The path and the first The self-inductance value of the path, The coupling coefficient is... ;

[0077] It should be noted that: Determined through three-dimensional electromagnetic simulation or experimental fitting;

[0078] S123, combine the self-inductance value with the mutual inductance value to generate a mutual inductance coupling matrix;

[0079] Based on the path numbering order, place the self-inductance values ​​of each path in the diagonal elements of the matrix, and place the mutual inductance values ​​between paths in the corresponding off-diagonal elements to generate a mutual inductance coupling matrix.

[0080] Represented as:

[0081]

[0082] In the formula, It is the mutual inductance coupling matrix.

[0083] S13. Based on the maximum mutual inductance difference in each row of the mutual inductance coupling matrix, identify the structural location where there is abrupt boundary between the circuits. Use the abrupt boundary location as the target area for local inductance structure adjustment. Construct a longitudinal magnetic flux guiding groove structure and insert it into the gap layer between the upper and lower copper busbars. The longitudinal magnetic flux guiding groove structure is used to locally suppress the magnetic coupling strength at the abrupt location.

[0084] Specifically, the steps for identifying the structural locations where abrupt boundary changes exist between circuits are as follows:

[0085] S131, extract the mutual inductance value corresponding to each row in the mutual inductance coupling matrix;

[0086] It should be noted that the mutual inductance coupling matrix consists of self-inductance value and mutual inductance value. The mutual inductance value of each row represents the magnetic coupling strength between that path and the other paths.

[0087] By reading the mutual inductance values ​​line by line, the coupling distribution characteristics between each path and other paths can be established. The extraction process directly depends on the mutual inductance coupling matrix generated by S123, without the need to repeatedly calculate the self-inductance values.

[0088] S132, perform a difference operation on adjacent mutual inductance values ​​in the same row, and select the value with the largest difference as the maximum mutual inductance difference of the row.

[0089] It should be noted that the maximum mutual inductance difference reflects the degree of flux imbalance of a path under different coupled objects; a larger value indicates that the path has abrupt coupling in space. The maximum mutual inductance difference can be used to preliminarily identify potential abrupt boundary regions.

[0090] S133, based on the distribution results of the maximum mutual inductance difference, locates the structural location where abrupt boundary exists;

[0091] It should be noted that: by comparing the maximum mutual inductance difference of all paths, the locations where the concentration of the difference is significantly higher than that of other paths are marked as mutation boundaries;

[0092] This positioning process is reflected in the mutual inductance coupling matrix as abnormal peak points of single-row differences;

[0093] After positioning, the location of this structure is used as the target area for local inductance structure adjustment, and a longitudinal magnetic flux guiding groove structure is inserted in the gap layer to weaken the magnetic coupling strength at the abrupt change point.

[0094] S14. Based on the three-dimensional power circuit model and gate drive circuit model after inserting the flux guide slot structure, perform transient current distribution simulation and gate flyback peak voltage simulation. The transient current distribution simulation is used to determine whether the current difference of each parallel device is less than the current balancing threshold value. The gate flyback peak voltage simulation is used to determine whether the gate flyback voltage is less than the set voltage protection threshold.

[0095] Specifically, the steps for performing transient current distribution simulation are as follows:

[0096] S141, Establish a three-dimensional power loop model including a longitudinal flux guide slot structure;

[0097] It should be noted that the three-dimensional power loop model includes the parallel symmetrical path structure from the power pins to the busbar, the double-layer symmetrical arrangement of the upper and lower copper busbars, and the longitudinal flux guiding slot structure inserted in the gap layer. This model fully reflects the power loop geometric arrangement and abrupt boundary adjustments determined in steps S11 to S13.

[0098] S142, perform time-domain simulation of the current distribution of each parallel device;

[0099] Specifically, the DC bus power supply excitation voltage is applied to the three-dimensional power loop model. Mutual inductance coupling matrix The change of current in each parallel power device over time is calculated to obtain the transient current distribution value;

[0100] Represented as:

[0101]

[0102] Let be the transient current distribution value for each parallel power device, where , For the first The transient current distribution values ​​of parallel power devices, The independent variable representing the integral is time;

[0103] This is the distribution vector of the DC bus power supply excitation voltage values ​​on each path;

[0104] For example, if each parallel path is directly connected to both ends of the busbar (typical symmetrical layout), then each path receives the same excitation, and the allocation vector on each path is represented as:

[0105]

[0106] All assignment vectors are equal to 1. If some paths in the design are connected differently due to pin configurations, for example, only some paths are connected to a voltage source, then... The corresponding allocation vector is 0 or a value between 0 and 1;

[0107] This is the initial moment. At that time, the current distribution values ​​of each parallel power device, simply put, are the initial currents of each parallel path;

[0108] It should be noted that the simulation curves generated through time-domain simulation can intuitively reflect the degree of current balance among the parallel paths.

[0109] S143, calculate the current difference between parallel devices and compare it with the current balance threshold;

[0110] It should be noted that the current difference is the difference between the maximum device current value and the minimum device current value.

[0111] When the current difference is less than the current equalization threshold, the current distribution is deemed to meet the equalization requirements; if the current difference exceeds the threshold, the geometry or dimensions of the longitudinal flux guide slot structure need to be re-optimized.

[0112] Specifically, the steps for performing gate flyback spike voltage simulation are as follows:

[0113] S144, Establish a three-dimensional gate drive circuit model including a longitudinal flux guide slot structure;

[0114] It should be noted that the three-dimensional gate drive circuit model includes an independent equal-length path structure from the gate pin to the driver board terminal, gate lead-out paths arranged in the upper and lower copper busbars, and a longitudinal magnetic flux guiding slot structure inserted in the gap layer, thereby ensuring electrical isolation and magnetic coupling constraint with the power circuit model in the same spatial arrangement.

[0115] S145 performs transient voltage simulation of the gate turn-on and turn-off processes;

[0116] Specifically, a gate drive signal is loaded into a three-dimensional gate drive circuit model, the transient voltage values ​​of the gate pin during the turn-on and turn-off processes are calculated, and the voltage waveform curve containing the flyback spike is extracted.

[0117] S146, extract the gate flyback voltage value and compare it with the voltage protection threshold;

[0118] It should be noted that: the maximum gate flyback voltage value is extracted from the transient voltage waveform. When the gate flyback voltage value is less than the voltage protection threshold, the gate drive circuit is determined to meet the voltage protection requirements.

[0119] If the gate flyback voltage is greater than the voltage protection threshold, a symmetrical bleeder resistor structure needs to be added in subsequent steps to suppress the remaining spikes.

[0120] S15, when the transient current difference is less than the current balancing threshold and the gate flyback voltage is less than the voltage protection threshold, a symmetrical discharge resistor structure is inserted in each gate lead-out path. The discharge resistor structure forms a symmetrical connection between the gate output terminals of the upper and lower copper busbars to suppress the remaining reverse induction spikes in the gate path and solidify the final low parasitic inductance structure layout.

[0121] Specifically, the steps for inserting a symmetrical bleeder resistor structure in each gate lead-out path are as follows:

[0122] S151, discharge resistors are arranged between the gate output terminals of the upper and lower copper busbars respectively;

[0123] It should be noted that the range of values ​​for the bleed resistor is determined based on the gate drive current and the allowable power loss. The resistor should be installed close to the gate output terminal to reduce the introduction of additional parasitic inductance.

[0124] S152, connect the bleeder resistors in parallel in a symmetrical manner to insert a symmetrical bleeder resistor path structure.

[0125] Specifically, the bleeder resistors are arranged in pairs at symmetrical positions on the upper and lower copper busbars, and the parallel connection ensures the consistency of the resistance of the two paths.

[0126] This symmetrical path structure can maintain electrical and geometric balance, thereby ensuring that peak voltages are absorbed simultaneously.

[0127] Specifically, the suppression logic of the symmetrical bleeder resistor structure is as follows:

[0128] S153, when there is a residual reverse induced spike in the gate path, the bleeder resistor structure absorbs the spike voltage.

[0129] It should be noted that the bleed resistor reduces the peak voltage amplitude by converting peak energy into heat, thus preventing the peak from oscillating repeatedly in the gate drive path.

[0130] S154, after the peak voltage is discharged to the set attenuation range, maintains the voltage stability of the gate lead-out path;

[0131] Specifically, the attenuation range is determined by the gate driver's safe operating voltage, typically within 10% of the rated gate voltage;

[0132] S155 incorporates the bleed resistor structure as part of the final fixed layout to form a low parasitic inductance structure layout.

[0133] It should be noted that when the bleed resistor structure meets the peak suppression requirements, its geometric and electrical positions are fixed, and it is solidified together with the power circuit structure, the gate drive circuit structure and the longitudinal flux guide slot structure in the three-dimensional layout.

[0134] Specifically, the steps for solidifying the final low parasitic inductance structure layout are as follows:

[0135] S157 preserves the three-dimensional layout including the power circuit structure, the gate drive circuit structure, the longitudinal flux guide slot structure and the symmetrical discharge resistor structure.

[0136] It should be noted that the saved 3D layout can be directly exported as a manufacturing process file, ensuring consistency between electrical design and machining data.

[0137] S158 uses the solidified layout diagram as the basis for power module production, so as to realize the final implementation of the low parasitic inductance structure.

[0138] Specifically, the production process uses a fixed layout diagram as a standard to cut copper busbars, fill insulation layers, and weld bleed resistors, thereby ensuring that the inductance parameters of each module are consistent during mass production.

[0139] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired or wireless network. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0140] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only one method, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0141] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0142] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0143] Some of the data in the above formula are calculated by removing dimensions and taking their numerical values. The formula is the closest to the real situation obtained by software simulation of a large amount of collected data. The preset parameters and preset thresholds in the formula are set by those skilled in the art according to the actual situation or obtained through simulation of a large amount of data.

[0144] The above embodiments are only used to illustrate the technical methods of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical methods of the present invention without departing from the spirit and scope of the technical methods of the present invention.

Claims

1. A method for designing a low parasitic inductance structure layout in a SiC power module, characterized in that, The method includes: S11, Construct the initial power circuit structure and gate drive circuit structure of multiple parallel power devices in the SiC power module. The power circuit structure is a parallel symmetrical path structure from the power pin to the busbar, and the gate drive circuit structure is an independent path structure of the same length from the gate pin to the driver board terminal. Both the power circuit structure and the gate drive circuit structure are set in a double-layer copper busbar structure with upper and lower symmetry. S12, based on the geometric arrangement relationship between the power circuit structure and the gate drive circuit structure, calculate the parasitic inductance value and mutual inductance coupling value between each circuit, and construct a mutual inductance coupling matrix. Each element of the mutual inductance coupling matrix corresponds to the magnetic coupling strength between any two circuit paths. S13. Based on the maximum mutual inductance difference in each row of the mutual inductance coupling matrix, identify the structural location where there is abrupt boundary between the circuits. Use the abrupt boundary location as the target area for local inductance structure adjustment. Construct a longitudinal magnetic flux guiding groove structure and insert it into the gap layer between the upper and lower copper busbars. The longitudinal magnetic flux guiding groove structure is used to locally suppress the magnetic coupling strength at the abrupt location.

2. The low parasitic inductance structure layout design method in a SiC power module according to claim 1, characterized in that, The steps for constructing the power circuit structure and the gate drive circuit structure are as follows: S111 arranges the parallel path between the power pin and the busbar according to the symmetrical geometric position, and forms a symmetrical path of equivalent length in the upper and lower copper busbars; S112, arrange the lead-out paths between the gate pins and the driver board terminals of equal length independently, and maintain equivalent geometric positions within the upper and lower copper busbars; S113, a gap layer is set between the upper and lower copper busbars to separate the power circuit structure from the gate drive circuit structure.

3. The low parasitic inductance structure layout design method in a SiC power module according to claim 2, characterized in that, The steps for calculating the parasitic inductance and mutual inductance coupling values ​​between each loop, and constructing the mutual inductance coupling matrix are as follows: S121, based on the geometric parameters of the power circuit structure and the gate drive circuit structure, extract the equivalent self-inductance value of each path; S122, Calculate the mutual inductance value between two paths based on the spatial distribution relationship between paths; S123 combines the self-inductance value with the mutual inductance value to generate a mutual inductance coupling matrix.

4. The low parasitic inductance structure layout design method in a SiC power module according to claim 3, characterized in that, The steps to identify the structural locations where abrupt boundaries exist between circuits are as follows: S131, extract the mutual inductance value corresponding to each row in the mutual inductance coupling matrix; S132, perform a difference operation on adjacent mutual inductance values ​​in the same row, and select the value with the largest difference as the maximum mutual inductance difference of the row. S133, based on the distribution results of the maximum mutual inductance difference, locates the structural locations where abrupt boundary exists.

5. The low parasitic inductance structure layout design method in a SiC power module according to claim 4, characterized in that, The method further includes: S14. Based on the three-dimensional power circuit model and gate drive circuit model after inserting the flux guide slot structure, perform transient current distribution simulation and gate flyback peak voltage simulation. The transient current distribution simulation is used to determine whether the current difference of each parallel device is less than the current balancing threshold value. The gate flyback peak voltage simulation is used to determine whether the gate flyback voltage is less than the set voltage protection threshold. S15, when the transient current difference is less than the current balancing threshold and the gate flyback voltage is less than the voltage protection threshold, a symmetrical bleed resistor structure is inserted in each gate lead-out path. The bleed resistor structure forms a symmetrical connection between the gate output terminals of the upper and lower copper busbars to suppress the remaining reverse induction spikes in the gate path and solidify the final low parasitic inductance structure layout.

6. The low parasitic inductance structure layout design method in a SiC power module according to claim 5, characterized in that, The steps for performing a gate flyback spike voltage simulation are as follows: S144, Establish a three-dimensional gate drive circuit model including a longitudinal flux guide slot structure; S142, perform time-domain simulation of the current distribution of each parallel device; S143, calculate the current difference between parallel devices and compare it with the current balance threshold.

7. The low parasitic inductance structure layout design method in a SiC power module according to claim 6, characterized in that, The steps for performing a gate flyback spike voltage simulation are as follows: S144, Establish a three-dimensional gate drive circuit model including a longitudinal flux guide slot structure; S145 performs transient voltage simulation of the gate turn-on and turn-off processes; S146: Extract the gate flyback voltage value and compare it with the voltage protection threshold.

8. The low parasitic inductance structure layout design method in a SiC power module according to claim 7, characterized in that, The steps for inserting a symmetrical bleed resistor structure in each gate lead-out path are as follows: S151, discharge resistors are arranged between the gate output terminals of the upper and lower copper busbars respectively; S152, the bleeder resistors are connected in parallel in a symmetrical manner to insert a symmetrical bleeder resistor path structure.

9. A low parasitic inductance structure layout design method in a SiC power module according to claim 8, characterized in that, The suppression logic of the symmetrical bleeder resistor structure is as follows: S153, when there is a residual reverse induced spike in the gate path, the bleeder resistor structure absorbs the spike voltage. S154, after the peak voltage is discharged to the set attenuation range, maintains the voltage stability of the gate lead-out path; S155 incorporates the bleed resistor structure as part of the final fixed layout to form a low parasitic inductance structure layout.

10. A low parasitic inductance structure layout design method in a SiC power module according to claim 9, characterized in that, The steps for solidifying the final low parasitic inductance structure layout are as follows: S157 preserves the three-dimensional layout including the power circuit structure, the gate drive circuit structure, the longitudinal flux guide slot structure and the symmetrical discharge resistor structure. S158 uses the solidified layout diagram as the basis for power module production, so as to realize the final implementation of the low parasitic inductance structure.

Images