On-chip integrated photon calculation chip architecture based on three-dimensional diffraction layer

Abstract

The invention provides an on-chip integrated photon calculation chip architecture based on a three-dimensional diffraction layer, and the architecture comprises an input layer which encodes input information into an optical mode of an optical fiber bundle, carries out the processing of the trained and optimized three-dimensional diffraction layer, and couples the information into an optical mode of a silicon waveguide through a vertical grating array; the middle layer is used for modulating the information processed by the vertical grating array; and the output layer converts the modulated light information to spatial distribution of light through a vertical grating array, outputs the light information after passing through a trained three-dimensional diffraction layer, and finally captures and presents an image result through an infrared CCD (Charge Coupled Device). According to the invention, the capacity and throughput of the computing architecture are improved.

Description

Technical Field

[0001] This invention belongs to the field of photonic chip computing, and in particular relates to an on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer. Background Technology

[0002] The rapid development of Artificial General Intelligence (AGI) is accompanied by an ever-increasing demand for computing performance. For complex, multimodal information from the real world, high-capacity and high-throughput computing architectures are urgently needed. In the post-Moore's Law era, the ever-increasing demands for performance have become challenging. In recent years, Optical Neural Networks (ONNs) have attracted much attention due to their advantages of low power consumption and ultra-high computational bandwidth. On-chip ONN implementations based on integrated photonic chips offer advantages such as high integration density, strong reconfigurability, optical / electro-optic nonlinearity, and the ability to be hybrid-designed and packaged with optoelectronic chips. Several classic on-chip ONN implementation schemes include coherent methods based on integrated Mach-Zehnder interferometer (MZI) meshes, wavelength division multiplexing (WDM) processing based on micro-ring modulators, and photonic parallel convolution tensor kernels implemented using phase change materials (PCMs). However, their computational scale is significantly limited by large size and high energy consumption.

[0003] Diffractive neural networks (DNNs) are network architectures that utilize the diffraction and interference effects of light to perform computational tasks similar to those of neural networks, and are also applicable to optical computing. They can achieve various functions based on the design of passive diffraction layers using deep learning, learning data digitally using multi-layered artificial neural networks in computers. The advantage of DNNs in terms of neuron density lies mainly in their ability to increase computational power and handle complex tasks through multi-layered optical diffraction structures, parallel information processing, and deep network structures. Currently, researchers have proposed on-chip DNN schemes on integrated photonic chip platforms that can build higher-density neural networks to some extent, but their degrees of freedom are still limited compared to three-dimensional DNNs. Therefore, there is an urgent need for high-capacity and high-throughput computing architectures to meet the demands of data-intensive computing. Summary of the Invention

[0004] The purpose of this invention is to provide an on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer, combining an integrated photonic chip (PIC) with a diffractive neural network (DNN). This allows for the complementary advantages of both the PIC and the DNN, forming a high-capacity and high-throughput computing architecture. The technical solution adopted is as follows:

[0005] An on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer includes:

[0006] Input layer 1 encodes the input information into the optical mode of the fiber bundle, processes it through a trained and optimized three-dimensional diffraction layer, and couples it into the optical mode of the silicon waveguide through a vertical grating array.

[0007] Intermediate layer 2 is used to modulate the information processed by the vertical grating array;

[0008] Output layer 3 diffracts the modulated light information onto the spatial distribution of light through a vertical grating array. After being trained by the three-dimensional diffraction layer, the output is finally captured and presented by an infrared CCD.

[0009] Preferably, the specific structure of the input layer 1, the intermediate layer 2, and the output layer 3 is as follows:

[0010] The input layer 1 includes an optical information input layer 1-1, a first three-dimensional diffraction layer 1-2, and a first vertical grating array layer 1-3 arranged sequentially along the optical transmission path A.

[0011] The intermediate layer 2 is disposed between the first vertical grating array layer 1-3 and the second vertical grating array layer 3-3 along the optical transmission path B;

[0012] The output layer 3 includes a second vertical grating array layer 3-3, a second three-dimensional diffraction layer 3-2, and an optical information output layer 3-1 arranged sequentially along the optical transmission path C;

[0013] The angles between optical transmission path A and optical transmission path B, and between optical transmission path B and optical transmission path C are all 90 degrees.

[0014] Both the first three-dimensional diffraction layer 1-2 and the second three-dimensional diffraction layer 3-2 are formed on the top silicon dioxide layer; the top silicon dioxide layer forms the top of the integrated photonic chip PIC;

[0015] The top silicon dioxide layer extends between the first three-dimensional diffraction layer 1-2 and the optical information input layer 1-1, and between the second three-dimensional diffraction layer 3-2 and the optical information output layer 3-1.

[0016] Preferably, the first three-dimensional diffraction layer 1-2 and the second three-dimensional diffraction layer 3-2 are both parallel to the intermediate layer 2.

[0017] Preferably, the optical information input layer includes several fiber bundles, each composed of several optical fibers; the first vertical grating array layer 1-3 includes a coupler VGC array arranged corresponding to the fiber bundles.

[0018] Preferably, the first three-dimensional diffraction layer 1-2 is fabricated above the first vertical grating array layer 1-3 by two-photon polymerization technology, and the second three-dimensional diffraction layer 3-2 is fabricated above the second vertical grating array layer 3-3.

[0019] Preferably, the first three-dimensional diffraction layer 1-2 includes several diffraction neural networks (DNNs).

[0020] Preferably, the input information is a light source in the communication band.

[0021] Preferably, the intermediate layer 2 is an array of electro-optic modulators, acousto-optic modulators, or thermo-optic modulators.

[0022] Compared with the prior art, the advantages of the present invention are:

[0023] 1. By combining integrated photonic chips (PIC) with diffractive neural networks (DNN), a novel on-chip optical computing architecture is proposed. This architecture can complement the advantages of both integrated photonic chips and three-dimensional diffractive neural networks, further improving the neuron density and network scale of optical computing chips, providing support for more complex and higher-dimensional large-scale data processing. The potential advantages of this architecture in terms of computing speed and energy consumption are explored, and a photonic computing system is constructed, providing a hardware solution for realizing photonic neural morphology using silicon-based materials.

[0024] 2. This chip can achieve high-speed and high-efficiency computing. The addition of the three-dimensional diffraction layer can not only increase the network size, but also further improve the chip's computing power, meet the needs of large-scale data processing, realize precise control of light field propagation, and perform artificial intelligence tasks such as pattern recognition. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of an on-chip integrated photonic computing chip based on a three-dimensional diffraction layer.

[0026] Figure 2 This is a schematic diagram of the on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer.

[0027] Figure 3 A schematic cross-sectional view of the top silicon dioxide layer of an integrated photonic chip combined with a DNN;

[0028] Figure 4 This is the confusion matrix of the prediction results of the trained optical neural network.

[0029] Among them, 1 is the input layer, 1-1 is the optical information input layer, 1-2 is the first three-dimensional diffraction layer, and 1-3 is the first vertical grating array layer.

[0030] 2. Intermediate layer

[0031] 3. Output layer, 3-1. Optical information output layer, 3-2. Second three-dimensional diffraction layer, 3-3. Second vertical grating array layer. Detailed Implementation

[0032] The on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer of the present invention will be described in more detail below with reference to the schematic diagrams, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving the advantageous effects of the invention. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0033] like Figure 1 As shown, an on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer includes:

[0034] Input layer 1 encodes the input information into the optical mode of the fiber bundle, processes it through a trained and optimized three-dimensional diffraction layer, and couples it into the optical mode of the silicon waveguide through a vertical grating array.

[0035] Intermediate layer 2 is used to modulate the information processed by the vertical grating array;

[0036] Output layer 3 converts the modulated light information into a spatial distribution of light through a vertical grating array, outputs it after passing through a trained three-dimensional diffraction layer, and finally captures and presents the image result through an infrared CCD.

[0037] like Figures 2-3 As shown, the specific structure of input layer 1, intermediate layer 2, and output layer 3 is as follows:

[0038] Input layer 1 includes an optical information input layer 1-1, a first three-dimensional diffraction layer 1-2, and a first vertical grating array layer 1-3, arranged sequentially along the optical path transmission path A. "Vertical" refers to the fact that the vertical grating coupler (VGC) bends the horizontally propagating light path 90 degrees to emit it vertically.

[0039] That is, the optical information input layer 1 generates an optical signal carrying the input information, which is incident on the combined device of the first three-dimensional diffraction layer and the first vertical grating array layer.

[0040] The first three-dimensional diffraction layer processes the phase information generated during training into corresponding phase plates, which are placed behind the optical fiber to achieve precise control of the propagation of the light field and perform artificial intelligence tasks such as pattern recognition (taking the classification task of ten digits from 0 to 9 as an example).

[0041] Intermediate layer 2 is positioned between vertical grating array layer 1-3 and vertical grating array layer 3-3 along the optical transmission path B.

[0042] The middle layer is a programmable, reconfigurable photonic computing network used to implement on-chip matrix operations or nonlinear operations.

[0043] Output layer 3 includes a second vertical grating array layer 3-3, a second three-dimensional diffraction layer 3-2, and an optical information output layer 3-1, which are arranged sequentially along the optical transmission path C.

[0044] The modulated light information enters the combined device of the second three-dimensional diffraction layer and the second vertical grating array layer, and the image result is observed and presented by infrared CCD.

[0045] The angles between optical transmission path A and optical transmission path B, and between optical transmission path B and optical transmission path C are all 90 degrees.

[0046] The top silicon dioxide layer forms the top of the integrated photonic chip (PIC); three-dimensional diffraction layers 1-2 and 3-dimensional diffraction layers 3-2 are formed on the top silicon dioxide layer. In other words, silicon dioxide covers the top of the PIC chip structure to protect it.

[0047] The top silicon oxide layer extends between the first three-dimensional diffraction layer 1-2 and the light information input layer 1-1, and between the second three-dimensional diffraction layer 3-2 and the light information output layer 3-1, as shown below. Figure 3 As shown.

[0048] The three-dimensional diffraction layer is fabricated on the upper surface of the vertical grating array of the integrated photonic chip using two-photon polymerization technology, thereby achieving phase modulation and matching the dimensions of the two layers.

[0049] That is, by using two-photon polymerization technology, the first three-dimensional diffraction layer 1-2 is processed above the first vertical grating array layer 1-3, and the second three-dimensional diffraction layer 3-2 is processed above the second vertical grating array layer 3-3.

[0050] The first three-dimensional diffraction layer 1-2 and the second three-dimensional diffraction layer 3-2 are both parallel to the intermediate layer 2.

[0051] like Figure 2 As shown, only the first three-dimensional diffraction layer 1-2, the first vertical grating array layer 1-3, and the intermediate layer 2 are displayed; the second three-dimensional diffraction layer 3-2 and the second vertical grating array layer 3-3 are not displayed.

[0052] like Figure 3 As shown, Figure 2 The area marked by the red dashed line represents a cross-sectional view of the first three-dimensional diffraction layer 1-2 fabricated above the first vertical grating array layer 1-3. The red lines represent the silicon waveguide layer and silicon substrate layer, the gray lines represent the top silicon dioxide layer TOX and the bottom silicon dioxide layer BOX, and the blue lines represent the three-dimensional diffraction layer DNN.

[0053] Figure 3 In the process, the top silica layer TOX was color-coded, and a portion of the top silica layer of the three-dimensional diffraction layer DNN was set as a white area.

[0054] Existing integrated photonic chip (PIC) technologies include:

[0055] The layers are arranged in sequence: top silicon dioxide layer (TOX), silicon waveguide layer (middle layer 2, first vertical grating array layer 1-3 and second vertical grating array layer 3-3), bottom silicon dioxide layer (BOX), and silicon substrate (Si Substrate).

[0056] In this embodiment, the diffraction neural network (DNN) is integrated into the top silicon dioxide layer of the integrated photonic chip (PIC).

[0057] That is, the first three-dimensional diffraction layer 1-2 and the first vertical grating array layer 1-3 in the input layer 1, the intermediate layer 2, and the second three-dimensional diffraction layer 3-2 and the second vertical grating array layer 3-3 in the output layer are on one PIC.

[0058] A cross-sectional view of the structure combining the integrated photonic chip (PIC) with a three-dimensional diffraction layer is shown below. Figure 3 As shown, a layer of silicon dioxide material is placed on top of the vertical grating array, and photoresist material is added on top to realize DNN processing on the vertical grating array.

[0059] In this embodiment, both the input and output information are laser light sources in the 1550nm communication band.

[0060] The optical information input layer includes a 3x3 fiber bundle, which is composed of several optical fibers; the first vertical grating array layer 1-3 includes 3x3 couplers (VGCs) arranged corresponding to the fiber bundle. Light is input into the 3x3 optical fibers, encoding the input information onto the input silicon waveguide.

[0061] The intermediate layer 2 is a programmable photonic computing network composed of an array of electro-optic modulators, acousto-optic modulators, or thermo-optic modulators. It is located on the same chip as the grating array generated by the arrangement of the first vertical focusing grating coupler in the input layer 1, and the two are connected by a waveguide. Matrix multiplication and addition and nonlinear calculations are achieved using phase modulation, intensity modulation, etc. (such as Mach-Zehnder interferometers and micro-ring structures).

[0062] The middle layer 2 is a 3*3 micro-ring array. Here, the micro-rings are carrier-doped micro-ring modulators. In this example, the parameters are a micro-ring radius r = 10 μm and a gap between the straight waveguide and the micro-rings = 200 nm. Each micro-ring modulator modulates the input signal. The modulation process is to perform a multiply-add operation on the optical signal. That is, the amplitude and phase of the output signal are determined by the weights of the input signal and the micro-ring modulator.

[0063] The vertical grating array layer is a grating array generated by arranging vertical focusing grating couplers on the chip, with each vertical grating (coupler) corresponding to an optical fiber.

[0064] Two three-dimensional diffraction layers comprise several diffraction neural networks (DNNs). Transmission between layers is achieved through light diffraction in the free space of the silica layer; each point on the diffraction layer is a sub-source of a secondary spherical wave. The input to a neuron in the next layer is defined as the superposition of the outputs of all neurons in the previous layer after diffraction propagation at that neuron. The weight of each neuron is defined as the phase and amplitude of the unit optical structure. Training data is input from the input layer, and the output of the neural network is calculated using optical diffraction.

[0065] Two three-dimensional diffraction layers are formed by directly fabricating optical microstructures on transparent or optical materials using three-dimensional nanolithography based on two-photon polymerization. The optical microstructures of different sizes change the phase distribution of light, thereby achieving the control of light waves.

[0066] In this embodiment, a test experimental system for a vertical grating coupler is built to observe and record the output light field data of the vertical grating array, and input it into the theoretical calculation model of the DNN for training.

[0067] The training process for the three-dimensional diffraction layer network was completed based on optical system modeling and numerical simulation. Optical diffraction propagation in free space was modeled in Python, and the optical microstructure parameters of the diffraction layer were trained using a stochastic optimization method on the TensorFlow platform. This version ran on a computer running Windows 11.

[0068] The training set is a dataset obtained from FDTD simulation, and the test set is obtained by adjusting the proportions of amplitude and phase using MATLAB.

[0069] Specifically, the 3D diffraction layer utilizes FDTD simulation results to generate the training dataset. By calculating the transfer matrix (TM) of the simulation results and combining it with the simulated images, the amplitude and phase information of the speckle pattern at the output end are generated for training the DNN. The Adaptive Moment Estimation (Adam) optimization algorithm is then used to optimize the DNN's performance through iterative training.

[0070] Based on the trained optical diffraction layer microstructure parameters, a three-dimensional diffraction layer is fabricated above the vertical grating array of the integrated photonic chip. The output light field data after passing through the three-dimensional diffraction layer is recorded to verify the consistency between the experimental results and the theoretical model, so as to realize the task of recognizing digits 0 to 9.

[0071] That is, the three-dimensional diffraction layer is manufactured by three-dimensional two-photon nanolithography, which modulates the phase of the input light information according to the Rayleigh-Sommerfeld theory.

[0072] An adaptive moment estimation optimization algorithm was used, and the negative Pearson correlation coefficient and structural similarity index were used as evaluation indicators. The performance of the three-dimensional diffraction layer was optimized through repeated training.

[0073] Figure 4 This is the confusion matrix result of the prediction results of the trained optical neural network. The vertical axis represents the true labels of the test set (0-9), and the horizontal axis represents the predicted labels of the test set. Predicting from 1000 test sets, the final prediction result of this optical diffraction neural network can achieve an accuracy of over 90%.

[0074] In summary, this invention introduces a three-dimensional diffraction neural network into a two-dimensional integrated optical computing chip, further effectively improving the neuron density and network scale of the optical computing chip, providing support for more complex and higher-dimensional large-scale data processing, exploring its potential advantages in computing speed and energy consumption, and constructing a photonic computing system, providing a hardware solution for realizing photonic neuromorphism using silicon-based materials.

[0075] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. An on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer, characterized in that, include: The input layer (1) encodes the input information into the optical mode of the fiber bundle, processes it through a trained and optimized three-dimensional diffraction layer, and couples it into the optical mode of the silicon waveguide through a vertical grating array. The intermediate layer (2) is used to modulate the information processed by the vertical grating array; The output layer (3) diffracts the modulated light information onto the spatial distribution of light through a vertical grating array. After being trained by the three-dimensional diffraction layer, the output is finally captured and presented by an infrared CCD.

2. The on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer according to claim 1, characterized in that, The specific structure of the input layer (1), intermediate layer (2) and output layer (3) is as follows: The input layer (1) includes an optical information input layer (1-1), a first three-dimensional diffraction layer (1-2), and a first vertical grating array layer (1-3) arranged sequentially along the optical transmission path A; The intermediate layer (2) is disposed between the first vertical grating array layer (1-3) and the second vertical grating array layer (3-3) along the optical transmission path B; The output layer (3) includes a second vertical grating array layer (3-3), a second three-dimensional diffraction layer (3-2), and an optical information output layer (3-1) arranged sequentially along the optical transmission path C; The angles between optical transmission path A and optical transmission path B, and between optical transmission path B and optical transmission path C are all 90 degrees. Both the first three-dimensional diffraction layer (1-2) and the second three-dimensional diffraction layer (3-2) are formed on the top silicon dioxide layer; the top silicon dioxide layer forms the top of the integrated photonic chip PIC; The top silicon dioxide layer extends between the first three-dimensional diffraction layer (1-2) and the optical information input layer (1-1), and between the second three-dimensional diffraction layer (3-2) and the optical information output layer (3-1).

3. The on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer according to claim 2, characterized in that, The first three-dimensional diffraction layer (1-2) and the second three-dimensional diffraction layer (3-2) are both parallel to the intermediate layer (2).

4. The on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer according to claim 2, characterized in that, The optical information input layer includes several fiber bundles, each composed of several optical fibers; the first vertical grating array layer (1-3) includes a coupler VGC array arranged corresponding to the fiber bundles.

5. The on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer according to claim 2, characterized in that, The first three-dimensional diffraction layer (1-2) was fabricated above the first vertical grating array layer (1-3) using two-photon polymerization technology, and the second three-dimensional diffraction layer (3-2) was fabricated above the second vertical grating array layer (3-3).

6. The on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer according to claim 2, characterized in that, The first three-dimensional diffraction layer (1-2) includes several diffraction neural networks (DNNs).

7. The on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer according to claim 1, characterized in that, The input information is a light source in the communication band.

8. The on-chip integrated photonic computing chip architecture based on a three-dimensional diffraction layer according to claim 2, characterized in that, The intermediate layer (2) is an array of electro-optic modulators, acousto-optic modulators, or thermo-optic modulators.

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