Charging driving circuit and method thereof, display panel and display device

Abstract

The application discloses a charging driving circuit and a method thereof, a display panel and a display device, and relates to the technical field of display. The circuit comprises a voltage amplification driving module, a first driving adjustment module and a second driving adjustment module. When a driving chip provides a charging driving voltage to a non-inverting terminal of the voltage amplification driving module, a charging feedback voltage connected to a voltage output terminal of the voltage amplification driving module through an inverting terminal of the voltage amplification driving module is obtained, and a driving adjustment result is determined according to the charging driving voltage and the charging feedback voltage. The first driving adjustment module is controlled to drive a power supply voltage in a voltage lifting state to charge the voltage output terminal of the voltage amplification driving module according to the driving adjustment result. Alternatively, the second driving adjustment module is controlled to drive the voltage output terminal to discharge to the ground in a voltage descending state according to the driving adjustment result. The application aims to improve the charging driving performance of the display panel to reduce the chip loss.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a charging drive circuit and method thereof, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, the performance indicators of display panels, such as image quality, response speed and energy efficiency, have become key factors in measuring the quality of products. Charging performance, as an important part of this, has a direct impact on display effect and device energy consumption.

[0003] In the architecture of display panel driver chips, the charging circuit, as one of the core modules, directly determines the chip's driving efficiency and power consumption level. Traditional charging circuits generally adopt a fixed driving capability structure, that is, continuously outputting a constant current or voltage value throughout the entire charging cycle. However, the load characteristics of display panels exhibit typical RC (resistor-capacitor) charging and discharging characteristics, specifically, the charging current demand decreases exponentially over time, especially in the later stages of charging, where the current value approaches zero. This means that when the driving circuit maintains a high driving capability, because the actual current required by the load has decreased significantly in the later stages of charging, the fixed driving capability circuit structure still operates at full power, resulting in a large amount of energy being wasted ineffectively. This leads to increased losses in the driver chip and the risk of exceeding temperature specifications.

[0004] Therefore, improving the charging drive performance of display panels to reduce chip wear is a pressing technical problem that needs to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a charging drive circuit and method thereof, a display panel, and a display device, which aim to improve the charging drive performance of the display panel to reduce chip losses.

[0006] To achieve the above objectives, this application provides a charging drive circuit, the charging drive circuit comprising:

[0007] A voltage amplification drive module, wherein the inverting terminal of the voltage amplification drive module is electrically connected to the voltage output terminal of the voltage amplification drive module, and the voltage amplification drive module is configured to receive the charging feedback voltage of the voltage output terminal through the inverting terminal when the drive chip provides a charging drive voltage to the non-inverting terminal of the voltage amplification drive module, and determine the drive adjustment result based on the charging drive voltage and the charging feedback voltage;

[0008] A first drive adjustment module is electrically connected to the first control terminal of the voltage amplification drive module. The first drive adjustment module is configured to control the power supply voltage to charge the voltage output terminal based on the drive adjustment result being a voltage boost state.

[0009] The second drive adjustment module is electrically connected to the second control terminal of the voltage amplification drive module. The second drive adjustment module is configured to control the voltage output terminal to discharge to ground based on the drive adjustment result being a voltage drop state.

[0010] In one embodiment, the first drive adjustment module includes a first resistor, a second resistor, a first capacitor, a first parallel unit, and a first operational amplifier;

[0011] The inverting input terminal of the first operational amplifier is electrically connected to the first terminal of the first resistor and the first terminal of the first parallel unit, respectively, and the second terminal of the first resistor is electrically connected to the first inverting voltage terminal.

[0012] The first operational output terminal of the first operational amplifier is electrically connected to the first control terminal, and the second terminal of the first parallel unit is electrically connected between the first operational output terminal and the first control terminal;

[0013] The non-inverting input terminal of the first operational amplifier is electrically connected to the first terminal of the second resistor and the first terminal of the first capacitor, respectively. The second terminal of the second resistor is electrically connected to the first non-inverting voltage terminal, and the second terminal of the first capacitor is grounded.

[0014] In one embodiment, the first drive adjustment module includes a third resistor, a fourth resistor, a second capacitor, a second parallel unit, and a second operational amplifier;

[0015] The out-of-phase input terminal of the second operational amplifier is electrically connected to the first terminal of the third resistor and the first terminal of the second parallel unit, respectively, and the second terminal of the third resistor is electrically connected to the second out-of-phase voltage terminal.

[0016] The second operational output terminal of the second operational amplifier is electrically connected to the second control terminal, and the second terminal of the second parallel unit is electrically connected between the second operational output terminal and the second control terminal.

[0017] The non-inverting input terminal of the second operational amplifier is electrically connected to the first terminal of the fourth resistor and the first terminal of the second capacitor, respectively. The second terminal of the fourth resistor is electrically connected to the second non-inverting voltage terminal, and the second terminal of the second capacitor is grounded.

[0018] In one embodiment, the charging drive circuit further includes a timing control module, a first switching element, and a second switching element;

[0019] The first end of the first switch is electrically connected to the output end of the first drive adjustment module, the second end of the first switch is electrically connected to the first control end of the voltage amplification drive module, and the control end of the first switch is electrically connected to the first switch control end of the timing control module.

[0020] The first end of the second switch is electrically connected to the output end of the second drive adjustment module, the second end of the second switch is electrically connected to the second control end of the voltage amplification drive module, and the control end of the second switch is electrically connected to the second switch control end of the timing control module.

[0021] In one embodiment, the timing control module includes a timing control chip, as well as a communication receiver and a counter integrated within the driver chip;

[0022] The timing control chip is connected to the communication receiver, the clock input source of the counter is connected to the clock signal source of the communication receiver, and the counting storage end of the counter is connected to the preset counting transmission end of the communication receiver.

[0023] In one embodiment, the voltage amplification drive module includes a potential follower that integrates a first MOS transistor and a second MOS transistor;

[0024] The positive input terminal of the potential follower is electrically connected to the driver chip, and the negative input terminal of the potential follower is electrically connected to the potential output terminal of the potential follower. The positive input terminal of the potential follower is the non-inverting input of the voltage amplification driver module, the negative input terminal of the potential follower is the inverting input of the voltage amplification driver module, and the potential output terminal of the potential follower is the voltage output terminal of the voltage amplification driver module.

[0025] The first path terminal of the first MOSFET is electrically connected to the power supply terminal, and the first path terminal of the first MOSFET is electrically connected to the first path terminal of the second MOSFET.

[0026] The first path terminal of the first MOSFET is electrically connected to the connection node of the first path terminal of the second MOSFET, and is electrically connected to the potential output terminal of the potential follower; the second path of the second MOSFET is grounded.

[0027] The gate terminal of the first MOS transistor forms the first control terminal and is electrically connected to the first drive adjustment module, and the gate terminal of the second MOS transistor forms the second control terminal and is electrically connected to the second drive adjustment module.

[0028] Furthermore, to achieve the above objectives, this application also provides a charging driving method, which is applied to the charging driving circuit described in any of the above claims, and the charging driving method includes:

[0029] When the charging drive voltage of the driver chip is detected, the charging feedback voltage of the voltage amplification drive module is determined, and the voltage amplification drive module is controlled to determine the drive adjustment result based on the charging drive voltage and the charging feedback voltage.

[0030] The first drive adjustment module is controlled to charge the voltage output terminal of the voltage amplification drive module with the drive power supply voltage according to the drive adjustment result indicating a voltage boost state; or,

[0031] The second drive adjustment module is controlled to drive the voltage output terminal to discharge to ground based on the drive adjustment result indicating a voltage drop.

[0032] In one embodiment, the charging driving method further includes:

[0033] The driving time of the target driving adjustment module is determined based on the charging driving requirements of the display panel. The target driving adjustment module is any one of the first driving adjustment module and the second driving adjustment module.

[0034] Determine the signal period of the preset clock signal source, and determine the counting threshold based on the driving time and the signal period;

[0035] When the target drive adjustment module controls the voltage output terminal according to the drive adjustment result, it accumulates the number of occurrences of the preset clock signal source until the number of occurrences reaches the counting threshold, at which point the target drive adjustment module is turned off.

[0036] In addition, to achieve the above objectives, this application also provides a display panel, the display panel including the charging drive circuit described in any of the above claims;

[0037] A driver module integrating a driver chip is configured to trigger the driver chip to provide a charging drive voltage to the non-inverting terminal of the voltage amplification driver module according to the actual application scenario.

[0038] In one embodiment, the actual application scenarios include partial pixel refresh scenarios and low-temperature environment scenarios;

[0039] The driving module includes:

[0040] A local update control unit is configured to detect pixel change areas in the display area where data changes occur during the local pixel refresh scenario, generate a corresponding charging control signal based on the area ratio and average grayscale value of the pixel area, and trigger the driver chip to output a charging drive voltage that matches the charging control signal.

[0041] A temperature compensation unit is configured to detect the operating temperature of the display panel in the low-temperature environment and output a temperature compensation signal to the driver chip when the operating temperature is lower than a preset critical low-temperature threshold, so that the driver chip can output a charging drive voltage that matches the temperature compensation signal.

[0042] In addition, to achieve the above objectives, this application also provides a display device, which includes the display panel described above;

[0043] Alternatively, a memory, a processor, and a charging driver stored in the memory and executable on the processor, wherein the processor, when executing the charging driver, implements the steps of the charging driving method as described in any of the preceding embodiments.

[0044] The charging drive circuit described in this application achieves a significant improvement in charging drive performance and effectively reduces chip losses through the coordinated operation of a voltage amplification drive module, a first drive adjustment module, and a second drive adjustment module. Specifically, the voltage amplification drive module can accurately determine the drive adjustment result based on the charging drive voltage and the charging feedback voltage. This allows the first drive adjustment module to control the power supply voltage to charge the voltage output terminal when the drive adjustment result is a voltage rise, and the second drive adjustment module to control the voltage output terminal to discharge to ground when the drive adjustment result is a voltage drop. This achieves dynamic adjustment of the charging current, enabling it to adaptively adjust according to changes in the load characteristics of the display panel. This significantly improves the charging drive performance of the display panel, avoids ineffective energy consumption caused by continuously maintaining high drive capability in the later stages of charging, and thus reduces the losses of the drive chip. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of a potential follower circuit;

[0048] Figure 2 It is the RC load network of the LCD screen;

[0049] Figure 3 This is a schematic diagram of the charging waveform of a potential follower as the load changes;

[0050] Figure 4 This is a structural block diagram of the first embodiment of the charging drive circuit of this application;

[0051] Figure 5 This is a schematic diagram of the first drive adjustment module involved in the embodiment of this application;

[0052] Figure 6 This is a schematic diagram of the second drive adjustment module involved in the embodiments of this application;

[0053] Figure 7 This is a schematic diagram illustrating the change in the on-current of the MOS transistor involved in the embodiments of this application;

[0054] Figure 8 This is a schematic diagram of the charging drive circuit involved in the embodiments of this application;

[0055] Figure 9 This is a schematic diagram of the charging waveform of the voltage amplification drive module under the corresponding drive adjustment module in the embodiment of this application;

[0056] Figure 10 This is a schematic diagram of the timing control module involved in the embodiments of this application;

[0057] Figure 11 This is a schematic diagram of the driving module involved in the embodiments of this application;

[0058] Figure 12 This is a schematic diagram of the structure of the display device involved in the embodiments of this application.

[0059] Explanation of icon numbers:

[0060] 10. Voltage amplification drive module; 20. First drive adjustment module; 30. Second drive adjustment module; X1. First control terminal of voltage amplification drive module; X2. Second control terminal of voltage amplification drive module; R1. First resistor; R2. Second resistor; C1. First capacitor; 21. First parallel unit;

[0061] A1, First operational amplifier; R3, Third resistor; R4, Fourth resistor; C2, Second capacitor; 31, Second parallel unit; A2, Second operational amplifier; 40, Timing control module; K1, First switch; K2, Second switch; T1, First MOSFET; T2, Second MOSFET; OP, Potential follower; 40, Driver module; 41, Driver chip; 42, Partial update control unit; 43, Temperature compensation unit.

[0062] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0063] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0064] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0065] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0066] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0067] In the field of liquid crystal display panel technology, the source driver (also known as the driver chip) is one of the core components. Its output often employs a potential follower circuit structure based on an operational amplifier to drive the pixel units on the display panel. Specifically, a schematic diagram of the potential follower circuit is shown below. Figure 1 As shown, this circuit generates two key control signals, V1 and V2, through the complex logic circuitry inside the operational amplifier. Signal V1 directly acts on the gate of the first MOS transistor (PMOS transistor) T1 to control its conduction state; while signal V2 acts on the gate of the second MOS transistor (NMOS transistor T2) to achieve precise control over the conduction and cutoff of NMOS transistor T2.

[0068] During circuit operation, when the input voltage Vp is higher than the reference voltage Vn (Vp > Vn), the operational amplifier output satisfies the condition AVDD - V1 > the threshold voltage Vth1 of PMOS transistor T1, causing PMOS transistor T1 to turn on. Simultaneously, the V2 signal is lower than the threshold voltage Vth2 of NMOS transistor T2, causing NMOS transistor T2 to turn off. In this state, the power supply voltage AVDD discharges to the output terminal through the turned-on PMOS transistor T1, causing the output voltage to gradually rise. Conversely, when Vp < Vn, AVDD - V1 < Vth1 causes PMOS transistor T1 to turn off, while V2 > Vth2 turns on NMOS transistor T2. In this case, the output terminal discharges to ground through NMOS transistor T2, causing the output voltage to decrease.

[0069] Furthermore, considering that the output of the source driver of the liquid crystal display screen is actually connected to a continuously distributed RC series load network (such as... Figure 2 As shown in the diagram, this load characteristic places stringent requirements on the driving capability of the potential follower. During the transition of the output voltage from low to high (Vp > Vn), if the driving capability of the potential follower is sufficient, its charging current will naturally decrease as the output voltage gradually approaches the input voltage, forming a typical charging waveform. Similarly, a similar charging current attenuation phenomenon will be observed when the output voltage transitions from high to low (Vp < Vn).

[0070] However, in practical applications, especially for large-size LCD panels, due to cost constraints and unavoidable impedance factors in the signal transmission path, the driving capability of the potential follower often fails to meet the high current demand of the output RC load during the initial charging stage. This leads to significant deviations in the actual charging waveform, such as... Figure 3The waveform L1 is shown in the diagram (waveform L2 represents the theoretical waveform when the driving capability is sufficient). Specifically, when the source driver output voltage switches, the output terminal requires a longer time to reach the target voltage value. As the resolution and refresh rate of LCD displays continue to increase, the charging time of each row of pixels is further compressed, exacerbating the problem of insufficient charging. Ultimately, this may cause the liquid crystal pixels to fail to reach the target voltage within the specified time, resulting in display defects.

[0071] To address the aforementioned insufficient driving capability, traditional solutions tend to increase the pre-amplifier bias current ibias within the source driver, thereby increasing the voltage levels of AVDD-V1 and V2, and consequently enhancing the on-current of PMOS transistor T1 and NMOS transistor T2, thus improving the overall driving capability. However, this approach has significant drawbacks: firstly, a continuous high-current drive not only increases design costs but may also cause the source driver to maintain high driving capability in the later stages of charging (i.e., when the output voltage is close to the target value), resulting in unnecessary energy consumption; secondly, excessive current flowing through PMOS transistor T1 and NMOS transistor T2 exacerbates device heating, increasing the risk of exceeding temperature specifications and affecting product reliability and lifespan.

[0072] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art.

[0073] Therefore, in order to improve the charging drive performance of the display panel and reduce chip losses, this application provides a charging drive circuit and method, a display panel, and a display device.

[0074] This application provides a charging drive circuit, referring to... Figure 4 As shown, Figure 4 This is a structural block diagram of a first embodiment of the charging drive circuit of this application. The charging drive circuit includes:

[0075] A voltage amplification drive module 10 is provided, wherein the inverting terminal of the voltage amplification drive module 10 is electrically connected to the voltage output terminal of the voltage amplification drive module 10, and the voltage amplification drive module 10 is configured to receive the charging feedback voltage of the voltage output terminal through the inverting terminal when the drive chip provides a charging drive voltage to the non-inverting terminal of the voltage amplification drive module 10, and determine the drive adjustment result based on the charging drive voltage and the charging feedback voltage.

[0076] In this embodiment, refer to Figure 4The voltage amplification drive module 10 receives the target input voltage V_in provided by the drive chip through the non-inverting input. This input voltage V_in is represented as voltage Vp (i.e., charging drive voltage) at the non-inverting input of the voltage amplification drive module 10. Simultaneously, the voltage amplification drive module 10 introduces the actual output voltage V_out of the voltage output terminal as the charging feedback voltage Vn to the inverting input in real time. Next, by comparing the magnitudes of the charging drive voltage Vp and the charging feedback voltage Vn, the voltage amplification drive module 10 can accurately obtain the drive adjustment result reflecting the degree of deviation between the actual output voltage V_out and the target input voltage V_in. Subsequently, the voltage amplification drive module 10 automatically switches to the appropriate target drive adjustment module based on the drive adjustment result, so that the target drive adjustment module can adaptively adjust the voltage signal output by the voltage output terminal as the load characteristics of the display panel change, thereby significantly improving the charging drive performance of the display panel.

[0077] The first drive adjustment module 20 is electrically connected to the first control terminal X1 of the voltage amplification drive module. The first drive adjustment module 20 is configured to control the power supply voltage to charge the voltage output terminal based on the drive adjustment result being a voltage rise state.

[0078] In this embodiment, refer to Figure 4 The first drive adjustment module 20, through coordinated control with the voltage amplification drive module 10, achieves precise charging control based on real-time voltage feedback. Specifically, when the voltage amplification drive module 10 determines that the charging drive voltage Vp is greater than the charging feedback voltage Vn, it generates a drive adjustment result characterizing the voltage rise state, triggering the first drive adjustment module 20 to output voltage V_o1, which acts on the first control terminal X1 to connect the power supply terminal to the first control terminal X1, so that the power supply voltage AVDD provided by the power supply terminal charges the voltage output terminal.

[0079] In a specific embodiment, refer to Figure 1 ,as well as Figures 4 to 5 , Figure 4 The first control terminal X1 shown is... Figure 1 The gate terminal of the first MOSFET T1 is shown. During the process of the first drive regulation module 20 charging the voltage output terminal according to the drive regulation result characterizing the voltage rise state, this application utilizes... Figure 5 The virtual short and virtual open characteristics of the first operational amplifier A1 are used to construct an integrating circuit containing resistor R1 and capacitor C3 to characterize the first drive adjustment module 20. For example, when the drive adjustment result is a voltage rise state where the charging drive voltage Vp > the charging feedback voltage Vn, then voltage Vrp1 > voltage Vrn1 can be determined; next, based on the mathematical model of this integrating circuit... It can be seen that when voltage Vrp1 > voltage Vrn1, the output voltage V_o1 increases linearly or exponentially with time, thus forming a voltage slope that conforms to the charging characteristics of the panel. In particular, through the negative correlation between the gate-source voltage Vgs1 = V_o1 - AVDD (voltage V_o1 < power supply voltage AVDD) of the first control terminal X1 and the conduction current, the first MOSFET T1 is in a strong conducting state to provide a large current for fast charging when the voltage V_o1 is large in the initial stage of charging. As V_o1 rises, the absolute value of Vgs1 decreases, that is, the operating point of the first MOSFET T1 gradually shifts to the constant current region, and finally achieves a smooth transition of the charging current from large to small. This process not only ensures charging efficiency but also effectively avoids overcharging, significantly improving the charging drive performance of the display panel. It not only avoids the ineffective energy consumption caused by maintaining high driving capability in the later stage of charging and reduces the loss of the drive chip, but also avoids the phenomenon of excessive current flowing through the second MOSFET aggravating device heating, ensuring the stable and efficient operation of the display panel.

[0080] The second drive adjustment module 30 is electrically connected to the second control terminal X2 of the voltage amplification drive module. The second drive adjustment module 30 is configured to control the voltage output terminal to discharge to ground based on the drive adjustment result being a voltage drop state.

[0081] In this embodiment, when the voltage amplification drive module 10 determines that the charging drive voltage Vp is less than the charging feedback voltage Vn, it generates a drive adjustment result characterizing the voltage drop state, triggering the second drive adjustment module 30 to output voltage V_o2 to act on the first control terminal X1X2 to connect the connection link from the second control terminal X2 to the ground terminal, thereby pulling the voltage of the voltage output terminal down to the ground terminal, thereby realizing discharge to ground.

[0082] In a specific embodiment, Figure 4 The second control terminal X2 shown is... Figure 1 The gate terminal of the second MOSFET T2 is shown, and at this time, the gate terminal voltage Vgs2 of the second MOSFET T2 is positive. For example, combined with... Figure 4 as well as Figure 6 It can be seen that the voltage V_o2 output by the second drive adjustment module 30 is equivalent to the gate voltage Vgs2 of the second MOSFET T2 (i.e., gate voltage Vgs2 = voltage V_o2). For example, when the drive adjustment result is a voltage drop state where the charging drive voltage Vp < the charging feedback voltage Vn, the second drive adjustment module 30 outputs voltage V_o2 based on voltage Vrp2 < voltage Vrn2; next, according to the mathematical model of this integrator circuit... It can be seen that when voltage Vrp2 < voltage Vrn2, the integral term As time t gradually decreases, the voltage V_o2 output by the second drive adjustment module 30 gradually decreases over time. At this time, the gate voltage Vgs2 decreases as the voltage V_o2 decreases. Next, based on the operating characteristics of the second MOS transistor T2 (i.e., the NMOS transistor), when the gate voltage Vgs2 decreases, the conduction current gradually decreases, thus meeting the requirement that the panel charging current decreases from large to small. This not only avoids the problems of increased device heating and increased risk of exceeding temperature specifications caused by excessive current flowing through the second MOS transistor, but also significantly reduces the loss of the drive chip.

[0083] Further, in some feasible embodiments, the first drive adjustment module 20 includes a first resistor R1, a second resistor R2, a first capacitor C1, a first parallel unit 21, and a first operational amplifier A1; the inverting input terminal of the first operational amplifier A1 is electrically connected to the first terminal of the first resistor R1 and the first terminal of the first parallel unit 21, and the second terminal of the first resistor R1 is electrically connected to the first inverting voltage terminal; the first operational output terminal of the first operational amplifier A1 is electrically connected to the first control terminal X1, and the second terminal of the first parallel unit 21 is electrically connected between the first operational output terminal and the first control terminal X1; the non-inverting input terminal of the first operational amplifier A1 is electrically connected to the first terminal of the second resistor R2 and the first terminal of the first capacitor C1, the second terminal of the second resistor R2 is electrically connected to the first non-inverting voltage terminal, and the second terminal of the first capacitor C1 is grounded.

[0084] In this embodiment, refer to Figure 5The first drive adjustment module 20 provided in this application improves the charging drive performance when the actual output voltage V_out changes from low voltage to high voltage through the cooperation of the first operational amplifier A1 and the resistor-capacitor network. Specifically, in the voltage rise state when the charging drive voltage Vp is greater than the charging feedback voltage Vn, the inverting input terminal of the first operational amplifier A1 is connected to the voltage Vrn1 provided by the first inverting voltage terminal through the first resistor R1. At this time, the non-inverting input terminal of the first operational amplifier A1 is connected to the voltage Vrp1 provided by the first non-inverting voltage terminal through the second resistor R2, and the grounded first capacitor C1 is connected to the non-inverting input terminal of the first operational amplifier A1 to avoid high-frequency noise interference to the voltage Vrp1. Next, since the voltage Vrp2 > the voltage Vrn2, the feedback loop formed by the first parallel unit 21 connected between the inverting input terminal and the first operational output terminal of the first operational amplifier A1 can provide real-time feedback that the difference (Vrp1-Vrn1) gradually increases over time. Combined with the integral characteristics of the resistor-capacitor network formed by the first resistor R1 and the third capacitor in the first parallel unit 21, the voltage V_o1 exhibits a linear or exponential growth trend that conforms to the panel charging characteristics over time, forming an ideal voltage slope. Next, since Figure 4 The gate-source voltage Vgs1 at the first control terminal X1 is V_o1 - AVDD. At this point, the gate-source voltage Vgs1 is negative. As the voltage V_o1 gradually increases over time and approaches the supply voltage AVDD, the absolute value of the gate-source voltage Vgs1 becomes smaller. Figure 7 The UGS shown represents the absolute value of the gate-source voltage Vgs1. Figure 4 The first control terminal X1 shown is... Figure 1 The gate terminal of the first MOS transistor T1 (PMOS transistor) shown, when Figure 7 The smaller the UGS shown, the smaller the conduction current of the PMOS transistor. As time goes by, the driving current also decreases, which meets the requirement that the panel charging current decreases from large to small and avoids the redundant power consumption generated in the later stage of charging in the traditional fixed driving mode.

[0085] It should be noted that, in order to avoid Figure 5 The voltage division of the fifth resistor R5 shown in the figure is such that, in this application, the resistance value of the fifth resistor R5 is set to be much larger than... Figure 5 The capacitive reactance of the first resistor R1 and the third capacitor C3 is shown. Furthermore, the voltages Vrp1 and Vrn1, the first resistor R1, and the third capacitor C3 are not fixed values ​​and can be customized according to the actual application of the panel; this application does not impose any restrictions on them.

[0086] The second drive adjustment module 30 includes a third resistor R3, a fourth resistor R4, a second capacitor C2, a second parallel unit 31, and a second operational amplifier A2. The out-of-phase input terminal of the second operational amplifier A2 is electrically connected to the first terminal of the third resistor R3 and the first terminal of the second parallel unit 31, respectively. The second terminal of the third resistor R3 is electrically connected to the second out-of-phase voltage terminal. The second operational output terminal of the second operational amplifier A2 is electrically connected to the second control terminal X2. The second terminal of the second parallel unit 31 is electrically connected between the second operational output terminal and the second control terminal X2. The non-in-phase input terminal of the second operational amplifier A2 is electrically connected to the first terminal of the fourth resistor R4 and the first terminal of the second capacitor C2, respectively. The second terminal of the fourth resistor R4 is electrically connected to the second non-in-phase voltage terminal, and the second terminal of the second capacitor C2 is grounded.

[0087] In this embodiment, the present application improves the charging drive performance when the actual output voltage V_out changes from high voltage to low voltage by constructing a second drive adjustment module 30, which includes a second operational amplifier A2 and a resistor-capacitor network working together. Specifically, when the charging drive voltage Vp < the charging feedback voltage Vn, in the voltage drop state, the second out-of-phase voltage terminal is connected to the out-of-phase input terminal of the second operational amplifier A2 through the third resistor R3 to form a reference voltage input path, ensuring that the out-of-phase input terminal of the second operational amplifier A2 receives a stable and reliable voltage Vrn2. At this time, the non-inverting input terminal of the second operational amplifier A2 is connected to the voltage Vrp2 provided by the second non-inverting voltage terminal through the fourth resistor R4, and the grounded second capacitor C2 is connected to the non-inverting input terminal of the second operational amplifier A2 to avoid high-frequency noise interference to the voltage Vrp2. Next, since the voltage Vrp2 < the voltage Vrn2, a feedback loop formed between the non-inverting input terminal and the second output terminal of the second operational amplifier A2 can be connected through the second parallel unit 31. The real-time feedback difference (Vrp2-Vrn2) gradually decreases over time, thus it can be seen that the voltage V_o2 output by the second operational amplifier A2 gradually decreases over time. Figure 4 The second control terminal X2 shown is... Figure 1 The gate terminal of the second MOS transistor T2 (NMOS transistor) is shown. In other words, the gate terminal voltage Vgs2 of the NMOS transistor decreases as the voltage V_o2 decreases, which makes the conduction current of the NMOS transistor also decrease. This meets the requirement that the panel charging current decreases from large to small, and effectively avoids the energy redundancy loss of traditional circuits in the low load stage.

[0088] It should be noted that, in order to avoid Figure 6 The voltage division of the sixth resistor R6 shown is such that, in this application, the sixth resistor R6 is set to be much larger than... Figure 6The capacitive reactance of the third resistor R3 and the fourth capacitor C4 is shown. Furthermore, the voltages Vrp2 and Vrn2, the third resistor R3, and the fourth capacitor C4 are not fixed values ​​and can be customized according to the actual application of the panel; this application does not impose any restrictions here.

[0089] Furthermore, in some other feasible embodiments, reference is made to... Figure 8 , Figure 8 This is a schematic diagram of a charging drive circuit involved in an embodiment of this application. The charging drive circuit further includes a timing control module 40, a first switch K1, and a second switch K2. The first end of the first switch K1 is electrically connected to the output end of the first drive adjustment module 20, the second end of the first switch K1 is electrically connected to the first control end X1 of the voltage amplification drive module, and the control end of the first switch K1 is electrically connected to the first switch control end of the timing control module 40. The first end of the second switch K2 is electrically connected to the output end of the second drive adjustment module 30, the second end of the second switch K2 is electrically connected to the second control end X2 of the voltage amplification drive module, and the control end of the second switch K2 is electrically connected to the second switch control end of the timing control module 40.

[0090] In this embodiment, when the actual output voltage V_out changes from low voltage to high voltage (i.e., Vp > Vn), the charging waveform of the first drive adjustment module 20 driving the voltage amplification drive module 10 is used. Figure 9 The waveform L1_1 in the figure represents the theoretical charging waveform when the actual output voltage V_out changes from low voltage to high voltage, as shown in the figure. Figure 9 The waveform L2_1 shown is used to represent this. When the actual output voltage V_out changes from high voltage to low voltage (i.e., Vp < Vn), the charging waveform of the second drive adjustment module 30 driving the voltage amplification drive module 10 is represented by... Figure 9 The waveform L1_2 in the figure represents the theoretical charging waveform when the actual output voltage V_out changes from low voltage to high voltage, as shown in the figure. Figure 9 The waveform L2_2 shown represents this. In other words, due to the given... Figure 2 The charging characteristics of the RC series load network shown are Uc=U0*[1-e^(-t / RC)], I=C*dUc / dt, where Uc is the load capacitor voltage of the RC series load network; U0 is the actual output voltage V_out; R is the resistance value of the RC series load network; C is the capacitance value of the RC series load network; e represents the natural constant, approximately equal to 2.71828; and t represents time.

[0091] Therefore, when the capacitive load in the RC series load network is almost saturated, the charging current is very small. When the power consumption of this charging is much smaller than the power consumption of the time-domain output regulator (i.e., the corresponding drive regulation module), activating the time-domain output regulator during this period has the side effect of increasing power consumption. To mitigate this side effect, refer to... Figure 8 After adding a first switch K1 to the output terminal of the first drive adjustment module 20, it is connected to the first control terminal X1 (i.e., the gate terminal of the first MOSFET T1). Similarly, after adding a second switch K2 to the output terminal of the second drive adjustment module 30, it is connected to the first control terminal X1 (i.e., the gate terminal of the second MOSFET T2). Furthermore, the control terminals of the first switch K1 and the second switch K2 are connected to the timing control module 40 to control the drive operating time of the first drive adjustment module 20 and the second drive adjustment module 30. Figure 8 The driving capability of the potential follower OP shown can meet the requirements. Figure 2 When the panel load in the display panel is driven, the corresponding drive adjustment module is turned off. At this time, the maximum drive capability of the potential follower OP remains the same as the drive capability when the corresponding drive adjustment module is turned off. That is, while reducing the power consumption of the corresponding drive adjustment module, the drive capability requirement is guaranteed.

[0092] Furthermore, in some feasible embodiments, reference is made to Figure 10 , Figure 10 This is a schematic diagram of the timing control module 40 involved in the embodiment of this application. The timing control module 40 includes a timing control chip, a communication receiver and a counter integrated in the driver chip; the timing control chip is connected to the communication receiver, the clock input source of the counter is connected to the clock signal source of the communication receiver, and the count storage end of the counter is connected to the preset count transmission end of the communication receiver.

[0093] In this embodiment, based on the timing control chip Figure 2 The charging drive demand of the displayed panel is calculated based on the driving time of the time-domain output regulator (i.e., any one of the first drive regulation module 20 and the second drive regulation module 30), and the driving time is determined accordingly. Figure 10 The signal period of the preset clock signal source shown is calculated. Figure 10 After the count threshold of Count NO is reached, the data is sent to the counter for storage via the communication receiver. Next, when the required time-domain output regulator drives the voltage amplifier drive module 10, the counter accumulates the number of occurrences of the preset clock signal source until the accumulated number of occurrences reaches the count threshold. Then, the required time-domain output regulator is turned off to avoid wasting the power consumption of the time-domain output regulator.

[0094] It should be noted that the communication receiver can be understood as a P2P receiver.

[0095] Furthermore, in some other feasible embodiments, reference is made to... Figure 8 The voltage amplification and driving module 10 includes a potential follower OP integrating a first MOSFET T1 and a second MOSFET T2. The positive input terminal of the potential follower OP is electrically connected to the driving chip, and the negative input terminal of the potential follower OP is electrically connected to its potential output terminal. Specifically, the positive input terminal of the potential follower OP is the non-inverting input of the voltage amplification and driving module 10, the negative input terminal is the inverting input, and the potential output terminal is the voltage output terminal of the voltage amplification and driving module 10. The first MOSFET T1... The first path terminal is electrically connected to the power supply terminal, and the first path terminal of the first MOSFET T1 is electrically connected to the first path terminal of the second MOSFET T2; the connection point of the first path terminal of the first MOSFET T1 being electrically connected to the first path terminal of the second MOSFET T2 is electrically connected to the potential output terminal of the potential follower OP, and the second path of the second MOSFET T2 is grounded; the gate terminal of the first MOSFET T1 forms the first control terminal X1 and is electrically connected to the first drive adjustment module 20, and the gate terminal of the second MOSFET T2 forms the second control terminal X2 and is electrically connected to the second drive adjustment module 30.

[0096] In this embodiment, refer to Figure 8 The potential follower OP connects the target input voltage V_in provided by the driver chip to its own positive input terminal to form a charging drive voltage Vp at the positive input terminal. At the same time, the potential follower OP introduces the actual output voltage V_out of its potential output terminal as the charging feedback voltage Vn to its own negative input terminal in real time. Then, the potential follower OP compares the magnitude of the charging drive voltage Vp and the charging feedback voltage Vn. When the charging drive voltage Vp is greater than the charging feedback voltage Vn, a drive adjustment result characterizing the voltage rise state is generated, which triggers the output voltage V_o1 of the first drive adjustment module 20 to act on the gate terminal of the first MOS transistor T1 to turn on the first MOS transistor T1, so that the power supply voltage AVDD provided by the power supply terminal charges the voltage output terminal.

[0097] In another embodiment, when the charging drive voltage Vp is less than the charging feedback voltage Vn, a drive adjustment result characterizing the voltage drop state is generated, which triggers the second drive adjustment module 30 to output voltage V_o2 to the gate terminal of the second MOS transistor T2 to turn on the second MOS transistor T2, so that the voltage output terminal can discharge to ground.

[0098] In summary, the charging drive circuit configured in this application, through the coordinated operation of the voltage amplification drive module 10, the first drive adjustment module 20, and the second drive adjustment module 30, achieves a significant improvement in charging drive performance and effectively reduces chip losses. Specifically, the voltage amplification drive module 10 can accurately determine the drive adjustment result based on the charging drive voltage and the charging feedback voltage. This allows the first drive adjustment module 20 to control the power supply voltage to charge the voltage output terminal when the drive adjustment result is a voltage rise, and the second drive adjustment module 30 to control the voltage output terminal to discharge to ground when the drive adjustment result is a voltage drop. This achieves dynamic adjustment of the charging current, enabling it to adaptively adjust with changes in the load characteristics of the display panel. This significantly improves the charging drive performance of the display panel, avoids ineffective energy consumption caused by continuously maintaining high drive capability in the later stages of charging, and thus reduces the losses of the drive chip.

[0099] Furthermore, based on the first embodiment of the charging drive circuit of this application, a second embodiment of the charging drive method of this application is proposed. The charging drive method of this application is applied to the charging drive circuit of any of the above-mentioned applications. The charging drive method of this application is executed by a display device applied to the charging drive circuit. The charging drive method of this application includes the following implementation steps S10 to S30.

[0100] Step S10: When the charging drive voltage of the driver chip is detected, the charging feedback voltage of the voltage amplification drive module 10 is determined, and the voltage amplification drive module 10 is controlled to determine the drive adjustment result based on the charging drive voltage and the charging feedback voltage.

[0101] In this embodiment, refer to Figure 4 When the display device detects the charging drive voltage Vp of the driver chip, it connects the charging drive voltage Vp to the non-inverting input of the voltage amplification drive module 10. At this time, the voltage amplification drive module 10 controls the actual output voltage V_out of its voltage output terminal to be introduced as the charging feedback voltage Vn to its own inverting input in real time. By comparing the magnitude of the charging drive voltage Vp and the charging feedback voltage Vn, the voltage amplification drive module 10 can accurately obtain the drive adjustment result reflecting the degree of deviation between the actual output voltage V_out and the target input voltage V_in. Subsequently, the voltage amplification drive module 10 automatically switches to the appropriate target drive adjustment module according to the drive adjustment result, so that the target drive adjustment module can adaptively adjust the voltage signal output by the voltage output terminal as the load characteristics of the display panel change, thereby greatly improving the charging drive performance of the display panel.

[0102] Step S20: Control the first drive adjustment module 20 to charge the voltage output terminal of the voltage amplification drive module 10 according to the drive adjustment result being a voltage boost state.

[0103] In this embodiment, after the display device detects that the drive adjustment result is a voltage rise state, it controls the first drive adjustment module 20 to respond to the voltage rise state by applying the voltage V_o1 output by the first drive adjustment module 20 to the display device. Figure 4 The voltage amplification drive module shown has a connection link between the power supply terminal and the first control terminal X1, so that the power supply voltage AVDD provided by the power supply terminal charges the voltage output terminal.

[0104] Step S30: Control the second drive adjustment module 30 to drive the voltage output terminal to discharge to ground based on the drive adjustment result of the voltage drop state.

[0105] In this embodiment, after the display device detects that the drive adjustment result is a voltage drop, it controls the second drive adjustment module 30 to respond to the voltage drop state by applying the voltage V_o2 output by the second drive adjustment module 30 to the display device. Figure 4 The voltage amplification drive module shown has a connection link on the second control terminal X2 to the ground terminal, which pulls the voltage of the voltage output terminal down to the ground terminal, thereby achieving discharge to ground.

[0106] Furthermore, in some feasible embodiments, the charging driving method may also include the following implementation steps A10 to A30.

[0107] Step A10: Determine the driving working time of the target driving adjustment module based on the charging driving requirements of the display panel. The target driving adjustment module is any one of the first driving adjustment module 20 and the second driving adjustment module 30.

[0108] In this embodiment, with Figure 2 Taking the display panel shown as an example, after determining the load characteristics RC of the resistance and capacitance in the display panel, the load capacitor voltage Uc of the RC series load network is calculated according to Uc=U0*[1-e^(-t / RC)]. The current I of the RC series load network can be accurately calculated according to I=C*dUc / dt, where Uc is the load capacitor voltage of the RC series load network; U0 is the actual output voltage V_out; R is the resistance value of the RC series load network; and C is the capacitance value of the RC series load network. Subsequently, after determining that the charging drive requirement of the display panel is the target charge Q required for the normal operation of the RC series load network, the simultaneous equations C*Uc=I^2*T0 are obtained according to Q=C*Uc and Q=I^2*T0. Then, the driving time T0 of the target drive adjustment module can be accurately calculated.

[0109] Step A20: Determine the signal period of the preset clock signal source, and determine the counting threshold based on the driving working time and the signal period.

[0110] In this embodiment, refer to Figure 10 After determining the signal period of the preset clock signal source through the timing control chip, the driving working time T0 of the target drive adjustment module is converted into the counting threshold Count NO required by the counter according to the preset counting calculation formula, and the counting threshold Count NO is written into the code in the timing control chip. Next, the timing control chip sends the preset clock signal source and the code representing the counting threshold Count NO to the counter in the driver chip through the communication receiver.

[0111] Step A30: When the target drive adjustment module controls the voltage output terminal according to the drive adjustment result, it accumulates the number of occurrences of the preset clock signal source until the number of occurrences reaches the counting threshold, and then shuts down the target drive adjustment module.

[0112] In this embodiment, a preset clock signal source is used as a timing signal. When the target drive adjustment module controls the voltage output terminal according to the drive adjustment result, the drive chip is triggered to start a counter to accumulate the number of occurrences of the preset clock signal source. When the accumulated number of occurrences reaches the counting threshold, the target drive adjustment module is turned off to avoid the power consumption waste caused by the target drive adjustment module, thereby further improving the charging drive performance of the display panel.

[0113] In addition, this application also provides a display panel, as shown in the reference. Figure 11 The display panel includes a charging drive circuit of any of the above; a drive module 40 integrating a drive chip 41, wherein the drive module 40 is configured to trigger the drive chip 41 to provide a charging drive voltage to the non-inverting terminal of the voltage amplification drive module 40 according to the actual application scenario.

[0114] In this embodiment, the traditional driving module 40 typically adopts a global driving method with fixed parameters, which is difficult to adapt to the needs of complex scenarios such as local pixel updates and temperature changes. Especially in the scenario of local refresh, the traditional driving module 40 cannot dynamically adjust the driving parameters according to the characteristics of the pixel change area, resulting in excessive power consumption when refreshing a small area and voltage overshoot when updating a large area; while in the environment of temperature change, the change of carrier mobility will affect the pixel charging efficiency, resulting in uneven display brightness.

[0115] Reference Figure 11In this application, the output terminal of the driver chip 41 in the driver module 40 is electrically connected to the non-inverting terminal of the voltage amplification driver module 40 in the charging driver circuit to achieve intelligent display driving control. Specifically, in the actual application scenario of partial pixel refresh, the driver module 40 monitors the pixel feature parameters of the pixel change area in real time, and dynamically generates the optimal charging control signal based on the pixel feature parameters to control the output of the charging driving voltage of the driver chip 41. This avoids the energy waste caused by the traditional fixed parameter driving method and effectively solves the voltage fluctuation problem during large-area refresh. In the actual application scenario of low temperature environment, the driver module 40 automatically generates a temperature compensation signal to adjust the driving voltage parameters through a temperature adaptive compensation mechanism to control the output of the charging driving voltage of the driver chip 41, effectively maintaining the driving stability of the driver module 40 and overcoming the impact of extreme temperature on the display effect. At the same time, the charging driving voltage output by the driver module 40 is adjusted through the real-time feedback mechanism of the voltage amplification driver module 40 to ensure the uniformity and stability of display brightness under different application scenarios.

[0116] Furthermore, in some other feasible embodiments, the actual application scenarios include partial pixel refresh scenarios and low-temperature environment scenarios; the driving module 40 includes:

[0117] The local update control unit 42 is configured to detect pixel change areas in the display area where data changes occur during the local pixel refresh scenario, generate a corresponding charging control signal based on the area ratio and grayscale average value of the pixel area, and trigger the driver chip 41 to output a charging drive voltage that matches the charging control signal.

[0118] In this embodiment, the local update control unit 42 scans the pixel data changes in the display area of ​​the display panel in real time to obtain the pixel change area where pixel data updates have occurred; then, it calculates the area ratio of the number of pixels in the pixel change area to the total number of pixels in the display area, and calculates the grayscale average value of all pixels in the pixel change area; then, it outputs the area ratio and the grayscale average value to a preset optimization algorithm model, so that the optimization algorithm model can generate a charging control signal that dynamically adjusts the driving parameters based on the weighted combination coefficient of the area ratio and the grayscale average value.

[0119] It should be noted that the expression of this optimization algorithm model is K=w1*α+w2*β, where α is the area proportion; w1 is the weight coefficient of the area proportion; β is the gray average value; w2 is the weight coefficient of the gray average value; and K is the weighted combination coefficient.

[0120] In a specific embodiment, when the area ratio is less than a preset area ratio threshold, the initial charging voltage amplitude and pixel refresh charging time for the small area refresh are calculated based on an optimized algorithm model. Next, when the average grayscale value is less than a preset grayscale threshold, a positive slope compensation (+0.05V / μs*(X-β) / 64) is applied to the initial charging voltage amplitude to calculate the actual charging voltage amplitude. μs refers to the time unit microsecond, and X refers to the preset grayscale threshold, which can be 128. The above is only one feasible implementation method. Please do not impose any restrictions here; or / and, when the average grayscale value is less than the preset grayscale threshold, the initial charging voltage amplitude value should be compensated with a negative slope (-0.05V / μs*(X-β) / 64) to obtain the actual charging voltage amplitude value; then, a charging control signal carrying the actual charging voltage amplitude value and the pixel refresh charging time is output to the driver chip 41, so that the driver chip 41 can delay the pixel refresh charging time under the action of the charging control signal to provide the voltage amplification driving module 40 with a charging driving voltage characterizing the actual charging voltage amplitude value.

[0121] In addition, it should be noted that the initial charging voltage amplitude is calculated based on the formula V=V0*(1-K), where V is the initial charging voltage amplitude, V0 is the preset reference charging voltage, and K is the weighted combination coefficient.

[0122] The pixel refresh charging time is calculated based on the formula T=T0*(1-K), where V is the pixel refresh charging time, T0 is the preset baseline charging time, and K is the weighted combination coefficient.

[0123] In another embodiment, when the area ratio is greater than a preset area ratio threshold, the current charging voltage amplitude value V_adj for the large area refresh is calculated according to the formula V_adj=V0*(1+K). Then, a charging control signal carrying the current charging voltage amplitude value and a dual-stage drive control command is generated and sent to the driver chip 41. At this time, the driver chip 41, based on the dual-stage drive control command, quickly charges to 92% V_adj at a high slope (2.5V / μs), then switches from a high slope to a low slope (0.4V / μs) to buffer the remaining 8% V_adj to prevent overcharging.

[0124] Temperature compensation unit 43 is configured to detect the operating temperature of the display panel in the low-temperature environment scenario, and when the operating temperature is less than a preset critical low temperature threshold, output a temperature compensation signal to the driver chip 41 so that the driver chip 41 can output a charging drive voltage that matches the temperature compensation signal.

[0125] In this embodiment, in a low-temperature environment, the temperature compensation unit 43 detects the working temperature T_work in real time through a temperature sensor integrated on the display panel. When T_work is lower than the preset critical low temperature threshold T_c (usually set to 0℃), the temperature compensation mechanism is activated to overcome the impact of extreme temperature on the display effect. Specifically, firstly, the basic compensation coefficient K_T = 1 + k * ΔT is calculated based on the temperature difference ΔT = T_c - T_work, where k is a temperature sensitivity coefficient related to material properties. Next, nonlinear correction is performed by combining the average grayscale value β of the current frame to generate a temperature compensation voltage V_comp = V0 * [K_T + 0.2tan(β / 128)], where the tan(β / 128) function is used to smooth the grayscale effect. Then, this temperature compensation voltage is superimposed on the reference charging voltage to obtain the final compensation voltage amplitude, and the charging time T_comp is extended to T_comp = T0 * [1 + 0.5(ΔT / 10)^1.3]. Subsequently, a temperature compensation signal carrying the final compensation voltage and the charging time T_comp is output to the driver chip 41, so that the driver chip 41 can extend the charging time T_comp under the action of the temperature compensation signal to provide the voltage amplification driving module 40 with a charging driving voltage that represents the final compensation voltage amplitude, ensuring that the display uniformity can still be maintained when the carrier mobility decreases in a low-temperature environment.

[0126] In addition, this application also provides a display device. Please refer to... Figure 12 , Figure 12 This is a schematic diagram of the structure of a display device involved in an embodiment of this application. Specifically, the display device in this embodiment may be a device for locally running a charging drive method.

[0127] like Figure 12 As shown, the display device in this embodiment may include: a display panel or processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0128] The memory 1005 is disposed on the main body of the display device. The memory 1005 stores a program that performs corresponding operations when executed by the processor 1001. The memory 1005 is also used to store parameters used by the display device. The memory 1005 can be a high-speed RAM or a stable, non-volatile memory, such as a disk storage device. Optionally, the memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0129] Those skilled in the art will understand that Figure 12 The display device structure shown does not constitute a limitation on the display device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0130] like Figure 12 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a charging driver.

[0131] exist Figure 12 In the display device shown, the processor 1001 can be used to call the charging driver stored in the memory 1005 and execute the steps of the charging driver method as described above.

[0132] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0133] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0134] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a display device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0135] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A charging drive circuit, characterized in that, The charging drive circuit includes: A voltage amplification drive module, wherein the inverting terminal of the voltage amplification drive module is electrically connected to the voltage output terminal of the voltage amplification drive module, and the voltage amplification drive module is configured to receive the charging feedback voltage of the voltage output terminal through the inverting terminal when the drive chip provides a charging drive voltage to the non-inverting terminal of the voltage amplification drive module, and determine the drive adjustment result based on the charging drive voltage and the charging feedback voltage; A first drive adjustment module is electrically connected to the first control terminal of the voltage amplification drive module. The first drive adjustment module is configured to control the power supply voltage to charge the voltage output terminal based on the drive adjustment result being a voltage boost state. The second drive adjustment module is electrically connected to the second control terminal of the voltage amplification drive module. The second drive adjustment module is configured to control the voltage output terminal to discharge to ground based on the drive adjustment result being a voltage drop state. The charging drive circuit also includes a timing control module, a first switch, and a second switch. The first terminal of the first switch is electrically connected to the output terminal of the first drive adjustment module, and the second terminal of the first switch is electrically connected to the first control terminal of the voltage amplification drive module. The control terminal of the first switch is electrically connected to the first switch control terminal of the timing control module. The first terminal of the second switch is electrically connected to the output terminal of the second drive adjustment module, and the second terminal of the second switch is electrically connected to the second control terminal of the voltage amplification drive module. The control terminal of the second switch is electrically connected to the second switch control terminal of the timing control module. The voltage amplification drive module includes a potential follower that integrates a first MOSFET and a second MOSFET. The positive input terminal of the potential follower is electrically connected to the driver chip, and the negative input terminal of the potential follower is electrically connected to the potential output terminal of the potential follower. The positive input terminal of the potential follower is the non-inverting input of the voltage amplification driver module, the negative input terminal of the potential follower is the inverting input of the voltage amplification driver module, and the potential output terminal of the potential follower is the voltage output terminal of the voltage amplification driver module. The first path terminal of the first MOS transistor is electrically connected to the power supply terminal, and the first path terminal of the first MOS transistor is electrically connected to the first path terminal of the second MOS transistor. The connection point of the first path terminal of the first MOS transistor connected to the first path terminal of the second MOS transistor is electrically connected to the potential output terminal of the potential follower. The second path of the second MOS transistor is grounded. The gate terminal of the first MOS transistor constitutes the first control terminal and is electrically connected to the first drive adjustment module, and the gate terminal of the second MOS transistor constitutes the second control terminal and is electrically connected to the second drive adjustment module.

2. The charging drive circuit as described in claim 1, characterized in that, The first drive adjustment module includes a first resistor, a second resistor, a first capacitor, a first parallel unit, and a first operational amplifier. The inverting input terminal of the first operational amplifier is electrically connected to the first terminal of the first resistor and the first terminal of the first parallel unit, respectively. The second terminal of the first resistor is electrically connected to the first inverting voltage terminal. The first operational output terminal of the first operational amplifier is electrically connected to the first control terminal. The second terminal of the first parallel unit is electrically connected between the first operational output terminal and the first control terminal. The non-inverting input terminal of the first operational amplifier is electrically connected to the first terminal of the second resistor and the first terminal of the first capacitor, respectively. The second terminal of the second resistor is electrically connected to the first non-inverting voltage terminal. The second terminal of the first capacitor is grounded. The second drive adjustment module includes a third resistor, a fourth resistor, a second capacitor, a second parallel unit, and a second operational amplifier. The out-of-phase input terminal of the second operational amplifier is electrically connected to the first terminal of the third resistor and the first terminal of the second parallel unit, respectively. The second terminal of the third resistor is electrically connected to the second out-of-phase voltage terminal. The second operational output terminal of the second operational amplifier is electrically connected to the second control terminal. The second terminal of the second parallel unit is electrically connected between the second operational output terminal and the second control terminal. The non-in-phase input terminal of the second operational amplifier is electrically connected to the first terminal of the fourth resistor and the first terminal of the second capacitor, respectively. The second terminal of the fourth resistor is electrically connected to the second non-in-phase voltage terminal. The second terminal of the second capacitor is grounded.

3. The charging drive circuit as described in claim 1, wherein the timing control module includes a timing control chip, and a communication receiver and a counter integrated within the drive chip; The timing control chip is connected to the communication receiver, the clock input source of the counter is connected to the clock signal source of the communication receiver, and the counting storage end of the counter is connected to the preset counting transmission end of the communication receiver.

4. A charging driving method, characterized in that, The charging driving method is applied to the charging driving circuit according to any one of claims 1 to 3, and the charging driving method includes: When the charging drive voltage of the driver chip is detected, the charging feedback voltage of the voltage amplification drive module is determined, and the voltage amplification drive module is controlled to determine the drive adjustment result based on the charging drive voltage and the charging feedback voltage. The first drive adjustment module is controlled to charge the voltage output terminal of the voltage amplification drive module with the drive power supply voltage according to the drive adjustment result indicating a voltage boost state; or, The second drive adjustment module is controlled to drive the voltage output terminal to discharge to ground based on the drive adjustment result indicating a voltage drop.

5. The charging driving method as described in claim 4, characterized in that, The charging driving method further includes: The driving time of the target driving adjustment module is determined based on the charging driving requirements of the display panel. The target driving adjustment module is any one of the first driving adjustment module and the second driving adjustment module. Determine the signal period of the preset clock signal source, and determine the counting threshold based on the driving time and the signal period; When the target drive adjustment module controls the voltage output terminal according to the drive adjustment result, it accumulates the number of occurrences of the preset clock signal source until the number of occurrences reaches the counting threshold, at which point the target drive adjustment module is turned off.

6. A display panel, characterized in that, The display panel includes the charging drive circuit according to any one of claims 1 to 3; A driver module integrating a driver chip is configured to trigger the driver chip to provide a charging drive voltage to the non-inverting terminal of the voltage amplification driver module according to the actual application scenario.

7. The display panel as described in claim 6, characterized in that, The practical application scenarios include partial pixel refresh scenarios and low-temperature environment scenarios; The driving module includes: A local update control unit is configured to detect pixel change areas in the display area where data changes occur during the local pixel refresh scenario, generate a corresponding charging control signal based on the area ratio and grayscale average value of the pixel change area, and trigger the driver chip to output a charging drive voltage that matches the charging control signal. A temperature compensation unit is configured to detect the operating temperature of the display panel in the low-temperature environment and output a temperature compensation signal to the driver chip when the operating temperature is lower than a preset critical low-temperature threshold, so that the driver chip can output a charging drive voltage that matches the temperature compensation signal.

8. A display device, characterized in that, The display device includes the display panel as described in claim 6; or, A memory, a processor, and a charging driver stored in the memory and executable on the processor, wherein the processor, when executing the charging driver, implements the steps of the charging driving method as described in any one of claims 4 to 5.

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