Processing method of coreless packaging substrate and coreless packaging substrate

Abstract

The embodiment of the invention provides a coreless packaging substrate processing method and a coreless packaging substrate, and the method comprises the steps: providing a supporting plate which comprises a base material, first copper foils attached to the two sides of the base material, and second copper foils attached to the first copper foils; pressing a first prepreg and a third copper foil on the second copper foil; performing pattern manufacturing on the third copper foil to form a circuit pattern; a second prepreg and a fourth copper foil are pressed on the third copper foil, and the thickness of the second prepreg is different from that of the first prepreg, so that the thickness of a second dielectric layer formed by curing the second prepreg is the same as that of a first dielectric layer formed by curing the first prepreg; and separating the first copper foil from the second copper foil to obtain two coreless packaging substrates. According to the processing method provided by the embodiment of the invention, substrate warping caused by uneven stress of the first dielectric layer and the second dielectric layer can be reduced, so that the warping degree of the coreless packaging substrate can be reduced, and the production yield of a subsequent process is improved.

Description

Technical Field

[0001] This application relates to the field of packaging substrate processing technology, and in particular to a processing method for a coreless packaging substrate and a coreless packaging substrate. Background Technology

[0002] With the development of ultra-thin semiconductor chips, the requirements for ultra-thin packaging substrates are also becoming increasingly stringent. Coreless packaging substrates, due to the removal of the core layer, offer the advantage of thinner substrate thickness compared to conventional packaging substrates. The dielectric layers of coreless packaging substrates are prepregs made of fiberglass cloth impregnated with BT resin. Layering requires high temperature and high pressure to bond and cure the prepregs.

[0003] Currently, in the industry, when adding layers to coreless packaging substrates, each layer uses prepreg of the same thickness. Due to differences in copper thickness and residual copper content in each layer, the actual thickness of each dielectric layer after curing varies significantly. This inconsistency in dielectric layer thickness leads to uneven stress after curing shrinkage. Without a core layer for support, the warpage of the coreless packaging substrate can reach 15-30mm, severely affecting subsequent manufacturing processes. Summary of the Invention

[0004] This application provides a method for processing a coreless packaging substrate and a coreless packaging substrate, which can reduce the warpage of the coreless packaging substrate and improve the production yield of subsequent processes.

[0005] This application provides a method for processing a coreless packaging substrate, including: A support plate is provided, the support plate comprising a substrate, a first copper foil attached to both sides of the substrate, and a second copper foil attached to the first copper foil; A first prepreg and a third copper foil are laminated onto the second copper foil; A pattern is fabricated on the third copper foil to form a circuit pattern; A second prepreg and a fourth copper foil are laminated onto the third copper foil, wherein the thickness of the second prepreg is different from the thickness of the first prepreg, so that the thickness of the second dielectric layer formed by the curing of the second prepreg is the same as the thickness of the first dielectric layer formed by the curing of the first prepreg. The first copper foil and the second copper foil are separated to obtain two coreless packaging substrates. The coreless packaging substrates include a second copper foil, a first prepreg, a third copper foil, a second prepreg, and a fourth copper foil stacked in sequence.

[0006] In some embodiments, before the first prepreg and the third copper foil are laminated onto the second copper foil, the method further includes: performing a first drilling to form a plurality of first through holes extending from one side of the second copper foil to the other side of the second copper foil; After the first prepreg and the third copper foil are laminated onto the second copper foil, the process further includes: performing a second drilling to form a plurality of second through holes extending from one side of the third copper foil to the other side of the third copper foil.

[0007] In some embodiments, the thickness of the first dielectric layer is calculated according to the following formula: Te1=Ta-3.14*(D1 / 2)²*N1*t / S Where Te1 is the thickness of the first dielectric layer, Ta is the thickness of the first prepreg, D1 is the diameter of the first through-hole, N1 is the number of holes in the first through-hole, t is the thickness of the coreless packaging substrate, and S is the area of ​​the coreless packaging substrate.

[0008] In some embodiments, the thickness of the second dielectric layer is calculated according to the following formula: Te2=Tb-3.14*(D2 / 2)²*N2*t / S-Tc*(1-c%) Where Te2 is the thickness of the second dielectric layer, Tb is the thickness of the second prepreg, D2 is the aperture of the second via, N2 is the number of vias, Tc is the thickness of the third copper foil, and c% is the residual copper percentage after the third copper foil forms the circuit pattern.

[0009] In some embodiments, the bonding conditions for laminating the first prepreg and the third copper foil onto the second copper foil are different from the bonding conditions for laminating the second prepreg and the fourth copper foil onto the third copper foil, so that the amount of resin overflow of the first prepreg is greater than the amount of resin overflow of the second prepreg.

[0010] In some embodiments, the heating rate when pressing the first prepreg and the third copper foil onto the second copper foil is less than the heating rate when pressing the second prepreg and the fourth copper foil onto the third copper foil, so as to prolong the melt flow time of the first prepreg.

[0011] In some embodiments, the high-voltage transition temperature when pressing the first prepreg and the third copper foil onto the second copper foil is lower than the high-voltage transition temperature when pressing the second prepreg and the fourth copper foil onto the third copper foil, so as to accelerate the resin flowability of the first prepreg.

[0012] In some embodiments, the highest pressure when pressing the first prepreg and the third copper foil onto the second copper foil is greater than the highest pressure when pressing the second prepreg and the fourth copper foil onto the third copper foil, so as to accelerate the resin flowability of the first prepreg.

[0013] In some embodiments, the roughness of the second copper foil is greater than that of the fourth copper foil, so that the amount of the first prepreg filling the second copper foil is greater than the amount of the second prepreg filling the fourth copper foil.

[0014] This application also provides a coreless packaging substrate, which is prepared by any of the processing methods described above.

[0015] In the processing method of the coreless packaging substrate provided in this application embodiment, the thickness of the second prepreg is different from that of the first prepreg, which enables the thickness of the second dielectric layer formed by the curing of the second prepreg to be the same as the thickness of the first dielectric layer formed by the curing of the first prepreg. Therefore, after separating the first copper foil and the second copper foil to obtain two coreless packaging substrates, it is possible to ensure that the stress generated by the curing shrinkage of the first dielectric layer and the second dielectric layer of the coreless packaging substrate is uniform, reducing the warping of the substrate caused by uneven stress. Therefore, it is possible to reduce the warping of the coreless packaging substrate and improve the production yield of subsequent processes. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the first process of processing a coreless packaging substrate according to an embodiment of this application.

[0018] Figure 2 A schematic diagram of a support plate is provided for the processing method of this application embodiment.

[0019] Figure 3 This is a schematic diagram illustrating the processing method of this application, which involves pressing a first prepreg and a third copper foil together.

[0020] Figure 4 This is a schematic diagram of the processing method of this application for forming a circuit pattern on a third copper foil.

[0021] Figure 5 This is a schematic diagram illustrating the processing method of this application for pressing a second prepreg and a fourth copper foil.

[0022] Figure 6 This is a schematic diagram of the coreless packaging substrate obtained by the processing method of this application embodiment.

[0023] Figure 7 This is a schematic diagram of a second process for processing a coreless packaging substrate according to an embodiment of this application.

[0024] Figure 8 This table compares experimental data on dielectric layer thickness and warpage of coreless packaging substrates for traditional solutions and solutions proposed in this application.

[0025] Figure 9 This is a temperature and pressure curve diagram of the processing method of this application for pressing the first semi-cured sheet and the third copper foil.

[0026] Figure 10 This is a temperature and pressure curve diagram of the processing method of this application for pressing the second prepreg and the fourth copper foil. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0028] This application provides a method for processing a coreless packaging substrate, which can reduce the warpage of the coreless packaging substrate and improve the production yield of subsequent processes.

[0029] refer to Figure 1 , Figure 1 This is a schematic diagram of a first process for processing a coreless packaging substrate according to an embodiment of this application. The processing method includes the following steps: 11. A support plate is provided, the support plate including a substrate, a first copper foil attached to both sides of the substrate, and a second copper foil attached to the first copper foil; 12. Press the first prepreg and the third copper foil onto the second copper foil; 13. Create a pattern on the third copper foil to form a circuit pattern; 14. A second prepreg and a fourth copper foil are laminated on a third copper foil, wherein the thickness of the second prepreg is different from the thickness of the first prepreg, so that the thickness of the second dielectric layer formed by the curing of the second prepreg is the same as the thickness of the first dielectric layer formed by the curing of the first prepreg. 15. Separate the first copper foil from the second copper foil to obtain two coreless packaging substrates. The coreless packaging substrates include a second copper foil, a first prepreg, a third copper foil, a second prepreg, and a fourth copper foil stacked in sequence.

[0030] Please refer to the above. Figures 2 to 6 , Figure 2 A schematic diagram of a support plate is provided for the processing method of this application embodiment. Figure 3 This is a schematic diagram illustrating the processing method of this application, which involves pressing together a first prepreg and a third copper foil. Figure 4 This is a schematic diagram illustrating the processing method of this application for forming a circuit pattern on a third copper foil. Figure 5This is a schematic diagram illustrating the processing method of this application, which involves laminating a second prepreg and a fourth copper foil. Figure 6 This is a schematic diagram of the coreless packaging substrate obtained by the processing method of this application embodiment.

[0031] First, a support plate is provided, which serves as a support material during the subsequent pressing process. This support plate can be referred to as the Detach Core. For example... Figure 2 As shown, the support plate includes a substrate 21, a first copper foil 22 attached to both sides of the substrate 21, and a second copper foil 23 attached to the first copper foil 22. In one example, the thickness of the first copper foil 22 is 18 μm, and the thickness of the second copper foil 23 is 3 μm. The first copper foil 22 is a carrier copper foil, and the second copper foil 23 is an ultrathin copper foil.

[0032] Subsequently, the first prepreg 24 and the third copper foil 25 are laminated onto the second copper foil 23, as follows: Figure 3 As shown. It should be noted that the first prepreg 24 and the third copper foil 25 are laminated onto the second copper foil 23 on each side. The lamination process needs to be carried out under certain temperature and pressure conditions. In one example, the thickness of the third copper foil 25 is 12 μm.

[0033] Subsequently, patterns are fabricated on the third copper foil 25 to form a circuit pattern, such as... Figure 4 As shown, a circuit pattern 251 is formed on the third copper foil 25. Specifically, the circuit pattern 251 can be formed through processes such as film lamination, exposure, development, and etching.

[0034] Subsequently, as Figure 5 As shown, a second prepreg 26 and a fourth copper foil 27 are laminated onto the third copper foil 25. The thickness of the second prepreg 26 is different from the thickness of the first prepreg 24, so that the thickness of the second dielectric layer formed by the second prepreg 26 is the same as the thickness of the first dielectric layer formed by the first prepreg 24. Specifically, the thickness of the second prepreg 26 can be calculated based on the thickness of the first prepreg 24 and the requirement that the thickness of the second dielectric layer be the same as the thickness of the first dielectric layer. It should be noted that the second prepreg 26 and the fourth copper foil 27 are laminated onto the third copper foil 25 on each side. The lamination process also needs to be carried out under certain temperature and pressure conditions. In one example, the fourth copper foil 27 is an ultra-thin copper foil with a thickness of 3 μm.

[0035] Subsequently, the first copper foil 22 and the second copper foil 23 are separated to obtain two coreless packaging substrates. For example... Figure 6 As shown, the coreless packaging substrate includes a second copper foil 23, a first prepreg 24, a third copper foil 25, a second prepreg 26, and a fourth copper foil 27 stacked in sequence.

[0036] Understandably, in this embodiment, the thickness of the second prepreg 26 is different from the thickness of the first prepreg 24, which enables the thickness of the second dielectric layer formed by the curing of the second prepreg 26 to be the same as the thickness of the first dielectric layer formed by the curing of the first prepreg 24. Therefore, after separating the first copper foil 22 and the second copper foil 23 to obtain two coreless packaging substrates, it is possible to ensure that the stress generated by the curing shrinkage of the first dielectric layer and the second dielectric layer of the coreless packaging substrate is uniform, reducing the substrate warping caused by uneven stress. Thus, the warping of the coreless packaging substrate can be reduced, and the production yield of subsequent processes can be improved.

[0037] Data obtained from actual testing shows that the warpage of existing coreless packaging substrates is as high as 15-30mm, resulting in a horizontal line jamming defect rate of over 10% in subsequent processes. In contrast, the warpage of the coreless packaging substrate in this embodiment can be controlled within 10mm, reducing the horizontal line jamming defect rate to less than 0.5%. Therefore, the coreless packaging substrate of this embodiment can significantly reduce the warpage of the coreless packaging substrate, thereby greatly reducing the defect rate in subsequent processes and improving production yield.

[0038] In some embodiments, reference Figure 7 , Figure 7 This is a schematic diagram of a second process for processing a coreless packaging substrate according to an embodiment of this application.

[0039] Step 12, before pressing the first prepreg and the third copper foil onto the second copper foil, also includes step 16: performing a first drilling to form a plurality of first through holes extending from one side of the second copper foil to the other side of the second copper foil; Step 12, after pressing the first prepreg and the third copper foil onto the second copper foil, also includes step 17: performing a second drilling to form a plurality of second through holes extending from one side of the third copper foil to the other side of the third copper foil.

[0040] In the first drilling process, multiple first through holes are formed on the support plate, extending from one side of the second copper foil 23 to the other side. In practical applications, the first through holes are formed in the edge area of ​​the support plate. The first through holes are used for positioning in subsequent processes and for sealing the edges to prevent accidental separation between the first copper foil 22 and the second copper foil 23.

[0041] The second drilling creates multiple second through holes that extend from one side of the third copper foil 25 to the other side of the third copper foil 25. In practical applications, the second through holes are also formed in the edge area of ​​the support plate, and they can also be used for positioning in subsequent processes.

[0042] In some embodiments, in order to make the thickness of the second dielectric layer formed by the curing of the second prepreg 26 the same as the thickness of the first dielectric layer formed by the curing of the first prepreg 24, the thicknesses of the first prepreg 24 and the second prepreg 26 can be set and calculated in the following manner: When the first prepreg 24 is laminated, both the second copper foil 23 at the bottom and the third copper foil 25 at the top are plain copper foils without any circuit patterns, meaning the residual copper rate is 100%. Based on the principle that the volume of the prepreg resin remains constant during lamination, the thickness of the first dielectric layer formed by the curing of the first prepreg 24 can be calculated as follows: the thickness of the first dielectric layer is equal to the thickness of the first prepreg 24 minus the amount of resin filling the first through-hole. In other words, the thickness of the first dielectric layer is calculated using the following formula: Te1=(Ta*S-3.14*(D1 / 2)²*N1*t) / S=Ta-3.14*(D1 / 2)²*N1*t / S Where Te1 is the thickness of the first dielectric layer, Ta is the thickness of the first prepreg 24, D1 is the diameter of the first through hole, N1 is the number of holes in the first through hole, t is the thickness of the coreless packaging substrate, and S is the area of ​​the coreless packaging substrate (i.e., the area of ​​one side of the support plate).

[0043] During the lamination of the second prepreg 26, the third copper foil 25 at its bottom is etched to form a circuit pattern 251, with a residual copper rate of c%. The fourth copper foil 27 at its top is a plain copper foil without a circuit pattern, meaning the residual copper rate is 100%. Based on the principle that the volume of the prepreg resin remains constant during lamination, the thickness of the second dielectric layer formed by the curing of the second prepreg 26 can be calculated as follows: the thickness of the second prepreg 26 is equal to the thickness of the second prepreg 26 minus the amount of resin filling the second through-hole and the amount of resin filling the gaps in the circuit pattern 251. In other words, the thickness of the second dielectric layer is calculated using the following formula: Te2=(Tb*S-3.14*(D2 / 2)²*N2*t- Tc*(1-c%)*S) / S=Tb-3.14*(D2 / 2)²*N2*t / S-Tc*(1-c%) Where Te2 is the thickness of the second dielectric layer, Tb is the thickness of the second prepreg 26, D2 is the aperture of the second via, N2 is the number of the second vias, t is the thickness of the coreless packaging substrate, S is the area of ​​the coreless packaging substrate (i.e., the area on one side of the support plate), Tc is the thickness of the third copper foil 25, and c% is the residual copper percentage of the third copper foil 25 after forming the circuit pattern 251.

[0044] It should be noted that, since the third copper foil 25 forms a circuit pattern 251 after etching, its residual copper rate is c%. After the entire copper layer is etched to form the circuit (the circuit pattern 251), the exposed copper-free substrate area needs to be filled with prepreg resin. This will cause the thickness of the second dielectric layer on the third copper foil 25 to decrease. Therefore, when calculating Te2 in the above formula, the value of the decrease in the thickness of the second dielectric layer caused by the filling of the copper-free substrate area of ​​the third copper foil 25 with prepreg resin needs to be subtracted, that is, Tc*(1-c%).

[0045] In this embodiment, the thickness of the second dielectric layer is the same as the thickness of the first dielectric layer, i.e., Te2 = Te1. Therefore, the thickness Tb of the second prepreg 26 can be calculated based on the thickness Ta of the first prepreg 24, using the following formula: Tb=Ta-3.14*(D1 / 2)²*N1 / S+3.14*(D2 / 2)²*N2 / S+Tc*(1-c%) For example, the thickness of the prepreg used in the two lamination processes of a 3-layer coreless packaging substrate is as follows: The first prepreg 24 used in the first lamination has a thickness Ta=20um, a first through-hole diameter D1=0.25mm, a first through-hole number N1=10000, a second through-hole diameter D2=0.25mm, a second through-hole number N2=20000, a third copper foil 25 has a thickness Tc=12um, and the residual copper rate after the third copper foil 25 forms the circuit pattern 251 is 50%. The package substrate area S=513mm*623mm=319599mm², so the final calculated thickness Tb of the second prepreg 26 is 26um.

[0046] It should be noted that in practical applications, the diameters of the first through-hole (D1) and the second through-hole (D2) range from 0.25mm to 3.00mm, and the number of the first through-hole (N1) and the number of the second through-hole (N2) range from tens of thousands to millions. Smaller through-hole diameters and fewer through-holes have a smaller impact on the calculation of the thickness Tb of the second prepreg 26; larger through-hole diameters and more through-holes have a greater impact on the calculation of the thickness Tb of the second prepreg 26. In the example above, the diameters of the first through hole D1 and the second through hole D2 are both 0.25 mm, the number of the first through holes N1 = 10000, and the number of the second through holes N2 = 20000. The values ​​of the through hole diameter and the number of through holes are very small, so they have little impact on the calculation of the thickness Tb of the second prepreg 26. As the value of the through hole diameter and the value of the number of through holes increase, the impact on the calculation of the thickness Tb of the second prepreg 26 will become more and more obvious.

[0047] refer to Figure 8 , Figure 8This table compares experimental data on dielectric layer thickness and warpage of the coreless packaging substrate between conventional and proposed solutions. Figure 8 As can be seen, in traditional solutions, the difference between the thickness of the first dielectric layer and the second dielectric layer is significant, resulting in a warpage of 13mm to 20mm for the coreless packaging substrate. In the solution of this application, the difference between the thickness of the first dielectric layer and the second dielectric layer is very small, and their thicknesses are very close, resulting in a warpage of 5mm to 8mm for the coreless packaging substrate. Therefore, the solution of this application can significantly improve the warpage of the coreless packaging substrate.

[0048] In practical applications, the selection of prepreg series and models is mainly based on its dielectric constant Dk and dielectric loss Df. To ensure functionality, each dielectric layer should use the same series of prepregs. The thickness of the same series of prepregs depends on the glass fiber type and resin content. The standard thickness of each model within the same series of prepregs is defined by the manufacturer and cannot be arbitrarily adjusted. Taking the GHPL-830NS series of prepregs as an example, the standard thicknesses of the #1017 model glass fiber with different resin contents are as follows: SF66#1017 20um, SF68#1017 22um, SF70#1017 24um, SF74#1017 29um, SF76#1017 32um, and SF78#1017 35um.

[0049] In the example above, when the first prepreg 24 used in the first lamination is SF66#1017 with a thickness of 20µm, there is no corresponding 26µm prepreg available as the second prepreg 26. In this case, the second prepreg 26 selected is SF70#1017 with a thickness of 24µm, which is the closest in thickness. Therefore, the thickness Te2 of the second dielectric layer after lamination and curing is still 2µm less than the thickness Te1 of the first dielectric layer. Therefore, further optimization and improvement are needed to reduce the warpage caused by the difference in thickness between the first and second dielectric layers.

[0050] In some embodiments, to further reduce the warpage caused by the thickness difference between the first and second dielectric layers, the bonding conditions for laminating the first prepreg 24 and the third copper foil 25 onto the second copper foil 23 are different from the bonding conditions for laminating the second prepreg 26 and the fourth copper foil 27 onto the third copper foil 25, so that the amount of resin overflow of the first prepreg 24 is greater than that of the second prepreg 26, thereby making the thickness of the first dielectric layer approach or equal to the thickness of the second dielectric layer.

[0051] In some embodiments, the heating rate when pressing the first prepreg 24 and the third copper foil 25 onto the second copper foil 23 is less than the heating rate when pressing the second prepreg 26 and the fourth copper foil 27 onto the third copper foil 25, so as to prolong the melt flow time of the first prepreg 24.

[0052] For example, in one instance, when the first prepreg 24 and the third copper foil 25 are laminated onto the second copper foil 23, the heating rate is 2.0℃ / min to 2.5℃ / min; when the second prepreg 26 and the fourth copper foil 27 are laminated onto the third copper foil 25, the heating rate is 3.0℃ / min to 3.5℃ / min. Therefore, relative to the second prepreg 26, the melt flow time of the first prepreg 24 can be extended, and the amount of adhesive overflow during the lamination of the first prepreg 24 can be increased.

[0053] In some embodiments, the high-voltage transition temperature when pressing the first prepreg 24 and the third copper foil 25 onto the second copper foil 23 is lower than the high-voltage transition temperature when pressing the second prepreg 26 and the fourth copper foil 27 onto the third copper foil 25, so as to accelerate the resin flowability of the first prepreg 24.

[0054] For example, in one instance, when pressing the first prepreg 24 and the third copper foil 25 onto the second copper foil 23, the high-pressure transition temperature is 130°C to 140°C; when pressing the second prepreg 26 and the fourth copper foil 27 onto the third copper foil 25, the high-pressure transition temperature is 150°C to 160°C. Therefore, it is possible to accelerate resin flow by applying high pressure before the lowest viscosity point of the first prepreg 24.

[0055] In some embodiments, the highest pressure when pressing the first prepreg 24 and the third copper foil 25 onto the second copper foil 23 is greater than the highest pressure when pressing the second prepreg 26 and the fourth copper foil 27 onto the third copper foil 25, so as to accelerate the resin flowability of the first prepreg 24.

[0056] For example, in one instance, when the first prepreg 24 and the third copper foil 25 are pressed onto the second copper foil 23, the maximum pressure is 45 kg / cm² to 50 kg / cm²; when the second prepreg 26 and the fourth copper foil 27 are pressed onto the third copper foil 25, the maximum pressure is 35 kg / cm² to 40 kg / cm². Therefore, the pressure on the resin in the first prepreg 24 promotes resin flow.

[0057] refer to Figure 9 and Figure 10 , Figure 9 This is a temperature and pressure curve diagram of the processing method of this application for pressing the first prepreg 24 and the third copper foil 25 together. Figure 10 This is a temperature and pressure curve of the processing method of this application for pressing the second semi-cured sheet 26 and the fourth copper foil 27 together. Figure 9 Semi-cured sheet A indicates the first semi-cured sheet 24. Figure 10 The term "medium-prepreg B" indicates the second half-prepreg, 26.

[0058] like Figure 9As shown, the temperature settings for the prepreg A lamination process are as follows: the first stage temperature rises from the initial temperature of 30~50℃ to 180℃ in 40~50 minutes; the second stage temperature is 180℃ and held for 20~30 minutes; the third stage temperature rises from 180℃ to 220℃ in 5~10 minutes; the fourth stage temperature is 220℃ and held for 90~110 minutes; and the fifth stage temperature drops from 220℃ to 40~60℃ in 40~60 minutes.

[0059] The pressure settings for the prepreg A lamination process are as follows: Stage 1: Initial pressure 5~10 kg / cm², constant pressure time 10~15 min; Stage 2: Pressure increases from 5~10 kg / cm² to 25~35 kg / cm², time 5~10 min; Stage 3: Pressure 25~35 kg / cm², constant pressure 10~15 min; Stage 4: Pressure increases from 25~35 kg / cm² to 45~50 kg / cm², time 10~20 min; Stage 5: Pressure 45~50 kg / cm², constant pressure 140~160 min; Stage 6: Pressure decreases from 45~50 kg / cm² to 5~10 kg / cm², then constant pressure 30~40 min.

[0060] like Figure 10 As shown, the temperature settings for the prepreg B lamination process are as follows: the first stage temperature rises from the initial temperature of 30~50℃ to 180℃ in 25~35 minutes; the second stage temperature is 180℃ and held for 35~45 minutes; the third stage temperature rises from 180℃ to 220℃ in 5~10 minutes; the fourth stage temperature is 220℃ and held for 90~110 minutes; and the fifth stage temperature drops from 220℃ to 40~60℃ in 40~60 minutes.

[0061] The pressure settings for the prepreg B lamination process are as follows: First stage: initial pressure 5~10 kg / cm², constant pressure time 15~20 min; Second stage: pressure increases from 5~10 kg / cm² to 25~35 kg / cm², time 5~10 min; Third stage: pressure 25~35 kg / cm², constant pressure 15~20 min; Fourth stage: pressure increases from 25~35 kg / cm² to 45~50 kg / cm², time 15~25 min; Fifth stage: pressure 45~50 kg / cm², constant pressure 130~150 min; Sixth stage: pressure decreases from 45~50 kg / cm² to 5~10 kg / cm², then constant pressure 30~40 min.

[0062] By adjusting the bonding conditions of the first prepreg 24 and the second prepreg 26 as described above, the amount of adhesive overflow of the first prepreg 24 can be increased from 3%~5% before the adjustment to 8%~10%, which is about 5% more than before the adjustment. Its thickness after bonding and curing can be reduced by 20um*5%=1um. At this time, the thickness Te2 of the second dielectric layer is reduced from 2um less than the thickness Te1 of the first dielectric layer to 1um less. Therefore, the thickness difference between the second dielectric layer and the first dielectric layer can be further reduced, thereby further reducing the warpage of the coreless packaging substrate.

[0063] In some embodiments, to further reduce the warpage caused by the thickness difference between the first dielectric layer and the second dielectric layer, the roughness of the second copper foil 23 may be made greater than the roughness of the fourth copper foil 27, so that the amount of the first prepreg 24 filling the second copper foil 23 is greater than the amount of the second prepreg 26 filling the fourth copper foil 27.

[0064] For example, in one instance, the second copper foil 23 can use an ultra-low copper foil with Rz=2.2µm, and the fourth copper foil 27 can use an extremely low copper foil with Rz=1.3µm. Therefore, the amount of the first prepreg 24 filling the second copper foil 23 is 2.2µm*(1 / 2)-1.3µm*(1 / 2)=0.45µm more than the amount of the second prepreg 26 filling the fourth copper foil 27. At this point, the thickness Te2 of the second dielectric layer is reduced from 1µm less than the thickness Te1 of the first dielectric layer to 0.55µm less. Therefore, the thickness difference between the second and first dielectric layers can be further reduced, thereby further reducing the warpage of the coreless packaging substrate.

[0065] In practical applications, copper foil of different thicknesses has various specifications for copper tooth roughness. For example, when replacing 3µm thick copper foil with 12µm thick copper foil, the copper tooth roughness can be selected from 1.5 to 4.5, and the difference in dielectric layer thickness can be as high as 4.5µm*(1 / 2)-1.5µm*(1 / 2)=1.5µm.

[0066] The above methods, including using prepregs of varying thicknesses (resin content), controlling resin overflow by adjusting the prepreg lamination conditions, and employing copper foils with different copper foil roughness, are used to collectively reduce the thickness difference between the first and second dielectric layers, thereby reducing the warpage of the coreless packaging substrate. In practical applications, one or more of these methods can be combined based on the specific product requirements to minimize the warpage of the final coreless packaging substrate.

[0067] This application also provides a coreless packaging substrate, which is prepared by the processing method of any of the above embodiments.

[0068] In the description of this application, it should be understood that terms such as “first” and “second” are used only to distinguish similar objects and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0069] The processing method of the coreless packaging substrate and the coreless packaging substrate provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for processing a coreless packaging substrate, characterized in that, include: A support plate is provided, the support plate comprising a substrate, a first copper foil attached to both sides of the substrate, and a second copper foil attached to the first copper foil; A first prepreg and a third copper foil are laminated onto the second copper foil; A pattern is fabricated on the third copper foil to form a circuit pattern; A second prepreg and a fourth copper foil are laminated onto the third copper foil, wherein the thickness of the second prepreg is different from the thickness of the first prepreg, so that the thickness of the second dielectric layer formed by the curing of the second prepreg is the same as the thickness of the first dielectric layer formed by the curing of the first prepreg. The first copper foil and the second copper foil are separated to obtain two coreless packaging substrates. The coreless packaging substrates include a second copper foil, a first prepreg, a third copper foil, a second prepreg, and a fourth copper foil stacked in sequence.

2. The processing method according to claim 1, characterized in that: Before pressing the first prepreg and the third copper foil onto the second copper foil, the method further includes: performing a first drilling to form a plurality of first through holes extending from one side of the second copper foil to the other side of the second copper foil; After the first prepreg and the third copper foil are laminated onto the second copper foil, the process further includes: performing a second drilling to form a plurality of second through holes extending from one side of the third copper foil to the other side of the third copper foil.

3. The processing method according to claim 2, characterized in that, The thickness of the first dielectric layer is calculated according to the following formula: Te1=Ta-3.14*(D1 / 2)²*N1*t / S Where Te1 is the thickness of the first dielectric layer, Ta is the thickness of the first prepreg, D1 is the diameter of the first through-hole, N1 is the number of holes in the first through-hole, t is the thickness of the coreless packaging substrate, and S is the area of ​​the coreless packaging substrate.

4. The processing method according to claim 3, characterized in that, The thickness of the second dielectric layer is calculated according to the following formula: Te2=Tb-3.14*(D2 / 2)²*N2*t / S-Tc*(1-c%) Where Te2 is the thickness of the second dielectric layer, Tb is the thickness of the second prepreg, D2 is the aperture of the second via, N2 is the number of vias, Tc is the thickness of the third copper foil, and c% is the residual copper percentage after the third copper foil forms the circuit pattern.

5. The processing method according to any one of claims 1 to 4, characterized in that, The bonding conditions for laminating the first prepreg and the third copper foil onto the second copper foil are different from the bonding conditions for laminating the second prepreg and the fourth copper foil onto the third copper foil, so that the amount of resin overflow of the first prepreg is greater than the amount of resin overflow of the second prepreg.

6. The processing method according to claim 5, characterized in that, The heating rate when pressing the first prepreg and the third copper foil onto the second copper foil is less than the heating rate when pressing the second prepreg and the fourth copper foil onto the third copper foil, so as to prolong the melt flow time of the first prepreg.

7. The processing method according to claim 5, characterized in that, The high-voltage transition temperature when pressing the first prepreg and the third copper foil onto the second copper foil is lower than the high-voltage transition temperature when pressing the second prepreg and the fourth copper foil onto the third copper foil, so as to accelerate the resin flowability of the first prepreg.

8. The processing method according to claim 5, characterized in that, The highest pressure applied when pressing the first prepreg and the third copper foil onto the second copper foil is greater than the highest pressure applied when pressing the second prepreg and the fourth copper foil onto the third copper foil, so as to accelerate the resin flowability of the first prepreg.

9. The processing method according to any one of claims 1 to 4, characterized in that, The roughness of the second copper foil is greater than that of the fourth copper foil, so that the amount of the first prepreg filling the second copper foil is greater than the amount of the second prepreg filling the fourth copper foil.

10. A coreless packaging substrate, characterized in that, The coreless packaging substrate is prepared by the processing method described in any one of claims 1 to 9.

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