Semiconductor device and preparation method thereof
By forming the first trench and uniformly doping it in the SGT-MOSFET device, the problems of high resistance and breakdown in the accumulation region are solved, and the uniformity of current distribution and device reliability are improved.
Patent Information
- Application Number
- CN202510969543.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-14
- Publication Date
- 2025-11-11
AI Technical Summary
Traditional SGT-MOSFET devices have high accumulation region resistance RA and channel drift region resistance RD. The excessively high ion doping concentration at the bottom of the deep trench makes the device susceptible to high voltage breakdown.
By forming a first trench in the epitaxial layer and performing ion doping, followed by etching to form a second trench, and then using a diffusion process to uniformly dope the sidewalls and bottomwalls of the trench, the resistance is reduced and the current concentration is decreased, thus avoiding electric field concentration.
The accumulation region resistance RA and drift region resistance RD are reduced, avoiding breakdown caused by electric field concentration, and improving the reliability and current distribution uniformity of the device.
Smart Images
Figure CN120933228A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a semiconductor device and its fabrication method. Background Technology
[0002] The on-resistance Rdon of an SGT-MOSFET (Shielded Gate Trench Metal-Oxide-Semiconductor Field-Effect Transistor) includes many types of resistance, which can be categorized based on the current flow path: source contact resistance R... SC Source resistance R SOURCE Channel resistance R CH Accumulation region resistance R A Drift region resistance R D Substrate resistance R SUB and drain contact resistance R DC Among them, the source contact resistance R SC Source resistance R SOURCE and drain contact resistance R DC The values of these are very small and can be ignored. Therefore, the main factor affecting the on-resistance Rdon is the channel resistance R. CH Accumulation region resistance R A and drift region resistance R D .
[0003] When a positive bias voltage is applied to the device gate, the current flowing from the inversion layer into the drift region passes through an accumulation layer, causing electrons to flow along the trench surface, thus generating an accumulation region resistance R. A Among them, the accumulation region resistance R A It is inversely proportional to the electron mobility of the accumulation layer.
[0004] Those skilled in the art have observed that, during the forward conduction of a conventional SGT-MOSFET device, the current density is primarily concentrated near the trench sidewalls, regardless of whether it is in the accumulation or drift region, leading to a decrease in the accumulation region resistance R. A and channel drift region resistance R D The concentration is relatively high. Furthermore, those skilled in the art have discovered that when the ion doping concentration at the bottom of the deep trench is too high, the device is prone to breakdown due to excessively concentrated electric field. Summary of the Invention
[0005] This application provides a semiconductor device and its fabrication method, which can solve the problem of the accumulation region resistance R of traditional SGT-MOSFET devices. A and channel drift region resistance R D The problem is at least one of the following: the high ion doping concentration at the bottom of the deep trench makes the device susceptible to high voltage breakdown.
[0006] On one hand, embodiments of this application provide a method for fabricating a semiconductor device, including:
[0007] A substrate is provided on which an epitaxial layer and a hard mask layer are formed;
[0008] The hard mask layer is etched down to the surface of the epitaxial layer to form a plurality of spaced openings;
[0009] According to the opening, the epitaxial layer of a first thickness is etched to form a first trench;
[0010] By using a diffusion process, ions of a first conductivity type are doped in the epitaxial layer of the sidewalls and bottomwalls of the first trench to form an ion-doped region.
[0011] According to the opening, the epitaxial layer of a second thickness is etched downward to form a second trench;
[0012] Remove the hard mask layer;
[0013] A field oxide layer is formed, which covers the surface of the epitaxial layer and the sidewalls and bottom wall of the second trench.
[0014] Optionally, in the method for fabricating the semiconductor device, during the process of performing first conductivity type ion doping on the epitaxial layer of the sidewalls and bottomwalls of the first trench through a diffusion process to form an ion-doped region, the diffusion doping source gas is PH3; the flow rate of PH3 is 50 sccm to 200 sccm; the process temperature is 800℃ to 1200℃; and the process duration is 2h to 6h.
[0015] Optionally, in the method for fabricating the semiconductor device, during the process of performing first conductivity type ion doping on the epitaxial layer of the sidewalls and bottomwalls of the first trench through a diffusion process to form an ion-doped region, the diffusion doping source gas is AsH3; the flow rate of AsH3 is 10 sccm to 100 sccm; the process temperature is 800℃ to 1200℃; and the process duration is 2h to 6h.
[0016] Optionally, in the method for fabricating the semiconductor device, the doping concentration of the ion-doped region is 2E16 atoms / cm². 3 ~4E16atoms / cm 3 .
[0017] Optionally, in the method for fabricating the semiconductor device, the ratio of the first thickness to the second thickness is (1:1) to (50:1).
[0018] Optionally, in the method for fabricating the semiconductor device, a wet etching process is used to remove the hard mask layer.
[0019] Optionally, in the method for fabricating the semiconductor device, the field oxide layer is formed using a furnace tube oxidation process.
[0020] Optionally, in the method for fabricating the semiconductor device, the thickness of the field oxide layer is 100 nm to 1000 nm.
[0021] Optionally, in the method for fabricating the semiconductor device, the first conductivity type is N-type.
[0022] On the other hand, embodiments of this application also provide a semiconductor device, including:
[0023] A substrate on which an epitaxial layer is formed;
[0024] The second trench is arranged at intervals in the epitaxial layer;
[0025] The first conductivity type of ion-doped region is located in the epitaxial layer of the sidewall of the second trench, wherein the depth of the ion-doped region from top to bottom is a first thickness; the depth of the second trench from top to bottom is the sum of the first thickness and the second thickness.
[0026] A field oxide layer, which covers the surface of the epitaxial layer and the sidewalls and bottomwalls of the second trench.
[0027] The technical solution of this application has at least the following advantages:
[0028] This application provides a semiconductor device and its fabrication method. In the fabrication method, after etching an epitaxial layer of a first thickness to form a first trench, a diffusion process is used to perform ion doping of a first conductivity type on the epitaxial layer of the sidewalls and bottom wall of the first trench to form an ion-doped region. Subsequently, based on the opening, an epitaxial layer of a second thickness is etched downwards to form a second trench. This application, through the diffusion process, can uniformly dope the epitaxial layer of the sidewalls and bottom wall of the first trench, thereby forming an ion-doped region with uniform concentration. The distribution of charge carriers on the sidewalls of the first trench is more uniform. When a voltage is applied to the device, charge carriers are more likely to accumulate in the sidewall region of the first trench, forming a wider conductive channel. According to the resistance calculation formula, this is equivalent to increasing the current cross-sectional area, thereby reducing the resistance R of the accumulation region. A and drift region resistance R D Meanwhile, uniform doping avoids localized high-resistance regions and reduces current concentration, allowing current to pass more evenly through the sidewalls of the first trench. This reduces the resistance R in the accumulation region. A and drift region resistance R DFurthermore, the epitaxial layer at the bottom of the first trench is etched downwards to form the final deep trench (second trench), which reduces the ion doping concentration at the bottom of the final second trench, thereby avoiding breakdown caused by electric field concentration due to the high doping concentration at the bottom of the deep trench. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0030] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;
[0031] Figures 2-7 This is a schematic diagram of the semiconductor structure in each process step of the semiconductor device fabrication according to an embodiment of the present invention;
[0032] The reference numerals in the attached figures are explained as follows:
[0033] 10-Substrate, 20-Epipolar layer, 21-First trench, 22-Second trench, 30-Hard mask layer, 31-Opening, 40-Photoresist layer, 50-Ion doped region, 60-Field oxide layer. Detailed Implementation
[0034] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0035] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0036] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0037] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0038] This application provides a method for fabricating a semiconductor device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. The method for fabricating the semiconductor device includes:
[0039] First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of the semiconductor structure after the opening is formed according to an embodiment of this application. A substrate 10 is provided, on which an epitaxial layer 20 and a hard mask layer 30 are formed.
[0040] Then, proceed to step S2: Continue to refer to Figure 2 A photoresist layer 40 is formed on the hard mask layer 30. An opening pattern is defined on the photoresist layer 40 by photolithography. Using the patterned photoresist layer 40 as a mask, the hard mask layer 30 is etched to the surface of the epitaxial layer 20 to form a plurality of spaced openings 31.
[0041] Next, proceed to step S3: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the formation of the first trench according to an embodiment of this application. The epitaxial layer 20 of a first thickness is etched according to the opening 31 to form the first trench 21.
[0042] In this embodiment, the epitaxial layer 20 of the first thickness is etched using a dry etching process to form the first trench 21.
[0043] Further, proceed to step S4: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the formation of the ion-doped region in an embodiment of this application. Through a diffusion process, the epitaxial layer 20 of the sidewall and bottom wall of the first trench 21 is doped with ions of the first conductivity type to form the ion-doped region 50.
[0044] Preferably, the first conductivity type is N-type.
[0045] In this embodiment, during the process of N-type ion doping in the epitaxial layer 20 of the sidewall and bottom wall of the first trench 21 through diffusion process to form ion-doped region 50, the diffusion doping source gas is PH3; the flow rate of PH3 is 50 sccm to 200 sccm; the process temperature is 800℃ to 1200℃; and the process duration is 2h to 6h.
[0046] Preferably, the doping concentration of the ion-doped region is 2E16 atoms / cm². 3 ~4E16atoms / cm 3 .
[0047] In another embodiment, during the process of N-type ion doping in the epitaxial layer 20 of the sidewall and bottom wall of the first trench 21 through a diffusion process to form an ion-doped region 50, the diffusion doping source gas is AsH3; the flow rate of AsH3 is 10 sccm to 100 sccm; the process temperature is 800℃ to 1200℃; and the process duration is 2h to 6h.
[0048] In this application, a diffusion process is used to diffuse impurity atoms from the gaseous state or source into the epitaxial layer at high temperatures (800–1200°C). Through thermal motion, these atoms diffuse to the target region, allowing for uniform ion doping in the epitaxial layer 20 on the sidewalls and bottom of the first trench 21. This forms a uniformly concentrated ion-doped region 50, resulting in a more uniform carrier distribution on the sidewalls of the first trench 21. When a voltage is applied to the device, carriers accumulate more easily in the sidewall region of the first trench 21, forming a wider conductive channel. According to the resistance calculation formula, this is equivalent to increasing the current cross-sectional area, thereby reducing the resistance R in the accumulation region. A and drift region resistance R D Meanwhile, uniform doping avoids localized high-resistance regions and reduces current concentration, allowing current to pass more evenly through the sidewalls of the first trench 21. This reduces the resistance R in the accumulation region. A and drift region resistance R D .
[0049] Next, proceed to step S5: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the second trench in an embodiment of this application. According to the opening 31, the epitaxial layer 20 of the second thickness is etched downward to form the second trench 22.
[0050] In this embodiment, a dry etching process is used to continue etching the epitaxial layer 20 to a second thickness to form a second trench 22.
[0051] Preferably, the ratio of the first thickness to the second thickness is (1:1) to (50:1).
[0052] Further, proceed to step S6: Refer to Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after removing the hard mask layer according to an embodiment of this application, wherein the hard mask layer 30 has been removed.
[0053] In this embodiment, the hard mask layer 30 is removed using a wet etching process.
[0054] Finally, proceed to step S7: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the formation of the field oxide layer according to an embodiment of this application. The field oxide layer 60 is formed, which covers the surface of the epitaxial layer 20 and the sidewalls and bottom wall of the second trench 22.
[0055] Preferably, the field oxide layer 60 is formed using a furnace tube oxidation process.
[0056] Preferably, the thickness of the field oxide layer 60 is 100 nm to 1000 nm.
[0057] In this application, the epitaxial layer at the bottom of the first trench is etched downwards to form the final deep trench (second trench), which reduces the ion doping concentration at the bottom of the final second trench, thereby avoiding breakdown caused by electric field concentration due to excessive doping concentration at the bottom of the deep trench.
[0058] Based on the same inventive concept, this application also provides a semiconductor device, see reference. Figure 7 The semiconductor device includes:
[0059] Substrate 10, on which an epitaxial layer 20 is formed;
[0060] The second trench 22 is arranged at intervals in the epitaxial layer 20;
[0061] The first conductivity type of ion-doped region 50 is located in the epitaxial layer 20 of the sidewall of the second trench 22, wherein the depth of the ion-doped region 50 from top to bottom is a first thickness; the depth of the second trench 22 from top to bottom is the sum of the first thickness and the second thickness.
[0062] A field oxide layer 60 covers the surface of the epitaxial layer and the sidewalls and bottomwalls of the second trench.
[0063] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided on which an epitaxial layer and a hard mask layer are formed; The hard mask layer is etched down to the surface of the epitaxial layer to form a plurality of spaced openings; According to the opening, the epitaxial layer of a first thickness is etched to form a first trench; By using a diffusion process, ions of a first conductivity type are doped in the epitaxial layer of the sidewalls and bottomwalls of the first trench to form an ion-doped region. According to the opening, the epitaxial layer of a second thickness is etched downward to form a second trench; Remove the hard mask layer; A field oxide layer is formed, which covers the surface of the epitaxial layer and the sidewalls and bottom wall of the second trench.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, In the process of forming an ion-doped region by performing first conductivity type ion doping on the epitaxial layer of the sidewall and bottom wall of the first trench through diffusion process, the diffusion doping source gas is PH3; the flow rate of PH3 is 50 sccm to 200 sccm; the process temperature is 800℃ to 1200℃; and the process duration is 2h to 6h.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that, In the process of forming an ion-doped region by performing first conductivity type ion doping on the epitaxial layer of the sidewall and bottom wall of the first trench through diffusion process, the diffusion doping source gas is AsH3; the flow rate of AsH3 is 10 sccm to 100 sccm; the process temperature is 800℃ to 1200℃; and the process duration is 2h to 6h.
4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The doping concentration of the ion-doped region is 2E16 atoms / cm². 3 ~4E16atoms / cm 3 .
5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The ratio of the first thickness to the second thickness is (1:1) to (50:1).
6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The hard mask layer is removed using a wet etching process.
7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The field oxide layer is formed using a furnace tube oxidation process.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the field oxide layer is 100 nm to 1000 nm.
9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first conductivity type is N-type.
10. A semiconductor device, characterized in that, include: A substrate on which an epitaxial layer is formed; The second trench is arranged at intervals in the epitaxial layer; The first conductivity type of ion-doped region is located in the epitaxial layer of the sidewall of the second trench, wherein the depth of the ion-doped region from top to bottom is a first thickness; the depth of the second trench from top to bottom is the sum of the first thickness and the second thickness. A field oxide layer, which covers the surface of the epitaxial layer and the sidewalls and bottomwalls of the second trench.