A method of manufacturing a semiconductor structure and a semiconductor structure

Abstract

The present application provides a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises the following steps: providing a substrate; forming a stack layer on the substrate; etching part of the stack layer and part of the substrate to form a first trench in the substrate and in the stack layer; forming a sacrificial layer on the sidewall of the first trench and on the stack layer; filling the first trench to form a shallow trench isolation structure, wherein the shallow trench isolation structure comprises a step portion formed in the stack layer; removing the sacrificial layer adhered to the surface of the step portion; forming a protective layer on the exposed surface of the shallow trench isolation structure, wherein the protective layer has amine groups; and sequentially removing the stack layer and the protective layer. The present application can improve the manufacturing yield of the shallow trench isolation structure, and reduce the probability of the double peak effect and the leakage current of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Technology

[0002] Shallow trench isolation (STI) is widely used in submicron-level semiconductor processes. STI reduces the area of ​​the isolation region, providing minimal active area intrusion and a flatter surface. However, due to localized stress concentration, the oxide layer in the STI corner region is over-etched during substrate oxide etching, resulting in lateral erosion. Consequently, when the substrate oxide is stripped, the oxide layer in the STI corner region is unintentionally removed preferentially from the trench corner, forming a recessed structure (as shown in the attached figure). Figure 10 (As shown). During the formation of the gate structure, the presence of the recessed structure can lead to overfilling of the polysilicon, resulting in parasitic transistors. The presence of parasitic transistors increases the probability of leakage current in the device. Summary of the Invention

[0003] The purpose of this invention is to provide a method for manufacturing a semiconductor structure and a semiconductor structure, so as to improve the manufacturing yield of shallow trench isolation structures and reduce the bimodal effect and leakage current probability of devices.

[0004] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0005] This invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0006] Provide a substrate;

[0007] A stacked layer is formed on the substrate;

[0008] Etch a portion of the stacked layer and a portion of the substrate to form a first trench in the substrate and the stacked layer;

[0009] A sacrificial layer is formed on the trench wall of the first trench and on the stacked layer;

[0010] The first trench is filled to form a shallow trench isolation structure, wherein the shallow trench isolation structure includes a stepped portion formed in the stacked layer;

[0011] Remove the sacrificial layer attached to the surface of the stepped portion;

[0012] A protective layer is formed on the exposed surface of the shallow trench isolation structure, wherein the protective layer has amine groups; and

[0013] Remove the stacked layer and the protective layer in sequence.

[0014] In one embodiment of the present invention, in the step of forming the shallow trench isolation structure, the first trench is filled to form a step portion of the shallow trench isolation structure, and the material of the shallow trench isolation structure is further deposited to form a polished layer on the step portion and the stacked layer.

[0015] In one embodiment of the present invention, before removing the sacrificial layer attached to the surface of the stepped portion, the polishing layer, part of the stacked layer and part of the shallow trench isolation structure are ground away until the stepped portion reaches a preset height.

[0016] In one embodiment of the present invention, in the step of forming the stacked layer, a substrate oxide layer is formed on the substrate, and an etch stop layer is formed on the substrate oxide layer.

[0017] In one embodiment of the present invention, after the step portion reaches the preset height, and before removing the sacrificial layer attached to the surface of the step portion, a portion of the etch stop layer is removed, wherein the etch stop layer is etched at a ratio of 50% to 99%.

[0018] In one embodiment of the present invention, in the step of removing the stacked layer and the protective layer, the etchant for removing the etch stop layer is a phosphoric acid solution, the etchant for removing the substrate oxide layer is a hydrofluoric acid solution, and the etchant for removing the protective layer is a mixed solution of sulfuric acid and hydrogen peroxide.

[0019] In one embodiment of the present invention, the sacrificial layer is a silicon layer doped with boron ions.

[0020] In one embodiment of the present invention, in the step of forming a protective layer, a reaction layer is formed on the surface of the step portion, and the reaction layer is treated with an organic solvent under a heating environment to form the protective layer.

[0021] This invention provides a semiconductor structure, comprising:

[0022] Substrate;

[0023] A stacked layer is disposed on the substrate;

[0024] A shallow trench isolation structure, wherein a portion of the shallow trench isolation structure is disposed in the substrate and a portion of the shallow trench isolation structure is located outside the substrate, wherein the portion of the shallow trench isolation structure located outside the substrate is a stepped portion;

[0025] A sacrificial layer is located in the substrate and covers the surface of the shallow trench isolation structure;

[0026] A protective layer covering the exposed surface of the stepped portion, wherein the protective layer contains amine groups; and

[0027] A second trench extends through the stacked layer and connects to the surface of the sacrificial layer, wherein the second trench is located between the step portion and the stacked layer.

[0028] In one embodiment of the present invention, the height of the stacked layer is less than the height of the step portion.

[0029] As described above, this invention provides a method for manufacturing a semiconductor structure and a semiconductor structure with the following unexpected technical effects: it can form a shallow trench isolation structure with a complete surface, avoiding the formation of any depressions on the shallow trench isolation structure or the substrate surface during the shallow trench isolation structure formation process. This is beneficial to improving the forming yield of semiconductor devices in subsequent semiconductor processes and reducing the probability of leakage current in semiconductor devices. Furthermore, the semiconductor structure manufacturing method provided by this invention utilizes a structure with inefficient double-peak effect. While reducing or even eliminating the double-peak effect of semiconductor devices through ion diffusion, it can also protect the corners of the shallow trench isolation structure, avoiding the formation of parasitic transistors, thereby minimizing the double-peak effect and leakage current of the device. Moreover, the process optimization is extremely high, achieving a higher manufacturing yield. The semiconductor structure manufacturing method and semiconductor structure provided by this invention are particularly suitable for semiconductor processes at and below the submicron level and can significantly improve semiconductor process yield.

[0030] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure forming a substrate oxide layer, an etch stop layer, and a photoresist pattern in one embodiment of the present invention.

[0033] Figure 2 This is a schematic diagram of the structure forming the first trench in one embodiment of the present invention.

[0034] Figure 3 This is a schematic diagram of the structure of the sacrificial layer in one embodiment of the present invention.

[0035] Figure 4 This is a schematic diagram of the structure forming a polished layer and a shallow trench isolation structure in one embodiment of the present invention.

[0036] Figure 5This is a schematic diagram of the structure for removing the polishing layer in one embodiment of the present invention.

[0037] Figure 6 This is a schematic diagram of the structure forming the second trench in one embodiment of the present invention.

[0038] Figure 7 This is a schematic diagram of the structure forming the protective layer in one embodiment of the present invention.

[0039] Figure 8 This is a schematic diagram of the structure for removing the etch stop layer and the substrate oxide layer in one embodiment of the present invention.

[0040] Figure 9 This is a schematic diagram of the structure with the protective layer removed in one embodiment of the present invention.

[0041] Figure 10 This is an electron microscope image of a shallow trench isolation structure with a recessed structure due to excessive etching in one embodiment of the present invention.

[0042] Figure 11 This is a schematic diagram of the structure forming the protective layer in one embodiment of the present invention.

[0043] Figure 12 This is a schematic diagram illustrating the principle of fluoride ion adsorption in one embodiment of the present invention.

[0044] In the figure: 100, substrate; 101, first trench; 102, sacrificial layer; 103, shallow trench isolation structure; 1031, step portion; 104, polished layer; 105, second trench; 106, protective layer; 200, substrate oxide layer; 300, etch stop layer; 400, photoresist pattern; 500, recessed structure. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] This invention provides a semiconductor structure and a method for manufacturing the same, wherein the semiconductor structure is a structure for forming a semiconductor device. The semiconductor device can be one or more of the following: Field Effect Transistor (FET), Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), Complementary Metal-Oxide Semiconductor (CMOS), Insulated Gate Bipolar Transistor (IGBT), Fast Recovery Diode (FRD), High Efficiency Diode (HED), Constant Voltage Diode, High Frequency Diode, Light-Emitting Diode (LED), Gate Turn-off Thyristor (GTO), Light Triggered Thyristor (LTT), Thyristor, Charge Coupled Device (CCD image sensor), Digital Signal Processor (DSP), Photo Relay, or Micro Processor.

[0047] Please see Figure 1 As shown, in the semiconductor structure manufacturing method provided by the present invention, a substrate 100 is first provided. In this embodiment, substrate 100 may also refer to a wafer used in semiconductor processing. Furthermore, substrate 100 may include doped and undoped semiconductor or epitaxial semiconductor layers, which may be supported by a substrate of semiconductor or insulating material and other semiconductor structures known to those skilled in the art. Additionally, the term conductor may include semiconductor. Specifically, substrate 100 is, for example, a silicon substrate forming a semiconductor structure. Substrate 100 may include a substrate and a silicon layer disposed on the substrate. The substrate may be, for example, a semiconductor substrate material such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc., and the silicon layer is formed on the substrate.

[0048] Please see Figure 1As shown, in one embodiment of the present invention, a substrate oxide layer 200 is formed on a substrate 100, followed by the formation of an etch stop layer 300 on the substrate oxide layer 200. In this embodiment, silicon oxide is deposited on the substrate 100 by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) to form the substrate oxide layer 200. The thickness of the substrate oxide layer 200 is not limited in the present invention. Next, silicon nitride material is deposited on the substrate oxide layer 200 by chemical vapor deposition or plasma-enhanced chemical vapor deposition to form the etch stop layer 300. The thickness of the etch stop layer 300 is not limited in the present invention. In this embodiment, the thickness of the etch stop layer 300 is greater than the thickness of the substrate oxide layer 200. In this embodiment, after the etch stop layer 300 is formed, a photoresist pattern 400 is formed on the etch stop layer 300. Specifically, photoresist is spin-coated onto the etch stop layer 300 to form a photoresist layer, and the photoresist layer is patterned by methods such as exposure etching to form a photoresist pattern 400. The photoresist pattern 400 defines the maximum width of the shallow trench. Specifically, the area covered by the photoresist pattern 400 is the area used to form the active region in the semiconductor device design.

[0049] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after forming the etch stop layer 300, using the photoresist pattern 400 as a mask, a portion of the etch stop layer 300, a portion of the substrate oxide layer 200, and a portion of the substrate 100 are removed to form a first trench 101 on the substrate 100. In this embodiment, the blank area of ​​the photoresist pattern 400 is used as the etching process window, and dry etching is used to sequentially remove the etch stop layer 300, the substrate oxide layer 200, and the substrate 100, thereby forming the first trench 101 on the substrate 100. The first trench 101 penetrates the etch stop layer 300 and the substrate oxide layer 200, extending into the substrate 100. Specifically, the first trench 101 is partially located in the substrate 100, partially located between adjacent substrate oxide layers 200, and partially located between adjacent etch stop layers 300. After forming the first trench 101, the photoresist pattern 400 is removed by an ashing process.

[0050] Please see Figure 2 and Figure 3As shown, in one embodiment of the present invention, after forming the first trench 101 and removing the photoresist pattern 400, a sacrificial layer 102 is formed on the trench wall of the first trench 101 and the etch stop layer 300. In this embodiment, a doped silicon material is attached to the trench wall of the first trench 101 and the etch stop layer 300 by means of chemical vapor deposition or plasma-enhanced chemical vapor deposition, thereby forming the sacrificial layer 102. The dopant ions of the sacrificial layer 102 are boron ions, and the thickness of the sacrificial layer 102 is, for example, 5 angstroms to 200 angstroms. It should be noted that in semiconductor devices using metal-oxide-semiconductor field-effect transistors as basic components, MOSFETs include a MOS transistor and two PN junctions closely adjacent to the MOS transistor. As the effective channel length and width of the MOSFET become smaller, the probability of device failure due to the double-peak effect of the MOSFET and semiconductor devices using such transistors also increases. Because it is difficult to maintain a consistent doping concentration between the sidewalls and the central region of a transistor, and because transistor manufacturing cannot perfectly conform to the design pattern, parasitic transistors may conduct before the semiconductor device when a reverse voltage is applied. This can lead to the MOSFET not achieving the expected technical performance in a circuit, resulting in device failure. The sacrificial layer 102 uses boron-doped silicon material, which can balance the ion concentration between the edge and central regions of the active region, thereby helping to reduce or even eliminate the bimodal effect of the semiconductor device. The edge of the active region refers to the interface between the substrate 100 and the first trench 101, which is also the interface between the subsequently formed shallow trench isolation structure 103 and the substrate 100. In this embodiment, in the process of forming the sacrificial layer 102, silane is used as the raw material and borane as the doping gas, and the sacrificial layer 102 is formed by chemical vapor deposition on the trench wall of the first trench 101 and the etch stop layer 300. The trench wall of the first trench 101 refers to the exposed surface newly formed after etching of the etch stop layer 300, the substrate oxide layer 200, and the substrate 100. For example... Figure 2 and Figure 3 As shown in the figure, the first trench 101 in this embodiment has a rectangular and trapezoidal cross-section. In other embodiments of the invention, the cross-section of the first trench 101 may also be trapezoidal. Under the protection of the etch stop layer 300, the trench segments of the first trench 101 located in the etch stop layer 300 and the trench segments in the substrate oxide layer 200 have good vertical surfaces. Therefore, the surface of the sacrificial layer 102 can also have a good flat surface.

[0051] Please see Figure 3 and Figure 4As shown, in one embodiment of the present invention, after forming the first trench 101, the first trench 101 is filled to form a shallow trench isolation structure 103 in the first trench 101, and a polishing layer 104 is formed on the shallow trench isolation structure 103 and the etch stop layer 300. In this embodiment, the first trench 101 is filled by chemical vapor deposition or plasma-enhanced chemical vapor deposition until the first trench 101 is completely filled, forming the shallow trench isolation structure 103. The shallow trench isolation structure 103 includes a stepped portion 1031, which is the portion of the shallow trench isolation structure 103 that is higher than the substrate 100. The portion of the shallow trench isolation structure 103 filled in the substrate 100 can be used to isolate active regions in the substrate 100, thereby forming multiple well structures in the substrate 100. The filling material of the first trench 101 is, for example, tetraethyl orthosilicate (TEOS). In this embodiment, after filling the first trench 101, tetraethoxysilane is deposited on the step portion 1031 and the etch stop layer 300 to form a thin film structure, thereby forming a polished layer 104. It should be noted that the shallow trench isolation structure 103 and the polished layer 104 can also be formed from a material comprising silicon oxide, silicon dioxide, carbon-doped silicon dioxide, nitrogen-doped silicon dioxide, germanium-doped silicon dioxide, or phosphorus-doped silicon dioxide. Furthermore, the shallow trench isolation structure 103 and the polished layer 104 can be conformally deposited using atmospheric chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LCCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sub-atmospheric chemical vapor deposition (SACVD), high-density plasma chemical vapor deposition (HDPCVD), and photo-induced chemical vapor deposition (PDCVD). Those skilled in the art will understand that other insulating materials can be deposited on the first trench 101 to achieve the purpose of electrically isolating the component regions. Furthermore, in the realm understood by those skilled in the art, other known methods can also be used to deposit and form the shallow trench isolation structure 103 and the polished layer 104.

[0052] Please see Figure 4 and Figure 5As shown, in one embodiment of the present invention, after forming the shallow trench isolation structure 103 and the polishing layer 104, the polishing layer 104 is removed. In this embodiment, after forming the polishing layer 104, the surface of the etch stop layer 300 is used as the reference layer for polishing and grinding. The polishing layer 104 is ground by chemical mechanical polishing (CMP) to expose the surfaces of the etch stop layer 300 and the step portion 1031. In this embodiment, during the polishing layer 104 step, a portion of the etch stop layer 300 and the step portion 1031 can be removed, thereby ensuring that the height of the step portion 1031 reaches the designed preset height H. In this embodiment, during the chemical mechanical polishing process, etching can be stopped when the height of the step portion 1031 reaches the preset height H. The preset height H is set by the designer. The height of the step portion 1031 can be observed and measured during the chemical mechanical polishing process to ensure that the step portion 1031 of the shallow trench isolation structure 103 meets the process requirements at the end of the chemical mechanical polishing step, thus avoiding defects. In other embodiments of the present invention, when depositing the etch stop layer 300, the total thickness of the etch stop layer 300 and the substrate oxide layer 200 can be made greater than a preset height H, thereby providing an adjustment margin for polishing the step portion 1031 in subsequent processes. Furthermore, this process can improve the surface flatness of the etch stop layer 300, which is beneficial for balancing the etching rate of various regions in the substrate oxide layer 200 during subsequent etching processes, thereby protecting the surface of the substrate 100. This ensures that the substrate oxide layer 200 is completely removed while preventing over-etching of the surface of the substrate 100.

[0053] Please see Figure 5 and Figure 6 As shown, in one embodiment of the present invention, after removing the polishing layer 104, a portion of the etch stop layer 300 and a portion of the sacrificial layer 102 are removed, forming a second trench 105. In this embodiment, 50% to 99% of the etch stop layer 300 is removed by wet etching. Specifically, the etchant used for wet etching can be a phosphoric acid solution. After removing a portion of the etch stop layer 300, the sacrificial layer 102 located above the substrate 100 is then removed by wet etching, leaving only the sacrificial layer 102 located within the substrate 100. The etchant used to remove the sacrificial layer 102 can be an alkaline solution, such as tetramethylammonium hydroxide (C4H4H2O). 13NO) or ammonia monohydrate (NH4OH). The sacrificial layer 102 located above the substrate 100 refers to the sacrificial layer 102 attached to the outside of the step portion 1031. The substrate oxide layer 200 and the etch stop layer 300 are connected to form a stacked layer. After removing the sacrificial layer 102 outside the step portion 1031, the second trench 105 is located between the step portion 1031 and the stacked layer, with the surface of the sacrificial layer 102 as the trench bottom. After forming the second trench 105, the surface of the step portion 1031 is exposed. In this embodiment, the width of the second trench 105 is greater than the critical dimension of the semiconductor structure. The present invention does not limit the specific width of the second trench 105. After removing the sacrificial layer 102, the formed second trench 105 provides space for the formation of the protective layer 106 in subsequent processes, so that the protective layer 106 can be completely attached to the surface of the step portion 1031.

[0054] Please see Figure 6 and Figure 7 As shown, in one embodiment of the present invention, after forming the second trench 105, the surface of the step portion 1031 is treated to form a protective layer 106 on the surface of the step portion 1031. In this embodiment, a reactive layer, such as a chitosan layer, is attached to the surface of the step portion 1031. The chitosan layer is heated and treated at a temperature of, for example, 50°C to 200°C in an organic solvent environment, thereby modifying the chitosan layer and forming the protective layer 106 on the surface of the step portion 1031. In this embodiment, the organic solvent can be any one of toluene, acetone, and N-methylpyrrolidone, or any mixture of multiple solvents. The protective layer 106 is a nanocomposite material. Figure 11 As shown, silicon oxide and the amino groups of chitosan are linked, thereby forming a protective layer 106 on the exposed surface of the step 1031. The protective layer 106 contains amino groups. Since the surface of step 1051 has more -OH groups than the surface of the substrate oxide layer 200, the protective layer 106 preferentially forms on the surface of step 1031. It should be noted that due to the etching environment created by etching solutions such as phosphoric acid and hydrofluoric acid, step 1031 is under acidic conditions, and the surface of the protective layer 106 carries a positive charge. Therefore, the free amino groups in the chitosan structure are protonated, and a positively charged substance, namely -NH3, appears on the surface of the nanocomposite material. + .like Figure 12 As shown, under the action of electrostatic adsorption, -NH3 + It can attract F- ions, and when hydrofluoric acid is used as an etchant to perform the etching process, it can reduce the etching effect of F- ions on the connection between the step portion 1031 and the substrate 100, thereby protecting the shallow trench isolation structure 103 from being over-etched.

[0055] Please see Figures 7 to 9As shown, in one embodiment of the present invention, the etch stop layer 300, the substrate oxide layer 200, and the protective layer 106 are removed sequentially. In this embodiment, phosphoric acid is used to remove the residual etch stop layer 300 on the surface of the substrate oxide layer 200. Then, hydrofluoric acid is used to remove the substrate oxide layer 200. Under the protection of the protective layer 106, over-etching will not occur at the corners of the shallow trench isolation structure 103 connecting to the substrate 100. The corners of the shallow trench isolation structure 103 connecting to the substrate 100 are... Figure 9 The circled area. Next, the protective layer 106 is removed using sulfuric acid and hydrogen peroxide, exposing the surface of the stepped portion 1031, thus forming a shallow groove isolation structure 103 with a complete surface. In this embodiment, the chitosan-modified layer is removed using sulfuric acid and hydrogen peroxide, thereby removing the protective layer 106.

[0056] Please see Figure 9 and Figure 10 As shown, Figure 10 Electron micrograph of the corner of the shallow trench isolation structure 103 showing excessive etching. Figure 9 This is a corner structure diagram of the shallow trench isolation structure 103 obtained under the control method provided by the present invention. Figure 10 As shown, when an over-etched recessed structure 500 appears at the corner of the shallow trench isolation structure 103, this recessed structure 500 will continue during the formation process of the gate structure and even the formation process of the metal interconnect structure, when depositing the dielectric layer, polysilicon layer, and metal layer. To fill the recessed structure 500, excess polysilicon material or metal material will be added, resulting in parasitic device structures in the original device structure. The shallow trench isolation structure 103 provided by the present invention not only avoids the formation of the recessed structure 500, thereby improving the integrity of the shallow trench isolation structure 103, but also avoids the appearance of parasitic devices that are not required by the design in the semiconductor device, thereby reducing the possibility of leakage current in the device, thereby improving the chip manufacturing yield and the wafer yield on a single wafer.

[0057] This invention provides a method for manufacturing a semiconductor structure and a semiconductor structure. The method for manufacturing the semiconductor structure includes the following steps: providing a substrate; forming a stacked layer on the substrate; etching a portion of the stacked layer and a portion of the substrate to form a first trench in the substrate and the stacked layer; forming a sacrificial layer on the trench wall of the first trench and on the etch stop layer; filling the first trench to form a shallow trench isolation structure, wherein the shallow trench isolation structure includes a stepped portion formed in the stacked layer; removing the sacrificial layer attached to the surface of the stepped portion; forming a protective layer on the exposed surface of the shallow trench isolation structure, wherein the protective layer has amino groups; and sequentially removing the stacked layer and the protective layer. The unexpected technical effect of the method for manufacturing a semiconductor structure and the semiconductor structure provided by this invention is that it can form a shallow trench isolation structure with a complete surface, avoiding the formation of any recessed structures on the shallow trench isolation structure or the substrate surface during the process of forming the shallow trench isolation structure, which is beneficial to improving the molding yield of semiconductor devices in subsequent semiconductor processes and reducing the probability of leakage current in semiconductor devices. Furthermore, the semiconductor structure manufacturing method provided by this invention utilizes a structure with inefficient double-peak effect. While reducing or even eliminating the double-peak effect of the semiconductor device through ion diffusion, it also protects the corners of the shallow trench isolation structure, preventing the formation of parasitic transistors. This minimizes the double-peak effect and leakage current of the device, and the process optimization is extremely high, achieving higher manufacturing yields. The semiconductor structure manufacturing method and semiconductor structure provided by this invention are particularly suitable for submicron processes and below, and can significantly improve semiconductor process yields.

[0058] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: Provide a substrate; A stacked layer is formed on the substrate; Etch a portion of the stacked layer and a portion of the substrate to form a first trench in the substrate and the stacked layer; A sacrificial layer is formed on the trench wall of the first trench and on the stacked layer; The first trench is filled to form a shallow trench isolation structure, wherein the shallow trench isolation structure includes a stepped portion formed in the stacked layer; Remove the sacrificial layer attached to the surface of the stepped portion; A protective layer is formed on the exposed surface of the shallow trench isolation structure, wherein the protective layer has amine groups; and Remove the stacked layer and the protective layer in sequence.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, In the step of forming the shallow trench isolation structure, the first trench is filled to form the step portion of the shallow trench isolation structure, and the material of the shallow trench isolation structure is deposited to form a polished layer on the step portion and the stacked layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, Before removing the sacrificial layer attached to the surface of the stepped portion, the polishing layer, part of the stacked layer, and part of the shallow trench isolation structure are ground away until the stepped portion reaches a preset height.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, In the step of forming the stacked layer, a substrate oxide layer is formed on the substrate, and an etch stop layer is formed on the substrate oxide layer.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, After the step reaches the preset height, and before removing the sacrificial layer attached to the surface of the step, a portion of the etch stop layer is removed, wherein the etch stop layer is etched at a ratio of 50% to 99%.

6. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, In the step of removing the stacked layer and the protective layer, the etchant used to remove the etch stop layer is a phosphoric acid solution, the etchant used to remove the substrate oxide layer is a hydrofluoric acid solution, and the etchant used to remove the protective layer is a mixed solution of sulfuric acid and hydrogen peroxide.

7. A method for manufacturing a semiconductor structure according to claim 1 ， Its features are, The sacrificial layer is a silicon layer doped with boron ions.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, In the step of forming the protective layer, a reaction layer is formed on the surface of the step portion, and the reaction layer is treated with an organic solvent under a heating environment to form the protective layer.

9. A semiconductor structure, characterized in that, include: Substrate; A stacked layer is disposed on the substrate; A shallow trench isolation structure, wherein a portion of the shallow trench isolation structure is disposed in the substrate and a portion of the shallow trench isolation structure is located outside the substrate, wherein the portion of the shallow trench isolation structure located outside the substrate is a stepped portion; A sacrificial layer is located in the substrate and covers the surface of the shallow trench isolation structure; A protective layer covering the exposed surface of the stepped portion, wherein the protective layer contains amine groups; as well as A second trench extends through the stacked layer and connects to the surface of the sacrificial layer, wherein the second trench is located between the step portion and the stacked layer.

10. A semiconductor structure according to claim 9, characterized in that, The height of the stacked layer is less than the height of the step portion.

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