Power module chip junction temperature built-in NTC packaging structure and chip temperature measurement method

Abstract

The embodiment of the invention provides a power module chip junction temperature built-in NTC packaging structure and a chip temperature measurement method, and belongs to the technical field of semiconductors. The packaging structure comprises a shell, a substrate, a power module chip and an NTC thermistor, the shell is fixedly connected with the substrate through bolts, and the power module chip and the NTC thermistor are installed on the substrate; the housing is provided with an observation hole array, and the observation hole array is disposed above the power module chip, and is used for providing an infrared temperature measurement channel for the chip junction temperature of the power module chip. The NTC thermistor is used for detecting a chip NTC temperature signal of the power module chip. According to the embodiment of the invention, the junction temperature measurement precision can be improved, and the actual junction temperature of the chip in actual work can be directly detected.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a packaging structure and chip temperature measurement method for a power module chip with a built-in NTC junction temperature controller. Background Technology

[0002] Currently, the mainstream technical solution for monitoring the junction temperature of power devices is the infrared thermal imager-based temperature measurement method. This technology indirectly calculates the internal junction temperature of the chip by collecting temperature field distribution data on the device surface and combining it with a thermal resistance network model. However, for power modules with fully enclosed packaging (such as plastic-encapsulated modules, metal-welded sealed modules, etc.), the outer shell completely covers the chip surface during operation, which prevents the infrared thermal imager from obtaining effective thermal radiation signals. This results in the limitation of this technical solution in enclosed packaging scenarios.

[0003] As the junction temperature tolerance of silicon carbide devices has exceeded the 175°C threshold, the lack of real-time temperature monitoring in continuous operation scenarios of photovoltaic inverters may cause the junction temperature to exceed the SOA (Safe Operating Area) without being detected, accelerating chip aging. Thermal monitoring defects have become a key bottleneck restricting the improvement of system performance.

[0004] Another method for junction temperature monitoring is to indirectly infer the chip junction temperature based on the characteristics of thermistor parameters. This involves calculating the junction temperature by real-time monitoring of changes in key parameters such as the device's threshold voltage and on-resistance. While this method can monitor temperature during operation, it has significant limitations in practical applications. When the device operates under high current or high-frequency switching conditions, the linear relationship between thermistor parameters and temperature changes significantly, leading to distortion of the temperature calibration curve and thus drastically reducing the accuracy and reliability of junction temperature measurements. Summary of the Invention

[0005] The main objective of this application is to propose a packaging structure and chip temperature measurement method with a built-in NTC for the junction temperature of a power module chip, aiming to improve the accuracy of junction temperature measurement and directly detect the actual junction temperature of the chip during actual operation.

[0006] To achieve the above objectives, one aspect of this application provides a packaging structure for a power module chip with an integrated NTC junction temperature, including a housing, a substrate, a power module chip, and an NTC thermistor, wherein the housing is fixedly connected to the substrate by bolts, and the power module chip and the NTC thermistor are mounted on the substrate; The outer casing has an array of observation holes located above the power module chip, which is used to provide an infrared temperature measurement channel for the junction temperature of the power module chip. The NTC thermistor is used to detect the NTC temperature signal of the power module chip.

[0007] In some embodiments, the aperture diameter of the observation aperture array is 6-10 mm.

[0008] In some embodiments, the housing further includes a first NTC signal terminal and a second NTC signal terminal; The NTC thermistor is connected to the first NTC signal terminal and the second NTC signal terminal respectively via wires to form an NTC temperature detection circuit; The NTC temperature detection circuit is used to lead the chip's NTC temperature signal to the outside of the package structure.

[0009] In some embodiments, the straight-line distance between the NTC thermistor and the nearest contour edge of the power module chip is greater than or equal to 0.8 mm.

[0010] In some embodiments, the lower surface of the NTC thermistor is insulated, and the upper surface of the NTC thermistor is used for bonding to form a via.

[0011] In some embodiments, the surface of the substrate is covered with a double coating, the double coating comprising a primer coating and a black paint coating, wherein the primer coating is located between the substrate and the black paint coating; The primer coating is an insulating layer with a thickness of 100 micrometers or more, used for electrical isolation; The black paint coating is a composite coating with resin material as the base and carbon-based material as the filler, used for temperature measurement calibration.

[0012] To achieve the above objectives, another aspect of this application proposes a chip temperature measurement method, applied to the aforementioned power module chip with a built-in NTC junction temperature sensor. The method includes the following steps: The junction temperature of the power module chip is obtained by infrared thermometry using an observation aperture array. The NTC temperature of the power module chip is detected by an NTC thermistor to obtain the chip's NTC temperature signal. Curve fitting is performed on the relationship between the chip junction temperature and the chip NTC temperature signal to obtain the chip temperature rise mapping relationship; Based on the chip temperature rise mapping relationship, the current chip junction temperature is obtained by performing temperature conversion according to the current chip NTC temperature signal.

[0013] To achieve the above objectives, another aspect of this application proposes a chip temperature measurement system, the system comprising: The infrared temperature measurement module is used to perform infrared temperature measurement on the power module chip through the observation aperture array to obtain the chip junction temperature. The NTC temperature detection module is used to detect the NTC temperature of the power module chip through an NTC thermistor and obtain the chip's NTC temperature signal. The curve fitting module is used to perform curve fitting on the relationship between the chip junction temperature and the chip NTC temperature signal to obtain the chip temperature rise mapping relationship. The temperature conversion module is used to perform temperature conversion based on the chip temperature rise mapping relationship and the current chip NTC temperature signal to obtain the current chip junction temperature.

[0014] To achieve the above objectives, another aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method.

[0015] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0016] To achieve the above objectives, another aspect of this application provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0017] The embodiments of this application include at least the following beneficial effects: This application provides a packaging structure and chip temperature measurement method for a power module chip with a built-in NTC thermistor. The packaging structure includes a shell, a substrate, a power module chip, and an NTC thermistor. The shell is fixedly connected to the substrate by bolts, and the power module chip and the NTC thermistor are mounted on the substrate. An array of observation holes is provided on the shell, located above the power module chip, to provide an infrared temperature measurement channel for the chip's junction temperature. The NTC thermistor is used to detect the NTC temperature signal of the power module chip. The embodiments of this application can improve the accuracy of junction temperature measurement and directly detect the actual junction temperature of the chip during actual operation. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the package structure of the power module chip with built-in NTC junction temperature provided in the embodiments of this application; Figure 2 This is a schematic diagram of the 62mm standard package structure provided in the embodiments of this application; Figure 3 This is a schematic diagram of the aperture position of the observation aperture array provided in the embodiment of this application; Figure 4 This is a schematic diagram of the structure of the NTC temperature monitoring circuit of the isolation circuit provided in the embodiment of this application; Figure 5 This is a schematic diagram of the structure of the non-isolated NTC temperature monitoring circuit provided in the embodiments of this application; Figure 6 This is a schematic diagram illustrating the effect of the paint coating provided in the embodiments of this application; Figure 7 This is a flowchart of the chip temperature measurement method provided in the embodiments of this application; Figure 8 This is a schematic diagram of the relationship curve fitting provided in the embodiments of this application; Figure 9 This is a structural block diagram of the chip temperature measurement system provided in the embodiments of this application; Figure 10 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application.

[0019] Figure label: The components include: housing 100, substrate 200, power module chip 300, NTC thermistor 400, observation hole array 101, first NTC signal terminal 102, and second NTC signal terminal 103. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of systems and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] Before providing a detailed description of the embodiments of this application, the relevant technologies involved in the embodiments of this application will be described first.

[0023] In related technologies, some packaged power semiconductor devices (such as IGBTs and SiC MOSFETs) are widely used in industrial frequency converters and new energy inverters. Although their simplified design achieves basic switching functions, they have significant shortcomings in thermal management. This paper explores the thermal management aspects using a 62mm standard package. I. Physical limitations due to the lack of temperature monitoring function.

[0024] (1) Structural constraints: The four-terminal package does not reserve space for integration, and the internal lead frame adopts a single-layer copper structure, which cannot embed additional sensing elements like multi-layer substrate packages (such as EASYPACK 2B).

[0025] (2) Junction temperature estimation error: The method of estimating junction temperature (Tj) by back-calculating from shell temperature (Tc) has a deviation of ≥15℃ (based on JESD51-14 standard test data), and the error may expand to 30℃ under transient conditions.

[0026] (3) Thermal coupling failure: In the existing terminal layout, there is common impedance coupling between the power circuit and the signal circuit, which causes the source parasitic inductance (Ls) to reach the level of 5nH, further interfering with the monitoring accuracy of temperature-related parameters (such as Vce(sat)).

[0027] II. Comparison of performance gaps between mainstream packaging solutions.

[0028] In terms of functionality, the 62mm standard package has no temperature sampling points, making redundant detection impossible; junction temperature calibration relies on indirect calculation, with an error of ±20℃, resulting in poor calibration accuracy; and the 62mm standard package relies on case temperature feedback, resulting in a delay of up to 300ms, a long thermal response time, and an inability to respond quickly.

[0029] III. Derivative problems in practical applications.

[0030] (1) Reliability risk: The lack of real-time temperature monitoring may cause the junction temperature to exceed the SOA (Safe Operating Area) without being detected, accelerating chip aging (MTTF decreases by about 40%).

[0031] (2) Conservative derating design: In order to compensate for the lack of monitoring, the system needs to reserve a current margin of 15-20%, which will reduce the silicon area utilization rate.

[0032] (3) Obstacles to intelligent operation and maintenance: It is impossible to establish a junction temperature-lifetime correlation model, which does not meet the requirements of predictive maintenance.

[0033] In view of this, this application provides a packaging structure and chip temperature measurement method for a power module chip with a built-in NTC thermistor. The packaging structure includes a shell, a substrate, a power module chip, and an NTC thermistor. The shell is fixedly connected to the substrate by bolts, and the power module chip and NTC thermistor are mounted on the substrate. An array of observation holes is provided on the shell, located above the power module chip, to provide an infrared temperature measurement channel for the chip's junction temperature. The NTC thermistor is used to detect the NTC temperature signal of the power module chip. This application embodiment can improve the accuracy of junction temperature measurement and directly detect the actual junction temperature of the chip during actual operation.

[0034] The chip temperature measurement method provided in this application relates to the field of semiconductor technology. This chip temperature measurement method can be applied to a terminal, a server, or software running on a terminal or server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, or in-vehicle terminal, but is not limited to these. The server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network. The software can be an application implementing the chip temperature measurement method, but is not limited to the above forms.

[0035] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0036] Figure 1 This is a schematic diagram of a package structure for a power module chip with a built-in NTC junction temperature according to an embodiment of this application. Figure 1 The packaging structure includes a housing 100, a substrate 200, a power module chip 300, and an NTC thermistor 400. The housing is fixedly connected to the substrate by bolts, and the power module chip and the NTC thermistor are mounted on the substrate.

[0037] An observation aperture array 101 is provided on the outer casing. The observation aperture array is located above the power module chip and is used to provide an infrared temperature measurement channel for the junction temperature of the power module chip.

[0038] NTC thermistors are used to detect the NTC temperature signal of power module chips.

[0039] In this embodiment, for example, Figure 2 The technical challenge of junction temperature monitoring in the fully enclosed power module is addressed in this embodiment through a two-pronged design: firstly, an NTC thermistor is added inside the module; secondly, a black module is fabricated using an open-shell casing, and a black module calibration method is employed to establish a mapping model between the NTC temperature and the chip junction temperature.

[0040] Specifically, while related technologies provide indirect detection methods to infer chip junction temperature, the core pain point currently facing the industry is that fully enclosed power modules (such as plastic-encapsulated / metal-welded packages) are physically shielded by their outer casings, making it impossible for traditional infrared thermal imagers to perform effective temperature measurements. Furthermore, some early package models lack pre-installed NTC thermistors, creating a "double-blind" monitoring dilemma that severely restricts product reliability assessment. Therefore, this embodiment uses an improvement on the 62mm standard package structure as an example for illustration.

[0041] Currently, power modules have two typical housing designs: plug-in type and bolt-fixed type. The plug-in type structure is limited by space layout and only has four signal terminal sockets required for basic drive (including upper and lower bridge gates and Kelvin source terminals). Although this design simplifies the installation process, it restricts functional expansion. The bolt-fixed housing, with its design of four terminals on each side, reserves the expansion capability of four sockets on the right side while maintaining the same core functions, providing a hardware foundation for the development of system-level monitoring functions. Therefore, this embodiment adopts the bolt-fixed housing to connect to the substrate.

[0042] In the power module packaging process, after the side frame of the enclosed housing is cured, mechanical grinding to remove the top of the housing due to structural limitations would prevent subsequent bending processes from being implemented. To address this bottleneck, this embodiment pre-marks the power module chip layout positions and performs precise hole drilling in specific areas of the housing to create an array of observation holes on the housing corresponding to the power module chip positions. Figure 3 As shown, the chip can be directly observed inside each hole.

[0043] For example, firstly, the coordinates of the power module chip are marked on the inner surface of the housing using an optical positioning system to establish a position mapping relationship; secondly, an array of observation holes is processed in the marked area using laser micromachining technology. This array consists of multiple observation holes, each aligned with a power module chip; finally, before the housing is installed and cured, the chip status is visually detected through the observation holes to ensure that the observation hole array is located directly above the power module chip.

[0044] The aforementioned process of creating an observation aperture array not only solves the process compatibility issues of the enclosed housing, but also provides an infrared temperature measurement channel for temperature calibration while preserving the housing's framework to the maximum extent. This ensures sufficient structural strength during use, prevents power terminal bending failure, and enables non-destructive verification of the chip's position after packaging. Therefore, by creating slots in the housing, it becomes possible to monitor the chip junction temperature during module operation.

[0045] Furthermore, to address the issue of inaccurate chip junction temperature detection, an independent temperature measurement channel is established near the chip. By placing an NTC thermistor in a specific area of ​​the DBC substrate, the physical distance between the NTC thermistor and the power module chip is minimized, enabling the NTC thermistor to measure the ambient temperature of the power module chip and obtain the chip's NTC temperature signal.

[0046] Due to the unavoidable positional difference between the power module chip and the NTC thermistor, a temperature difference will occur between the chip junction temperature and the chip NTC temperature signal. Therefore, it is necessary to establish a temperature transfer model between the two. This model can use the experimentally obtained correlation curve between NTC and chip junction temperature to infer the chip junction temperature from the chip NTC temperature signal. By making a black module, the accurate value of the chip junction temperature can be calibrated, so as to realize the direct measurement of the chip junction temperature and the direct detection of the actual junction temperature of the chip during actual operation.

[0047] Experimental testing showed that after improvements to the 62mm standard package structure, such as... Figure 1 The packaging structure shown successfully increased junction temperature monitoring coverage from 0% to 100%, providing key data support for product life prediction.

[0048] It should be noted that, Figure 1 The packaging structure shown is intended to demonstrate improvements in packaging structure. To clearly show the internal structure, the side part of the shell is omitted, and only the top cover and opening features of the shell are shown. In actual packaging, the shell is a complete integral structure, which is fixedly connected to the substrate by bolts to form a sealed package.

[0049] This embodiment establishes a temperature-resistance characteristic database by adding an NTC thermistor inside the package structure. At the same time, it uses the black module calibration method to make a black module with an open shell. Through comparative experiments, a mapping relationship model between the chip NTC temperature signal and the chip junction temperature can be established. By monitoring the chip NTC temperature signal in real time, the actual junction temperature of the chip during actual operation can be directly detected.

[0050] In some embodiments, the aperture diameter of the observation aperture array is 6-10 mm.

[0051] In this embodiment, if the aperture diameter of the observation aperture array is too small, the imaging field of view will be severely limited, making it difficult to ensure coverage of the entire effective heat-generating area of ​​the chip. In order to facilitate clear differentiation between the central and edge areas of the power module chip, the minimum aperture diameter of a single observation aperture is 6mm.

[0052] Meanwhile, since opening holes inevitably reduces the structural strength of the casing, and the size of power module chips is usually no more than 10mm, the maximum diameter of a single observation hole is 10mm to avoid cracking or deformation due to insufficient strength.

[0053] It should be noted that the aperture position deviation needs to be controlled within ±0.05mm to ensure that the observation aperture array can be accurately positioned above the power module chip, providing a complete infrared temperature measurement channel.

[0054] Reference Figure 1 In some embodiments, the housing also includes a first NTC signal terminal 102 and a second NTC signal terminal 103.

[0055] The NTC thermistor is connected to the first NTC signal terminal and the second NTC signal terminal respectively through wires to form an NTC temperature detection circuit.

[0056] The NTC temperature sensing circuit is used to bring the chip's NTC temperature signal out to the outside of the package structure.

[0057] In this embodiment, the 62mm standard package configuration of the related technology only includes four core signal terminals: gate, collector / drain, power source, and Kelvin source, such as... Figure 2 As shown, its design with four terminals on each side only uses four terminals on one side, leaving the four reserved sockets on the right side unused and not fully utilized.

[0058] In view of this, this embodiment proposes an integrated temperature sensing solution, which utilizes unused sockets to add two signal terminals to construct an independent temperature measurement channel, thereby achieving higher junction temperature measurement accuracy without significantly changing the package size by simply adding signal terminals.

[0059] Specifically, such as Figure 1 As shown, an NTC temperature detection circuit is added by reusing the existing but unused signal terminals on the housing to avoid interference with the main circuit and achieve signal isolation design.

[0060] The NTC temperature detection circuit includes an NTC temperature sensor, a first NTC signal terminal, and a second NTC signal terminal. The NTC thermistor is connected to both the first and second NTC signal terminals via bonding wires. Figure 4 As shown, the acquired chip NTC temperature signal is extracted from the package structure through two NTC signal terminals for external devices to collect. It should be noted that NTC leads need to be electromagnetically shielded to prevent power circuit coupling noise.

[0061] In some embodiments, the straight-line distance between the NTC thermistor and the nearest contour edge of the power module chip is greater than or equal to 0.8 mm.

[0062] In this embodiment, the NTC thermistor used to monitor the temperature near the chip is arranged in two ways, such as... Figure 4 As shown, the first NTC layout is located near the bonding region. The advantage of this scheme is that the layout design and implementation are relatively simple, the layout is easier to implement, and the requirements for internal wiring and insulation distance of the module are lower, which is conducive to improving process robustness and controlling manufacturing costs. However, the heat transfer path is longer, resulting in a large temperature difference between the temperature measured by the NTC thermistor and the chip junction temperature. Moreover, the monitoring data is easily affected by the temperature field fluctuations inside the module, and the measurement data also fluctuates greatly. Therefore, the stability and accuracy are relatively limited.

[0063] like Figure 5 As shown, the second type of NTC thermistor is directly placed next to the power module chip. This layout has more stringent requirements for layout design, but it greatly shortens the thermal path between the NTC thermistor and the power module chip. The measured temperature is closer to the chip junction temperature, and the accuracy of the measured data is higher. This greatly improves the accuracy of temperature monitoring and dynamic response characteristics, and is especially suitable for application scenarios with high requirements for junction temperature estimation accuracy and real-time performance.

[0064] It should be noted that, theoretically, the closer the NTC thermistor is to the power module chip, the better. However, the power module chip operates at a high potential of several hundred volts, while the NTC circuit is a low-voltage circuit. If the physical distance is too close, breakdown can easily occur between the power module chip and the NTC thermistor. Therefore, 0.8 mm is taken as the safe distance between the nearest contour edge of the NTC thermistor and the power module chip. The straight-line distance between the nearest contour edge of the NTC thermistor and the power module chip should be greater than or equal to the safe distance.

[0065] It is understandable that in actual engineering design, the placement of NTC thermistors can be selected based on actual packaging constraints, performance indicators, cost requirements, and other practical considerations. This application does not impose any specific restrictions on this placement.

[0066] In some embodiments, the lower surface of the NTC thermistor is insulated, and the upper surface of the NTC thermistor is used for bonding to form a path.

[0067] In this embodiment, the NTC thermistor is currently fully conductive, therefore its soldering surface is the electrical connection surface. To meet the requirements of electrical isolation, it can only be soldered into an isolation circuit, such as... Figure 4 As shown, the isolation circuit where the NTC thermistor is located is laid out in a safe area far away from the power module chip. Therefore, the NTC thermistor is always a large distance away from the power module chip.

[0068] To allow the NTC thermistor to be placed as close as possible to the power module chip, this embodiment modifies the structure of the NTC thermistor. The lower surface of the NTC thermistor is insulated to serve as a soldering surface, and bonding can only be performed on the surface to form a path. In the modified NTC thermistor, the soldering surface and the electrical connection surface are independent, allowing the NTC thermistor to be placed closer to the chip. Figure 5 As shown, the NTC thermistor no longer needs to be placed in the isolation circuit, which can overcome the layout limitations and be installed closer to the power module chip.

[0069] In some embodiments, the surface of the substrate is covered with a double coating, which includes a primer coating and a black paint coating, wherein the primer coating is located between the substrate and the black paint coating.

[0070] The primer coating is an insulating layer with a thickness of 100 micrometers or more, used for electrical isolation.

[0071] The black paint coating is a composite coating with resin as the base material and carbon-based material as the filler, used for temperature measurement calibration.

[0072] In this embodiment, after the 62mm power terminal is soldered, the original process should be to apply sealant to the outer shell for curing and to use silicone gel potting. However, since the black module needs to be kept open for infrared observation, the silicone gel potting scheme is abandoned and the insulating varnish is used to undertake all electrical isolation functions. The black varnish layer also has the function of temperature measurement and calibration.

[0073] Specifically, high-temperature tape is first used to seal the seam area around the base plate to form a temporary isolation zone, preventing the subsequent spraying of insulating paint or black paint from seeping into the sealing groove and thus avoiding affecting the final curing effect of the sealant.

[0074] Next, a double-coating process is adopted. First, an insulating primer (thickness ≥100μm) is sprayed, and then a black paint with resin material as base and carbon-based material as filler is applied to achieve full surface coverage without dead corners. The chip edges and terminal roots are treated with special attention. The resin material includes, but is not limited to, silicone resin or epoxy resin, and the carbon-based material includes, but is not limited to, fillers such as graphite and carbon black.

[0075] After the painting process is completed, remove the tape. The coating effect is as follows: Figure 6 As shown, the outer shell is assembled and cured normally to produce the finished product.

[0076] This embodiment also provides a chip temperature measurement method, applied to the aforementioned packaging structure, which includes the following steps: Step S101: The power module chip is subjected to infrared temperature measurement through an observation aperture array to obtain the chip junction temperature.

[0077] Step S102: The NTC temperature of the power module chip is detected by an NTC thermistor to obtain the chip's NTC temperature signal.

[0078] Step S103: Perform curve fitting on the relationship between the chip junction temperature and the chip NTC temperature signal to obtain the chip temperature rise mapping relationship.

[0079] Step S104: Based on the chip temperature rise mapping relationship, perform temperature conversion according to the current chip NTC temperature signal to obtain the current chip junction temperature.

[0080] In this embodiment, as Figure 3 As shown, the observation aperture array provides a non-contact channel for the infrared detector, enabling non-contact temperature measurement of the power module chip using an infrared thermal imager during infrared temperature measurement.

[0081] Specifically, such as Figure 7 As shown, the standard 62mm package is pre-treated with special surface treatment according to the packaging structure provided in this application. A hole is made on the outer shell corresponding to the position directly above the chip, and black paint is applied to the ceramic substrate to meet the optical characteristics requirements for infrared thermometry, thus completing the sample preparation of the device under test (DUT). Then, the packaged DUT is placed on a fixed base plate, and standard wiring of the power and signal terminals is completed (including necessary circuits such as gate drive and current detection). Idle terminals are activated to construct an NTC test channel (using a 4-wire measurement system to eliminate lead wire errors). An infrared thermal imager is mounted directly above the DUT, and the field of view is adjusted to cover the entire chip area, ensuring that all power module chips can be captured through the observation hole array. The blackbody emissivity is calibrated (referencing the emissivity parameters of the black paint coating).

[0082] To avoid edge heat dissipation interference, the highest temperature in the central area of ​​the chip is collected non-contactly using an infrared thermal imager as a characteristic value of the chip junction temperature, thus obtaining the chip junction temperature.

[0083] Understandably, infrared devices need to avoid interference from ambient light, so testing in a dark room is preferred.

[0084] During infrared temperature measurement, the NTC temperature of the device under test is simultaneously detected. The NTC thermistor detects the NTC temperature around the chip and leads the chip's NTC temperature signal to the outside of the package. The NTC resistance value can be directly acquired externally via an electrical signal. For example, the NTC thermistor can be connected to an ammeter through an NTC test circuit to sample the chip's NTC temperature signal detected by the NTC thermistor.

[0085] It should be noted that when recording data, the direct observation results of infrared thermometry and the reading data of NTC temperature detection need to be collected simultaneously, and both should be marked with a unified timestamp to ensure that the time delay is less than 10ms.

[0086] In the entire operating environment of the power module, since the chip cannot be placed directly on the NTC, there will inevitably be a temperature difference. In this embodiment, the thermistor is placed as close as possible to the chip, and what is obtained is actually the temperature around the chip. Therefore, in subsequent experiments, it is necessary to obtain the corresponding curve of the NTC and chip junction temperature through experiments.

[0087] Specifically, to find the temperature gap between the power module chip and the NTC, it is necessary to find the correspondence between the chip NTC temperature signal and the chip junction temperature so as to deduce the chip junction temperature from the chip NTC temperature signal.

[0088] To address the temperature difference between the NTC and the power module chip, a mathematical model was constructed to establish the relationship between the measured NTC value and the actual junction temperature using multi-condition test data.

[0089] For example, a stepped current is applied starting from 10% of the rated value, with each step held for 5 minutes, to obtain chip junction temperature and chip NTC temperature signals under different operating conditions. During the measurement, the dual-channel data are compared in real time, and the test is immediately paused if the abnormal temperature difference exceeds 15°C. In addition, the temperature resistance of the sealant is monitored throughout the test to prevent softening at high temperatures that could lead to leakage.

[0090] A mathematical model of the relationship between NTC measurement value and actual junction temperature is established based on multi-condition measurement data, and the temperature mapping relationship Tj=f(T_{NTC})+ΔT_{cal} is obtained, where ΔT_{cal} is calibrated by the black module reference.

[0091] like Figure 8 As shown, by testing under different power conditions, the degree of chip heating is different, and the corresponding relationship between NTC and chip junction temperature is obtained. The corresponding curve is fitted. According to the fitted curve, the temperature rise of thermal imaging Tj is approximately (5.67) * NTC temperature rise.

[0092] Through experimental verification, based on the successfully established mapping relationship model between NTC temperature and chip junction temperature, after adding an NTC thermistor to the new 62mm power module package structure, the current chip junction temperature can be accurately calculated by monitoring the current chip NTC temperature signal in real time and using a temperature conversion algorithm.

[0093] This embodiment achieves traceability of measurement results through a standardized calibration process, making it suitable for high-reliability application scenarios that require long-term temperature monitoring. It does not require modification of the module's internal structure, maintaining the original reliability and effectively solving the technical requirement of real-time monitoring of the chip core temperature during the operation of the power module, providing key data support for system reliability assessment.

[0094] Reference Figure 9 This application also provides a chip temperature measurement system that can implement the above method. The system includes: The infrared temperature measurement module is used to perform infrared temperature measurement on the power module chip through an observation aperture array to obtain the chip junction temperature.

[0095] The NTC temperature detection module is used to detect the NTC temperature of the power module chip through an NTC thermistor and obtain the chip's NTC temperature signal.

[0096] The curve fitting module is used to perform curve fitting on the relationship between the chip junction temperature and the chip NTC temperature signal to obtain the chip temperature rise mapping relationship.

[0097] The temperature conversion module is used to perform temperature conversion based on the chip temperature rise mapping relationship and the current chip NTC temperature signal to obtain the current chip junction temperature.

[0098] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0099] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0100] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0101] Reference Figure 10 , Figure 10The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 901 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0102] The memory 902 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 902 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 902 and is called and executed by the processor 901 using the methods described in the embodiments of this application.

[0103] The input / output interface 903 is used to implement information input and output.

[0104] The communication interface 904 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0105] Bus 905 transmits information between various components of the device, such as processor 901, memory 902, input / output interface 903, and communication interface 904.

[0106] The processor 901, memory 902, input / output interface 903, and communication interface 904 are connected to each other within the device via bus 905.

[0107] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0108] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0109] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0110] It is understood that the content of the above method embodiments is applicable to the embodiments of this program product. The specific functions implemented by the embodiments of this program product are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0111] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0112] This application provides a packaging structure and chip temperature measurement method for a power module chip with a built-in NTC thermistor. The packaging structure includes a shell, a substrate, a power module chip, and an NTC thermistor. The shell is fixedly connected to the substrate by bolts, and the power module chip and NTC thermistor are mounted on the substrate. An array of observation holes is provided on the shell, located above the power module chip, to provide an infrared temperature measurement channel for the chip's junction temperature. The NTC thermistor is used to detect the NTC temperature signal of the power module chip. This application improves the accuracy of junction temperature measurement, directly detecting the actual junction temperature of the chip during operation.

[0113] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0114] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0115] The system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0116] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0117] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0118] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0119] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or units may be electrical, mechanical, or other forms.

[0120] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0121] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0122] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0123] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A packaging structure for a power module chip with an integrated NTC junction temperature, characterized in that, The device includes a housing, a substrate, a power module chip, and an NTC thermistor, wherein the housing is fixedly connected to the substrate by bolts, and the power module chip and the NTC thermistor are mounted on the substrate. The outer casing has an array of observation holes located above the power module chip, which is used to provide an infrared temperature measurement channel for the junction temperature of the power module chip. The NTC thermistor is used to detect the NTC temperature signal of the power module chip.

2. The packaging structure according to claim 1, characterized in that, The aperture diameter of the observation aperture array is 6-10 mm.

3. The packaging structure according to claim 1, characterized in that, The housing also includes a first NTC signal terminal and a second NTC signal terminal; The NTC thermistor is connected to the first NTC signal terminal and the second NTC signal terminal respectively via wires to form an NTC temperature detection circuit; The NTC temperature detection circuit is used to lead the chip's NTC temperature signal to the outside of the package structure.

4. In the packaging structure according to claim 1, the straight-line distance between the NTC thermistor and the nearest contour edge of the power module chip is greater than or equal to 0.8 mm.

5. The packaging structure according to claim 1, characterized in that, The lower surface of the NTC thermistor is insulated, and the upper surface of the NTC thermistor is used for bonding to form a circuit.

6. The packaging structure according to claim 1, characterized in that, The surface of the substrate is covered with a double coating, which includes a primer coating and a black paint coating, wherein the primer coating is located between the substrate and the black paint coating; The primer coating is an insulating layer with a thickness of 100 micrometers or more, used for electrical isolation; The black paint coating is a composite coating with resin material as the base and carbon-based material as the filler, used for temperature measurement calibration.

7. A chip temperature measurement method, applied to the packaging structure as described in any one of claims 1 to 6, characterized in that, Includes the following steps: The junction temperature of the power module chip is obtained by infrared thermometry using an observation aperture array. The NTC temperature of the power module chip is detected by an NTC thermistor to obtain the chip's NTC temperature signal. Curve fitting is performed on the relationship between the chip junction temperature and the chip NTC temperature signal to obtain the chip temperature rise mapping relationship; Based on the chip temperature rise mapping relationship, the current chip junction temperature is obtained by performing temperature conversion according to the current chip NTC temperature signal.

8. A chip temperature measurement system, characterized in that, The system includes: The infrared temperature measurement module is used to perform infrared temperature measurement on the power module chip through the observation aperture array to obtain the chip junction temperature. The NTC temperature detection module is used to detect the NTC temperature of the power module chip through an NTC thermistor and obtain the chip's NTC temperature signal. The curve fitting module is used to perform curve fitting on the relationship between the chip junction temperature and the chip NTC temperature signal to obtain the chip temperature rise mapping relationship. The temperature conversion module is used to perform temperature conversion based on the chip temperature rise mapping relationship and the current chip NTC temperature signal to obtain the current chip junction temperature.

9. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method of claim 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of claim 7.

Images