Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a cage, a semiconductor chip, a package, and a first redistribution layer. The cage has a first cage surface, a second cage surface opposite the first cage surface, and a cavity from the first cage surface to the second cage surface. The semiconductor chip is disposed in the cavity. The package covers the semiconductor chip. The first redistribution layer is formed over the package and the semiconductor chip.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] The chip (or die) and the substrate need to be aligned to ensure accurate contact. Generally, chip displacement / slippage may be caused by (1) the difference in the coefficients of thermal expansion between the chip and the substrate, and (2) the chip size. The larger the chip size, the greater the warping of the substrate, and the greater the warping, the less accurate the contact. Summary of the Invention

[0003] One embodiment of the present invention provides a semiconductor device. The semiconductor device includes a cage-like component, a semiconductor chip, a package, and a first redistribution layer. The cage-like component has a first cage-like component surface, a second cage-like component surface opposite to the first cage-like component surface, and a cavity extending from the first cage-like component surface to the second cage-like component surface. The semiconductor chip is disposed in the cavity. The package covers the semiconductor chip. The first redistribution layer is formed above the package and the semiconductor chip.

[0004] In one example, the cavity extends to the surface of the first cage-like member.

[0005] In one example, the semiconductor chip has a back side, and the back side of the semiconductor chip is flush with the surface of the second cage of the cage.

[0006] In one example, the semiconductor chip protrudes relative to the surface of the first cage-like member of the cage-like member.

[0007] In one example, the package has a package side, the cage has a cage side, and the package side and the cage side are flush with each other.

[0008] In one example, the cage has a cage surface and the package covers the cage surface and the first cage surface, but exposes the second cage surface.

[0009] In one example, the cavity is a blind via located on a cage-like component, which is a substrate. The semiconductor chip is a flip-chip with an active surface, which is bonded to the substrate in the blind via, with the active surface facing the blind via.

[0010] In one example, the semiconductor chip is a flip-chip with an active surface, a first redistribution layer is disposed on the surface of the second cage and the active surface, and the package covers the first cage surface of the cage.

[0011] In one example, the semiconductor device further includes a conductive layer. The conductive layer is located within the cavity. A semiconductor chip is disposed on the conductive layer, the package has a package surface and a through-hole extending from the package surface to the conductive layer, and the semiconductor device further includes a conductive portion located within the through-hole.

[0012] In one example, the semiconductor device further includes a conductive portion. The conductive portion extends from the surface of the second cage to the surface of the first cage.

[0013] In one example, the semiconductor device further includes a second layer and a third layer. The second layer is disposed on the surface of the second cage-like member. The third layer is disposed on the surface of the first cage-like member and located between the first layer and the surface of the first cage-like member. A conductive portion electrically connects the second layer and the third layer.

[0014] In one example, the package is disposed in a cavity and between one side of the semiconductor chip and the side of the cavity.

[0015] Another embodiment of the present invention provides a method for manufacturing a semiconductor device. The manufacturing method includes the following steps: disposing a cage-like member on a carrier, wherein the cage-like member has a first cage-like member surface, a second cage-like member surface opposite to the first cage-like member surface, and a cavity extending from the first cage-like member surface to the second cage-like member surface; disposing a semiconductor chip in the cavity; disposing a package covering the semiconductor chip; disposing a first overlay layer covering the package and the semiconductor chip; and removing the carrier to expose the first overlay layer.

[0016] In one example, the step of configuring the first overlay to cover the package and the semiconductor chip includes: configuring the first overlay on a carrier; transferring the first overlay via the carrier to the package and the semiconductor chip; and removing the carrier.

[0017] In one example, the manufacturing method further includes removing a portion of the cage-like component and the semiconductor chip.

[0018] In one example, during the step of configuring the package to cover the semiconductor chip, the package further covers one side of the cage-like component.

[0019] In one example, a cage-like component containing a cavity with a blind via is disposed on a carrier; the semiconductor chip is a flip-chip, flip-chip bonded into the blind via, with one active surface of the semiconductor chip facing the blind via.

[0020] In one example, the manufacturing method further includes: disposing a conductive layer in a cavity; disposing a semiconductor chip on the conductive layer in the cavity; disposing a package covering the semiconductor chip; forming a through-hole extending from a package surface of the package to the conductive layer; and forming a conductive portion in the through-hole.

[0021] In one example, the step of configuring the cage-like member on the carrier includes: forming a conductive portion, wherein the conductive portion extends from the surface of the second cage-like member to the surface of the first cage-like member.

[0022] In one example, the step of configuring the cage-like member on the carrier includes: configuring a second layer of fabric on the surface of the second cage-like member; and configuring a third layer of fabric on the surface of the first cage-like member, wherein the third layer of fabric is located between the first layer of fabric and the surface of the first cage-like member, and the conductive portion is electrically connected to the second layer of fabric and the third layer of fabric.

[0023] In one example, in the step of configuring the package to cover the semiconductor chip, the package is configured in a cavity and between one side of the semiconductor chip and one side of the cavity.

[0024] This invention primarily addresses the issue that during the chip packaging reconstruction process of wafer-level packaging or panel-level packaging products, the molding compound may cause excessive chip displacement during the covering process of the package, thereby affecting the workability and stability of subsequent processes (such as the fabrication of redistribution layers). Therefore, it proposes various improvements to the package structure and manufacturing process to improve and ensure high yield and output of the final product. Attached Figure Description

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0026] Figure 1A A schematic diagram of a semiconductor device according to an embodiment of the present invention is shown.

[0027] Figure 1B Showing according to Figure 1A A cross-sectional view of the semiconductor device along direction 1B-1B'.

[0028] Figure 2 A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown.

[0029] Figure 3 A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown.

[0030] Figure 4 A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown.

[0031] Figure 5 A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown.

[0032] Figure 6A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown.

[0033] Figure 7 A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown.

[0034] Figure 8 A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown.

[0035] Figures 9A-9I Show Figure 1B A process diagram illustrating a method for manufacturing an embodiment of a semiconductor device.

[0036] Figures 10A-10C Show Figure 1B A process diagram of a manufacturing method for another embodiment of a semiconductor device.

[0037] Figures 11A-11C Show Figure 2 A process diagram illustrating a method for manufacturing an embodiment of a semiconductor device.

[0038] Figures 12A-12I Show Figure 3 A process diagram illustrating a method for manufacturing an embodiment of a semiconductor device.

[0039] Figures 13A-13C Show Figure 3 A process diagram of a manufacturing method for another embodiment of a semiconductor device.

[0040] Figures 14A-14I A process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0041] Figures 15A-15I Show Figure 3 A process diagram of a semiconductor device manufacturing method.

[0042] Figures 16A-16G Show Figure 4 A process diagram illustrating a method for manufacturing an embodiment of a semiconductor device.

[0043] Figures 17A-17J Show Figure 5 A process diagram illustrating a method for manufacturing an embodiment of a semiconductor device.

[0044] Figures 18A-18I Show Figure 6 A process diagram illustrating a method for manufacturing an embodiment of a semiconductor device.

[0045] Figures 19A-19J Show Figure 7 A process diagram illustrating a method for manufacturing an embodiment of a semiconductor device.

[0046] Figures 20A-20CShow Figure 7 A process diagram of a manufacturing method for another embodiment of a semiconductor device.

[0047] Figures 21A-21G Show Figure 8 A process diagram illustrating a method for manufacturing an embodiment of a semiconductor device.

[0048] Figure 22A A schematic diagram of a panel-level package according to one embodiment is shown.

[0049] Figure 22B Show Figure 22A A cross-sectional view of the panel-level package along direction 22B-22B'.

[0050] Figure label:

[0051] 10,20,40: Carrier

[0052] 11,21: Release layer

[0053] 40r: Cavity

[0054] 55a: Hole

[0055] 55: Spacers

[0056] 57: Filler

[0057] 100, 100', 200, 300, 400, 500, 600, 700, 800, 900: Semiconductor devices

[0058] 110, 310, 410, 610: Cage-shaped components

[0059] 110', 410', 610': cage plate

[0060] 110c, 310c, 410c, 610c: Cavity

[0061] 110s1, 310s1, 410s1, 610s1: Surface of the first cage-like component

[0062] 110s², 310s², 410s², 610s²: Surface of the second cage-like component

[0063] 110s3, 310s3, 410s3, 610s3: Side of the first cage-like component

[0064] 110s4, 610s4: Side of the second cage-like component

[0065] 120, 220, 520, 620, 720: Semiconductor chips

[0066] 120s, 520s, 720s: Side view

[0067] 120b, 520b, 520u, 620b, 620u: Chip surface

[0068] 121,221,721: Base

[0069] 122: Front-end process structure

[0070] 123: Back-end process structure

[0071] 124,150,624:Contact

[0072] 124u: Contact surface

[0073] 130, 230, 430, 630: Package

[0074] 130', 230': Package material

[0075] 130s, 130u: Package side

[0076] 130A: Packaging Island

[0077] 140: First layer of fabric

[0078] 140': First layer structure

[0079] 140s, 440s, 460s: Side of the re-weave layer

[0080] 141: Conductive pad

[0081] 142,450,750: Conductive parts

[0082] 143: Dielectric layer

[0083] 220b: Chip surface

[0084] 230b, 630u: Package surface

[0085] 400A: Semiconductor Components

[0086] 440: Second layer

[0087] 440': Second layer structure

[0088] 460: Third layer

[0089] 460': Third layer structure

[0090] 520u: Chip surface

[0091] 670: Bottom filling

[0092] 721b: First Surface

[0093] 721u: Second Surface

[0094] 722, 724, 725: Electrodes

[0095] 723: Solder

[0096] 724u, 725u: Electrode surface

[0097] 750a: Hole

[0098] 750u, 770b: Conductive surfaces

[0099] 770: Conductive layer

[0100] 770u: Surface

[0101] 810:Substrate

[0102] d1: Distance

[0103] DS: Divider

[0104] P1: Cutting Channel

[0105] t1, t2, t3, t4: Thickness Detailed Implementation

[0106] The following embodiments are disclosed to illustrate the present invention in detail. These embodiments are for illustrative purposes only and are not intended to limit the scope of patent protection of the present invention. Furthermore, minor components may be omitted in the following embodiments to highlight the technical features of the present invention.

[0107] Please refer to Figures 1A and 1B. Figure 1A A schematic diagram of a semiconductor device 100 according to an embodiment of the present invention is shown, and Figure 1B Showing according to Figure 1A A cross-sectional view of the semiconductor device 100 along direction 1B-1B'.

[0108] As shown in Figures 1A and 1B, the semiconductor device 100 includes at least one cage-like member 110, at least one semiconductor chip 120, a package 130, a first redistribution layer (RDL) 140, and at least one contact 150. The cage-like member 110 has a first cage-like member surface 110s1, a second cage-like member surface 110s2 opposite to the first cage-like member surface 110s1, and a cavity 110c extending from the first cage-like member surface 110s1 toward the second cage-like member surface 110s2. The semiconductor chip 120 is disposed within the cavity 110c. The package 130 covers the semiconductor chip 120. The first redistribution layer 140 is disposed above the package 130 and the semiconductor chip 120. The cage-like member 110 can restrain the displacement of the semiconductor chip 120. Furthermore, during the manufacturing process of the semiconductor device 100, the semiconductor chip 120 can be placed in the cavity 110c of the cage-like member 110 to be confined in the cavity 110c, thereby improving the positioning accuracy of the semiconductor chip 120 and the first layer 140.

[0109] Furthermore, chip displacement / slippage is caused by: (1) the difference in the coefficient of thermal expansion (CTE) between the carrier, the molding compound, and the embedded chip, as well as the chemical shrinkage of the molding compound; and (2) the influence of chip size, chip adhesion to the release layer, flow behavior of the molding compound, and related forces on the chip during compression molding. Geometry (e.g., carrier type and thickness, mold thickness, chip thickness, total silicon content / density, side panel size, etc.) also plays an important role in chip displacement / slippage and panel warpage. The solutions in this application, including but not limited to chip cages / stops / constrainers, permanent die bonding, related processes, and adaptive patterning, may help to minimize the impact. The term "bonding" in this application may also be referred to as "bonding".

[0110] Furthermore, warpage is also caused by differences in the coefficients of thermal expansion between the carrier, molding compound, and embedded chip, and is affected by the chemical shrinkage of the molding compound. Geometry (e.g., carrier type and thickness, die thickness, chip thickness, total silicon content / density, side panel dimensions, etc.) also plays a significant role in chip displacement / slippage and panel warpage. The solution of this application includes thicker, more rigid carriers (including cage-like treatments) / support substrates with sufficient thickness and thermomechanical properties (e.g., coefficient of thermal expansion, modulus, etc.) to minimize warpage. Separate overmolding islands (see Figures 22A and 22B) can be used to separate die blocks from other die blocks to minimize thermal expansion mismatch, mold flow, and other effects. Lower coefficients of thermal expansion, lower modulus molding compounds or encapsulation materials, and adaptive patterning can minimize warpage effects.

[0111] Furthermore, the fine-line / space (L / S) capability in semiconductor devices can be equal to or less than 2 / 2 μm. Significant FOPLP process development is required to address the major technological and material challenges posed by the substantial increase in panel area. Building more and finer L / S redistribution layers on large panels leads to reduced yield and increased chip waste. The solution presented in this application includes heterogeneous integration of wafer and substrate technologies, aided by FOPLP (e.g., building finer L / S redistribution layers on a carrier wafer, testing them to ensure known good structures, dicing the wafer, and bonding the known good redistribution layers to the dies on the panel). A horizontal-level fine L / S redistribution layer is created using liquid resist spraying, and a vertical-level fine L / S redistribution layer is formed using laser drilling, DRIE, dry argon desmear, physical vapor deposition (CVD) of barrier / seed layers, dry film, metalhard mask, copper pillar plating, wet cleaning, and combinations thereof. Built-in redistribution layer test circuitry (e.g., daisy chains), multi-site panel-level testing, and / or chip-related built-in self-test (BIST) are implemented.

[0112] In this embodiment, the cage-like component 110 may be formed of materials including metal, glass, ceramic, etc. In one embodiment, the cage-like component 110 may not include any circuit components.

[0113] like Figure 1A As shown, the cage-like member 110 is in a dead loop shape. In another embodiment, the cage-like member 110 may be an open-ring shape. Viewed from above (towards the -Z axis), the cage-like member 110 may be polygonal (e.g., rectangle, triangle, etc.), circular, elliptical, etc. The cage-like member 110 has a first cage-like member side 110s3 and a second cage-like member side 110s4 opposite to the first cage-like member side 110s3. The distance d1 between the second cage-like member side 110s4 of the cage-like member 110 and the side 120s of the semiconductor chip 120 may be between, for example, 1 micrometer to 10 micrometers, such as 1 micrometer, 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, 9 micrometers, or 10 micrometers. Such a distance d1 can improve the positioning accuracy of the semiconductor chip 120 and the first redistribution layer 140.

[0114] In this embodiment, the cavity 110c is a through hole. For example, the cavity 110c extends from the surface 110s2 of the second cage-like member to the surface 110s1 of the first cage-like member. In another embodiment, the cavity 110c is, for example, a blind hole.

[0115] like Figure 1B As shown, the semiconductor chip 120 includes a substrate 121, a front-end-of-line (FEOL) structure 122, a back-end-of-line (BEOL) structure 123, and at least one contact 124. The substrate 121 is, for example, a portion of a silicon wafer. The front-end-of-line structure 122 is formed within and / or on the substrate 121, the back-end-of-line structure 123 is formed within and / or on the front-end-of-line structure 122 and electrically connected to it, and the contact 124 is formed on and electrically connected to the back-end-of-line structure 123. The contact 124 is, for example, a solder ball, a microbump, a micropillar, etc.

[0116] like Figure 1B As shown, the semiconductor chip 120 has a chip surface (back side of the chip) 120b, which is exposed outside the cavity 110c, and the chip surface 120b of the semiconductor chip 120 is aligned with (e.g., flush with) the second cage surface 110s2 of the cage-like member 110. Furthermore, the semiconductor chip 120 protrudes relative to the first cage surface 110s1 of the cage-like member 110.

[0117] like Figure 1BAs shown, the package 130 encapsulates the cage-like component 110 and the semiconductor chip 120. For example, the package 130 covers the first cage-like surface 110s1 and the second cage-like side 110s4 of the cage-like component 110, the side 120s of the semiconductor chip 120, and the side of the contact 124, but exposes the second cage-like surface 110s2 and the first cage-like side 110s3 of the cage-like component 110. In addition, the package 130 also fills a portion of the cavity 110c.

[0118] like Figure 1B As shown, the package 130 has a package side 130s, and the package side 130s and the first cage side 110s3 are aligned with each other (e.g., flush). Furthermore, during the manufacturing process of the semiconductor device 100, the package side 130s and the first cage side 110s3 are formed, for example, by division (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0119] Furthermore, the encapsulation 130 may be, for example, a molding compound, laminated photoresist, etc. The molding compound includes, for example, a novolac-based resin, epoxy resin, silicone resin, or other suitable encapsulation material, and may contain suitable fillers such as powdered silica (SiO2). The molding compound may be formed through, for example, transfer molding, compression molding, lamination, etc.

[0120] like Figure 1BAs shown, a first re-layer 140 is disposed on and / or above the package 130 and the semiconductor chip 120. The first re-layer 140 is electrically connected to the semiconductor chip 120. For example, the first re-layer 140 is electrically connected to the contact 124 of the semiconductor chip 120. The first re-layer 140 includes at least one conductive pad 141 for receiving the contact 150. Since the semiconductor chip 120 is confined in the cavity 110c, the positioning accuracy of the contact 124 of the semiconductor chip 120 and the conductive pad 141 of the first re-layer 140 can be improved. The first re-layer 140 includes a conductive portion 142 and a dielectric layer 143. Furthermore, the first re-layer 140 has a re-layer side 140s, and the re-layer side 140s is aligned with (e.g., flush with) the first cage-like member side 110s3. Furthermore, during the manufacturing process of the semiconductor device 100, the redistribution layer side 140s and the first cage-like member side 110s3 are formed, for example, by slitting (e.g., sawing, such as diamond blade sawing or laser sawing). The conductive portion 142 may be formed of a material including metals (e.g., copper), and the dielectric layer 143 may be formed of a material including polyimide (PI), oxides, etc.

[0121] like Figure 1B As shown, contacts 150 are disposed on the first overlay 140. For example, each contact 150 is disposed on a corresponding conductive pad 141 of the first overlay 140. The semiconductor device 100 is, for example, a ball grid array (BGA), and the contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0122] Please refer to Figure 2 The diagram shows a cross-sectional view of a semiconductor device 200 according to another embodiment of the present invention.

[0123] like Figure 2 As shown, semiconductor device 200 includes at least one semiconductor chip 220, package 230, first redistribution layer 140, and at least one contact 150. Semiconductor device 200 includes the same or similar features as semiconductor device 100, wherein at least one difference is that the cage member 110 may be omitted in semiconductor device 200.

[0124] like Figure 2As shown, the semiconductor chip 220 includes a substrate 221, a front-end process structure 122, a back-end process structure 123, and at least one contact 124. The substrate 221 is, for example, a part of a silicon wafer. The front-end process structure 122 is formed in and / or on the substrate 221. The back-end process structure 123 is formed in and / or on the front-end process structure 122 and is electrically connected to the front-end process structure 122. The contact 124 is formed on the back-end process structure 123 and is electrically connected to the back-end process structure 123. The contact 124 is, for example, a solder ball, a micro-bump, a micro-column, etc.

[0125] As Figure 2 shown, the substrate 221 has a thickness t1. Compared with Figure 1B the substrate 121, the thickness t1 of the substrate 221 is less than the thickness of the substrate 121 in the same direction. The package 230 has a thickness t2. Compared with Figure 1B the package 130, the thickness t2 of the package 230 is less than the thickness of the package 130 in the same direction. In addition, during the manufacturing process of the semiconductor device 200, Figure 1B the cage-like member 110, a part of the semiconductor chip 120, and a part of the package 130 can be removed, for example, by grinding. After removal, a thinned semiconductor chip 220 and a thinned package 230 are formed. After removal, the substrate 221 of the semiconductor chip 220 forms a chip surface 220b, and the package 230 forms a package surface 230b, where the chip surface 220b of the semiconductor chip 220 and the package surface 230b of the package 230 are aligned (e.g., flush) with each other.

[0126] Please refer to Figure 3 , which shows a cross-sectional view of a semiconductor device 300 according to another embodiment of the present invention.

[0127] As Figure 3 shown, the semiconductor device 300 includes at least one cage-like member 310, at least one semiconductor chip 120, a package 130, a first redistribution layer 140, and at least one contact 150. The cage-like member 310 has a first cage-like member surface 310s1, a second cage-like member surface 310s2 opposite to the first cage-like member surface 310s1, and a cavity 310c extending from the first cage-like member surface 310s1 to the second cage-like member surface 310s2. The semiconductor chip 120 is disposed in the cavity 310c. The package 130 covers the semiconductor chip 120. The first redistribution layer 140 is disposed above the package 130 and the semiconductor chip 120. The cage-like member 310 can restrict the displacement amount of the semiconductor chip 120. In addition, during the manufacturing process of the semiconductor device 300, the semiconductor chip 120 can be placed in the cavity 310c of the cage-like member 310 to be restricted in the cavity 310c, thereby improving the positioning accuracy between the semiconductor chip 120 and the first redistribution layer 140.

[0128] In this embodiment, the cage-like member 310 may be formed of a material including organic or inorganic materials, such as metal, glass, ceramic, etc. In one embodiment, the cage-like member 310 does not include any circuit components. The cage-like member 310 may be formed of the same or similar material as the cage-like member 110.

[0129] In an embodiment, cavity 310c may include the same or similar features as described above. In this embodiment, cavity 310c is a through hole. For example, cavity 310c extends from the second cage surface 310s2 to the first cage surface 310s1. In another embodiment, cavity 310c is, for example, a blind hole.

[0130] like Figure 3 As shown, the package 130 covers the first cage-like member side 310s3 and the first cage-like member surface 310s1, but exposes the second cage-like member surface 310s2. Furthermore, the redistribution side 140s of the first redistribution layer 140 and the package side 130s of the package 130 are exposed from the semiconductor device 300. The redistribution side 140s of the first redistribution layer 140 and the package side 130s of the package 130 are aligned with each other (e.g., flush). Moreover, during the manufacturing process of the semiconductor device 300, the redistribution side 140s and the package side 130s are formed, for example, by splitting (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0131] Please refer to Figure 4 This shows a cross-sectional view of a semiconductor device 400 according to another embodiment of the present invention.

[0132] like Figure 4 As shown, the semiconductor device 400 includes a cage-like member 410, at least one semiconductor chip 120, a package 430, a first redistribution layer 140, at least one contact 150, a second redistribution layer 440, at least one conductive portion 450, and a third redistribution layer 460. The cage-like member 410 has a first cage-like surface 410s1, a second cage-like surface 410s2 opposite to the first cage-like surface 410s1, and a cavity 410c extending from the first cage-like surface 410s1 to the second cage-like surface 410s2. The semiconductor chip 120 is disposed in the cavity 410c. The package 430 covers the semiconductor chip 120. The first redistribution layer 140 is disposed above the package 430 and the semiconductor chip 120. The cage-like member 410 can restrain the displacement of the semiconductor chip 120. Furthermore, during the manufacturing process of the semiconductor device 400, the semiconductor chip 120 can be placed in the cavity 410c of the cage-like member 410 to be constrained in the cavity 410c, thereby improving the positioning accuracy of the semiconductor chip 120 and the first overlapping layer 140.

[0133] In this embodiment, the cage-like member 410 is, for example, a substrate, such as a laminated substrate, a silicon substrate, etc. The substrate may include at least one circuit component.

[0134] In this embodiment, the cavity 410c of the cage-like member 410 is, for example, a blind hole. Furthermore, the cavity 410c extends from the first cage-like member surface 410s1 to the second cage-like member surface 410s2, but does not extend to the second cage-like member surface 410s2.

[0135] like Figure 4 As shown, in this embodiment, at least a portion of the package 430 is disposed within the cavity 410c and located between the side 120s of the semiconductor chip 120 and the side 410c1 of the cavity 410c. In this embodiment, the package 430 does not cover the first cage surface 410s1 of the cage 410. Furthermore, the package 430 may be formed of the same or similar material as the package 130. In another embodiment, the package 430 may be formed of materials such as epoxy resin, polyimide, silicone, polyxylylenes, soloxane polyimide, benzocy clobutene, etc.

[0136] Figure 4 As shown, the first pleated fabric layer 140 is disposed above and / or above the third pleated fabric layer 460. The second pleated fabric layer 440 is disposed on the second cage-like surface 410s2, and the third pleated fabric layer 460 is disposed on the first cage-like surface 410s1 and located between the first pleated fabric layer 140 and the first cage-like surface 410s1. The second pleated fabric layer 440 includes the same or similar features (e.g., structure) as the first pleated fabric layer 140, and the third pleated fabric layer 460 includes the same or similar features (e.g., structure) as the first pleated fabric layer 140.

[0137] Figure 4 As shown, the cage-like member 410 has a first cage-like member side 410s3, the first layer 140 has a layer side 140s, the second layer 440 has a layer side 440s, and the third layer 460 has a layer side 460s. The first cage-like member side 410s3, the layer side 140s, the layer side 440s, and the layer side 460s are aligned with each other (e.g., flush). Furthermore, during the manufacturing of the semiconductor device 400, the first cage-like member side 410s3, the layer side 140s, the layer side 440s, and the layer side 460s are formed, for example, by division (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0138] Figure 4As shown, the conductive portion 450 electrically connects the second repetitive layer 440 and the third repetitive layer 460. Furthermore, the conductive portion 450 extends from the surface 410s2 of the second cage-like member to the surface 410s1 of the first cage-like member to electrically connect the second repetitive layer 440 and the third repetitive layer 460. In embodiments, the conductive portion 450 is, for example, a conductive via or a conductive pillar. The conductive portion 450 may be formed of a material including, for example, metals (e.g., copper) or alloys thereof.

[0139] Please refer to Figure 5 The diagram shows a cross-sectional view of a semiconductor device 500 according to another embodiment of the present invention.

[0140] like Figure 5 As shown, the semiconductor device 500 includes at least one cage-like member 110, at least one semiconductor chip 520, a package 130, a first redistribution layer 140, and at least one contact 150. The cage-like member 110 has a first cage-like member surface 110s1, a second cage-like member surface 110s2 opposite to the first cage-like member surface 110s1, and a cavity 110c extending from the first cage-like member surface 110s1 to the second cage-like member surface 110s2. The semiconductor chip 520 is disposed within the cavity 110c. The package 130 covers the semiconductor chip 520. The first redistribution layer 140 is disposed above the package 130 and the semiconductor chip 520. The cage-like member 110 can restrain the displacement of the semiconductor chip 520. Furthermore, during the manufacturing process of the semiconductor chip, the semiconductor chip 520 can be placed in the cavity 110c of the cage-like member 110 and constrained within the cavity 110c, which can increase the positioning accuracy of the semiconductor chip 520 and the first overlapping layer 140.

[0141] like Figure 5 As shown, the cage-like member 110 is in a dead loop shape. In another embodiment, the cage-like member 110 may be in an open ring shape. Viewed from above, the cage-like member 110 may be polygonal (e.g., rectangular, triangular, etc.), circular, elliptical, etc. The cage-like member 110 has a first cage-like member side 110s3 and a second cage-like member side 110s4 opposite to the first cage-like member side 110s3. The distance d1 between the second cage-like member side 110s4 of the cage-like member 110 and the side 520s of the semiconductor chip 520 may be, for example, between 1 micrometer and 10 micrometers, such as 1 micrometer, 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, 9 micrometers, or 10 micrometers. Such a distance d1 can improve the positioning accuracy of the semiconductor chip 520 and the first redistribution layer 140.

[0142] In this embodiment, the cavity 110c is a through hole. Furthermore, the cavity 110c extends from the second cage-like surface 110s2 to the first cage-like surface 110s1. In another embodiment, the cavity 110c is, for example, a blind hole.

[0143] like Figure 5 As shown, semiconductor chip 520 includes a substrate 121, a front-end processing structure 122, and a back-end processing structure 123. Compared to semiconductor chip 120, semiconductor chip 520 may omit the contact 124. The substrate 121 is, for example, a portion of a silicon wafer. The front-end processing structure 122 is formed within and / or on the substrate 121, and the back-end processing structure 123 is formed within and / or on the front-end processing structure 122 and electrically connected to the front-end processing structure 122. The back-end processing structure 123 is electrically connected to the contact 150 through a first redistribution layer 140.

[0144] like Figure 5 As shown, the semiconductor chip 520 has a chip surface 520b, which is exposed in the cavity 110c, and the chip surface 520b of the semiconductor chip 520 is aligned with (e.g., flush with) the second cage surface 110s2 of the cage 110. Furthermore, the semiconductor chip 520 protrudes relative to the first cage surface 110s1 of the cage 110. Additionally, the semiconductor chip 520 has a chip surface 520u relative to the chip surface 520b, and the package 130 has a package surface 130u, which is aligned with (e.g., flush with) the chip surface 520u. Furthermore, during the manufacturing of the semiconductor device 500, the package surface 130u and the chip surface 520u are formed, for example, through techniques such as polishing and chemical-mechanical planarization (CMP).

[0145] like Figure 5 As shown, the package 130 encapsulates the cage-like member 110 and the semiconductor chip 520. For example, the package 130 covers the first cage-like member surface 110s1, the second cage-like member side 110s4, and the side 520s of the semiconductor chip 520, but exposes the chip surface 520u of the semiconductor chip 520. In addition, the package 130 also fills a portion of the cavity 110c.

[0146] like Figure 5 As shown, the package 130 has a package side 130s, and the package side 130s and the first cage side 110s3 are aligned with each other (e.g., flush). Furthermore, during the manufacturing process of the semiconductor device 500, the package side 130s and the first cage side 110s3 are formed, for example, by division (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0147] like Figure 5 As shown, the first re-layout layer 140 is disposed above and / or below the package 130 and the semiconductor chip 520. The first re-layout layer 140 is electrically connected to the semiconductor chip 520. For example, the first re-layout layer 140 is electrically connected to the back-end process structure 123 of the semiconductor chip 520. The first re-layout layer 140 includes at least one conductive pad 141 for receiving a contact 150. Furthermore, the first re-layout layer 140 has re-layout side surfaces 140s, and the re-layout side surfaces 140s and the first cage-like side surfaces 110s3 are aligned with each other (e.g., flush). In addition, during the manufacturing process of the semiconductor device 500, the re-layout side surfaces 140s and the first cage-like side surfaces 110s3 are formed by, for example, division (e.g., sawing, such as diamond blade sawing or laser sawing).

[0148] Please refer to Figure 6 The diagram shows a cross-sectional view of a semiconductor device 600 according to another embodiment of the present invention.

[0149] like Figure 6 As shown, the semiconductor device 600 includes at least one cage-like member 610, at least one semiconductor chip 620, a package 630, at least one contact 150, and an underfill 670. The cage-like member 610 has a first cage-like member surface 610s1, a second cage-like member surface 610s2 opposite to the first cage-like member surface 610s1, and a cavity 610c extending from the first cage-like member surface 610s1 to the second cage-like member surface 610s2. In this embodiment, the cavity 610c is, for example, a blind via. The semiconductor chip 620 is disposed in the cavity 610c. The package 630 covers the semiconductor chip 620 and the cage-like member 610. The cage-like member 610 can restrain the displacement of the semiconductor chip 620. Furthermore, during the manufacturing process of the semiconductor device 600, the semiconductor chip 620 can be placed in the cavity 610c of the cage-like member 610 to be constrained in the cavity 610c, thereby improving the positioning accuracy of the semiconductor chip 620.

[0150] In this embodiment, the cage-like component 610 may include at least one circuit component. The cage-like component 610 is, for example, a semiconductor substrate such as a circuit board. Alternatively, the cage-like component 610 may be a laminate substrate, a silicon substrate, a high thermal conductivity substrate, a metal substrate, a combination thereof, or based on other types of materials.

[0151] like Figure 6As shown, the semiconductor chip 620 is a flip chip with a chip surface 620b (e.g., an active surface). The semiconductor chip 620 is bonded to a cage-like member 610 (e.g., a substrate) in a cavity 610c (e.g., a blind via), with the chip surface 620b facing the cavity 610c. The semiconductor chip 620 includes a substrate 121, a front-end process structure 122, a back-end process structure 123, and at least one contact 624. The substrate 121 is, for example, part of a silicon chip. The front-end process structure 122 is formed within and / or on the substrate 121, the back-end process structure 123 is formed within and / or on the front-end process structure 122 and electrically connected to the front-end process structure 122, and the contact 624 is formed on the back-end process structure 123 and electrically connected to the back-end process structure 123. Contact 624 is disposed on and electrically connected to chip surface 620b. Contact 624 may be, for example, solder ball, microbump, or micropillar. Semiconductor chip 620 is electrically connected to cage 610 through contact 624.

[0152] like Figure 6 As shown, the semiconductor chip 620 protrudes from the first cage-like surface 610s1 of the cage-like component 610. Furthermore, the semiconductor chip 620 has a chip surface 620u, and the package 630 has a package surface 630u, wherein the package surface 630u and the chip surface 620u are aligned with each other (e.g., flush). Moreover, during the manufacturing process of the semiconductor device 600, the package surface 630u and the chip surface 620u are formed, for example, through grinding, chemical mechanical planarization, etc.

[0153] like Figure 6 As shown, the package 630 encapsulates the cage-like component 610 and the semiconductor chip 620. For example, the package 630 covers the first cage-like surface 610s1 and the second cage-like side 610s4 of the cage-like component 610, the side 620s of the semiconductor chip 620, and the side of the contact 624, but exposes the second cage-like surface 610s2 and the first cage-like side 610s3 of the cage-like component 610. In addition, the package 630 also fills a portion of the cavity 610c.

[0154] like Figure 6 As shown, the package 630 has a package side 630s, and the package side 630s and the first cage side 610s3 are aligned with each other (e.g., flush). Furthermore, during the manufacturing process of the semiconductor device 600, the package side 630s and the first cage side 610s3 are formed, for example, by dicing (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0155] Furthermore, the package 630 may be formed of the same or similar material as the package 130. In another embodiment, the package 630 may be formed of materials including epoxy resin, polyimide, silicone, polyxylene, polyimide, benzocyclobutene, etc.

[0156] like Figure 6 As shown, contact 150 is disposed on the second cage surface 610s2 of cage 610. Semiconductor device 600 is, for example, a ball grid array, and contact 150 is, for example, a solder ball (or BGA ball), microbump, etc.

[0157] Please refer to Figure 7 The diagram shows a cross-sectional view of a semiconductor device 700 according to another embodiment of the present invention.

[0158] like Figure 7 As shown, the semiconductor component 700 includes at least one cage-like member 110, at least one semiconductor chip 720, a package 130, a first redistribution layer 140, at least one contact 150, at least one conductive portion 750, and a conductive layer 770. The cage-like member 110 has a first cage-like surface 110s1, a second cage-like surface 110s2 opposite to the first cage-like surface 110s1, and a cavity 110c extending from the first cage-like surface 110s1 to the second cage-like surface 110s2. The semiconductor chip 720 is disposed within the cavity 110c. The package 130 covers the semiconductor chip 720. The first redistribution layer 140 is disposed above the package 130 and the semiconductor chip 720. The cage-like member 110 can restrain the displacement of the semiconductor chip 720. Furthermore, during the manufacturing process of the semiconductor device 700, the semiconductor chip 720 can be placed in the cavity 110c of the cage-like member 110 to be confined within the cavity 110c, thereby improving the positioning accuracy of the semiconductor chip 720 and the first layer 140.

[0159] like Figure 7 As shown, a semiconductor chip 720 is disposed on a conductive layer 770, and a package 130 has a package surface 130u and a through-hole extending from the package surface 130u to the conductive layer 770. A conductive portion 750 is disposed within the through-hole. In one embodiment, the conductive portion 750 is, for example, a conductive via or a conductive pillar. The conductive portion 750 may be formed of a material comprising, for example, a metal (e.g., copper) or an alloy thereof. The conductive layer 770 may be formed of a material comprising, for example, a metal (e.g., copper) or an alloy thereof.

[0160] like Figure 7As shown, in this embodiment, the semiconductor chip 720 is, for example, a transistor. The semiconductor chip 720 includes a substrate 721, an electrode 722, solder 723, and a plurality of electrodes 724 and 725. The substrate 721 is, for example, a portion of a silicon wafer. Although not shown, the substrate 721 includes at least one transistor circuit. The electrode 722 is formed within and / or on a first surface 721b of the substrate 721, and the solder 723 is formed within and / or on the electrode 722 and electrically connected to the electrode 722. The semiconductor chip 720 is disposed on a conductive layer 770 through the solder 723. The transistor circuit of the substrate 721 is electrically connected to the conductive layer 770 through the electrodes 722 and the solder 723, and electrically connected to the first redistribution layer 140 through the electrodes 724 and 725. The electrodes 724 and 725 are formed on a second surface 721u of the substrate 721 and electrically connected to the first redistribution layer 140.

[0161] like Figure 7 As shown, the cage-like member 110 is a closed ring. In another embodiment, the cage-like member 110 may be an open ring. Viewed from above, the cage-like member 110 may be a polygon (rectangle, triangle, etc.), a circle, an ellipse, etc. The cage-like member 110 has a first cage-like member side 110s3 and a second cage-like member side 110s4 opposite to the first cage-like member side 110s3.

[0162] In this embodiment, the cavity 110c is a through hole. Furthermore, the cavity 110c extends from the second cage-like surface 110s2 to the first cage-like surface 110s1. In another embodiment, the cavity 110c is, for example, a blind hole.

[0163] like Figure 7 As shown, the package 130 encapsulates the cage 110 and the semiconductor chip 720. For example, the package 130 covers the first cage surface 110s1, the second cage side 110s4, and the side 720s of the semiconductor chip 720. In addition, the package 130 also fills a portion of the cavity 110c.

[0164] like Figure 7 As shown, the package 130 has a package side 130s, and the package side 130s and the first cage side 110s3 are aligned with each other (e.g., flush). Furthermore, during the manufacturing process of the semiconductor device 700, the package side 130s and the first cage side 110s3 are formed, for example, by splitting (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0165] like Figure 7As shown, the first layer 140 has a layer side 140s, wherein the layer side 140s and the first cage-like member side 110s3 are aligned with each other (e.g., flush). Furthermore, during the manufacturing process of the semiconductor device 700, the layer side 140s and the first cage-like member side 110s3 are formed, for example, by division (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0166] As described above, any of the semiconductor components 100 to 700 is, for example, a fan-out structure, such as a fan-out wafer-level packaging (FOWLP). FOWLP can be used in a wide variety of applications, including application processors, PMICs, RF, 5G antenna-in-packag (AiP), audio codecs, automotive radar, and high-performance computing and datacenter (HPC) for mobile devices (e.g., smartphones) and wearable devices (e.g., smartwatches). Compared to known flip-chip packages, FOWLP offers advantages such as thinner, smaller packages, higher I / O density, better RF performance, and lower thermal resistance. However, in another embodiment, the semiconductor device can also be designed as a fan-in structure.

[0167] Please refer to Figure 8 This shows a cross-sectional view of a semiconductor device 800 according to another embodiment of the present invention.

[0168] like Figure 8 As shown, the semiconductor device 800 includes a substrate 810, a redistribution layer 140, and at least one contact 150. The substrate 810 is, for example, a semiconductor substrate containing at least one semiconductor circuit. The redistribution layer 140 is disposed on the substrate 810 and includes at least one conductive pad 141. The contact 150 is disposed on the redistribution layer 140. The semiconductor device 800 is, for example, a ball grid array (BGA), and the contact 150 is, for example, a solder ball (or BGA ball), a microbump, etc.

[0169] Please refer to Figures 9A-9I , Figures 9A-9I Show Figure 1B A flowchart of a manufacturing method for an embodiment of a semiconductor device 100.

[0170] like Figure 9AAs shown, a carrier 10 is provided, on which a release layer 11 is disposed. In one embodiment, the release layer 11 is formed on the carrier 10, for example, by deposition. The carrier 10 can be based on glass, an IC substrate, metal, or a suitable material with sufficient thickness to minimize warpage.

[0171] like Figure 9B As shown, a cage-like plate 110' is disposed on the carrier 10 through the release layer 11. The cage-like plate 110' includes at least one cage-like member 110, each cage-like member 110 having a cavity 110c. When the cage-like plate 110' includes multiple cage-like members 110, the cage-like members 110 are connected to each other. The cage-like members 110 can be separated in subsequent processes using, for example, a splitting technique. The cage-like members 110 can be thin, laminated photoresist. In one embodiment, the cage-like plate 110' can be formed by a deposition method, wherein deposition includes printing, coating, etc. Furthermore, the thickness of the cage-like plate 110' can be, for example, between 200 micrometers and 300 micrometers.

[0172] like Figure 9C As shown, at least one semiconductor chip 120 is disposed on a carrier 10 via a release layer 11. Each semiconductor chip 120 is disposed in a corresponding cavity 110c of a cage-like plate 110'. Each semiconductor chip 120 includes a substrate 121, a front-end process structure 122, a back-end process structure 123, and at least one contact 124. The substrate 121 is, for example, a portion of a silicon wafer. The front-end process structure 122 is formed in and / or on the substrate 121, the back-end process structure 123 is formed in and / or on the front-end process structure 122 and electrically connected to the front-end process structure 122, and the contact 124 is formed on and electrically connected to the back-end process structure 123. The contact 124 is, for example, a solder ball, a microbump, a micropillar, etc. The substrate 121 has a chip surface 120b, wherein the chip surface 120b of the substrate 121 is disposed on the carrier 10 via the release layer 11. In addition, the thickness t3 of the semiconductor chip 120 is greater than the thickness t4 of the cage plate 110'.

[0173] like Figure 9D As shown, a package material 130' covering the semiconductor chip 120 and the cage plate 110' is formed using methods such as transfer molding and compression molding. The package material 130' covers the side of the semiconductor chip 120 and fills a portion of the cavity 110c.

[0174] like Figure 9E As shown, Figure 9DA portion of the package material 130' can be removed by methods such as grinding or chemical mechanical planarization. After removal, a contact surface 124u of the contact 124 of the semiconductor chip 120 and a package surface 130u of the package surface 130' are formed, wherein the contact surface 124u and the package surface 130u are aligned with each other (e.g., flush).

[0175] like Figure 9F As shown, the first layered structure 140' on the carrier 20 is transferred to Figure 9E The semiconductor chip 120 and the package material 130' are in the carrier 20. Before transfer, a first refolding structure 140' may be pre-formed on the carrier 20 using, for example, at least one semiconductor process. In one embodiment, the first refolding structure 140' may be formed on a release layer 21 disposed on the carrier 20.

[0176] like Figure 9G As shown, Figure 9F The carrier 20 and release layer 21 are removed from the first layer structure 140', where the conductive pad 141 of the first layer structure 140' is exposed.

[0177] like Figure 9H As shown, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0178] like Figure 9I As shown, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first re-layout structure 140', the cage plate 110', the package material 130', and the carrier 10 to form at least one semiconductor device 100. After segmentation, the cage plate 110' forms at least one cage member 110, the first re-layout structure 140' forms at least one first re-layout 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor device 100 includes the cage member 110, at least one semiconductor chip 120, the package 130, the first re-layout 140, and at least one contact 150.

[0179] Then, the semiconductor device 100 is... Figure 9I The release layer 11 and the carrier 10 are separated. After separation, the second cage surface 110s2 of the cage 110, the chip surface 120b of the semiconductor chip 120, and the package surface 130b of the package 130 of the semiconductor device 100 are all exposed.

[0180] In another embodiment, Figure 9GThe carrier 10 and release layer 11 can be replaced by an adhesive tape, and then at least one contact 150 is formed at the first overlay structure 140' (e.g., ...). Figure 9H On the conductive pad 141 (as shown), and then using methods such as sawing (e.g., diamond blade sawing or laser sawing) Figure 9I As shown, at least one segmented channel P1 is formed through a portion of the first layered structure 140', the cage plate 110', the encapsulation material 130', and the tape to form at least one semiconductor device 100. Furthermore, other embodiments of the semiconductor device manufacturing method include dicing techniques that are the same as or similar to the semiconductor device 10 manufacturing method, which will not be described further here.

[0181] Please refer to Figures 10A-10C , Figures 10A-10C Show Figure 1B A process diagram of a manufacturing method for another embodiment of the semiconductor device 100.

[0182] like Figure 10A As shown, in Figure 9E Following the initial steps, a first superstructure 140' is formed on the package material 130' and the semiconductor chip 120 using techniques such as plating, lithography, deposition, and etching. The conductive pads 141 of the first superstructure 140' are exposed and facing upwards. In this embodiment, the first superstructure 140' is formed through a process other than transfer. In other words, the first superstructure 140' is formed directly on the package material 130' and the semiconductor chip 120 without the need for a carrier 20.

[0183] like Figure 10B As shown, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0184] like Figure 10C As shown, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first re-layout structure 140', the cage plate 110', the package material 130', and the carrier 10 to form at least one semiconductor device 100. After segmentation, the cage plate 110' forms at least one cage member 110, the first re-layout structure 140' forms at least one first re-layout 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor device 100 includes the cage member 110, at least one semiconductor chip 120, the package 130, the first re-layout 140, and at least one contact 150.

[0185] Then, the semiconductor device 100 is... Figure 10C The release layer 11 and the carrier 10 are separated. After separation, the second cage surface 110s2 of the cage 110, the chip surface 120b of the semiconductor chip 120, and the package surface 130b of the package 130 of the semiconductor device 100 are all exposed.

[0186] Please refer to Figures 11A-11C , Figures 11A-11C Show Figure 2 A process diagram of a manufacturing method of an embodiment of a semiconductor device 200.

[0187] like Figure 11A As shown, in Figure 10A After the steps, methods such as grinding and chemical mechanical planarization can be used to remove [the impurities]. Figure 10A The cage-like plate 110', a portion of the semiconductor chip 120 (e.g., substrate 121), and a portion of the package material 130'. After removal, Figure 10A The substrate 121 is thinned to form a substrate 221, wherein the substrate 221 has a thickness t1, and Figure 10A The package material 130' is thinned to form package material 230', wherein package material 230' has a thickness t2. After removal, package material 230' forms package surface 230b, and the substrate 121 of semiconductor chip 220 forms chip surface 220b, wherein chip surface 220b of semiconductor chip 220 and package surface 230b of package 230 are aligned with each other (e.g., flush).

[0188] like Figure 11B As shown, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 may be, for example, contact balls (or BGA balls), microbumps, etc.

[0189] like Figure 11C As shown, Figure 11B The structure shown is disposed on the carrier 20 through the release layer 21. Then, at least one segmented channel P1 can be formed through a portion of the first repetition structure 140', the encapsulation material 230', and the carrier 20 using methods such as sawing (e.g., diamond blade sawing or laser sawing) to form at least one semiconductor device 200. After segmentation, the first repetition structure 140' forms at least one first repetition 140, and the encapsulation material 230' forms at least one encapsulation 230. After segmentation, each semiconductor device 200 includes at least one semiconductor chip 220, an encapsulation 230, the first repetition 140, and at least one contact 150. In one embodiment, the carrier 20 is, for example, an adhesive tape.

[0190] Then, the semiconductor device 200 is... Figure 11C The release layer 21 and the carrier 20 are separated. After separation, the chip surface 220b of the semiconductor chip 220 and the package surface 230b of the package 230 are exposed.

[0191] Please refer to Figures 12A-12I , Figures 12A-12I Show Figure 3 A process diagram of a manufacturing method of an embodiment of a semiconductor device 300.

[0192] like Figure 12A As shown, a carrier 10 is provided on which a release layer 11 is disposed. In one embodiment, the release layer 11 is formed on the carrier 10, for example, by deposition.

[0193] like Figure 12B As shown, at least one cage-like member 310 is disposed on the carrier 10 through the release layer 11, and each cage-like member 310 has a cavity 310c. The cage-like member 310 can be a metal, organic or inorganic stopper.

[0194] like Figure 12C As shown, at least one semiconductor chip 120 is disposed on the carrier 10 through a release layer 11. Each semiconductor chip 120 is disposed in a corresponding cavity 310c of the cage 310. The semiconductor chip 120 includes a substrate 121, a front-end process structure 122, a back-end process structure 123, and at least one contact 124. The substrate 121 is, for example, a portion of a silicon wafer. The front-end process structure 122 is formed in and / or on the substrate 121, the back-end process structure 123 is formed in and / or on the front-end process structure 122 and electrically connected to the front-end process structure 122, and the contact 124 is formed on and electrically connected to the back-end process structure 123. The contact 124 is, for example, a solder ball, a microbump, a micropillar, etc. The substrate 121 has a chip surface 120b, wherein the chip surface 120b of the substrate 121 is disposed on the carrier 10 via the release layer 11. In addition, the thickness t3 of the semiconductor chip 120 is greater than the thickness t4 of the cage-like component 310.

[0195] like Figure 12D As shown, a package material 130' covering the semiconductor chip 120 and the cage 310 is formed using methods such as transfer molding and compression molding. The package material 130' fills a portion of the cavity 310c.

[0196] like Figure 12EAs shown, techniques such as polishing and chemical mechanical planarization can be used to remove a portion of the package material 130'. After removal, the contact surface 124u of the contact 124 of the semiconductor chip 120 and the package surface 130u of the package surface 130' are formed, wherein the contact surface 124u and the package surface 130u are aligned with each other (e.g., flush).

[0197] like Figure 12F As shown, the first layered structure 140' on the carrier plate 20 is transferred to... Figure 12E The semiconductor chip 120 and the package material 130' are on the carrier 20. Before transfer, a first refolding structure 140' may be pre-formed on the carrier 20 using, for example, at least one semiconductor process. In one embodiment, the first refolding structure 140' may be formed on a release layer 21 disposed on the carrier 20.

[0198] like Figure 12G As shown, Figure 12F The carrier 20 and release layer 21 are removed from the first layer structure 140', where the conductive pad 141 of the first layer structure 140' is exposed.

[0199] like Figure 12H As shown, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0200] like Figure 12I As shown, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first re-layer structure 140', the package material 130', and the carrier 10 to form at least one semiconductor device 300. After segmentation, the first re-layer structure 140' forms at least one first re-layer 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor component 300 includes a cage-like member 310, at least one semiconductor chip 120, a package 130, a first re-layer 140, and at least one contact 150.

[0201] Then, the semiconductor device 300 is... Figure 12I The release layer 11 and the carrier 10 are separated. After separation, the chip surface 120b of the semiconductor chip 120, the second cage surface 310s2 of the cage 310, and the package surface 130b of the package 130 are exposed.

[0202] Please refer to Figures 13A-13C , Figures 13A-13C Show Figure 3 A process diagram of a manufacturing method for another embodiment of the semiconductor device 300.

[0203] like Figure 13A As shown, in Figure 12E Following the steps, techniques such as deposition, photolithography, etching, and electroplating can be used to form a first superstructure 140' on the package material 130' and the semiconductor chip 120, with the conductive pads 141 of the first superstructure 140 exposed and facing upwards. In this embodiment, the first superstructure 140' is formed through a process other than transfer. In other words, the first superstructure 140' is formed directly on the package material 130' and the semiconductor chip 120, without the need for the carrier 20.

[0204] like Figure 13B As shown, contacts 150 are formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 may be, for example, solder balls (or BGA balls), microbumps, etc.

[0205] like Figure 13C As shown, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first re-layer structure 140', the package material 130', and the carrier 10 to form at least one semiconductor device 300. After segmentation, the first re-layer structure 140' forms at least one first re-layer 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor component 300 includes a cage-like member 310, at least one semiconductor chip 120, a package 130, a first re-layer 140, and at least one contact 150.

[0206] Then, the semiconductor device 300 is... Figure 13C The release layer 11 and the carrier 10 are separated. After separation, the chip surface 120b of the semiconductor chip 120, the second cage surface 310s2 of the cage 310, and the package surface 130b of the package 130 are exposed.

[0207] In another embodiment, Figure 13A After the steps, the semiconductor device 300 can adopt the same... Figures 11A-11C Formed by the same or similar manufacturing steps.

[0208] Please refer to Figures 14A-14I , Figures 14A-14I A process diagram illustrating a method for manufacturing a semiconductor device 100' according to an embodiment of the present invention is shown.

[0209] like Figure 14A As shown, at least one semiconductor chip 120 is bonded to a carrier 10' through a bonding layer 11', wherein the bonding layer 11' is formed, for example, by anodizing.

[0210] like Figure 14BAs shown, techniques such as transfer molding and compression molding can be used to form a package material 130' covering the semiconductor chip 120 on the carrier 10'.

[0211] like Figure 14C As shown, techniques such as grinding and chemical mechanical planarization can be used to remove [the material]. Figure 14B A portion of the package material 130'. After removal, the contact surface 124u of the contact 124 of the semiconductor chip 120 and the package surface 130u of the package surface 130' are aligned with each other (e.g., flush).

[0212] like Figure 14D As shown, the first layered structure 140' on the carrier 20 is transferred to Figure 14C The semiconductor chip 120 and the package material 130' are on the carrier 20. Before transfer, a first refolding structure 140' may be pre-formed on the carrier 20 using, for example, at least one semiconductor process. In one embodiment, the first refolding structure 140' may be formed on a release layer 21 disposed on the carrier 20.

[0213] like Figure 14E As shown, Figure 14D The carrier 20 and release layer 21 are removed from the first layer structure 140', wherein the conductive pad 141 of the first layer structure 140' is exposed.

[0214] like Figure 14F As shown, removal can be achieved using, for example, wet etching, back grinding, chemical-mechanical polishing, dry etching (e.g., reactive ion etching), or a combination thereof. Figure 14E The carrier 10 and the bonding layer 11' are removed. After removal, the chip surface 120b of the semiconductor chip 120 and the package surface 130b of the package material 130' are formed, wherein the chip surface 120b and the package surface 130b can be aligned with each other (e.g., flush).

[0215] like Figure 14G As shown, Figure 14F The structure is configured on the carrier 10', wherein the carrier 10' is, for example, an adhesive tape.

[0216] like Figure 14H As shown, contacts 150 are formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 may be, for example, solder balls (or BGA balls), microbumps, etc.

[0217] like Figure 14IAs shown, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first refolding structure 140', the package material 130', and the carrier 10' to form at least one semiconductor device 100'. After segmentation, the first refolding structure 140' forms at least one first refold 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor device 100' includes a semiconductor chip 120, a package 130, a first refold 140, and at least one contact 150.

[0218] Then, the semiconductor device 100' is... Figure 14I Separation was performed on carrier 10'. After separation, Figure 14I The chip surface 120b of the semiconductor chip 120 and the package surface 130b of the package 130 are exposed.

[0219] Please refer to Figures 15A-15I , Figures 15A-15I Show Figure 2 A process diagram of the manufacturing method of the semiconductor device 200.

[0220] like Figure 15A As shown, a carrier 40 is provided on which a release layer 41 is disposed. In one embodiment, the release layer 41 is formed on the carrier 40, for example, by deposition. The carrier 40 has a cavity 40r, wherein the release layer 41 is also formed on at least one of all sidewalls of the cavity 40r.

[0221] like Figure 15B As shown, at least one semiconductor chip 120 is disposed on the carrier 40 via a release layer 41, wherein the semiconductor chip 120 is disposed within a cavity 40r of the carrier 40. The cavity 40r of the carrier 40 can restrain the displacement of the semiconductor chip 120. Furthermore, the semiconductor chip 120 can be disposed within the cavity 40r of the carrier 40 to be restrained within the cavity 40r.

[0222] like Figure 15C As shown, techniques such as transfer molding and compression molding can be used to form a package material 130' covering the semiconductor chip 120 and the carrier 40. The package material 130' fills a portion of the cavity 40r, thereby improving the adhesion between the semiconductor chip 120 and the first layered structure 140' (the first layered structure 140' is in...). Figure 15E The positioning accuracy is formed during the manufacturing process.

[0223] like Figure 15DAs shown, techniques such as polishing and chemical mechanical planarization can be used to remove a portion of the package material 130'. After removal, the contact surface 124u of the contact 124 of the semiconductor chip 120 and the package surface 130u of the package surface 130' are aligned with each other (e.g., flush).

[0224] like Figure 15E As shown, a first overlay structure 140' can be formed over the package material 130' and the semiconductor chip 120 using, for example, at least one semiconductor process. The first overlay structure 140' includes at least one conductive pad 141, which is exposed and facing upwards.

[0225] like Figure 15F As shown, techniques such as grinding and chemical mechanical planarization can be used to remove [the material]. Figure 15E A portion of the substrate 121 and the entire carrier 40. After removal, Figure 15E The substrate 121 is thinned to form a substrate 221, wherein the substrate 221 has a thickness t1, and Figure 15E The encapsulation material 130' is thinned to form encapsulation material 230', wherein the encapsulation material 230' has a thickness t2.

[0226] like Figure 15G As shown, Figure 15F The structure is disposed on the carrier 20 through the release layer 21.

[0227] like Figure 15H As shown, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0228] like Figure 15I As shown, techniques such as sawing (e.g., diamond sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first refolding structure 140', the package material 230', and the carrier 20 to form at least one semiconductor device 200. After segmentation, the first refolding structure 140' forms at least one first refold 140, and the package material 230' forms at least one package 230. After segmentation, each semiconductor device 200 includes at least one semiconductor chip 220, a package 230, a first refold 140, and at least one contact 150.

[0229] Then, the semiconductor device 200 is... Figure 15I The release layer 21 and the carrier 20 are separated. After separation, the chip surface 220b of the semiconductor chip 220 and the package surface 230b of the package 230 are exposed.

[0230] Please refer to Figures 16A-16G , Figures 16A-16G Show Figure 4 A process diagram illustrating a manufacturing method of an embodiment of a semiconductor device 400.

[0231] like Figure 16A As shown, a carrier 10 is provided on which a release layer 11 is disposed. In one embodiment, the release layer 11 is formed on the carrier 10, for example, by deposition.

[0232] like Figure 16B As shown, a semiconductor component 400A is disposed on a carrier 10 through a release layer 11. The semiconductor component 400A includes a cage-like plate 410', a second re-layer structure 440', at least one conductive portion 450, and a third re-layer structure 460'. The cage-like plate 410' has a first cage-like surface 410s1, a second cage-like surface 410s2 opposite to the first cage-like surface 410s1, and at least one cavity 410c extending from the first cage-like surface 410s1 to the second cage-like surface 410s2. In this embodiment, the cavity 410c is, for example, a blind via. The cage-like component 410' can be a laminated substrate, a silicon substrate, a high thermal conductivity substrate, a metal substrate, a combination thereof, or based on other types of materials. The conductive portion 450 electrically connects the second re-layer structure 440' and the third re-layer structure 460'. In addition, the conductive part 450 extends from the surface 410s2 of the second cage-like member to the surface 410s1 of the first cage-like member to electrically connect the second layered structure 440' and the third layered structure 460'.

[0233] like Figure 16C As shown, at least one semiconductor chip 120 is disposed in a corresponding cavity 410c. The cage plate 410' can restrain the displacement of the semiconductor chip 120, and since the semiconductor chip 120 can be placed in the cavity 410c of the cage plate 410' and thus restrained within the cavity 410c, the relationship between the semiconductor chip 120 and the first layered structure 140' (the first layered structure 140' in...) can be improved. Figure 16E The positioning accuracy is formed by the steps.

[0234] like Figure 16D As shown, a package 430 filling the cavity 410c is formed using techniques such as glue dispense, transfer molding, or compression molding. In another embodiment, if necessary, techniques such as polishing or chemical mechanical planarization can be used to remove a portion of the package 430 to expose the contacts 124 of the semiconductor chip 120.

[0235] like Figure 16EAs shown, a first layer structure 140' is formed above the third layer structure 460' and the contact 124 of the semiconductor chip 120 using techniques such as electroplating, photolithography, deposition, and etching. The first layer structure 140' includes at least one conductive pad 141 exposed therefrom. In another embodiment, the first layer structure 140' may employ, for example... Figure 9F The transfer method shown is used to form it.

[0236] like Figure 16F As shown, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0237] like Figure 16G As shown, the process can involve sawing (e.g., diamond blade sawing or laser sawing) to form at least one segmented channel P1 passing through a portion of the first re-layer structure 140', the third re-layer structure 460', the cage plate 410', the second re-layer structure 440', and the carrier 10 to form at least one semiconductor device 400. After segmentation, the cage plate 410' forms at least one cage member 410, the first re-layer structure 140' forms at least one first re-layer 140, the third re-layer structure 460' forms at least one third re-layer 460, and the second re-layer structure 440' forms at least one second re-layer 440. After segmentation, each semiconductor device 400 includes a cage member 410, at least one semiconductor chip 120, a package 430, a first re-layer 140, at least one contact 150, a second re-layer 440, at least one conductive portion 450, and a third re-layer 460.

[0238] Then, the semiconductor device 400 is... Figure 16G The release layer 11 and the carrier 10 are separated. After separation, the second re-fabric layer 440 is exposed.

[0239] Please refer to Figures 17A-17J , Figures 17A-17J Show Figure 5 A process diagram illustrating a manufacturing method of an embodiment of a semiconductor device 500.

[0240] like Figure 17A As shown, a carrier 10 is provided on which a release layer 11 is disposed. In one embodiment, the release layer 11 is formed on the carrier 10, for example, by deposition.

[0241] like Figure 17BAs shown, the cage-like plate 110' is disposed on the carrier 10 via the release layer 11. The cage-like plate 110' includes at least one cage-like member 110, each cage-like member 110 having a cavity 110c. When the cage-like plate 110' includes multiple cage-like members 110, the cage-like members 110 are connected to each other. The cage-like members 110 can be divided in subsequent processes using, for example, a segmentation technique.

[0242] like Figure 17C As shown, at least one semiconductor chip 520 is disposed on the carrier 10 through the release layer 11. Each semiconductor chip 520 is disposed in the cavity 110c of the corresponding cage plate 410'. The semiconductor chip 520 includes a substrate 121, a front-end processing structure 122, and a back-end processing structure 123. Compared to semiconductor chip 120, the semiconductor chip 520 can omit the contact 124. The semiconductor chip 520 is disposed on the carrier 10 through the back-end processing structure 123.

[0243] like Figure 17D As shown, a package material 130' covering the semiconductor chip 520 and the cage plate 110' is formed using techniques such as transfer molding and compression molding. The package material 130' covers the side of the semiconductor chip 520 and fills a portion of the cavity 110c.

[0244] like Figure 17E As shown, techniques such as polishing and chemical mechanical planarization can be used to remove a portion of the package material 130' to expose the chip surface 520u of the semiconductor chip 520. After splitting, the package material 130' forms the package surface 130u, and the package surface 130u is aligned with the chip surface 520u (e.g., flush).

[0245] like Figure 17F As shown, the carrier 10 with release layer 11 is removed from the carrier 10, exposing the chip surface 520b of the back-end process structure 123 of semiconductor chip 520 and the second cage plate surface 110s2 of cage plate 110'.

[0246] like Figure 17G As shown, techniques such as electroplating, photolithography, deposition, and etching can be used to form a first overlay structure 140' above the cage-like plate 110' and the back-end process structure 123 of the semiconductor chip 520. The first overlay structure 140' includes at least one conductive pad 141.

[0247] like Figure 17H As shown, Figure 17G The structure shown is flipped so that the first layer structure 140' faces upward, and then disposed on the carrier 20 via the release layer 21, wherein the encapsulation surface 130u and the chip surface 520u are disposed on the carrier 20, and the conductive pad 141 faces upward.

[0248] like Figure 17I As shown, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0249] like Figure 17J As shown, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first re-layout structure 140', the cage plate 110', the package material 130', and the carrier 20 to form at least one semiconductor device 500. After segmentation, the cage plate 110' forms at least one cage member 110, the first re-layout structure 140' forms at least one first re-layout 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor device 500 includes the cage member 110, at least one semiconductor chip 520, the package 130, the first re-layout 140, and at least one contact 150.

[0250] Then, the semiconductor device 500 is... Figure 17J The release layer 21 and the carrier 20 are separated. After separation, the chip surface 520u of the semiconductor chip 520 and the package surface 130u of the package 130 are exposed.

[0251] Please refer to Figures 18A-18I , Figures 18A-18I Show Figure 6 A process diagram illustrating a manufacturing method of an embodiment of a semiconductor device 600.

[0252] like Figure 18A As shown, a carrier 10 is provided on which a release layer 11 is disposed. In one embodiment, the release layer 11 is formed on the carrier 10, for example, by deposition.

[0253] like Figure 18B As shown, a cage-like plate 610' is disposed on a carrier 10 via a release layer 11. The cage-like plate 610' has a first cage-like surface 610s1, a second cage-like surface 610s2 opposite to the first cage-like surface 610s1, and at least one cavity 610c extending from the first cage-like surface 610s1 toward the second cage-like surface 610s2. In this embodiment, the cavity 610c is, for example, a blind via. In this embodiment, the cage-like plate 610' may include at least one circuit component. The cage-like plate 610' may be a laminated substrate, a silicon substrate, a high thermal conductivity substrate, a metal substrate, a combination thereof, or based on other types of materials.

[0254] like Figure 18CAs shown, at least one semiconductor chip 620 is disposed on the bottom surface of cavity 610c. Semiconductor chip 620 is a flip-chip having a chip surface 620b (e.g., an active surface). Semiconductor chip 620 includes a substrate 121, a front-end process structure 122, a back-end process structure 123, and at least one contact 624. Substrate 121 is, for example, part of a silicon wafer. Front-end process structure 122 is formed within and / or on substrate 121, back-end process structure 123 is formed within and / or on front-end process structure 122 and electrically connected to front-end process structure 122, and contact 624 is formed on and connected to back-end process structure 123. Contact 624 is disposed on and electrically connected to chip surface 620b, and contact 624 is, for example, a solder ball, microbump, micropillar, etc. Semiconductor chip 620 is electrically connected to cage 610 through contact 624.

[0255] like Figure 18C As shown, the bottom filler 670 of the contacts 624 covering the semiconductor chip 620 is formed by means of, for example, dispensing.

[0256] like Figure 18D As shown, the encapsulation material 630' covering the semiconductor chip 620, the cage plate 610', and the bottom filler 670 are formed by methods such as transfer molding and compression molding.

[0257] like Figure 18E As shown, a portion of the package material 630' can be removed using methods such as grinding or chemical mechanical planarization to expose the chip surface 620u of the semiconductor chip 620. After slitting, the package material 630' forms the package surface 630u, wherein the package surface 630u is aligned with (e.g., flush with) the chip surface 620u.

[0258] like Figure 18F As shown, the carrier 10 with release layer 11 is removed to expose the second cage surface 610s2 of cage plate 610'.

[0259] like Figure 18G As shown, Figure 18F The structure shown is flipped so that the second cage-like surface 610s2 of the cage plate 610' faces upward, and then this structure is disposed on the carrier 20 through the release layer 21, wherein the encapsulation surface 630u and the chip surface 620u are both disposed on the carrier 20.

[0260] like Figure 18H As shown, at least one contact 150 is formed on the second cage-like surface 610s2 of the cage-like plate 610'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0261] like Figure 18IAs shown, at least one segmentation channel P1 can be formed through a portion of the cage plate 610', the package material 630', and the carrier 20 using techniques such as sawing (e.g., diamond blade sawing or laser dicing) to form at least one semiconductor device 600. After dicing, the cage plate 610' forms at least one cage member 610, and the package material 630' forms at least one package 630. After dicing, each semiconductor device 600 includes the cage member 610, at least one semiconductor chip 620, the package 630, and the underfill adhesive 670.

[0262] Then, as shown in the figure, the semiconductor device 600 is... Figure 18I The release layer 21 and the carrier 20 are separated. After separation, the chip surface 620u of the semiconductor chip 620 and the package surface 630u of the package 630 are exposed.

[0263] Please refer to Figures 19A-19J , Figures 19A-19J Show Figure 7 A process diagram of a manufacturing method for an embodiment of a semiconductor device 700.

[0264] like Figure 19A As shown, a carrier 10 is provided on which a release layer 11 is disposed. In one embodiment, the release layer 11 is formed on the carrier 10, for example, by deposition.

[0265] like Figure 19B As shown, the cage-like plate 110' is disposed on the carrier 10 via a release layer 11. The cage-like plate 110' includes at least one cage-like member 110, each cage-like member 110 having a cavity 110c. When the cage-like plate 110' includes multiple cage-like members 110, the cages 110 are connected to each other. The cage-like members 110 can be separated in subsequent processes using, for example, splitting techniques. Furthermore, the cage-like member 110' is, for example, a thin, laminated photoresist layer.

[0266] like Figure 19CAs shown, at least one conductive layer 770 can be disposed on the release layer 11 of the carrier 10 in the cavity 110c using methods such as electroplating or deposition. Next, at least one semiconductor chip 720 is disposed on the conductive layer 770. The semiconductor chip 720 includes a substrate 721, an electrode 722, solder 723, and multiple electrodes 724 and 725. The substrate 721 is, for example, a portion of a silicon wafer. Although not shown, the substrate 121 includes at least one transistor circuit. The electrode 722 is formed in and / or on a first surface 721b of the substrate 721, and the solder 723 is formed in and / or on the electrode 722 and electrically connected to the electrode 722. The semiconductor chip 720 is disposed on the conductive layer 770 through the solder 723. The transistor circuit within the substrate 721 is electrically connected to the conductive layer 770 through the electrode 722 and the solder 723. Electrodes 724 and 725 are formed on a second surface 721u of the substrate 721. Electrodes 724 and 725 are, for example, solder bumps, solder balls, etc. Semiconductor chip 720 is disposed on a portion of the surface 770u of conductive layer 770, and another portion of the surface 770u of conductive layer 770 is exposed (not covered by semiconductor chip 720).

[0267] like Figure 19D As shown, methods such as transfer molding and compression molding can be used to form a package material 130' covering the semiconductor chip 720, the cage plate 110', and the conductive layer 770. The package material 130' covers the side of the semiconductor chip 720 and fills a portion of the cavity 110c.

[0268] like Figure 19E As shown, a portion of the package material 130' can be removed using methods such as grinding or chemical mechanical planarization to expose the electrodes 724 and 725 of the semiconductor chip 720. Then, electrode 724 forms electrode surface 724u, electrode 725 forms electrode surface 725u, and package material 130' forms package surface 130u, wherein electrode surface 724u, electrode surface 725u, and package surface 130u are aligned with each other (e.g., flush).

[0269] like Figure 19F As shown, at least one hole 750a extending from the package surface 130u of the package 130 to the conductive layer 770 can be formed using methods such as laser drilling, photolithography, and etching.

[0270] like Figure 19GAs shown, at least one conductive portion 750 filling the corresponding hole 750a can be formed using methods such as electroplating or deposition, wherein the conductive portion 750 is electrically connected to the conductive layer 770. In one embodiment, if necessary, methods such as polishing or chemical mechanical planarization can be used to remove part of the package material 130' and part of the conductive portion 750 to expose the electrodes 724 and 725 of the semiconductor chip 720. In one embodiment, the electrode surface 724u, the electrode surface 725u, the package surface 130u, and the conductive surface 750u of the conductive portion 750 are aligned with each other (e.g., flush).

[0271] like Figure 19H As shown, the first layered structure 140' on the carrier 20 is transferred to Figure 19G The semiconductor chip 720, conductive portion 750, and package material 130' are attached to the substrate 20. Prior to transfer, a first superposition structure 140' can be pre-formed on the substrate 20 using at least one semiconductor process (e.g., deposition, photolithography, electroplating, etching, etc.). In one embodiment, the first superposition structure 140' can be formed on a release layer 21 disposed on the substrate 20. The first superposition structure 140' is electrically connected to the electrodes 724, 725 and conductive portion 750 of the semiconductor chip 720.

[0272] like Figure 19I As shown, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0273] like Figure 19J As shown, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first re-layer structure 140', the cage plate 110', the package material 130', and the carrier 10 to form at least one semiconductor device 700. After segmentation, the cage plate 110' forms at least one cage member 110, the first re-layer structure 140' forms at least one first re-layer 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor component 700 includes the cage member 110, at least one semiconductor chip 720, the package 130, the first re-layer 140, at least one contact 150, at least one conductive portion 750, and at least one conductive layer 770.

[0274] Then, the semiconductor component 700 is... Figure 19J The release layer 11 and the carrier 10 are separated. After separation, the second cage surface 110s2 of the cage 110, the conductive surface 770b of the conductive layer 770, and the encapsulation surface 130b of the encapsulation body 130 are exposed.

[0275] Please refer to Figures 20A-20C , Figures 20A-20C Show Figure 7 A process diagram of a manufacturing method for another embodiment of the semiconductor device 700.

[0276] like Figure 20A As shown, at Figure 19G Following these steps, techniques such as electroplating, photolithography, deposition, and etching can be used to form a first superstructure 140' on the package material 130', the semiconductor chip 720, and the conductive portion 750. The conductive pad 141 of the first superstructure 140' is exposed and facing upwards. The first superstructure 140' is electrically connected to the conductive portion 750 of the semiconductor chip 720 and the electrodes 724 and 725. In this embodiment, the first superstructure 140' is formed through a process other than transfer. In other words, the first superstructure 140' is formed directly on the package material 130', the semiconductor chip 720, and the conductive portion 750, without the need for a carrier 20.

[0277] like Figure 20B As shown, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0278] like Figure 20C As shown, techniques such as sawing (e.g., diamond saw or laser saw) can be used to form at least one segmented channel P1 passing through a portion of the first re-layer structure 140', the cage plate 110', the encapsulation material 130', and the carrier 10 to form at least one semiconductor device 700. After segmentation, the cage plate 110' forms at least one cage member 110, the first re-layer structure 140' forms at least one first re-layer 140, and the encapsulation material 130' forms at least one encapsulation 130. After segmentation, each semiconductor component 700 includes the cage member 110, at least one semiconductor chip 720, the encapsulation 130, the first re-layer 140, at least one contact 150, at least one conductive portion 750, and at least one conductive layer 770.

[0279] Then, the semiconductor component 700 is... Figure 20C The release layer 11 and the carrier 10 are separated. After separation, the second cage surface 110s2 of the cage 110, the conductive surface 770b of the conductive layer 770 and the encapsulation surface 130b of the encapsulation body 130 are exposed.

[0280] Please refer to Figures 21A-21G , Figures 21A-21G Show Figure 8 A process diagram illustrating a manufacturing method of an embodiment of a semiconductor device 800.

[0281] like Figure 21A As shown, a carrier 50 is provided. The carrier 50 is, for example, glass.

[0282] like Figure 21B As shown, a spacer 55 is provided, wherein the spacer 55 has at least one hole 55a. In this embodiment, the hole 55a is, for example, a through hole. The spacer 55 may be formed of a material including polyimide, metal, etc.

[0283] like Figure 21C1 and 21C2 As shown, Figure 21C2 Show Figure 21C1 A cross-sectional view of the structure along direction 21C2-21C2'. The spacer 55 is disposed on the carrier 50 through the release layer 51, characterized in that the release layer 51 is formed on the carrier 50, for example, by deposition.

[0284] like Figure 21D1 and 21D2 As shown, Figure 21D2 Show Figure 21D1 The structure is shown in a cross-sectional view along direction 21D2-21D2'. At least one substrate 810 is disposed in a hole 55a, wherein each substrate 810 is disposed within a corresponding hole 55a. Then, using techniques such as coating, dispensing, molding, etc., a filler 57 is formed to fill the space between the substrate 810 and the sidewalls of the hole 55a. Then, using techniques such as electroplating, photolithography, deposition, etching, etc., a first overlapping layer structure 140' is formed above the substrate 810 and the filler 57. The first overlapping layer structure 140' includes at least one conductive pad 141, and the conductive pad 141 is located above the substrate 810. In other words, the conductive pad 141 overlaps with the substrate 810 on the Z-axis. The filler 57 can fix the relative position between the spacer 55 and the substrate 810. The filler 57 here can be a polymer encapsulant, oxide, silicon substrate, etc., commonly used in integrated circuit (IC) packages or liquid crystal display (LCD) driver IC packages. In one embodiment, the substrate 810 is, for example, an uncutter semiconductor wafer. The substrate 810 may include at least one integrated circuit. Furthermore, the thickness of the substrate 810 is equal to the thickness of the spacer 55 (e.g., on the Z-axis).

[0285] like Figure 21E As shown, at least one dividing channel P1 is formed along the edge of the substrate 810 through the first re-layer structure 140' using a method such as laser dividing. After dividing, the first re-layer structure 140' forms at least one first re-layer 140.

[0286] Then, to Figure 21E The filler 57 and release layer 51 (in the case of using a UV-release layer) are photodissociated (e.g., irradiated with UV). Preferably, the spacer 55 can be reused.

[0287] like Figure 21F As shown, after photodissociation, the structure including the first re-layer 140 and the substrate 810 is separated from the filler 57 and the release layer 51.

[0288] like Figure 21G As shown, at least one contact 150 is formed on the conductive pad 141 of the first layer 140 to form a semiconductor device 800. Multiple contacts 150 are arranged in a grid array. The contacts 150 are, for example, solder bumps, solder balls (or BGA balls). Then, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to... Figure 21G The semiconductor device 800 is simplified to form multiple semiconductor dies.

[0289] In another embodiment, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to... Figure 21F The structure is simplified to form multiple semiconductor dies, and then at least one contact 150 is formed on the conductive pad 141 of the first redistribution layer 140 of the semiconductor die.

[0290] Please refer to Figure 22A and 22B , Figure 22A A schematic diagram of panel-level packaging according to one embodiment is shown, while Figure 22B Show Figure 22A A cross-sectional view of the panel-level package along direction 22B-22B'.

[0291] Fan-out panel-level packaging (FOPLP) can significantly reduce assembly costs by 30% to 40% compared to FOWLP, provided that the related processes of chip placement, molding, and redistribution can be scaled up at the same production volume. Currently, FOPLP is used in low-end / mid-range, high-volume applications, such as power management ICs, which employ relatively relaxed size requirements, such as linewidth / spacing (L / S) equal to or greater than 10μm / 10μm and even more relaxed redistribution.

[0292] As shown in Figures 22A and 22B, in a panel-level package (e.g., a fan-out panel-level package or a fan-in panel-level package), multiple semiconductor devices 900 are disposed on a carrier 10 through a release layer 11. Each semiconductor device 900 is, for example, a semiconductor die, such as an active chip or a passive component. In another embodiment, this semiconductor die can be pre-bumped using a mature, high-volume, fine L / S wafer-level process (relative to the relatively new via-aperture / metal-fill process in large-panel fan-out panel-level packages) prior to FOPLP, wherein the bumps include solder bumps, copper pillar microbumps, gold bumps, or other bumps suitable for fine pitch. The package body material 130' includes multiple package islands 130A, wherein a dividing channel DS is formed at adjacent package islands 130A. Therefore, it can minimize thermal expansion coefficient mismatch, mold flow, and other effects. Lower thermal expansion coefficients, lower modulus molding compounds or package materials, and adaptive patterning can be used to minimize warpage effects.

[0293] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the claims.

Claims

1. A semiconductor device, comprising: A cage-like component has a first cage-like component surface, a second cage-like component surface opposite to the first cage-like component surface, and a cavity extending from the first cage-like component surface to the second cage-like component surface. A semiconductor chip is disposed in the cavity; A package that covers the semiconductor chip; as well as A first layer is formed on top of the package and the semiconductor chip.

2. The semiconductor device as claimed in claim 1, characterized in that, The cavity extends to the surface of the first cage-like member.

3. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor chip has a back surface, and the back surface of the semiconductor chip is flush with the surface of the second cage-like member of the cage-like member.

4. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor chip protrudes relative to the surface of the first cage-like member of the cage-like member.

5. The semiconductor device as claimed in claim 1, characterized in that, The package has a package side, the cage has a cage side, and the package side and the cage side are flush with each other.

6. The semiconductor component as claimed in claim 1, characterized in that, The cage-like component has a cage-like surface, and the package covers the cage-like surface and the first cage-like surface, but exposes the second cage-like surface.

7. The semiconductor device as claimed in claim 1, characterized in that, The cavity is a blind hole located on the cage-like component, which is a substrate. The semiconductor chip is a flip-chip with an active surface, which is bonded to the substrate in the blind hole, with the active surface facing the blind hole.

8. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor chip is a flip-chip with an active surface. The first redistribution layer is disposed on the surface of the second cage and the active surface, and the package covers the surface of the first cage of the cage.

9. The semiconductor device as claimed in claim 1, characterized in that, Including: A conductive layer is located inside the cavity; The semiconductor chip is disposed on the conductive layer, the package has a package surface and a through hole extending from the package surface to the conductive layer, and the semiconductor device further includes a conductive portion located within the through hole.

10. The semiconductor device as claimed in claim 1, characterized in that, Including: A conductive portion extends from the surface of the second cage-like member to the surface of the first cage-like member.

11. The semiconductor device as claimed in claim 10, characterized in that, Including: A second layer of fabric is disposed on the surface of the second cage-like member; as well as A third layer of fabric is disposed on the surface of the first cage-like member and located between the first layer of fabric and the surface of the first cage-like member; The conductive part is electrically connected to the second layer and the third layer.

12. The semiconductor device as claimed in claim 10, characterized in that, The package is disposed within the cavity and between one side of the semiconductor chip and the side of the cavity.

13. A manufacturing method, further comprising: A cage-like component is disposed on a carrier, wherein the cage-like component has a first cage-like component surface, a second cage-like component surface opposite to the first cage-like component surface, and a cavity extending from the first cage-like component surface to the second cage-like component surface. A semiconductor chip is placed in the cavity; Configure a package to cover the semiconductor chip; A first layer is configured to cover the package and the semiconductor chip; as well as Remove the carrier to expose the first layer of fabric.

14. The manufacturing method as described in claim 13, characterized in that, The steps of configuring the first overlay layer to cover the package and the semiconductor chip include: The first layer of fabric is configured on the carrier; The first re-layer is transferred via the carrier to the package and the semiconductor chip; and Remove the carrier.

15. The manufacturing method as described in claim 13, characterized in that, Including: Remove the cage-like component and a portion of the semiconductor chip.

16. The manufacturing method as described in claim 13, characterized in that, In the step of configuring the package to cover the semiconductor chip, the package further covers one side of the cage-like member.

17. The manufacturing method as described in claim 13, characterized in that, The cage-like member containing a blind via is disposed on the carrier; the semiconductor chip is a flip chip, which is flip-chip bonded to the blind via, and an active surface of the semiconductor chip faces the blind via.

18. The manufacturing method as described in claim 13, characterized in that, Including: A conductive layer is disposed inside the cavity; The semiconductor chip is disposed on the conductive layer within the cavity; The package is configured to cover the semiconductor chip; A through-hole is formed, the through-hole extending from a package surface of the package to the conductive layer; and A conductive portion is formed within the through hole.

19. The manufacturing method as described in claim 13, characterized in that, The steps of configuring the cage-like component on the carrier include: A conductive portion is formed, wherein the conductive portion extends from the surface of the second cage to the surface of the first cage.

20. The manufacturing method as described in claim 19, characterized in that, The steps of configuring the cage-like component on the carrier include: A second layer of fabric is disposed on the surface of the second cage-like member; and A third layer of fabric is disposed on the surface of the first cage-like member, wherein the third layer of fabric is located between the first layer of fabric and the surface of the first cage-like member, and the conductive portion is electrically connected to the second layer of fabric and the third layer of fabric.

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