Semiconductor device including interconnect structure and method of manufacturing same

Abstract

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes: a base layer; a first metal line extending in a first direction on the base layer; a second metal line extending in the first direction on the base layer and adjacent to the first metal line at the same level; and a metal jumper wire between the first metal wire and the second metal wire at the same level, in which the metal jumper wire connects the first metal wire and the second metal wire.

Description

Technical Field

[0001] The apparatus and methods consistent with embodiments of the present disclosure relate to semiconductor devices including interconnect structures in which metal jumper structures are formed between two adjacent metal lines. Background Technology

[0002] The performance of semiconductor devices is affected by how interconnect structures are formed within them. Interconnect structures include back-end process (BEOL) structures, such as metal lines and vias, which connect front-end process (FEOL) structures to voltage sources or other circuit elements via middle-end process (MOL) structures. FEOL structures include transistor structures, such as channel structures, source / drain regions, and gate structures, while MOL structures include contact plugs formed on the source / drain regions and gate structures.

[0003] As semiconductor devices have evolved to have high device density and high performance, the design and formation of interconnect structures including metal lines and pathways in the critical pitch region have become more difficult and complex, while also requiring semiconductor devices to have improved resistance and capacitance (RC) characteristics.

[0004] The information disclosed in the background section was already known to the inventors prior to implementing the embodiments described herein, or it is technical information obtained in the process of implementing the embodiments described herein. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the Invention

[0005] This disclosure provides example embodiments of interconnect structures for semiconductor devices, wherein adjacent metal lines on the same metal layer or at the same level are connected by metal jumpers without using overlay or underlay metal lines or pathways.

[0006] According to one or more embodiments, a semiconductor device is provided, which may include: a substrate; a first metal line extending in a first direction on the substrate; a second metal line extending in the first direction on the substrate and adjacent to the first metal line at the same level; and a metal jumper at the same level between the first metal line and the second metal line, wherein the metal jumper connects the first metal line and the second metal line.

[0007] According to one or more embodiments, a semiconductor device is provided, which may include: a substrate; and a plurality of metal lines extending in a first direction at the same level on the substrate, wherein a first metal line of the plurality of metal lines has a protrusion protruding toward a second metal line adjacent to the first metal line in a second direction intersecting the first direction, the protrusion connecting the first metal line and the second metal line.

[0008] According to one or more embodiments, a method for manufacturing a semiconductor device is provided. The method may include: providing a substrate; forming a first metal line and a second metal line on the substrate at the same level, the first metal line and the second metal line being adjacent to each other and extending in a first direction; and forming a metal jumper at the same level between the first metal line and the second metal line, such that the metal jumper connects the first metal line and the second metal line. Attached Figure Description

[0009] The exemplary embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 A plan view of a semiconductor device including interconnect structures is shown.

[0011] Figure 2 and Figure 3 A plan view of each semiconductor device including an interconnect structure is shown according to some embodiments.

[0012] Figure 4A A plan view of a semiconductor device including an interconnect structure according to one or more embodiments is shown, the interconnect structure having metal jumpers connecting metal lines at the same level. Figure 4B The following are illustrated according to one or more embodiments. Figure 4A The line A-A' shown intercepts Figure 4A A cross-sectional view of a semiconductor device.

[0013] Figures 5A-5F A cross-sectional view of an intermediate semiconductor device is shown after various steps in the fabrication of a semiconductor device including interconnect structures, according to one or more embodiments, in which metal jumpers are formed to connect two adjacent metal lines at the same level.

[0014] Figures 6A-6H A cross-sectional view of an intermediate semiconductor device is shown after various steps in the fabrication of a semiconductor device including interconnect structures, according to one or more other embodiments, in which metal jumpers are formed to connect two adjacent metal lines at the same level.

[0015] Figures 7A-7D Each of the embodiments is shown separately. Figure 6E-6H The diagram shows a plan view of the intermediate semiconductor device.

[0016] Figure 8A A flowchart illustrating a method for manufacturing a semiconductor device including an interconnect structure according to one or more embodiments is shown, wherein reference is made to... Figures 5A-5F Metal jumpers are formed to connect two adjacent metal wires at the same level.

[0017] Figure 8B A flowchart illustrating a method for manufacturing a semiconductor device including an interconnect structure according to one or more embodiments is shown, wherein reference is made to... Figures 6A-6H Metal jumpers are formed to connect two adjacent metal wires at the same level.

[0018] Figure 9 This is a block diagram of a system-on-a-chip (SoC) 1000 according to one or more embodiments, including... Figures 4A-4B and Figure 5F The semiconductor device shown and Figure 6H and Figure 7D At least one of the semiconductor devices shown. Detailed Implementation

[0019] The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and can be implemented in various other forms. Each of the embodiments provided in the following description does not exclude association with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with this disclosure. For example, even if a matter described in a particular example or embodiment is not described in a different example or embodiment, such matter may be understood to be related to or combined with a different example or embodiment unless otherwise mentioned in its description. Furthermore, it should be understood that all descriptions of the principles, aspects, examples, and embodiments of this disclosure are intended to cover their structural and functional equivalents. Moreover, these equivalents should be understood to include not only currently known equivalents but also equivalents developed in the future, i.e., all devices invented to perform the same function, regardless of their structure. For example, the channel layer, sacrificial layer, and isolation layer described herein may take different types or forms, as long as this disclosure is applicable.

[0020] It should be understood that when an element, component, layer, pattern, structure, region, etc., of a semiconductor device (hereinafter collectively referred to as an "element") is described as being "above," "over," "below," "under," "connected to," or "attached to" another element of the semiconductor device, it may be directly located above, above, above, below, below, connected to, or attached to that other element, or an intermediary element may be present. Conversely, when an element of a semiconductor device is described as being "directly" above, above, above, below, below, or "directly connected to," or "directly attached to," another element of the semiconductor device, no intermediary element is present. Throughout this disclosure, the same reference numerals refer to the same elements.

[0021] For ease of description, this document uses spatial relative terms such as “above,” “above,” “upper,” “upper part,” “below,” “under,” “lower,” “left,” “right,” “lower left,” “lower right,” “upper left,” “upper right,” “center,” “middle,” etc., to describe the relationship between one element and another shown in the figures. It should be understood that, in addition to the orientations described in the figures, the spatial relative terms are intended to cover different orientations of the semiconductor device in use or operation. For example, if the semiconductor device in the figure is flipped, then an element described as “below” or “below” another element will be oriented “above” the other element. Therefore, the term “below” can cover both upper and lower orientations. Semiconductor devices can be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein are interpreted accordingly. As another example, when a device or structure including elements referred to as “left” and “right” elements are oriented differently, the elements referred to as “left” and “right” elements can be “right” and “left” elements. Therefore, in the following description, the "left" element and the "right" element can also be referred to as the "first" element or the "second" element, respectively, provided that their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" element and "upper" element can be referred to as the "first" element and the "second" element, respectively, with necessary descriptions to distinguish between the two elements.

[0022] It should be understood that although the terms “first,” “second,” “third,” “fourth,” “fifth,” “sixth,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0023] As used herein, when preceding a list of components, expressions such as “at least one of…” modify the entire list of components but not individual components within it. For example, the expression “at least one of a, b, and c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Here, when the terms “identical” or “equal” are used to compare the dimensions of two or more components, the term may encompass dimensions that are “substantially identical” or “substantially equal.” In this document, the term “isolation” may refer to electrical isolation or insulation.

[0024] It should also be understood that even if a particular step or operation in manufacturing an apparatus or structure is described earlier than another step or operation, that step or operation may be performed later than the other steps or operations, unless the other steps or operations are described as being performed after that step or operation.

[0025] This document describes numerous embodiments with reference to cross-sectional views as schematic diagrams of implementations (and intermediate structures). Therefore, variations from the illustrated shapes are expected as a result of, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments should not be construed as limited to the specific shapes of the areas shown herein, but rather include, for example, shape deviations due to manufacturing processes. The various areas shown in the figures are schematic in nature, and their shapes are not intended to represent the actual shapes of regions of the device, nor are they intended to limit the scope of this disclosure. Furthermore, in the figures, the dimensions and relative dimensions of layers and regions may be enlarged for clarity.

[0026] For the sake of brevity, conventional components of semiconductor devices may or may not be described in detail herein or shown in the accompanying drawings. For example, MOL or FEOL structures may not be shown or described in detail when they are not relevant to the concept of this disclosure.

[0027] Various embodiments of this disclosure are described below with reference to the accompanying drawings.

[0028] Figure 1 A plan view of a semiconductor device including interconnect structures is shown.

[0029] refer to Figure 1 The interconnect structure 10 formed in the BEOL process can be disposed on the base layer 100. Here, the base layer 100 can be a BEOL layer including another interconnect structure, a mid-process (MOL) layer including one or more contact structures, or a front-end process (FEOL) layer including one or more active devices (e.g., transistor structures) or passive devices (e.g., capacitors) of semiconductor devices.

[0030] The interconnect structure 10 may include multiple M1 metal lines M11-M13, multiple vias V11 and V12 formed on the M1 metal lines M11 and M12, and an M2 metal line M21 connecting the M1 metal lines M11 and M12 vias V11 and V12. The M1 metal lines may be formed extending in a first direction D1 and arranged at a predetermined pitch in a second direction D2 perpendicular to the first direction D1. The M1 metal lines may be formed at the same level, for example, at the M1 level (or M1 metal layer). Therefore, in the first direction D1 and the second direction D2, the bottom surfaces of the M1 metal lines may be horizontally coplanar or aligned, and their top surfaces may also be horizontally coplanar or aligned. The M1 and M2 metal lines and the vias V11 and V12 may be formed of metals or metal compounds including ruthenium (Ru), molybdenum (Mo), etc., and are not limited thereto; they may be formed by direct etching on an initial metal structure formed of the same metal or metal compound, without an inlay process.

[0031] When there is a design requirement to connect adjacent M1 metal lines M11 and M12 in the second direction D2, if the M1 metal lines are formed in a very high-density region or a critical minimum metal pitch region using a self-alignment method with spacers defining metal-to-metal distances, the current design / manufacturing scheme of the metal lines does not allow for direct connection of two M1 metal lines in the second direction D2. Therefore, two M1 metal lines can be connected at a higher level (e.g., M2 or M3 level (or M2 or M3 metal layer)) via two or more pathways in one or more pathway layers. However, the minimum pathway-to-path distance limitation in the critical minimum metal pitch region also does not allow for direct connection of two M1 metal lines in the second direction D2. Figure 1 The two pathways V11 and V12 shown are arranged in the second direction D2 and connected to each other by the overlying M2 metal wire, which are formed at the same level (or pathway layer).

[0032] Therefore, M1 metal wires M11 and M12 can be connected using two pathways. These two pathways are not arranged on the second direction D2, but are horizontally offset from each other on the two M1 metal wires M11 and M12 respectively, as shown below. Figure 2 and Figure 3 As shown.

[0033] Figure 2 and Figure 3 A plan view of each semiconductor device including an interconnect structure is shown according to some embodiments.

[0034] refer to Figure 2 The interconnect structure 20 may include a base layer 100, M1 metal lines M11-M13, a via V11, and an M2 metal line M21, which can be connected to... Figure 1 Those interconnect structures 10 shown are the same, therefore, repeated descriptions of them are omitted herein.

[0035] In interconnect structure 20, metal lines M11 and M12 can be connected via two horizontally offset paths V11 and V13, two adjacent metal lines M21 and M22, two paths V21 and V22, and metal line M31. These metal lines and paths can have the same material composition as those in interconnect structure 10.

[0036] Passages V11 and V13 are formed in the first passage layers on metal wires M11 and M12, respectively. Metal wires M21 and M22, formed at the same M2 level (or M2 metal layer) on passages V11 and V13, can extend in the second direction D2 and be arranged in the first direction D1. Two passages V21 and V22 can be formed in the second passage layers on the two metal wires M21 and M22, respectively. Metal wire M31 can be formed at the M3 level (or M3 metal layer) on the second passage layers to connect the two passages V21 and V22 by extending in the first direction D1.

[0037] Here, the connection between the two metal lines M11 and M12 in the critical minimum metal pitch region requires multiple additional interconnects, including the pathways V11, V13, V21, and V22 at the upper levels (two metal layers and two via layers), metal lines M21 and M22 of the M2 layer, and metal line M31 of the M3 layer. Therefore, the formation of the interconnect structure 20 of the semiconductor device can become complex, leading to an area penalty for the semiconductor device including the interconnect structure 20. Therefore, an alternative interconnect structure scheme can be considered as follows.

[0038] refer to Figure 3 The interconnect structure 30 may include a base layer 100, M1 metal wires M11-M13, and vias V11 and V13, which can be connected to... Figure 2 The interconnect structures 20 shown are the same, therefore, a repeated description thereof is omitted herein.

[0039] In the interconnect structure 30, M1 metal lines M11 and M12 can be connected via two horizontally offset paths V11 and V13 in the first pass layer, and a single wide M2 ​​metal line M23 at the M2 level (M2 metal layer), which extends in the first direction D1 and the second direction D2 to cover paths V11 and V13. However, in addition to using more than two layers (one metal layer and one pass layer), the wide area of ​​the M2 metal line M23 prevents the formation of other circuit elements or other metal lines or paths in the space occupied by the M2 metal line M23, which also leads to unnecessary area loss in the critical minimum metal pitch region.

[0040] The following implementation methods can solve the problem respectively. Figure 2 and Figure 3 The aforementioned problems with the interconnect structures 20 and 30 shown.

[0041] Figure 4A A plan view of a semiconductor device including an interconnect structure according to one or more embodiments is shown, the interconnect structure having metal jumpers connecting metal lines at the same level. Figure 4B The following are illustrated according to one or more embodiments. Figure 4A The line A-A' shown intercepts Figure 4A A cross-sectional view of a semiconductor device.

[0042] refer to Figure 4A and Figure 4B The interconnect structure 40 may include a base layer 100 and M1 metal lines M11-M13, which can be connected to... Figure 2 and Figure 3 The interconnect structures 20 and 30 shown are identical, therefore, their repeated description can be omitted in this paper.

[0043] However, unlike interconnect structures 20 and 30, interconnect structure 40 may include a metal jumper J1 to connect two M1 metal lines M11 and M12 at the same level as the two M1 metal lines, such as... Figure 4B As shown. Furthermore, metal jumper J1 can connect only a portion of metal wire M11 to the portion of metal wire M12 facing the second direction D2, as shown. Figure 4A As shown. Therefore, the length of the metal jumper J1 in the first direction D1 can be less than the length of at least one or each of the two metal wires M11 and M12. Therefore, the interconnect structure 40 can omit the upper-level path or metal wire formed in the interconnect structures 20 and 30, or omit the lower-level path or metal wire. Therefore, the connection length is shortened, thereby reducing the contact resistance and also achieving area gain. In addition, the manufacturing process of the interconnect structure 40 can be simplified compared to the manufacturing process of the interconnect structures 20 and 30.

[0044] Metal jumper J1 may have the same metal or metal compound as metal wires M11-M13, such as ruthenium (Ru). However, according to one or more other embodiments, the metal jumper may include different metals or metal compounds, including, but not limited to, copper (Cu), tungsten (W), cobalt (Co), aluminum (Al), etc. The top surface of metal jumper J1 may be horizontally coplanar or aligned with the top surfaces of metal wires M11-M13. Alternatively, according to one or more other embodiments, the top surface of metal jumper J1 may be at a higher or lower level than the top surfaces of metal wires M11-M13.

[0045] In the interconnect structure 40, a first contact pad 101 may be formed between the base layer 100 and the overlying M1 metal wires M11-M13. For example, the first contact pad 101 may be formed on the bottom surface of the M1 metal wires M11-M13 or on the top surface of the base layer 100, where the metal wires M11-M13 are connected to the base layer 100. Furthermore, a second contact pad 102 may be formed between the base layer 100 and the metal jumper J1, between the metal jumper J1 and the M1 metal wires M11, and between the metal jumper J1 and the M1 metal wires M12. For example, the second contact pad 102 may be formed on the bottom surface of the metal jumper J1 or on the top surface of the base layer 100, where the metal jumper J1 is connected to the base layer 100. The second contact pad 102 may extend in the third direction D3 on the right side surface of the M1 metal wire M11 and the left side surface of the M1 metal wire M12.

[0046] Contact pads 101 and 102 may be provided to reduce contact resistance and enhance adhesion properties between each M1 metal wire M11-M13 and the underlay structure on the base layer 100, and between the metal jumper J1 and each M1 metal wire M11 and M12. Contact pads 101 and 102 may each be formed of a material such as, but are not limited to, titanium nitride (TiN) or tantalum nitride (TaN).

[0047] Alternatively, according to one or more other embodiments, when the metal jumper J1 is isolated from the underlying structure on the base layer 100 while connecting the two M1 metal wires M11 and M12, a dielectric layer or air gap may be formed between the metal jumper J1 and the base layer 100. Therefore, in this case, the bottom surface of the metal jumper J1 may be at a higher level than the bottom surface of at least one of the two metal wires M11 and M12. In this case, according to one or more other embodiments, the second contact pad 102 may or may not be formed on the side surfaces of the M1 metal wires M11 and M12 connected to the metal jumper J1.

[0048] Intermetallic dielectric (IMD) materials such as silicon oxide (SiO2) can be formed as IMD layer 104 to surround the M1 metal lines M11-M13 and the metal jumper J1 for isolation purposes.

[0049] The following provides a method for manufacturing a semiconductor device including an interconnect structure with metal jumpers.

[0050] Figures 5A-5FA cross-sectional view of an intermediate semiconductor device is shown after various steps in the fabrication of a semiconductor device including interconnect structures, according to one or more embodiments, in which metal jumpers are formed to connect two adjacent metal lines at the same level.

[0051] refer to Figures 5A-5F The manufactured semiconductor device may be or can correspond to including Figure 4A and Figure 4B The semiconductor device with interconnect structure 40 shown, Figures 5A-5F The cross-sectional view of each of the intermediate semiconductor devices shown corresponds to Figure 4B The semiconductor device shown. Therefore, information regarding the above reference can be omitted. Figure 4A and Figure 4B The same structural elements are described repeatedly, and the same reference numerals and characters shown therein may be used in the following description.

[0052] refer to Figure 5A The intermediate semiconductor device may include multiple M1 metal lines M11-M13 with a predetermined pitch on the substrate 100, with a first contact pad 101 therebetween.

[0053] The M1 metal lines M11-M13 can be patterned by direct etching on the initial metal structure based on a hard mask pattern on the top surface of the initial metal structure. Direct etching can be performed from the top surface of the initial metal structure by, for example, dry etching such as reactive ion etching (RIE) to form the M1 metal lines M11-M13 on the substrate 100, with the first contact pad 101 located therebetween.

[0054] The initial metallic structure for forming the M1 metal wire can be ruthenium (Ru), which offers lower electrical resistance and reduced electromigration properties compared to other metallic materials such as copper (Cu). Alternatively, molybdenum (Mo) or cobalt (Co) can be used to form the initial metallic structure of the M1 metal wire.

[0055] The M1 metal wires M11-M13 can be formed to extend in the first direction D1 and be arranged in the second direction D2 at a predetermined pitch.

[0056] refer to Figure 5B In the previous steps ( Figure 5A An IMD layer 104 is formed on the intermediate semiconductor device obtained in the process to surround each of the M1 metal lines M11-M13, thereby isolating these M1 metal lines from each other and from other circuit elements.

[0057] Physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and combinations thereof, can be used to perform the deposition of the material in the preceding steps. Figure 5A The IMD layer 104 is formed by depositing a low-k dielectric material (such as silicon oxide (SiO2)) on an intermediate semiconductor device obtained in the process, but is not limited thereto. After the deposition of the low-k dielectric material, its top can be planarized (e.g., chemical mechanical polishing (CMP)) so that the top surfaces of the IMD layer 104 and the M1 metal lines M11-M13 are horizontally coplanar or aligned in the first direction D1 and the second direction D2.

[0058] refer to Figure 5C In the previous steps ( Figure 5B A hard mask layer 107 is formed on the top surface of the intermediate semiconductor device obtained in the next step, and it is patterned to expose the material to be exposed in the next step. Figure 5D The top surface of a portion of the IMD layer 104 is etched in the process to provide for subsequent steps ( Figure 5E In the space between the M1 metal wires M11 and M12, which will be connected to each other, a metal jumper will be formed.

[0059] Due to the small metal pitch between the two M1 metal lines M11 and M12, the opening O1 provided by the patterned hard mask layer 107 may not only expose what will be in the next step ( Figure 5D The top surface of a portion of the etched IMD layer 104 may also expose the top surfaces of the edge portions of the two M1 metal lines M11 and M12.

[0060] The hard mask layer 107 may be formed of a material such as silicon nitride (SiN, Si3N4, etc.), but is not limited thereto, and has etch selectivity relative to the low-k dielectric material of the IMD layer 104 (such as silicon oxide (SiO2)) and the metal or metal compound (e.g. Ru) forming the M1 metal lines M11 and M12.

[0061] refer to Figure 5D The IMD layer 104 can be patterned based on the opening O1 of the hard mask layer 107 to form a recess R1, which exposes the top surface of the base layer 100 between the M1 metal lines M11 and M12, the right side surface of the M1 metal line M11, and the left side surface of the M1 metal line M12 facing the right side surface of the M1 metal line M11.

[0062] The IMD layer 104, formed of a low-k dielectric material such as silicon oxide (SiO2), can be patterned relative to the hard mask layer 107 by, for example, wet etching using an etchant such as hydrofluoric acid (HF) and / or dry etching such as plasma etching or RIE.

[0063] refer to Figure 5EThe hard mask layer 107 patterned to form the recess R1 can be removed from the intermediate semiconductor device obtained in the previous steps, and a second contact pad 102 can be formed on the inner surface of the recess R1.

[0064] The removal of the hard mask layer 107 can be performed, for example, by ashing or stripping, but is not limited to these methods.

[0065] After removing the hard mask layer 107, a second contact pad 102 can be formed on the inner surface of the recess R1. This second contact pad 102 can be formed from the same material as the first contact pad 101 (e.g., TiN) to provide reduced contact resistance and enhance contact with the material to be used in the next step. Figure 5F The adhesion of the metal jumper wires filled therein. The formation of the second contact pad 102 can be performed, for example, by atomic layer deposition (ALD), but is not limited thereto.

[0066] refer to Figure 5F A metal jumper J1 can be formed in the recess R1 having the second contact pad 102 thereon to obtain Figure 4A and Figure 4B The semiconductor device shown includes interconnect structure 40.

[0067] The metal jumper J1 formed in the recess R1 can connect metal wires M11 and M12. For example, the metal jumper J1 can contact the right side surface of metal wire M11 and the left side surface of metal wire M12, with a second contact pad 102 between them, to connect the two metal wires M1. At this time, the metal jumper J1 can also contact the top surface of the underlay structure on the base layer 100, with the second contact pad 102 located therebetween.

[0068] Metal jumper J1 can be formed by depositing a metal or metal compound that is the same as or different from that of metal wires M11 and M12. For example, metal jumper J1 can be formed from ruthenium (Ru) or copper (Cu). When the metal or metal compound is formed in the recess R1, overflow can extend beyond the top surface of metal wires M11 and M12 in the first direction D1.

[0069] Return to reference Figure 5EWhen the second contact pad 102 is laminated in the recess R1, overflow of the material forming the second contact pad 102 (e.g., TiN) can be formed on at least the top surfaces of the M1 lines M11 and M12. Furthermore, when the metal jumper J1 fills the recess R1 having the second contact pad 102 thereon, overflow of the material forming the metal jumper J1 (e.g., Ru) can be formed on at least the top surfaces of the M1 lines M11 and M12. Therefore, after the metal jumper J1 is formed in the recess R1, this overflowed metal can be removed by planarization (e.g., CMP) such that the top surface of the metal jumper J1 can be horizontally coplanar or aligned with the top surfaces of the M1 metal lines M1 and M12 on the base layer 100 and the IMD layer 104. Alternatively, according to one or more other embodiments, the overflow metal of metal jumper J1 can be partially removed from the top surfaces of metal wires M11 and M12 of M1, so that the top surface of metal jumper J1 can maintain a layer higher than the top surfaces of metal wires M11 and M12 of M1. Otherwise, according to one or more other embodiments, the metal or metal compound forming metal jumper J1 can be partially filled in the recess R1 to connect the two metal wires.

[0070] Therefore, M1 metal lines M11 and M12 can be connected at the same level without the need for overlay or underlay paths and metal lines, thereby achieving reduced contact resistance, area gain and manufacturing simplicity in the critical minimum metal pitch region of semiconductor devices.

[0071] The metal jumper J1 can be formed by one or more different methods including the following embodiments.

[0072] Figures 6A-6H A cross-sectional view of an intermediate semiconductor device is shown after various steps in the fabrication of a semiconductor device including interconnect structures, according to one or more other embodiments, in which metal jumpers are formed to connect two adjacent metal lines at the same level.

[0073] refer to Figures 6A-6H The manufactured semiconductor device can be or can correspond to Figure 4A and Figure 4B The semiconductor device shown includes interconnect structure 40. Figures 6A-6H The cross-sectional view of each intermediate semiconductor device shown corresponds to Figure 4B The semiconductor device shown. Therefore, information regarding the above reference can be omitted. Figure 4A and Figure 4B The same structural elements are described repeatedly, and the same reference numerals and characters shown therein may be used in the following description.

[0074] refer to Figure 6AThe intermediate semiconductor device may include an initial metal structure M1 (with contact pads 101 therebetween) formed on a base layer 100, and a first hard mask layer 103 (with second hard mask patterns 105A and 105B thereon) on the top surface of the initial metal structure M1.

[0075] The initial metallic structure M1 can be formed from a metal or metal compound that allows direct etching thereon. For example, the initial metallic structure M1 can be formed from ruthenium (Ru) instead of copper (Cu), but is not limited thereto, as it is known that direct etching is difficult to perform on copper (Cu). The initial metallic structure M1 can extend in a first direction D1 and a second direction D2.

[0076] A first hard mask layer 103 can be formed by depositing a material such as silicon oxide (SiO2) on the top surface of the initial metal structure M1 using (but not limited to) PVD, CVD, PECVD, ALD, or combinations thereof, followed by planarization (e.g., CMP) on top of it. The first hard mask layer 103 can also extend in a first direction D1 and a second direction D2. For example, the first hard mask layer 103 can overlap with the initial metal structure M1 in both the first direction D1 and the second direction D2.

[0077] Furthermore, the second hard mask patterns 105A and 105B can be applied to the top surface of the first hard mask layer 103 in subsequent steps. Figure 6H and 7D The two M1 metal lines M11 and M13 are patterned below the first hard mask layer and are formed to extend in the D1 direction. Therefore, the second hard mask patterns 105A and 105B can have widths that define the widths of the M1 metal lines M11 and M13 in the second direction D2. The formation of the second hard mask patterns 105A and 105B can be performed on the second hard mask layer by, for example, photolithography. The second hard mask patterns 105A and 105B can be formed from silicon nitrides (e.g., SiN, Si3N4, etc.) that have etch selectivity relative to the first hard mask layer 103, which can be formed from, for example, silicon oxide (SiO2), but are not limited thereto.

[0078] refer to Figure 6B , can Figure 6A The intermediate semiconductor device includes a spacer 106 having a predetermined width in the second direction D2 formed on the side surface of the second hard mask patterns 105A and 105B.

[0079] Spacers 106 can be formed to define the metal-to-metal distance between M1 metal lines in the M1 metal layer; therefore, the predetermined width of spacers 106 will become the basis for subsequent steps ( Figure 6H and Figure 7DThe distance between two adjacent M1 metal lines formed in the process. The spacer 106 can be formed by an ALD of a material such as titanium nitride (TiN) or tantalum nitride (TaN) along the side surfaces of the second hard mask patterns 105A and 105B extending in the first direction D1, but is not limited thereto.

[0080] After spacers 106 are formed along the side surfaces of the second hard mask patterns 105A and 105B, an opening O2 may be formed between two adjacent spacers 106 (e.g., spacer 106 on the right side surface of the second hard mask pattern 105A and spacer 106 on the left side surface of the second hard mask pattern 105B). The spacers 106 may extend along the side surfaces of the second hard mask patterns 105A and 105B, which also extend in the first direction D1. Furthermore, the top surface of the spacers 106 may be horizontally coplanar or aligned with the top surfaces of the second hard mask patterns 105A and 105B.

[0081] refer to Figure 6C The third hard mask pattern 108 can be used to fill the area. Figure 6B An opening O2 is formed between two adjacent spacers 106 in an intermediate semiconductor device.

[0082] A third hard mask pattern 108 may be formed in the opening O2 so that the side surfaces of two adjacent spacers 106 extending in the first direction D1 along both sides of the opening O2 also extend in the first direction D1.

[0083] The third hard mask pattern 108 can be formed by depositing a material (e.g., silicon nitride) through, for example, PVD, CVD, PECVD, ALD, or a combination thereof, followed by planarizing (e.g., CMP) the top surfaces of the second hard mask patterns 105A, 105B, spacer 106, and the third hard mask pattern 108 so that the top surfaces are horizontally coplanar or aligned with each other. The material can be the same as the material used to form the second hard mask patterns 105A and 105B.

[0084] refer to Figure 6D The spacer 106 can be removed, leaving only the second and third hard mask patterns 105A, 105B and 108 on the top surface of the first hard mask layer 103.

[0085] The spacer 106 can be removed by, for example, dry etching (such as plasma etching or RIE) to selectively remove the spacer material (e.g., TiN or TaN, not limited thereto) relative to the hard mask pattern material (e.g., silicon nitride and silicon oxide, not limited thereto).

[0086] Since the hard mask patterns 105A, 108 and 105B to be arranged sequentially on the top surface of the first hard mask pattern 103 in the second direction D2 will be used in subsequent steps ( Figure 6H and Figure 7D The initial metal structure M1 is patterned with three M1 metal layers. The distance between two adjacent hard mask patterns 105A (or 105B) and 108 can define the metal-to-metal distance of the M1 metal line in the second direction D2, which is the same as the width of the spacer 106 in the same direction.

[0087] refer to Figure 6E , can Figure 6D A fourth hard mask layer 109 is formed on the intermediate semiconductor device and patterned to form an opening O3 corresponding to the metal jumper to be formed in a subsequent step.

[0088] The fourth hard mask layer 109 can be achieved through the previous steps ( Figure 6D The intermediate semiconductor device obtained in the process is formed by spin-coating a material such as silicon carbide (SiC) onto the top surface, thereby forming a spin-coated hard mask (SOH). Subsequently, a fourth hard mask layer 109 can be formed in subsequent steps (…). Figure 6H and Figure 7D The area below which the metal jumper is formed is patterned.

[0089] Since the metal jumper can be formed to connect only a portion of two adjacent M1 metal lines that will be patterned based on hard mask patterns 105A and 108 respectively, the opening O3 can be patterned to correspond only to the area of ​​the metal jumper, such as Figure 7A As shown, Figure 7A The following are illustrated according to one or more embodiments. Figure 6E The diagram shows a plan view of the intermediate semiconductor device.

[0090] refer to Figure 6F The fifth hard mask pattern 111 can be used for filling. Figure 6E An opening O3 is formed in the intermediate semiconductor device, and the fourth hard mask layer 109 can be removed from the intermediate semiconductor device.

[0091] The fifth hard mask pattern 111 can be formed by depositing a material similar to the materials of the second and third hard mask patterns 105A, 105B and 108 (e.g., silicon nitride) in the opening O3 by, for example, PVD, CVD, PECVD, ALD or a combination thereof, such that the fifth hard mask pattern 111 can fill a portion of the space between the second hard mask pattern 105A and the third hard mask pattern 108, which corresponds to a metal jumper that will be formed in a subsequent step.

[0092] Subsequently, the fourth hard mask layer 109 can be removed by, for example, peeling or ashing, and the fifth hard mask pattern 111 can be planarized (e.g., CMP) so that the top surface of the fifth hard mask pattern 111 can be horizontally coplanar or aligned with the top surfaces of the other hard mask patterns 105A, 105B and 108. Figure 7B The following are illustrated according to one or more embodiments. Figure 6F The diagram shows a plan view of the intermediate semiconductor device.

[0093] refer to Figure 6G The first hard mask layer 103 can be patterned on the top surface of the initial metal structure M1 based on the second, third and fifth hard mask patterns 105A, 105B, 108 and 111, thereby forming two first hard mask patterns 103A and 103B from the first hard mask layer 103.

[0094] Dry etching can be performed on the hard mask layer 103 based on a second hard mask pattern 105A, a fifth hard mask pattern 111, a third hard mask pattern 108, and another second hard mask pattern 105B arranged in this order on the top surface of the first hard mask layer 103 in the second direction D2.

[0095] Through the patterning operation in this step, the first hard mask layer 103 can be patterned to form first hard mask patterns 103A and 103B. The first hard mask pattern 103A can be vertically overlapped with the second hard mask pattern 105A, the fifth hard mask pattern 111 and the third hard mask pattern 108, and another first hard mask pattern 103B can be vertically overlapped with another second hard mask pattern 105B. Figure 7C The following are illustrated according to one or more embodiments. Figure 6G The diagram shows a plan view of the intermediate semiconductor device.

[0096] refer to Figure 6H The initial metal structure M1 can be patterned based on the first hard mask patterns 103A and 103B, which have other hard mask patterns 105A, 111, 108, and 105B, to form a structure like... Figure 7D The M1 metal wires M11-M13 and metal jumper J2 are shown. Figure 7D The following are illustrated according to one or more embodiments. Figure 6H The diagram shows a plan view of the intermediate semiconductor device.

[0097] Metal lines M11-M13 and metal jumper J2 formed between metal lines M11 and M12 can be patterned, for example, by dry etching (such as RIE or plasma etching). Since metal jumper J2 is formed based on a portion of the fifth hard mask pattern 111 and the first hard mask pattern 103A that is vertically overlapped by the fifth hard mask pattern 111, metal jumper J2 can be formed only between metal lines M11 and M12. Figure 6E and Figure 7A Between the portions of the opening O3 shown. Therefore, in the first direction D1, the length of the metal jumper J2 can be less than the length of at least one of the M1 metal wires M11 and M12. Therefore, the metal jumper J2 can take a protruding shape from the M1 metal wire M11 toward the M1 metal wire M12, and vice versa.

[0098] Here, metal jumper J2 can be formed together with metal wires M11 and M12 from the initial metal structure M1 as a single continuum structure. Therefore, no connecting surface, interface, or barrier layer needs to be formed between metal wire M11 and metal jumper J2, or between metal jumper J2 and metal wire M13. Instead, Figure 4A , Figure 4B and Figures 5A-5F The metal jumper J1 of the interconnect structure 40 shown can be connected to the M1 metal lines M11 and M12 via a second contact pad 102, which can form a connection surface, interface, or barrier layer. Even when the second contact pad 102 is not formed between the metal jumper J1 and the M1 metal lines M11 and M12 in the interconnect structure 40, a connection surface, interface, or barrier layer can still be formed between them because the metal jumper J1 is formed in the recess R1 between the M1 metal lines M11 and M12. Figure 5E-5F Metal lines M11 and M12 were formed before the formation of the depression R1.

[0099] like Figure 6H and Figure 7D The metal jumper J2 shown also achieves reduced contact resistance, area gain, and manufacturing simplicity because it eliminates the need for overlay metal wires and pathways to connect two adjacent M1 metal lines M11 and M12 at the same level. Furthermore, when forming the metal jumper J2 to connect the M1 metal lines M11 and M12, the contact resistance can be further reduced because, as mentioned above, no connecting surfaces, interfaces, or barrier layers are formed in the simultaneously formed single continuous structure.

[0100] Figure 8A A flowchart illustrating a method for manufacturing a semiconductor device including an interconnect structure according to one or more embodiments is shown, in which metal jumpers are formed to connect two adjacent metal lines at the same level. (Refer to...) Figures 5A-5F .

[0101] In step S10, multiple M1 metal lines can be patterned on the base layer to extend in the first direction D1, be arranged in the second direction D2, and be surrounded by the IMD layer. Figures 5A-5B ).

[0102] The M1 metal line can be located in the same M1 metal layer in the critical metal pitch region with extremely small metal line pitch in an intermediate semiconductor device. The M1 metal line can be directly etched from the initial metal structure formed of ruthenium (Ru).

[0103] In step S20, a recess can be formed in the IMD layer between two adjacent M1 metal lines among the multiple M1 metal lines. Figures 5C-5D ).

[0104] The recess may have a length less than at least one of the two metal wires in the first direction D1. The recess may or may not expose the top surface of the substrate. A contact pad formed of TiN or TaN may or may not be laminated in the inner surface of the recess.

[0105] In step S30, metal jumpers can be filled into the recesses in the IMD layer to connect two adjacent M1 metal lines in the second direction D2. Figure 5E-5F ).

[0106] Since the metal jumper fills the recess formed in the previous step S20, the metal jumper may have the same or similar shape as the recess in the plan view. Therefore, the length of the metal jumper in the first direction D1 may be less than at least one of the two M1 metal wires. In the case of forming a contact pad, the metal jumper can connect the two M1 metal wires through the contact pad, which can provide reduced contact resistance and enhanced adhesion properties. The material composition of the metal jumper may be the same as or different from the material composition of the M1 metal wires.

[0107] Figure 8B A flowchart illustrating a method for manufacturing a semiconductor device including an interconnect structure according to one or more embodiments is shown, in which metal jumpers are formed to connect two adjacent metal lines at the same level. (Refer to...) Figures 6A-6H .

[0108] In step S10, two hard mask patterns are formed on the initial metal structure, with an opening between the two hard mask patterns. The two hard mask patterns correspond to two M1 metal lines that will be connected to each other at the same M1 metal layer. Figures 6A-6E and Figure 7A ).

[0109] Two hard mask patterns ( Figure 6D105A and 108 in the figure can define the two M1 metal lines to be patterned below them in the next step. Figure 6H and Figure 7D The M11 and M12 patterns in the initial metal structure can have widths equal to the widths of the two M1 metal lines. Furthermore, the distance between the two hard mask patterns on the initial metal structure in the second direction D2 can define the width of the metal jumper to be patterned from the initial metal structure to connect the two M1 metal lines. The initial metal structure can be formed of ruthenium (Ru).

[0110] In step S20, another hard mask pattern may be formed on the initial metal structure to fill the opening between the two hard mask patterns formed in the previous step S10. Figure 6F and Figure 7B ).

[0111] Although the two hard mask patterns that define the two M1 metal lines can extend in the first direction D1, the hard mask pattern interposed therebetween (to fill the distance between the two hard mask patterns) may not extend in the first direction D1 to the full length of the two M1 metal lines.

[0112] In step S30, the initial metal structure can be patterned based on the three hard mask patterns obtained in previous steps S10 and S20 to form two adjacent M1 metal lines and a metal jumper connecting the two M1 metal lines in the second direction D2. Figure 6G-6H and Figures 7C-7D ).

[0113] Since the metal jumpers are patterned substantially simultaneously based on the three connected hard mask patterns, the two M1 metal lines and the metal jumpers between them can form a single continuous metal structure with the same material composition, without connecting surfaces, interfaces, or blocking layers. Furthermore, because the length of the intermediate hard mask pattern corresponding to the metal jumpers is shorter, the metal jumpers have a shorter length in the first direction D1 than the two M1 metal lines.

[0114] The above embodiments provide an interconnect structure including three M1 metal lines M11-M13 located on the M1 metal layer and a metal jumper J1 or J2 connecting two adjacent M1 metal lines M11 and M12 among the three M1 metal lines M11-M13. However, this disclosure is not limited thereto. According to one or more other embodiments, the metal jumper J1 or J2 may be formed in an interconnect structure having more or fewer than three M1 metal lines to connect two adjacent M1 metal lines. Furthermore, according to one or more other embodiments, the metal jumper J1 or J2 may connect two adjacent M2 metal lines in an M2 metal layer above the M1 metal layer or in different metal layers.

[0115] Figure 9 This is a block diagram of a system-on-a-chip (SoC) 1000 according to one or more embodiments, which includes Figures 4A-4B and Figure 5F The semiconductor device shown and Figure 6H and Figure 7D At least one of the semiconductor devices shown.

[0116] refer to Figure 9 The SoC 1000 can be an integrated circuit that integrates components of a computing system or other electronic system. As an example of the SoC 1000, an application processor (AP) may include at least one processor and components for various functions. The SoC 1000 may include a core 1011 (e.g., a processor), a digital signal processor (DSP) 1012, a graphics processing unit (GPU) 1013, embedded memory 1014, a communication interface 1015, and a memory interface 1016. The components of the SoC 1000 can communicate with each other via a bus 1007.

[0117] Core 1011 can process instructions and control the operation of components included in SoC 1000. For example, core 1011 can process a series of instructions to run an operating system and execute applications on the operating system. DSP 1012 can generate useful data by processing digital signals (e.g., digital signals provided from communication interface 1015). GPU 1013 can generate data for an image output by a display device from image data provided from embedded memory 1014 or memory interface 1016, or can encode image data.

[0118] Embedded memory 1014 can store data used by core 1011, DSP 1012, and GPU 1013. Communication interface 1015 can provide an interface for communication networks or one-to-one communication. Memory interface 1016 can provide an interface for external memory of SoC 1000 such as dynamic random access memory (RAM) (DRAM), flash memory, etc.

[0119] At least one of the core 1011, DSP 1012, GPU 1013, and / or embedded memory 1014 may include Figures 4A-4B and Figure 5F The semiconductor device shown and Figure 6H and Figure 7D At least one of the semiconductor devices shown.

[0120] The foregoing is an illustrative description of exemplary embodiments and should not be construed as limiting this disclosure. Although several exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the above embodiments without departing from the essence of this disclosure.

[0121] This application is based on and claims priority to U.S. Provisional Application No. 63 / 645,367, filed with the U.S. Patent and Trademark Office on May 10, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: grassroots level; A first metal wire extends in a first direction on the base layer; A second metal wire extends on the base layer in the first direction and is adjacent to the first metal wire at the same level; and A metal jumper wire, located at the same level between the first metal wire and the second metal wire. The metal jumper connects the first metal wire and the second metal wire.

2. The semiconductor device of claim 1, wherein the metal jumper has a length in the first direction that is smaller than that of the first metal wire or the second metal wire.

3. The semiconductor device of claim 1, wherein a contact pad is formed between the metal jumper and at least one of the first metal line and the second metal line.

4. The semiconductor device of claim 3, wherein the contact pad comprises titanium nitride.

5. The semiconductor device of claim 1, further comprising a contact pad between the substrate and the bottom surface of the first metal line or the second metal line.

6. The semiconductor device of claim 1, wherein the metal jumper contacts the first metal line and the second metal line without connecting surfaces, interfaces or barrier layers.

7. The semiconductor device of claim 1, wherein the first metal line, the second metal line, and the metal jumper have the same material composition.

8. The semiconductor device of claim 7, wherein the same material composition includes ruthenium (Ru).

9. The semiconductor device of claim 1, wherein the metal jumper has a material composition different from that of the first metal wire and the second metal wire.

10. The semiconductor device of claim 9, wherein the first metal line and the second metal line comprise ruthenium (Ru).

11. A semiconductor device, comprising: grassroots level; and Multiple metal wires extend in a first direction at the same level on the base layer. The first metal wire among the plurality of metal wires has a protrusion protruding toward a second metal wire adjacent to the first metal wire in a second direction intersecting the first direction, the protrusion connecting the first metal wire and the second metal wire.

12. The semiconductor device of claim 11, wherein the protrusion has a length in the first direction that is smaller than that of the first metal line or the second metal line.

13. The semiconductor device of claim 11, wherein the protrusion is located at the same level as the first metal line and the second metal line.

14. The semiconductor device of claim 11, wherein the top surfaces of the first metal line, the second metal line, and the protrusion are coplanar or aligned, and The first metal wire, the second metal wire, and the bottom surface of the protrusion are coplanar or aligned.

15. The semiconductor device of claim 11, wherein the first metal line, the metal jumper, and the second metal line form a single continuous metal structure.

16. The semiconductor device of claim 15, wherein the first metal line, the metal jumper, and the second metal line have the same material composition.

17. A method for manufacturing a semiconductor device, the method comprising: Provide for the grassroots; A first metal wire and a second metal wire are formed at the same level on the base layer, the first metal wire and the second metal wire being adjacent to each other and extending in a first direction; and A metal jumper is formed between the first metal wire and the second metal wire at the same level, such that the metal jumper connects the first metal wire and the second metal wire.

18. The method of claim 17, wherein the first metal wire, the second metal wire, and the metal jumper have the same material composition.

19. The method of claim 18, wherein the same material composition includes ruthenium (Ru).

20. The method of claim 19, wherein the metal jumper has a material composition different from that of the first metal wire and the second metal wire.

21. The method of claim 19, further comprising forming a contact pad between the metal jumper and at least one of the first metal wire and the second metal wire.

22. The method of claim 19, wherein the first metal wire, the metal jumper wire, and the second metal wire form a single continuous structure without connecting surfaces, interfaces, or barrier layers.

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