Semiconductor package structure and preparation method thereof, electronic device

Abstract

This application discloses a semiconductor packaging structure, its fabrication method, and an electronic device. The semiconductor packaging structure includes: a conductive layer comprising a first portion and a second portion spaced apart from the first portion along a first direction; electronic components located along a second direction on at least one side of the first portion and connected to the first portion; and an electrostatic discharge member connected to the second portion; wherein the first direction intersects the second direction. The electronic device includes a motherboard and the aforementioned semiconductor packaging structure, the motherboard being located along the second direction on one side of the semiconductor packaging structure, and the end of the electrostatic discharge member away from the second portion being connected to the motherboard.

Description

Technical Field

[0001] The embodiments of this application relate to the field of semiconductor technology, and in particular to semiconductor packaging structures and their preparation methods, and electronic devices. Background Technology

[0002] Solid-state drives (SSDs) are storage devices composed of solid-state electronic storage chips. They offer advantages such as high read and write speeds, low power consumption, and high stability, and are widely used in electronic devices such as laptops. Because semiconductor packaging structures like SSDs can experience electrostatic discharge (ESD) due to friction, contact, or induction, they typically undergo ESD immunity testing before leaving the factory to assess their stability and reliability in ESD environments.

[0003] Therefore, improving the electrostatic discharge immunity of semiconductor packaging structures is one of the technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0004] The semiconductor packaging structure, its preparation method, and electronic device provided in this application can solve or partially solve the above-mentioned deficiencies or other deficiencies in the prior art.

[0005] The semiconductor packaging structure provided in the first aspect of this application includes:

[0006] A conductive layer includes a first portion and a second portion spaced apart from the first portion along a first direction;

[0007] Electronic components, located along a second direction on at least one side of the first portion and connected to the first portion; and

[0008] An electrostatic discharge element is connected to the second part;

[0009] Wherein, the first direction intersects with the second direction.

[0010] The electronic device provided according to the second aspect of this application includes:

[0011] Semiconductor packaging structures, including:

[0012] A conductive layer includes a first portion and a second portion spaced apart from the first portion along a first direction;

[0013] An electronic component is located on at least one side of the second portion along a second direction and connected to the second portion; and an electrostatic discharge member is connected to the second portion;

[0014] A motherboard is located on one side of the semiconductor package structure along the second direction, and the end of the electrostatic discharge member away from the second part is connected to the motherboard.

[0015] Wherein, the first direction intersects with the second direction.

[0016] The method for fabricating a semiconductor packaging structure according to the third aspect of this application includes:

[0017] A conductive layer is formed, the conductive layer comprising a first portion and a second portion spaced apart from the first portion along a first direction;

[0018] An electronic component connected to the first portion is formed on at least one side of the first portion along the second direction; and

[0019] Connect the electrostatic discharge device to the second part;

[0020] Wherein, the first direction intersects with the second direction.

[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0022] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of the application. In the drawings:

[0023] Figure 1 This is a top view schematic diagram of a semiconductor packaging structure according to one embodiment of this application;

[0024] Figure 2 This is a top view schematic diagram of a semiconductor packaging structure according to another embodiment of this application;

[0025] Figure 3 This is a top view schematic diagram of a semiconductor packaging structure according to yet another embodiment of this application;

[0026] Figure 4 This is a top view schematic diagram of a semiconductor packaging structure according to another embodiment of this application;

[0027] Figure 5 This is a top view schematic diagram of an electronic device according to one embodiment of this application; and

[0028] Figure 6 This is a schematic flowchart of a method for fabricating a semiconductor packaging structure according to one embodiment of this application.

[0029] Figure label:

[0030] 100. Conductive layer; 110. First part; 120. Second part; 121. First sub-part;

[0031] 122. Second sub-section; 123. Through hole; 130. Connector; 200. Static discharge element;

[0032] 300. Static electricity protection components; 310. Resistors; 320. Capacitors; 400. Isolation strips;

[0033] 500. Electronic components; 600. Motherboard. Detailed Implementation

[0034] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0036] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0037] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0038] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0039] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] Furthermore, in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. Furthermore, in this application, the use of "connection" or "joint" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context.

[0041] Solid-state drives (SSDs) consist of a circuit board, a controller chip, a cache chip, and flash memory chips. The controller chip, cache chip, and flash memory chips are all mounted on the circuit board. The flash memory chips store data, the controller chip manages the data load across the various flash memory chips and acts as a data transfer intermediary, and the cache chip assists the controller chip in data processing. The cache chip typically uses Dynamic Random Access Memory (DRAM), while the flash memory chips typically use NAND flash memory.

[0042] SSDs may accumulate static electricity on their circuit boards due to friction, contact, or induction, leading to electrostatic discharge (ESD). The wideband, high-voltage electromagnetic interference generated by ESD can interfere with the SSD's electronic components, causing data loss or failure. Furthermore, ESD can generate high voltages within electronic components; if this voltage exceeds the component's withstand voltage, it can cause breakdown. Therefore, SSDs typically undergo ESD immunity testing before leaving the factory to assess their stability and reliability in ESD environments. This testing usually involves using an electrostatic discharge gun to discharge at designated test points on the SSD, such as the screws, to determine the maximum discharge voltage the SSD can withstand while maintaining normal function. Typically, SSDs can withstand a maximum discharge voltage of 6kV. Exceeding 6kV can damage, cause data loss, or lead to failure of electronic components such as controller chips, cache chips, and flash memory chips mounted on the SSD's circuit board. In some special scenarios, SSDs need to withstand ESD voltages greater than 6kV, even reaching 8kV.

[0043] Based on this, in order to at least solve some of the above-mentioned problems, the embodiments of this application provide a semiconductor packaging structure. Figures 1 to 4 Schematic diagrams of the semiconductor packaging structure in different embodiments of this application are shown. Figures 1 to 4 As shown, the semiconductor package structure includes a conductive layer 100, electronic components 500, and electrostatic discharge devices 200. The conductive layer 100 includes a first portion 110 and a second portion 120, which are spaced apart along a first direction. The electronic components 500 are located on at least one side of the first portion 110 along a second direction and are connected to the first portion 110. The electrostatic discharge devices 200 are connected to the second portion 120. The first and second directions intersect.

[0044] During electrostatic testing, an electrostatic discharge voltage can be applied to the electrostatic lead 200 using an electrostatic gun. However, since the electronic component 500 is mounted on the first part 110 of the circuit board in this embodiment, and the electrostatic lead 200 is connected to the second part 120 of the circuit board, and the first part 110 and the second part 120 are spaced apart, electrostatic charge cannot be directly conducted between the first part 110 and the second part 120. The electrostatic lead 200 provides a low-impedance current path, so most or all of the electrostatic charge conducted to the second part 120 is guided to other external devices through the electrostatic lead 200. Only a small portion or no electrostatic charge is conducted to the first part 110 through the second part 120. Therefore, the electrostatic charge has little effect on the electronic component 500 mounted on the first part 110. As can be seen, by arranging the first portion 110 and the second portion 120 of the conductive layer 100 at intervals, and mounting the electronic component 500 and the electrostatic discharge device 200 to the first portion 110 and the second portion 120 respectively, the electrostatic charge conducted through the second portion 120 to the first portion 110 can be reduced, thereby reducing the interference and damage of electrostatic charge to the electronic component 500. This improves the electrostatic discharge immunity of the entire semiconductor packaging structure, enabling the semiconductor packaging structure to withstand a larger electrostatic discharge voltage.

[0045] It should be noted that "the first direction intersects with the second direction" in the above text can generally be understood as meaning that the first direction and the second direction have an angle between them, such as the first direction and the second direction being perpendicular or approximately perpendicular to each other. For example, ... Figure 1 As shown, in the embodiments of this application, the first direction can be parallel to the paper surface, and the second direction can be perpendicular to the paper surface. For example, the first direction is parallel to the length or width direction of the conductive layer 100, and the second direction is parallel to the thickness direction of the conductive layer 100. The material of the conductive layer 100 can include, but is not limited to, at least one of metals such as copper, gold, aluminum, chromium, tin, nickel, titanium, zinc, and metal alloys such as tin-lead alloys.

[0046] Furthermore, the first portion 110 and the second portion 120 of the conductive layer 100 can be spaced apart in various ways. For example... Figures 1 to 3 As shown, the first portion 110 partially surrounds the second portion 120. With a fixed area of ​​the conductive layer 100, this arrangement allows the first portion 110 to have a relatively large area, enabling the installation of more or larger electronic components 500 within it. For example, as... Figure 1As shown, the edge of the first part 110 forms a semi-circular opening, and the shape of the second part 120 conforms to the shape of this opening. In other words, the second part 120 as a whole can also be semi-circular. The second part 120 is located inside the opening of the first part 110, and the arcuate edge of the opening is opposite to the arcuate edge of the second part 120. For example, as... Figure 3 As shown, the edge of the first part 110 forms a rectangular opening, and the second part 120 can also be rectangular in shape and located within the opening of the first part 110. It should be noted that the opening of the first part 110 can be semi-circular, rectangular, square, triangular, or other shapes; this application does not limit this. In some other embodiments, the second part 120 can also be located on one side of the first part 110 along the first direction, for example, the second part 120 is located to the left or right of the first part 110. Furthermore, in some other embodiments, to avoid obstructing the movement of certain electronic components 500 mounted on the first part 110, such as... Figure 4 The second portion 120 shown may include a first sub-portion 121 and a second sub-portion 122. The first sub-portion 121 is partially embedded in the first portion 110 and is connected to the electrostatic discharge member 200. The second sub-portion 122 is connected to the first sub-portion 121 and extends in a first direction away from the first sub-portion 121. The second sub-portion 122 is completely embedded in the first portion 110. As an example, the edge of the first portion 110 may have an opening, and the interior of the first portion 110 may have a channel extending to the opening. The first sub-portion 121 is at least partially located in the opening, and the second sub-portion 122 is located in the channel.

[0047] In some embodiments, an isolation gap exists between the first portion 110 and the second portion 120, extending along the second portion 120 toward the edge of the first portion 110. The width of the isolation gap may be the same or different at various points along its extension direction. In other embodiments, to further reduce electrostatic charge conducted through the second portion 120 to the first portion 110 and to minimize the impact of electrostatic charge on the electronic components 500 mounted on the first portion 110, an isolation strip 400 is also provided between the first portion 110 and the second portion 120. The isolation strip 400 extends along the second portion 120 toward the edge of the first portion 110; in other words, the first portion 110 and the second portion 120 are isolated by the isolation strip 400. The material of the isolation strip 400 may include, but is not limited to, dielectric materials or other materials with good insulating properties. The width of the isolation strip 400 may be the same or different at various points along its extension direction. As an example, the two ends of the isolation strip 400 are located on the same side of the first portion 110 along a first direction. Because the isolation strip 400 extends along the second portion 120 toward the edge of the first portion 110, such that when both ends of the isolation strip 400 are located on the same side of the first portion 110 along the first direction, the isolation strip 400 partially surrounds the second portion 120. For example, as Figures 1 to 4 As shown, the first direction can be considered as parallel to the plane of the paper. Both ends of the isolation strip 400 are located on the left side of the first portion 110 along the first direction. In other words, one end of the isolation strip 400 extends to the left edge of the first portion 110, and the other end of the isolation strip 400 also extends to the left edge of the first portion 110. Alternatively, both ends of the isolation strip 400 may also be located on the right, upper, or lower side of the first portion 110 along the first direction. In other embodiments, the two ends of the isolation strip 400 may be located on different sides of the first portion 110 along the first direction. For example, one end of the isolation strip 400 extends to the left edge of the first portion 110, and the other end extends to the lower edge of the first portion 110. Alternatively, one end of the isolation strip 400 extends to the upper edge of the first portion 110, and the other end extends to the lower edge of the first portion 110.

[0048] In some embodiments, the semiconductor package structure further includes an electrostatic discharge (ESD) protection element 300, one end of which is connected to the first portion 110 and the other end of which is connected to the second portion 120. The ESD protection element 300 can suppress the propagation of electrostatic charges in the conductive layer 100, clamp electrostatic voltage, and / or limit electrostatic current to prevent damage to the electronic components 500 mounted on the first portion 110 due to electrostatic discharge. The ESD protection element 300 may include, but is not limited to, at least one of a capacitor 320, a resistor 310, a clamping diode, a Zener diode, and a transient voltage suppressor. As an example, the ESD protection element 300 may include a resistor 310 and a capacitor 320 connected in parallel between the first portion 110 and the second portion 120. In other words, one end of the resistor 310 is connected to the first portion 110 and the other end of the resistor 310 is connected to the second portion 120, and one end of the capacitor 320 is connected to the first portion 110 and the other end of the capacitor 320 is connected to the second portion 120. Resistor 310 and capacitor 320 play different roles in electrostatic discharge (ESD) protection. Capacitor 320 absorbs ESD charge and smooths voltage changes, while resistor 310 limits the magnitude of ESD current conducted from the second part 120 to the first part 110, preventing sudden ESD current surges from impacting electronic components 500. Therefore, connecting capacitor 320 and resistor 310 in parallel between the first part 110 and the second part 120 improves the ESD immunity of the entire semiconductor package structure, enabling it to withstand higher ESD voltages. As an example, the first part 110 has a first and second pad near the edge of the second part 120, and the second part 120 has a third and fourth pad near the edge of the first part 110. The two ends of resistor 310 are soldered to the first and third pads, respectively, and the two ends of capacitor 320 are soldered to the second and fourth pads, respectively. As an example, to enhance the ESD immunity of the ESD protection component 300, this embodiment uses a small capacitor and a large resistor. For example, capacitor 320 is a picofarad-level capacitor, and resistor 310 is a megohm-level resistor. For example, a 320-volt capacitor is a nanofarad-level capacitor, and a 310-volt resistor is a megohm-level resistor.

[0049] In some embodiments, the first end of the electrostatic discharge element 200 contacts the surface of the second portion 120, and the second end of the electrostatic discharge element 200 penetrates through the second portion 120. As its name suggests, the electrostatic discharge element 200 is a component used to discharge static electricity and is conductive. The first end of the electrostatic discharge element 200 contacts the surface of the second portion 120, and the second end of the electrostatic discharge element 200, after penetrating the second portion 120, can be connected to other external devices or grounded. As an example, the electrostatic discharge element 200 is detachably connected to the second portion 120, and the second portion 120 has a through hole 123 for the electrostatic discharge element 200 to pass through, with the second end of the electrostatic discharge element 200 passing through the through hole 123 and then connected to other external devices or grounded. Therefore, during electrostatic testing, an electrostatic discharge voltage can be applied to the first end of the electrostatic discharge element 200 using an electrostatic gun. Since the first end of the electrostatic discharge element 200 is in contact with the surface of the second part 120, and the first part 110 is spaced apart from the second part 120, the electrostatic discharge element 200 provides a low-impedance current path. Most or all of the electrostatic charge conducted to the second part 120 is then conducted to other external equipment or the ground through the second end of the electrostatic discharge element 200. Only a small portion or no electrostatic charge is conducted to the first part 110 through the second part 120. Thus, the electrostatic charge has little effect on the electronic components 500 mounted on the first part 110.

[0050] like Figure 1 As shown, the semiconductor packaging structure in this embodiment may further include a connector 130, which is located along a first direction on the side of the first portion 110 away from the second portion 120 and connected to the first portion 110. The connector 130 may include a plurality of gold fingers extending from the side of the first portion 110 away from the second portion 120 along the first direction away from the second portion 120. The plurality of gold fingers can be connected to different electronic components 500 through the conductive layer 100 to enable signal transmission between the electronic components 500 and external devices.

[0051] In some embodiments, the semiconductor package structure may include a plurality of conductive layers 100 stacked sequentially along a second direction and an insulating layer located between two adjacent conductive layers 100. As an example, at least one of the plurality of conductive layers 100 may serve as a ground layer (GND), which includes the first portion 110 mentioned above and a second portion 120 spaced apart from the first portion 110 along the first direction. At least one of the remaining conductive layers may serve as a signal layer, power layer, or conductor layer. The structure of the signal layer, power layer, or conductor layer may differ from the structure of the ground layer, and the signal layer, power layer, or conductor layer may be a single, continuous metal foil or alloy foil. The insulating layer may be made of insulating materials such as glass fiber or polyimide.

[0052] In some embodiments, the semiconductor packaging structure in this application may include, but is not limited to, a solid-state drive (SSD). Furthermore, the electronic component 500 may include a cache chip, a flash memory chip, or a control chip. The flash memory chip may be a non-volatile chip, such as a NAND chip, a PROM (Programmable Read-Only memory) chip, or a NOR chip; the cache chip may be a volatile chip, such as a DRAM (Dynamic Random Access Memory) chip or an SRAM (Static Random-Access Memory) chip. The control chip may be designed to operate in a high duty cycle environment and may be configured to control the operation of the cache chip and flash memory chip, such as read, erase, and program operations. The control chip may also be configured to manage various functions related to data stored in or to be stored in the cache chip or flash memory chip, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the control chip is further configured to process error correction codes (ECC) related to data read from or written to the cache chip or flash memory chip. The control chip can also perform any other appropriate functions, such as formatting cache chips or flash memory chips. The control chip can communicate with external devices according to specific communication protocols. For example, the control chip can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0053] In addition, such as Figure 5 As shown in the figure, this application also provides an electronic device, which includes a semiconductor package structure and a motherboard 600. The semiconductor package structure includes a conductive layer 100, electronic components 500, and an electrostatic discharge device 200. The conductive layer 100 includes a first portion 110 and a second portion 120, which are spaced apart along a first direction. The electronic components 500 are located on at least one side of the first portion 110 along a second direction and are connected to the first portion 110. The motherboard 600 is located on one side of the semiconductor package structure along the second direction. One end of the electrostatic discharge device 200 is connected to the second portion 120, and the other end of the electrostatic discharge device 200 is connected to the motherboard 600. The first direction and the second direction intersect.

[0054] During electrostatic testing, an electrostatic discharge voltage can be applied to the electrostatic lead-out component 200 using an electrostatic gun. Most or all of the electrostatic charge conducted to the second part 120 is guided to the motherboard 600 through the electrostatic lead-out component 200. Only a small portion or no electrostatic charge is conducted to the first part 110 through the second part 120. Thus, the electrostatic charge has little effect on the electronic components 500 installed in the first part 110. As can be seen, by arranging the first portion 110 and the second portion 120 of the conductive layer 100 at intervals, electronic components 500 and electrostatic discharge leads 200 are respectively installed on the first portion 110 and the second portion 120, and the end of the electrostatic discharge lead 200 away from the second portion 120 is connected to the motherboard 600. This not only guides most or all of the electrostatic charge to the motherboard 600, thereby reducing the electrostatic charge conducted to the first portion 110 through the second portion 120, reducing the interference and damage of electrostatic charge to electronic components 500, improving the electrostatic discharge immunity of the entire semiconductor package structure, and enabling the semiconductor package structure to withstand a larger electrostatic discharge voltage, but also fixes the semiconductor package structure to the motherboard 600 with the help of the electrostatic discharge lead 200.

[0055] It should be noted that the electronic device provided in the embodiments of this application may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a semiconductor package structure therein.

[0056] As an example, the first end of the electrostatic discharge member 200 contacts the surface of the second portion 120, and the second end of the electrostatic discharge member 200 penetrates the second portion 120 and is connected to the motherboard 600. For example, as Figure 1 and Figure 5 As shown, the second part 120 has a through hole 123, and the motherboard 600 has a mounting hole (not shown) corresponding to the through hole 123. The second end of the electrostatic discharge member 200 passes through the through hole 123 and connects with the mounting hole. To facilitate subsequent maintenance and replacement of the semiconductor package structure, the electrostatic discharge member 200 is detachably connected to the motherboard 600. For example, the mounting hole of the motherboard 600 can be a threaded hole, and the electrostatic discharge member 200 can include a screw that is threaded into the threaded hole. The head of the screw is the first end of the screw, and the end of the screw shank away from its head is the second end of the screw. The through hole 123 can be located at the edge of the second part 120 away from the first part 110, and the shape of the through hole 123 can be, but is not limited to, semi-circular. During installation, the screw shank is passed through the through hole 123 of the second part 120 and screwed into the threaded hole of the motherboard 600 until the head of the screw contacts the conductive layer 100.

[0057] The following section compares the electrostatic discharge immunity tests conducted on the electronic device provided in this application and existing electronic devices. The test results are shown in Table 1 below:

[0058] Table 1. Electrostatic discharge interference test results of the electronic device of this application and existing electronic devices.

[0059]

[0060]

[0061] Wherein, ESD_C represents the voltage across capacitor 320, SD_R represents the voltage across resistor 310, CLK_SOC represents the noise voltage of the system clock, RST_SOC represents the noise voltage of the system reset chip, LDO_SOC represents the noise voltage of the system low-dropout linear regulator, RST_Finger represents the noise voltage of the gold finger of the corresponding reset chip, LDO_Finger represents the noise voltage of the gold finger of the corresponding low-dropout linear regulator, CLK_Finger represents the noise voltage of the gold finger of the corresponding system clock, E-Field represents the electric field strength at the control chip, and H-Field represents the magnetic field strength at the control chip.

[0062] As shown in Table 1, compared to existing electronic devices, the current-carrying capacity of the electrostatic discharge device 200 in this embodiment of the application is improved by 29%, the system noise voltage (CLK_SOC, RST_SOC, LDO_SOC) is reduced by at least 29%, the gold finger noise voltage (CLK_Finger, RST_Finger, LDO_Finger) is reduced by at least 41%, the electric field strength at the control chip is reduced by 3.2%, and the magnetic field strength at the control chip is reduced by 21%. It is evident that the electrostatic discharge immunity of the entire semiconductor package structure in this embodiment of the application is significantly improved, and the semiconductor package structure can withstand greater electrostatic discharge voltages.

[0063] like Figure 6 As shown, this application also provides a method for fabricating a semiconductor packaging structure, the method 1000 comprising:

[0064] S100: Forming a conductive layer 100, the conductive layer 100 including a first portion 110 and a second portion 120 spaced apart from the first portion 110 along a first direction (see...). Figure 1 );

[0065] S200, an electronic component 500 connected to the first portion 110 is formed on at least one side of the first portion 110 along the second direction (see S200). Figure 2 );

[0066] S300, connect the static discharge member 200 to the second part 120; wherein the first direction intersects the second direction.

[0067] As an example, the conductive layer 100 can be formed by: forming an initial conductive layer (not shown); forming an isolation trench on the initial conductive layer to divide the initial conductive layer into a first portion 110 and a second portion 120. Furthermore, to further reduce electrostatic charge conducted through the second portion 120 to the first portion 110 and to reduce the impact of electrostatic charge on the electronic components 500 mounted on the first portion 110, an isolation strip 400 can be formed by filling the isolation trench with a dielectric material after it has been formed.

[0068] In some embodiments, the fabrication method may further include connecting one end of the electrostatic discharge (ESD) protection element 300 to the first portion 110 and the other end of the ESD protection element 300 to the second portion 120. As an example, the ESD protection element 300 may include a resistor 310 and a capacitor 320. The first portion 110 has a first pad and a second pad near its edge adjacent to the second portion 120, and the second portion 120 has a third pad and a fourth pad near its edge adjacent to the first portion 110. When mounting the ESD protection element 300, one end of the resistor 310 may be soldered to the first pad, and the other end of the resistor 310 may be soldered to the third pad; one end of the capacitor 320 may be soldered to the second pad, and the other end of the capacitor 320 may be soldered to the fourth pad.

[0069] It should be understood that the various processes shown above can be used to reorder, add, or delete steps. As an example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application is achieved; no limitation is imposed herein. The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor packaging structure, characterized in that, include: A conductive layer includes a first portion and a second portion spaced apart from the first portion along a first direction; Electronic components, located along a second direction on at least one side of the first portion and connected to the first portion; and An electrostatic discharge element is connected to the second part; Wherein, the first direction intersects with the second direction.

2. The semiconductor packaging structure according to claim 1, wherein, The semiconductor packaging structure further includes: An electrostatic protection element, one end of which is connected to the first part and the other end of which is connected to the second part.

3. The semiconductor packaging structure according to claim 2, wherein, The electrostatic protection element includes: A capacitor, one end of which is connected to the first part, and the other end of which is connected to the second part; and The resistor has one end connected to the first part and the other end connected to the second part.

4. The semiconductor packaging structure according to claim 3, wherein, The capacitor is a picofarad-level capacitor or a nanofarad-level capacitor.

5. The semiconductor packaging structure according to claim 3, wherein, The resistor is a megaohm-level resistor.

6. The semiconductor packaging structure according to claim 1, wherein, The first part partially surrounds the second part.

7. The semiconductor packaging structure according to claim 1, wherein, The second part includes: A first sub-part is connected to the electrostatic lead-out member, and the first sub-part is partially embedded in the first part; and The second sub-part is connected to the first sub-part and extends along the first direction away from the first sub-part, and the second sub-part is completely embedded in the first part.

8. The semiconductor packaging structure according to any one of claims 1 to 7, wherein, The conductive layer further includes an insulating strip located between the first portion and the second portion and extending along the edge of the second portion toward the first portion.

9. The semiconductor packaging structure according to claim 8, wherein, The two ends of the isolation strip are located on the same side of the first part along the first direction.

10. The semiconductor packaging structure according to any one of claims 1 to 7, wherein, The first end of the electrostatic lead-out element is in contact with the surface of the second part, and the second end penetrates through the second part.

11. The semiconductor packaging structure according to claim 10, wherein, The second part has a through hole through which the second end of the electrostatic lead-out member passes.

12. The semiconductor packaging structure according to any one of claims 1 to 7, wherein, The semiconductor package structure further includes a connector located along the first direction on the side of the first portion away from the second portion and connected to the first portion.

13. The semiconductor packaging structure according to any one of claims 1 to 7, wherein, The electronic components include cache chips, flash memory chips, or control chips.

14. An electronic device, characterized in that, include: Semiconductor packaging structures, including: A conductive layer includes a first portion and a second portion spaced apart from the first portion along a first direction; Electronic components, located on at least one side of the second portion along the second direction and connected to the second portion; and An electrostatic discharge element is connected to the second part; A motherboard is located on one side of the semiconductor package structure along the second direction, and the end of the electrostatic discharge member away from the second part is connected to the motherboard. Wherein, the first direction intersects with the second direction.

15. The electronic device according to claim 14, wherein, The first end of the electrostatic discharge member contacts the surface of the second part, and the second end passes through the second part and is connected to the motherboard.

16. The electronic device according to claim 15, wherein, The second part has a through hole, the motherboard has a mounting hole corresponding to the through hole, and the second end of the electrostatic discharge member passes through the through hole and is connected to the mounting hole.

17. A method for fabricating a semiconductor packaging structure, characterized in that, include: A conductive layer is formed, the conductive layer comprising a first portion and a second portion spaced apart from the first portion along a first direction; An electronic component connected to the first part is formed on at least one side of the first part along the second direction; as well as Connect the electrostatic discharge device to the second part; Wherein, the first direction intersects with the second direction.

18. The method for fabricating a semiconductor packaging structure according to claim 17, wherein, Forming a conductive layer includes: Forming an initial conductive layer; and Isolation trenches are formed on the initial conductive layer to divide the initial conductive layer into the first portion and the second portion.

19. The method for fabricating a semiconductor packaging structure according to claim 18, wherein, The preparation method further includes: The isolation trench is filled with a medium material to form an isolation strip.

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