Anti-straight-through driving control circuit and method

Abstract

The invention discloses an anti-straight-through driving control circuit and method, and the method comprises the steps: dividing a pulse width modulation control signal transmitted by a digital signal processor into an upper bridge arm pulse width modulation control signal and a lower bridge arm pulse width modulation control signal, and carrying out the first-stage power amplification processing; obtaining an upper bridge arm pulse width modulation control signal and a lower bridge arm pulse width modulation control signal after first-stage power amplification; if no straight-through fault exists between the upper bridge arm pulse width modulation control signal and the lower bridge arm pulse width modulation control signal after the first-stage power amplification, the first-stage power amplification is carried out on the upper bridge arm pulse width modulation control signal and the lower bridge arm pulse width modulation control signal; and performing second-stage power amplification on the upper bridge arm pulse width modulation control signal and the lower bridge arm pulse width modulation control signal after the first-stage power amplification so as to drive the connection and disconnection of the upper bridge arm and the lower bridge arm of the IGBT inverter bridge, otherwise, invalidating the enable signal sent by the digital signal processor. And simultaneous conduction of upper and lower tubes of the same bridge arm of the IGBT inverter bridge is avoided.

Description

Technical Field

[0001] This invention relates to the field of drive circuit control, specifically to an anti-shoo-through drive control circuit and method. Background Technology

[0002] Inverter drive circuits are a core component of power electronic systems. Their main function is to precisely and reliably control the switching of power switching devices (such as IGBTs, MOSFETs, and SiCs) to efficiently and effectively convert direct current (DC) into alternating current (AC). They are widely used in motor drives, photovoltaic inverters, and uninterruptible power supplies (UPS). With the development of power electronics technology and the increase in the switching frequency of power devices, the reliability of drive circuits has become particularly important, directly affecting product stability. Therefore, higher requirements are placed on the control precision and protection response speed of drive circuits.

[0003] Shoot-through in the upper and lower arms of an IGBT is one of the most dangerous and destructive faults in power electronic converters (such as inverters, motor drivers, UPS, etc.). When the upper and lower IGBTs of the same arm conduct abnormally simultaneously, the DC bus voltage forms a catastrophic short-circuit current through the extremely low impedance loop (only the on-resistance of the two IGBTs), causing the IGBT chip temperature to spike rapidly within microseconds, far exceeding its limit and resulting in thermal damage. This also damages the drive circuit and surrounding components. Existing technologies to prevent shoot-through employ measures such as PWM control signals with dead time, fast-response deactivation circuits (DESAT), and optimized PCB layout. However, these measures are all protective measures implemented after shoot-through has occurred. This invention uses external logic circuitry to shut down the output of the drive chip when a shoot-through occurs, thereby preventing IGBT shoot-through and improving product reliability. Summary of the Invention

[0004] The purpose of this invention is to provide both a shoot-through prevention control circuit and a shoot-through prevention control method. This circuit and method can ensure that when the DSP malfunctions and the upper and lower bridge arm control signals simultaneously output high levels, the abnormal signal is not transmitted to the IGBT, thus preventing IGBT shoot-through damage. Similarly, when the buffer chip malfunctions and the upper and lower bridge arm control signals simultaneously output high levels, the abnormal signal is also prevented from being transmitted to the IGBT, thus preventing IGBT shoot-through damage.

[0005] To achieve this objective, the present invention provides an anti-short-through drive control circuit, which includes: The signal processing circuit is used to receive the pulse width modulation control signal sent by the digital signal processor, divide the pulse width modulation control signal into the upper bridge arm pulse width modulation control signal and the lower bridge arm pulse width modulation control signal, and perform the first stage power amplification processing on the upper bridge arm pulse width modulation control signal and the lower bridge arm pulse width modulation control signal to obtain the first stage power amplified upper bridge arm pulse width modulation control signal and the lower bridge arm pulse width modulation control signal. The drive circuit is used to receive the enable signal from the digital signal processor. When there is no shoot-through fault between the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal of the IGBT, the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal are amplified by the second stage to obtain the upper arm drive signal and the lower arm drive signal. The upper arm drive signal and the lower arm drive signal drive the upper arm and the lower arm of the IGBT inverter bridge to turn on and off. The fault control circuit is used to invalidate the enable signal issued by the digital signal processor when there is a shoot-through fault between the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal, so as to prevent the upper and lower transistors of the same arm of the IGBT inverter bridge from conducting simultaneously.

[0006] Furthermore, the signal processing circuit includes a digital signal processor (DSP) and a buffer. The DSP is used to generate complementary pulse width modulation (PWM) control signals, and the buffer is used to perform a first-stage power amplification on the PWM control signals.

[0007] Furthermore, the buffer includes a first buffer and a second buffer. The first buffer and the second buffer split the pulse width modulation control signal into an upper bridge arm pulse width modulation control signal and a lower bridge arm pulse width modulation control signal. The first buffer outputs the upper bridge arm pulse width modulation control signal after a first-stage power amplification, and the second buffer outputs the lower bridge arm pulse width modulation control signal after a first-stage power amplification.

[0008] Furthermore, the upper bridge arm pulse width modulation control signal includes a first upper bridge arm pulse width modulation control signal, a second upper bridge arm pulse width modulation control signal, and a third upper bridge arm pulse width modulation control signal; the lower bridge arm pulse width modulation control signal includes a first lower bridge arm pulse width modulation control signal, a second lower bridge arm pulse width modulation control signal, and a third lower bridge arm pulse width modulation control signal. The first upper bridge arm pulse width modulation control signal and the first lower bridge arm pulse width modulation control signal are a set of complementary signals; the second upper bridge arm pulse width modulation control signal and the second lower bridge arm pulse width modulation control signal are a set of complementary signals; and the third upper bridge arm pulse width modulation control signal and the third lower bridge arm pulse width modulation control signal are a set of complementary signals.

[0009] Furthermore, the fault control circuit includes six transistors arranged in an inverter bridge configuration. Three transistors on the upper arm of the inverter bridge receive pulse width modulation (PWM) control signals from the first buffer (after amplification by the first stage), namely, the first upper arm PWM control signal, the second upper arm PWM control signal, and the third upper arm PWM control signal. Three transistors on the lower arm of the inverter bridge receive pulse width modulation (PWM) control signals from the second buffer (after amplification by the first stage), namely, the first lower arm PWM control signal, the second lower arm PWM control signal, and the third lower arm PWM control signal. Two transistors receiving a set of complementary signals form a group, and one end of each group of transistors is grounded.

[0010] Furthermore, when none of the three complementary signals have a shoot-through fault, the enable signal issued by the digital signal processor (DSP) is transmitted to the driver isolation chip, enabling the driver isolation chip to work; when at least one of the three complementary signals has a shoot-through fault, the transistor receiving the complementary signal with the shoot-through fault forces the enable signal issued by the DSP to ground, causing the isolation driver chip to not work.

[0011] Furthermore, the driving circuit includes an isolated driving chip. After receiving the enable signal from the digital signal processor (DSP), the isolated driving chip amplifies the pulse width modulation (PWM) control signals of the first upper bridge arm, the second upper bridge arm, and the third upper bridge arm (after amplification by the first stage) and the pulse width modulation (PWM) control signals of the first lower bridge arm, the second lower bridge arm, and the third lower bridge arm (after amplification by the first stage) from the transistor inverter bridge in a second stage to obtain the corresponding IGBT driving signals to drive the IGBTs in the IGBT inverter bridge to turn on and off.

[0012] Furthermore, the number of isolated driver chips is six. The six isolated driver chips respectively receive the first upper bridge arm pulse width modulation control signal, the second upper bridge arm pulse width modulation control signal, and the third upper bridge arm pulse width modulation control signal after the first stage of power amplification output from the first buffer, and the first lower bridge arm pulse width modulation control signal, the second lower bridge arm pulse width modulation control signal, and the third lower bridge arm pulse width modulation control signal after the first stage of power amplification output from the second buffer, and perform a second stage of power amplification on each pulse width modulation control signal.

[0013] Furthermore, a method for preventing shoot-through drive control based on the aforementioned anti-shoot-through drive control circuit includes: The system receives the pulse width modulation control signal from the digital signal processor, divides the pulse width modulation control signal into an upper bridge arm pulse width modulation control signal and a lower bridge arm pulse width modulation control signal, and performs a first-stage power amplification on the upper and lower bridge arm pulse width modulation control signals to obtain the first-stage power amplified upper and lower bridge arm pulse width modulation control signals. The system receives the enable signal from the digital signal processor. When there is no shoot-through fault between the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal of the IGBT, the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal are amplified by a second stage to obtain the upper arm drive signal and the lower arm drive signal. The upper arm drive signal and the lower arm drive signal are used to drive the upper arm and the lower arm of the IGBT inverter bridge to turn on and off. When there is a shoot-through fault between the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal, the enable signal issued by the digital signal processor will be invalidated to prevent the upper and lower transistors of the same arm of the IGBT inverter bridge from conducting simultaneously.

[0014] The beneficial effects of this invention: Existing technologies rely on passive protection measures such as dead-time settings and desaturation protection, which cannot completely prevent shoot-through of the upper and lower bridge arms of the IGBT caused by DSP anomalies or buffer chip failures. This invention uses an anti-shoot-through drive control circuit to monitor the states of three complementary signal sets: UH / UL, VH / VL, and WH / WL. When any pair of signals is abnormally high at the same time (e.g., both UH and UL are high), the corresponding NPN transistors (such as Q1 and Q2) immediately conduct, forcibly pulling the enable signal (ENA) of the driver chip low to ground potential, thereby blocking the output of all driver chips (U1~U6) within nanoseconds. This invention achieves hard isolation from the source of the signal transmission path, completely blocking the possibility of abnormal control signals being transmitted to the IGBT gate. It prevents shoot-through short circuits of the upper and lower bridge arms caused by control signal disorder, significantly reduces the risk of IGBT damage due to instantaneous thermal overload, and greatly improves the reliability and system stability of the power electronic converter. Attached Figure Description

[0015] Figure 1 This is a circuit diagram of an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the present invention; Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to represent selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Example 1 like Figure 2 As shown, an anti-short-through drive control circuit includes: The signal processing circuit is used to receive the pulse width modulation control signal sent by the digital signal processor, divide the pulse width modulation control signal into the upper bridge arm pulse width modulation control signal and the lower bridge arm pulse width modulation control signal, and perform the first stage power amplification processing on the upper bridge arm pulse width modulation control signal and the lower bridge arm pulse width modulation control signal to obtain the first stage power amplified upper bridge arm pulse width modulation control signal and the lower bridge arm pulse width modulation control signal. The drive circuit is used to receive the enable signal from the digital signal processor. When there is no shoot-through fault between the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal of the IGBT, the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal are amplified by the second stage to obtain the upper arm drive signal and the lower arm drive signal. The upper arm drive signal and the lower arm drive signal drive the upper arm and the lower arm of the IGBT inverter bridge to turn on and off. The fault control circuit is used to invalidate the enable signal issued by the digital signal processor when there is a shoot-through fault between the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal, so as to prevent the upper and lower transistors of the same arm of the IGBT inverter bridge from conducting simultaneously.

[0018] In some technical solutions, the signal processing circuit includes a digital signal processor (DSP) and a buffer. The DSP is used to generate complementary pulse width modulation (PWM) control signals, and the buffer is used to perform a first-stage power amplification on the PWM control signals.

[0019] In some technical solutions, the buffer includes a first buffer and a second buffer. The first buffer and the second buffer split the pulse width modulation control signal into an upper bridge arm pulse width modulation control signal and a lower bridge arm pulse width modulation control signal. The first buffer outputs the upper bridge arm pulse width modulation control signal after a first-stage power amplification, and the second buffer outputs the lower bridge arm pulse width modulation control signal after a first-stage power amplification.

[0020] The first and second buffers amplify the complementary six-channel pulse width modulation (PWM) control signals generated by the DSP, preventing crosstalk between the six signals and avoiding the risk of false triggering caused by high-frequency switching noise. This makes the single-channel PWM control signal clearer and more accurate. The complementary PWM control signals generated by the DSP, combined with the buffers for first-stage power amplification, incorporate a hardware dead time at the signal source via the DSP to ensure an absolute turn-off window during the switching of the upper and lower bridge arm PWM control signals, eliminating shoot-through risk. Since the DSP pins can only provide milliamp-level drive current, the IGBT gate capacitor requires an instantaneous injection of ampere-level current to drive it during high-speed switching. Direct driving would result in severe hysteresis at the edges of the PWM control signal, causing the IGBT to remain in the linear amplification region for an extended period, leading to severe overheating and potential failure. The buffers, with an output capability of tens of milliamps, provide first-stage power amplification to the PWM signal, sharpening the edges of the PWM control signal and ensuring precise synchronization of power device switching operations under high-frequency conditions, providing a clear and accurate input signal for the subsequent isolation driver chip.

[0021] In some technical solutions, the upper bridge arm pulse width modulation control signal includes a first upper bridge arm pulse width modulation control signal, a second upper bridge arm pulse width modulation control signal, and a third upper bridge arm pulse width modulation control signal; the lower bridge arm pulse width modulation control signal includes a first lower bridge arm pulse width modulation control signal, a second lower bridge arm pulse width modulation control signal, and a third lower bridge arm pulse width modulation control signal; the first upper bridge arm pulse width modulation control signal and the first lower bridge arm pulse width modulation control signal are a set of complementary signals; the second upper bridge arm pulse width modulation control signal and the second lower bridge arm pulse width modulation control signal are a set of complementary signals; and the third upper bridge arm pulse width modulation control signal and the third lower bridge arm pulse width modulation control signal are a set of complementary signals.

[0022] Complementary signals are a set of signals generated by the DSP that have a dead time. This set of complementary signals controls the upper and lower transistors of the same arm of the IGBT inverter bridge. These complementary signals cannot simultaneously be high or low. If they are both high or low, it indicates a shoot-through fault within this set. The upper and lower transistors of the same arm of the IGBT inverter bridge controlled by this set of complementary signals will conduct simultaneously, causing irreversible damage to the IGBT drive circuit.

[0023] In some technical solutions, the fault control circuit includes six transistors arranged in an inverter bridge configuration. Three transistors on the upper arm of the inverter bridge receive pulse width modulation (PWM) control signals from the first buffer (after amplification by the first stage), namely, the first upper arm PWM control signal, the second upper arm PWM control signal, and the third upper arm PWM control signal. Three transistors on the lower arm of the inverter bridge receive pulse width modulation (PWM) control signals from the second buffer (after amplification by the first stage), namely, the first lower arm PWM control signal, the second lower arm PWM control signal, and the third lower arm PWM control signal. Two transistors receiving a set of complementary signals form a group, and one end of each group of transistors is grounded.

[0024] In some embodiments, the six transistors are arranged in the form of an inverter bridge. The three transistors in the upper arm of the inverter bridge are connected one-to-one with the three transistors in the lower arm of the inverter bridge. The emitters of the three transistors in the lower arm of the inverter bridge are grounded. When one transistor in the upper arm of the inverter bridge and one transistor in the symmetrically connected lower arm of the inverter bridge are turned on at the same time, since the emitter of the transistor in the lower arm is grounded, the transistors in the upper arm of the inverter bridge that are turned on at the same time and the transistors in the symmetrically connected lower arm of the inverter bridge are directly grounded, thereby forcibly grounding the enable signal (ENA) issued by the DSP.

[0025] In some technical solutions, when none of the three sets of complementary signals have a shoot-through fault, the enable signal issued by the processor DSP is transmitted to the driver isolation chip, enabling the driver isolation chip to work; when at least one of the three sets of complementary signals has a shoot-through fault, the transistor receiving the complementary signal with the shoot-through fault forces the enable signal issued by the digital signal processor DSP to ground, causing the isolation driver chip to not work.

[0026] When a group of transistors receives a set of complementary high-level signals, because one end of the transistors is grounded, the high-level signals are pulled low to 0. The output of the transistors is connected to the ENA pin of the driver isolation chip. When the high-level signals received by the transistors are pulled low to 0, ENA is pulled low to 0, and the driver isolation chip does not work.

[0027] In some technical solutions, the driving circuit includes an isolated driving chip. After receiving the enable signal from the digital signal processor (DSP), the isolated driving chip amplifies the pulse width modulation (PWM) control signals of the first upper bridge arm, the second upper bridge arm, and the third upper bridge arm (after amplification by the first stage) and the pulse width modulation (PWM) control signals of the first lower bridge arm, the second lower bridge arm, and the third lower bridge arm (after amplification by the first stage) from the transistor inverter bridge in a second stage to obtain the corresponding IGBT driving signals to drive the IGBTs in the IGBT inverter bridge to turn on and off.

[0028] The pulse width modulation (PWM) control signals of the first, second, and third upper bridge arms (after first-stage power amplification), and the pulse width modulation (PWM) control signals of the first, second, and third lower bridge arms (after first-stage power amplification), are then subjected to a second-stage power amplification to obtain the following drive signals: first upper bridge arm drive signal, second upper bridge arm drive signal, third upper bridge arm drive signal, first lower bridge arm drive signal, second lower bridge arm drive signal, and third lower bridge arm pulse drive signal. Each drive signal then drives the individual IGBT in the IGBT inverter bridge to turn on and off.

[0029] The isolated driver chip is used to perform a second-stage power amplification on the six pulse width modulation control signals after the first-stage power amplification of the buffer, so that the pulse width modulation control signals reach the drive control current of the IGBT, driving the IGBT to turn on and off.

[0030] In some technical solutions, the number of isolated driver chips is six. The six isolated driver chips respectively receive the pulse width modulation control signals of the first upper bridge arm, the second upper bridge arm, and the third upper bridge arm after being amplified by the first stage of power output from the first buffer, and the pulse width modulation control signals of the first lower bridge arm, the second lower bridge arm, and the third lower bridge arm after being amplified by the first stage of power output from the second buffer. Each pulse width modulation control signal is then amplified by the second stage of power output.

[0031] The six pulse width modulation (PWM) control signals are directly driven to turn on and off the IGBT inverter bridge after being amplified by the second stage of power amplification. The PWM control signals of the first upper bridge arm, the second upper bridge arm, the third upper bridge arm, the first lower bridge arm, the second lower bridge arm, and the third lower bridge arm, which are after being amplified by the first stage of power amplification, are each processed by an isolated driver chip for a second stage of power amplification. This ensures that the driving path of each IGBT is independent and blocks the risk of crosstalk between the multiple PWM control signals.

[0032] When any pair of complementary upper and lower bridge arm pulse width modulation control signals are simultaneously high-level abnormal signal pairs, the transistor receiving the abnormal signal pair is forced to ground, forcibly pulling the enable signal (ENA) issued by the DSP to ground low to 0V, thereby blocking the transmission of the shoot-through fault signal to the IGBT through hardware. The hardware-level shoot-through fault blocking mechanism based on signal logic detection of the driver isolation chip not only eliminates the risk of bridge arm shoot-through failure caused by DSP program abnormalities or buffer failures from the source, but also controls the IGBT through independent drive channels to ensure that the pulse width modulation control signals between non-faulty IGBTs do not affect each other.

[0033] Example 2 Figure 1The circuit diagram for this embodiment of the invention is shown below. U1 and U2 are buffers. The DSP sends six PWM control signals to the 1A, 2A, and 3A pins of buffers U1 and U2. U1 and U2 output signals UH, VH, WH and UL, VL, WL respectively. Buffers U1 and U2 perform a first-stage power amplification on the six PWM control signals to ensure their accuracy. UH (first upper bridge arm pulse width modulation control signal) and UL (first lower bridge arm pulse width modulation control signal), VH (second upper bridge arm pulse width modulation control signal) and VL (second lower bridge arm pulse width modulation control signal), WH (third upper bridge arm pulse width modulation control signal) and WL (third lower bridge arm pulse width modulation control signal) are complementary signals. There is a time dead zone between the complementary signals sent by the DSP. That is, when UH is high, UL is low. Similarly, when VH and WH are high, VL and WL are low. Q1, Q2, Q3, Q4, Q5, and Q6 are NPN transistors. UH, VH, and WH control the on / off states of Q1, Q3, and Q5, respectively. UL, VL, and WL control the on / off states of Q2, Q4, and Q6, respectively. Q1, Q3, and Q5 form the upper arm of the transistor inverter bridge, while Q2, Q4, and Q6 form the lower arm. The emitters of Q2, Q4, and Q6 are grounded. U3 to U8 are six isolated driver chips. One end of each isolated driver chip U3 to U8 is connected to Q1 to Q6 respectively. One end is connected in a one-to-one correspondence with the other end, and the other end is connected in a one-to-one correspondence with the six IGBTs in the IGBT inverter bridge. The function of the isolated driver chip is to perform a second-stage power amplification on the UH, VH, WH, UL, VL, WL signals output from buffers U1 and U2, directly driving the IGBT inverter bridge to turn on and off. ENA is the enable signal issued by the DSP, which controls the working state of driver chips U3~U8. Under normal operating conditions, when ENA is high, U3~U8 are working; when ENA is pulled low, U3~U8 are not working. The circuit working principle is as follows: When UH, VH, WH are high level and UL, VL, WL are low level, Q1, Q3, Q5 are turned on, Q2, Q4, Q6 are not turned on, ENA is high level, and U3~U8 receive UH, VH, WH, UL, VL, WL control signals to control the IGBT to turn on and off. When UH, VH, and WH are low, and UL, VL, and WL are high, Q1, Q3, and Q5 are not conducting, while Q2, Q4, and Q6 are conducting. ENA is high, and U3~U8 receive the control signals UH, VH, WH, UL, VL, and WL to control the IGBT's on / off state. When a DSP control malfunction or an output malfunction of any of the buffers in U1 or U2 causes at least one pair of complementary signals (UH and UL, VH and VL, WH and WL) to become non-complementary (a shoot-through fault exists), the enable signal from the DSP is grounded. This causes the isolated driver chip receiving the complementary signal with the shoot-through fault to stop working, preventing shoot-through in the IGBT inverter bridge. For example, when both UH and UL are high, UH and UL are used to drive Q1 and Q2 to conduct. Q1 and Q2 are grounded momentarily upon conduction. After Q1 and Q2 are grounded, the enable signal ENA is pulled to the GND pin. U3~U8 do not work, and the high-level UH and UL signals cannot be output to the IGBT through U3 and U4, preventing the IGBTs connected to U3 and U4 from being damaged due to common faults.

[0034] Example 3 A method for preventing shoot-through drive control based on the aforementioned anti-shoot-through drive control circuit, comprising: The system receives the pulse width modulation control signal from the digital signal processor, divides the pulse width modulation control signal into an upper bridge arm pulse width modulation control signal and a lower bridge arm pulse width modulation control signal, and performs a first-stage power amplification on the upper and lower bridge arm pulse width modulation control signals to obtain the first-stage power amplified upper and lower bridge arm pulse width modulation control signals. The system receives the enable signal from the digital signal processor. When there is no shoot-through fault between the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal of the IGBT, the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal are amplified by a second stage to obtain the upper arm drive signal and the lower arm drive signal. The upper arm drive signal and the lower arm drive signal are used to drive the upper arm and the lower arm of the IGBT inverter bridge to turn on and off. When there is a shoot-through fault between the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal, the enable signal issued by the digital signal processor will be invalidated to prevent the upper and lower transistors of the same arm of the IGBT inverter bridge from conducting simultaneously.

[0035] Example 4 The present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the method described in Embodiment 3.

[0036] The contents not described in detail in this specification are existing technologies known to those skilled in the art.

Claims

1. A cut-through drive control circuit, characterized in that, It includes: The signal processing circuit is used to receive the pulse width modulation control signal sent by the digital signal processor, divide the pulse width modulation control signal into the upper bridge arm pulse width modulation control signal and the lower bridge arm pulse width modulation control signal, and perform the first stage power amplification processing on the upper bridge arm pulse width modulation control signal and the lower bridge arm pulse width modulation control signal to obtain the first stage power amplified upper bridge arm pulse width modulation control signal and the lower bridge arm pulse width modulation control signal. The drive circuit is used to receive the enable signal from the digital signal processor. When there is no shoot-through fault between the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal of the IGBT, the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal are amplified by the second stage to obtain the upper arm drive signal and the lower arm drive signal. The upper arm drive signal and the lower arm drive signal drive the upper arm and the lower arm of the IGBT inverter bridge to turn on and off. The fault control circuit is used to invalidate the enable signal issued by the digital signal processor when there is a shoot-through fault between the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal, so as to prevent the upper and lower transistors of the same arm of the IGBT inverter bridge from conducting simultaneously.

2. The anti-straight-through drive control circuit according to claim 1, characterized in that: The signal processing circuit includes a digital signal processor (DSP) and a buffer. The DSP is used to generate complementary pulse width modulation (PWM) control signals, and the buffer is used to perform a first-stage power amplification on the PWM control signals.

3. The anti-straight-through drive control circuit according to claim 2, characterized in that: The buffer includes a first buffer and a second buffer. The first buffer and the second buffer split the pulse width modulation control signal into an upper bridge arm pulse width modulation control signal and a lower bridge arm pulse width modulation control signal. The first buffer outputs the upper bridge arm pulse width modulation control signal after the first stage of power amplification, and the second buffer outputs the lower bridge arm pulse width modulation control signal after the first stage of power amplification.

4. The anti-straight-through drive control circuit according to claim 3, characterized in that: The upper arm pulse width modulation (PWM) control signal includes a first upper arm PWM control signal, a second upper arm PWM control signal, and a third upper arm PWM control signal. The lower arm PWM control signal includes a first lower arm PWM control signal, a second lower arm PWM control signal, and a third lower arm PWM control signal. The first upper arm PWM control signal and the first lower arm PWM control signal are a set of complementary signals. The second upper arm PWM control signal and the second lower arm PWM control signal are a set of complementary signals. The third upper arm PWM control signal and the third lower arm PWM control signal are a set of complementary signals.

5. The anti-straight-through drive control circuit according to claim 4, characterized in that: The fault control circuit includes six transistors arranged in an inverter bridge configuration. Three transistors on the upper arm of the inverter bridge receive pulse width modulation (PWM) control signals from the first buffer (after amplification by the first stage), namely, the first upper arm PWM control signal, the second upper arm PWM control signal, and the third upper arm PWM control signal. Three transistors on the lower arm of the inverter bridge receive pulse width modulation (PWM) control signals from the second buffer (after amplification by the first stage), namely, the first lower arm PWM control signal, the second lower arm PWM control signal, and the third lower arm PWM control signal. Two transistors receiving a set of complementary signals form a group, and one end of each group of transistors is grounded.

6. The anti-straight-through drive control circuit according to claim 5, characterized in that: When none of the three complementary signals have a shoot-through fault, the enable signal sent by the digital signal processor (DSP) is transmitted to the driver isolation chip, enabling the driver isolation chip to work. When at least one of the three complementary signals has a shoot-through fault, the transistor receiving the complementary signal with the shoot-through fault forces the enable signal sent by the DSP to ground, causing the isolation driver chip to stop working.

7. The anti-straight-through drive control circuit according to claim 6, characterized in that: The driving circuit includes an isolated driving chip. After receiving the enable signal from the digital signal processor (DSP), the isolated driving chip amplifies the pulse width modulation (PWM) control signals of the first upper bridge arm, the second upper bridge arm, and the third upper bridge arm (after amplification by the first stage) and the pulse width modulation (PWM) control signals of the first lower bridge arm, the second lower bridge arm, and the third lower bridge arm (after amplification by the first stage) from the transistor inverter bridge in a second stage to obtain the corresponding IGBT driving signals to drive the IGBTs in the IGBT inverter bridge to turn on and off.

8. The anti-straight-through drive control circuit according to claim 7, characterized in that: The number of isolated driver chips is six. The six isolated driver chips respectively receive the first upper bridge arm pulse width modulation control signal, the second upper bridge arm pulse width modulation control signal, and the third upper bridge arm pulse width modulation control signal after the first stage of power amplification output from the first buffer, and the first lower bridge arm pulse width modulation control signal, the second lower bridge arm pulse width modulation control signal, and the third lower bridge arm pulse width modulation control signal after the first stage of power amplification output from the second buffer, and perform a second stage of power amplification on each pulse width modulation control signal.

9. A method for preventing direct-drive interference based on the anti-snap-through drive control circuit of claim 1, characterized in that, include: The system receives the pulse width modulation control signal from the digital signal processor, divides the pulse width modulation control signal into an upper bridge arm pulse width modulation control signal and a lower bridge arm pulse width modulation control signal, and performs a first-stage power amplification on the upper and lower bridge arm pulse width modulation control signals to obtain the first-stage power amplified upper and lower bridge arm pulse width modulation control signals. The system receives the enable signal from the digital signal processor. When there is no shoot-through fault between the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal of the IGBT, the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal are amplified by a second stage to obtain the upper arm drive signal and the lower arm drive signal. The upper arm drive signal and the lower arm drive signal are used to drive the upper arm and the lower arm of the IGBT inverter bridge to turn on and off. When there is a shoot-through fault between the upper arm pulse width modulation control signal and the lower arm pulse width modulation control signal, the enable signal issued by the digital signal processor will be invalidated to prevent the upper and lower transistors of the same arm of the IGBT inverter bridge from conducting simultaneously.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 9.

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