Mueller C unit circuit

Abstract

The invention discloses a Mueller C unit circuit. The Mueller C unit circuit comprises a first logic gate, a second logic gate, a third logic gate, a fourth logic gate and a fifth logic gate, the input end of the first logic gate is respectively connected with two input signals, the output end of the first logic gate is connected with the input end of the third logic gate, and the output end of the third logic gate is respectively connected with the input end of the second logic gate and the input end of the fifth logic gate; the input end of the second logic gate is respectively connected with two input signals, the output end of the second logic gate is respectively connected with the input end of the fourth logic gate, the input end of the first logic gate and the input end of the third logic gate, and the output end of the fourth logic gate is respectively connected with the input end of the fifth logic gate and the input end of the third logic gate. The Mueller C unit circuit is only composed of the logic gates, an MOS tube does not need to be adopted, and the implementation difficulty is low; and an EDA tool can be used for direct integration, multiple process libraries can be compatible at the same time, and process conversion is facilitated.

Description

Technical Field

[0001] This invention relates to the field of digital logic circuit technology, and in particular to a Mueller C-cell circuit. Background Technology

[0002] In the field of digital logic circuit technology, the Muller C-cell is an indispensable core unit in asynchronous circuit design. It combines the functions of a logic change device and a state-holding unit, playing a fundamental and crucial role in the construction and operation of asynchronous circuits. However, traditional Muller C-cells employ a fully custom design approach, where the correct implementation depends on precise adjustment of the dimensions of the NMOS and PMOS transistors within the delay unit. This design approach not only demands extremely high professional skills from designers but also makes the circuit design and debugging process complex and cumbersome, resulting in significant implementation difficulties for Muller C-cells. Furthermore, it limits their compatibility and flexibility across different process technologies, hindering efficient circuit design and widespread application. Summary of the Invention

[0003] The purpose of this invention is to provide a Mueller C-cell circuit. This Mueller C-cell circuit consists only of logic gates, eliminating the need for MOS transistors, thus simplifying its implementation. Furthermore, it can be directly synthesized using EDA tools, is compatible with multiple process libraries, and facilitates process conversion.

[0004] The technical solution of the present invention: a Mueller C-cell circuit, comprising a first logic gate, a second logic gate, a third logic gate, a fourth logic gate and a fifth logic gate; The first logic gate has two input signals connected to its input terminal, and its output terminal is connected to the input terminal of the third logic gate. The output terminal of the third logic gate is connected to the input terminal of the second logic gate and the input terminal of the fifth logic gate. The input terminal of the second logic gate is connected to two input signals respectively, and the output terminal of the second logic gate is connected to the input terminal of the fourth logic gate, the input terminal of the first logic gate and the input terminal of the third logic gate respectively. The output terminal of the fourth logic gate is connected to the input terminal of the fifth logic gate and the input terminal of the third logic gate respectively. The first logic gate, the second logic gate, the third logic gate, the fourth logic gate, and the fifth logic gate satisfy the following logical expression: ; ; ; ; ; in, and There are two input signals, This is the output of the first logic gate. This is the output of the second logic gate. The output of the third logic gate, The output of the fourth logic gate, This is the output of the fifth logic gate.

[0005] In the above-mentioned Mueller C-cell circuit, the first logic gate is a three-input NAND gate; The first and second input terminals of the three-input NAND gate are respectively connected to two input signals. The output terminal of the second logic gate is connected to the third input terminal of the three-input NAND gate, and the output terminal of the three-input NAND gate is connected to the input terminal of the third logic gate.

[0006] In the aforementioned Mueller C-cell circuit, the second logic gate includes a first logic circuit and a second logic circuit; The input terminal of the first logic circuit is connected to two input signals respectively. The output terminal of the first logic circuit and the output terminal of the third logic gate are both connected to the input terminal of the second logic circuit. The output terminal of the second logic circuit is connected to the input terminal of the fourth logic gate, the input terminal of the first logic gate, and the input terminal of the third logic gate respectively. The first logic circuit satisfies the following logical expression: , This is the output of the first logic circuit; The second logic circuit satisfies the following logical expression: The output terminal of the second logic circuit is the output terminal of the second logic gate.

[0007] In the aforementioned Mueller C-cell circuit, the first logic circuit is an OR gate, with two input terminals connected to two input signals respectively, and the output terminals of the OR gate and the third logic gate are both connected to the input terminals of the second logic circuit.

[0008] In the aforementioned Mueller C-cell circuit, the second logic circuit is a NAND gate; the output of the first logic circuit is connected to the first input of the NAND gate, the output of the third logic gate is connected to the second input of the NAND gate, and the output of the NAND gate is connected to the input of the fourth logic gate, the input of the first logic gate, and the input of the third logic gate, respectively.

[0009] The aforementioned Mueller C-cell circuit, wherein the third logic gate includes a third logic circuit and a fourth logic circuit; The output of the fourth logic gate and the output of the first logic gate are both connected to the input of the third logic circuit. The output of the third logic circuit and the output of the second logic gate are both connected to the input of the fourth logic circuit. The output of the fourth logic circuit is connected to the input of the second logic gate and the input of the fifth logic gate, respectively. The third logic circuit satisfies the following logical expression: , This is the output of the third logic circuit; The fourth logic circuit satisfies the following logical expression: The output terminal of the fourth logic circuit is the output terminal of the third logic gate.

[0010] In the aforementioned Mueller C-cell circuit, the third logic circuit is an OR gate; the output of the fourth logic gate is connected to the first input of the OR gate, the output of the first logic gate is connected to the second input of the OR gate, and the outputs of the OR gate and the second logic gate are both connected to the input of the fourth logic circuit.

[0011] In the aforementioned Mueller C-cell circuit, the fourth logic circuit is a NAND gate; The output of the third logic circuit is connected to the first input of the NAND gate, the output of the second logic gate is connected to the second input of the NAND gate, and the output of the NAND gate is connected to the input of the second logic gate and the input of the fifth logic gate, respectively.

[0012] In the aforementioned Mueller C-cell circuit, the fourth logic gate is an NOT gate; The output of the second logic gate is connected to the input of the NOT gate, and the output of the NOT gate is connected to the input of the fifth logic gate and the input of the third logic gate, respectively.

[0013] In the aforementioned Mueller C-cell circuit, the fifth logic gate is an AND gate; The output of the fourth logic gate is connected to the first input of the AND gate, and the output of the third logic gate is connected to the second input of the AND gate.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The Mueller C-cell circuit of the present invention consists only of logic gates, without the need for fully custom MOS transistors, and without the need to adjust the transistor size to achieve the function, thus reducing the difficulty of circuit design and implementation.

[0015] 2. The circuit of the present invention can be directly synthesized using EDA tools, and can be compatible with multiple process libraries at the same time, which is beneficial for conversion and application in different process scenarios.

[0016] 3. By optimizing the logic gate structure, this invention solves the race conditions that may exist in traditional circuits, avoids errors in asynchronous circuits, and improves the stability of circuit operation. Attached Figure Description

[0017] Figure 1 This is a structural block diagram of the Mueller C-cell circuit in an embodiment of the present invention; Figure 2 This is another circuit diagram of the Mueller C-cell circuit; Figure 3 This is a circuit diagram of the Mueller C-cell circuit in an embodiment of the present invention; Figure 4 for Figure 3 The simulation results are shown in the figure. Detailed Implementation

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments, but this should not be construed as limiting the present invention.

[0019] Example: A Mueller C-cell circuit, which achieves the following function: the output becomes 0 only when both inputs are 0, the output becomes 1 only when both inputs are 1, and the original output remains unchanged when the two inputs are not simultaneously.

[0020] like Figure 1 As shown, the Mueller C-cell circuit of this embodiment includes a first logic gate, a second logic gate, a third logic gate, a fourth logic gate, and a fifth logic gate. The input terminals of the first logic gate are respectively connected to two input signals, and the output terminal of the first logic gate is connected to the input terminal of the third logic gate. The output terminal of the third logic gate is respectively connected to the input terminals of the second and fifth logic gates. The input terminals of the second logic gate are respectively connected to two input signals, and the output terminal of the second logic gate is respectively connected to the input terminals of the fourth, first, and third logic gates. The output terminal of the fourth logic gate is respectively connected to the input terminals of the fifth and third logic gates. The first, second, third, fourth, and fifth logic gates satisfy the following logical expression: , , , , ;in, and There are two input signals, This is the output of the first logic gate. This is the output of the second logic gate. The output of the third logic gate, The output of the fourth logic gate, This is the output of the fifth logic gate, which is also the output of the Mueller C-cell circuit.

[0021] In this embodiment of the invention, two input signals , When all are low level "0", there is , Therefore, we can obtain: ; ; ; ; This means that the output becomes 0 when both inputs are 0.

[0022] Two input signals , At different times, such as High level "1", Low level "0", or Low level "0", For a high level "1", there is , Therefore, we can obtain: ; ; ; ; ; That is, the output of the Mueller C unit circuit always remains at The inverse value, The value is the one that was saved last time, thus enabling the Mueller C-cell circuit to maintain its original output even when the two inputs are different.

[0023] Two input signals , When both are high level "1", there is , Therefore, we can obtain: ; ;

[0024] ; but , ; ; This means that the output becomes 1 when both inputs are 1.

[0025] As can be seen from the above, the embodiments of the present invention utilize the first, second, third, fourth, and fifth logic gates in the Mueller C-cell circuit to achieve the function that the output becomes 0 when both inputs are 0, the output becomes 1 when both inputs are 1, and the output remains unchanged when the two inputs are different. The Mueller C-cell circuit is composed only of standard logic gates and does not require the use of custom MOS transistors, making it easy to implement. Furthermore, it can be directly synthesized using EDA tools and is compatible with multiple process libraries, which is beneficial for process conversion.

[0026] Furthermore, such as Figure 1 As shown, the second logic gate in this embodiment of the invention may include a first logic circuit and a second logic circuit. The input terminals of the first logic circuit are respectively connected to two input signals. The output terminals of the first logic circuit and the third logic gate are both connected to the input terminals of the second logic circuit. The output terminals of the second logic circuit are respectively connected to the input terminals of the fourth logic gate, the first logic gate, and the third logic gate. The first logic circuit satisfies the following logical expression: , The output of the first logic circuit is given, and the second logic circuit satisfies the following logical expression: The output of the second logic circuit is the output of the second logic gate. This ensures that the second logic gate satisfies the logical expression. .

[0027] Furthermore, such as Figure 1 As shown, the third logic gate in this embodiment of the invention may include a third logic circuit and a fourth logic circuit. The output terminal of the fourth logic gate and the output terminal of the first logic gate are both connected to the input terminal of the third logic circuit. The output terminal of the third logic circuit and the output terminal of the second logic gate are both connected to the input terminal of the fourth logic circuit. The output terminal of the fourth logic circuit is connected to the input terminal of the second logic gate and the input terminal of the fifth logic gate, respectively. The third logic circuit satisfies the following logical expression: , The output of the third logic circuit is given, and the fourth logic circuit satisfies the following logical expression: The output of the fourth logic circuit is the output of the third logic gate. This ensures that the third logic gate satisfies the logical expression. .

[0028] In addition to using Figure 1 In addition to using logic gates to construct the Mueller C unit, embodiments of the present invention can also employ... Figure 2 The logic gates constitute the Mueller C unit. Figure 2 The Mueller C-cell circuit includes two AND gates U1 and U3 and two OR gates U2 and U4. , , , Two input signals , When all are low level "0", there is , , , This achieves the function of outputting 0 when both inputs are 0; two input signals , At different times, there are , , , , This function, based on the previously saved value, ensures that the Mueller C-cell circuit maintains its original output even when the two inputs are different; two input signals , When both are high level "1", there is , , , This achieves the function of outputting 1 when both inputs are 1. However... Figure 2 The different lengths of each line, the different number of logic gates on each line, and the different signal delays on each line can create race conditions and cause errors in asynchronous circuits.

[0029] To solve the problem of competitive risk, such as Figure 3 As shown, in this embodiment of the invention, the preferred first logic gate is a three-input NAND gate U5, the preferred first logic circuit is an OR gate U6, the preferred second logic circuit is a NAND gate U7, the preferred third logic circuit is an OR gate U8, the preferred fourth logic circuit is a NAND gate U9, the preferred fourth logic gate is an NOT gate U10, and the preferred fifth logic gate is an AND gate U11. The first and second input terminals of the three-input NAND gate U5 are respectively connected to two input signals. , The two input terminals of OR gate U6 are respectively connected to two input signals. , The output of OR gate U6 is connected to the first input of NAND gate U7. The output of NAND gate U7 (the output of the second logic gate) is connected to the input of NOT gate U10 (the input of the fourth logic gate), the third input of three-input NAND gate U5, and the second input of NAND gate U9. The output of NOT gate U10 is connected to the first input of AND gate U11 and the first input of OR gate U8. The output of three-input NAND gate U5 (the output of the first logic gate) is connected to the second input of OR gate U8. The output of OR gate U8 is connected to the first input of NAND gate U9. The output of NAND gate U9 (the output of the third logic gate) is connected to the second input of AND gate U11 and the second input of NAND gate U7. Of course, the first, second, third, fourth, and fifth logic gates can each be connected in series with two NOT gates, thus enabling them to have AND... Figure 3 Different circuit structures; the first logic gate, the second logic gate, the third logic gate, the fourth logic gate, and the fifth logic gate can also be implemented with other structures to realize the corresponding logic expressions, which will not be introduced here.

[0030] Figure 3 The circuit's function of changing its output to 0 only when both inputs are 0, changing its output to 1 only when both inputs are 1, and maintaining its original output when both inputs are different has been explained above. Figure 3 The circuit was simulated, and the following results were obtained: Figure 4 The simulation results shown indicate that no race conditions were observed. This is mainly due to... Figure 3 The NAND gates U7 and U9 form the SR latch, which provides better stability and can solve race conditions and prevent errors in asynchronous circuits.

[0031] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0032] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A Mueller C-cell circuit, characterized in that, This includes the first logic gate, the second logic gate, the third logic gate, the fourth logic gate, and the fifth logic gate; The first logic gate has two input signals connected to its input terminal, and its output terminal is connected to the input terminal of the third logic gate. The output terminal of the third logic gate is connected to the input terminal of the second logic gate and the input terminal of the fifth logic gate. The input terminal of the second logic gate is connected to two input signals respectively, and the output terminal of the second logic gate is connected to the input terminal of the fourth logic gate, the input terminal of the first logic gate and the input terminal of the third logic gate respectively. The output terminal of the fourth logic gate is connected to the input terminal of the fifth logic gate and the input terminal of the third logic gate respectively. The first logic gate, the second logic gate, the third logic gate, the fourth logic gate, and the fifth logic gate satisfy the following logical expression: ； ； ； ； ； in, and There are two input signals, This is the output of the first logic gate. This is the output of the second logic gate. The output of the third logic gate, The output of the fourth logic gate, This is the output of the fifth logic gate.

2. The Mueller C-cell circuit according to claim 1, characterized in that, The first logic gate is a three-input NAND gate; The first and second input terminals of the three-input NAND gate are respectively connected to two input signals. The output terminal of the second logic gate is connected to the third input terminal of the three-input NAND gate, and the output terminal of the three-input NAND gate is connected to the input terminal of the third logic gate.

3. The Mueller C-cell circuit according to claim 1, characterized in that, The second logic gate includes a first logic circuit and a second logic circuit; The input terminal of the first logic circuit is connected to two input signals respectively. The output terminal of the first logic circuit and the output terminal of the third logic gate are both connected to the input terminal of the second logic circuit. The output terminal of the second logic circuit is connected to the input terminal of the fourth logic gate, the input terminal of the first logic gate, and the input terminal of the third logic gate respectively. The first logic circuit satisfies the following logical expression: , This is the output of the first logic circuit; The second logic circuit satisfies the following logical expression: The output terminal of the second logic circuit is the output terminal of the second logic gate.

4. The Mueller C-cell circuit according to claim 3, characterized in that, The first logic circuit is an OR gate, with two input terminals connected to two input signals respectively, and the output terminals of the OR gate and the third logic gate are both connected to the input terminals of the second logic circuit.

5. The Mueller C-cell circuit according to claim 3, characterized in that, The second logic circuit is a NAND gate; the output of the first logic circuit is connected to the first input of the NAND gate, the output of the third logic gate is connected to the second input of the NAND gate, and the output of the NAND gate is connected to the input of the fourth logic gate, the input of the first logic gate, and the input of the third logic gate, respectively.

6. The Mueller C-cell circuit according to claim 1, characterized in that, The third logic gate includes a third logic circuit and a fourth logic circuit; The output of the fourth logic gate and the output of the first logic gate are both connected to the input of the third logic circuit. The output of the third logic circuit and the output of the second logic gate are both connected to the input of the fourth logic circuit. The output of the fourth logic circuit is connected to the input of the second logic gate and the input of the fifth logic gate, respectively. The third logic circuit satisfies the following logical expression: , This is the output of the third logic circuit; The fourth logic circuit satisfies the following logical expression: The output terminal of the fourth logic circuit is the output terminal of the third logic gate.

7. The Mueller C-cell circuit according to claim 6, characterized in that, The third logic circuit is an OR gate; the output of the fourth logic gate is connected to the first input of the OR gate, the output of the first logic gate is connected to the second input of the OR gate, and the outputs of the OR gate and the second logic gate are both connected to the input of the fourth logic circuit.

8. The Mueller C-cell circuit according to claim 6, characterized in that, The fourth logic circuit is a NAND gate; The output of the third logic circuit is connected to the first input of the NAND gate, the output of the second logic gate is connected to the second input of the NAND gate, and the output of the NAND gate is connected to the input of the second logic gate and the input of the fifth logic gate, respectively.

9. The Mueller C-cell circuit according to claim 1, characterized in that, The fourth logic gate is a NOT gate; The output of the second logic gate is connected to the input of the NOT gate, and the output of the NOT gate is connected to the input of the fifth logic gate and the input of the third logic gate, respectively.

10. The Mueller C-cell circuit according to claim 1, characterized in that, The fifth logic gate is an AND gate; The output of the fourth logic gate is connected to the first input of the AND gate, and the output of the third logic gate is connected to the second input of the AND gate.

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