A gate voltage-enhanced sample-and-hold circuit and its asynchronous SARADC

Abstract

This invention discloses a gate voltage-enhanced sample-and-hold circuit and its asynchronous SAR ADC. The sample-and-hold circuit of this invention forms a transmission gate logic by connecting transistors M14 and M4 in parallel. Even with a large input amplitude of the differential input signal VIN / VIP, it can quickly pull down the node formed by the drains of transistors M5 and M4, thereby ensuring the rapid turn-on of transistor M7. The gate of transistor M1 is connected to an auxiliary path formed by transistors M12 and M13. This auxiliary path is activated during sampling to ensure the correct turn-on of transistor M1. Therefore, this invention can reduce the gate-end node capacitance of the sampling transistors in traditional sampling circuits, thereby accelerating sampling. It also increases the pull-down of the switching transistor at the VP node, accelerating the voltage boost and turn-on speed of the sampling switch, thus solving the technical problem of slow voltage boost and turn-on speed in existing sampling circuits. The gate voltage-enhanced sample-and-hold circuit of this invention is versatile and can be applied to various sampling applications.

Description

Technical Field

[0001] This invention relates to a sample-and-hold circuit and its analog-to-digital converter (ADC) in the field of integrated circuits, and more particularly to a gate voltage-enhanced sample-and-hold circuit and its asynchronous SAR ADC (Successive Approximation Register ADC). Background Technology

[0002] Please see Figure 1 Existing asynchronous SAR ADCs may include a clock generator, two sample-and-hold circuits, a capacitor array DAC, a comparator, and SAR logic. The clock generator operates based on control signals. Generate sampling clock The two sample-and-hold circuits operate according to the sampling clock. Sampling is performed as follows: The sample-and-hold circuit samples the differential input signals VIP and VIN to obtain the output signal VP. The second sample-and-hold circuit samples the differential input signals VIN and VIP to obtain the output signal VN. Initially, the two capacitor arrays of the capacitor array DAC are connected to VP and VN respectively through corresponding switch arrays. The sampled VP and VN are initially compared by a comparator. The SAR logic then calculates the output signal based on the comparator's comparison result (which refers to the comparator output V). OP The output of the comparator, the two output terminals V OP V ON When the comparator is not working, it outputs 1 for all values, and when the comparator is working, it outputs a pair of opposite 0 / 1 values. Therefore, the SAR logic receives V simultaneously. OP V ON It can be done via V OP V ON The two output signals determine whether the comparator is working, and thus whether the comparator's comparison work is complete. The output is a digital code B1, and simultaneously outputs two opposite digital logic control signals D. 1P D 1N Control the corresponding switches S in the two capacitor arrays respectively. 1p S 1n The opening and closing of the circuit determines how the two capacitors C1 and C2 are connected to VP and VN respectively, and then outputs the comparison clock. To the comparator. For example, when the comparison result is 1, the capacitor S connected to VP is controlled. 1p Open, then S 1n Then it remains closed. At this time, the comparator operates according to the comparison clock. The adjusted VP and VN are compared a second time, and so on, until VP and VN are each connected to only the last capacitor C in the two capacitor arrays. kP 、 C kN (exist Figure 1 (Taking 7 as an example, the comparator is based on the comparison clock.) Perform a final comparison, and SAR outputs the digital code B. k Therefore, the output of the SAR logic has two opposite digital logic control numbers D. 1P ~D kP D 1N ~D kN Comparison clocks k-bit numeric code sequence numbers B1 to B k .

[0003] Therefore, the conversion speed of an asynchronous SAR ADC is determined by the sampling speed of the sampling circuit and the processing speed of the SAR logic. A crucial factor affecting the SAR logic processing speed is the comparator's discrimination and reset times. Improving the sampling speed of the bootstrap switch and the comparator speed becomes a key consideration.

[0004] Please see Figure 2 These are two traditional sampling circuits. Figure 2 The sampling circuit shown in the middle area (a) is a traditional bootstrap switching circuit, in which node VG drives the gates of NMOS transistors M0, M1 and M2, resulting in a large load on capacitor C and a slow charging speed. Figure 2 The sampling circuit shown in area (b) is a fast boot switch circuit improved from the bootstrap switch circuit in area (a). M2 is removed to reduce the capacitive load on node VG, while M11 is added to the precharge node to connect VG to VDD, thereby accelerating the boost process of node VG. However, the pull-down speed of node VP is determined by the gate-source voltage VGS4 = VDD - VIP of M4. For large signal inputs VIP / VIN, the pull-down speed of this node will be slower, resulting in a slower boost and turn-on speed of the sampling switch.

[0005] Let's look again. Figure 1 The comparator used in the circuit typically employs a three-tailed comparator with anti-electrical faults, such as... Figure 3 As shown, Figure 3 Two outputs V OP V ONThe description is as above. The comparator is a three-stage comparator (TTC): two preamplifier stages (the number of preamplifier stages can be at least one) and a latch in the last stage. The latch is used to toggle and latch the latched 0 / 1 when the input is greater than the toggle threshold; the preamplifier is used to amplify the difference between the two input signals of the comparator stage by stage until the amplified difference reaches the toggle threshold of the latch. Figure 3 Comparators are often used to address the metastability problem of comparators (i.e., excessively long comparison time when the input signal is small), thereby speeding up the comparator's decision-making speed. Under small differential input conditions, TTC offers a faster decision-making speed than traditional Strong ARM and dual-tailed architectures. This advantage stems from its additional gain stage, which enhances small-signal amplification gain and provides greater design flexibility. TTC uses a dynamic amplifier as the first preamplifier stage, followed by a second preamplifier that acts as both an integrator and a latch, ultimately driving the final dynamic latch stage. While this architecture provides fast decision-making speed, its reset process is very slow because the second preamplifier stage and the third latch stage lack dedicated reset paths. The reset process relies entirely on the first preamplifier stage, meaning that the first stage reset drives the subsequent two stages, which severely limits the overall speed of the asynchronous SAR ADC. Summary of the Invention

[0006] (1) Technical problems to be solved

[0007] To address the technical problems of slow switching boost and conduction speed in existing sampling circuits, this invention provides a gate voltage enhanced sample-and-hold circuit and its asynchronous SAR ADC.

[0008] (2) Technical solution

[0009] This invention provides a gate voltage enhancement sample-and-hold circuit, comprising NMOS transistors M0, M1, M3-M4, M8-M12, PMOS transistors M5-M7, M13, M14, and capacitor C; a pair of differential input signals are respectively connected to the drains of M0 and M10, and the sources of M0 and M10 are connected to serve as the output terminal of the circuit to obtain the output signal; the gates of M0, M6, M7, M8, and M11 are connected, and the drains of M11, M5, M6, and M8 are all connected to a voltage source VDD; the gates of M11, M5, and M4 are all controlled by a sampling clock. The drain of M8 is connected to the drain of M9. The gates of M9, M3, M12, and M14 are all controlled by a clock that is opposite to the sampling clock. The sources of M3, M9, and M12 and the gate of M10 are all grounded; the source of M6 is connected to the sources of M13 and M7 and one end of C, and the other end of C is connected to the drains of M1 and M3 and the sources of M4 and M14; the source of M1 is connected to the drain of M0; the gate of M1 is connected to the drains of M12 and M13; and the gate of M13 is connected to the drains of M4, M5, and M14 and the gate of M7.

[0010] In another aspect, the present invention provides an asynchronous SAR ADC, which includes two of the above-mentioned gate voltage enhancement sample-and-hold circuits. The gate voltage enhancement sample-and-hold circuit one samples the differential input signals VIP and VIN to obtain the output signal VP; the gate voltage enhancement sample-and-hold circuit two samples the differential input signals VIN and VIP to obtain the output signal VN.

[0011] As a further improvement to the above scheme, the asynchronous SAR ADC also includes:

[0012] A capacitor array DAC is used to input VP and VN, utilizing a reference signal V. ref Adjustments were made sequentially from high to low levels.

[0013] The comparator is used to first compare the initial VP and VN once, and then compare the successively adjusted VP and VN k times in sequence;

[0014] SAR logic generates a corresponding 1+k bit digital code based on the results of 1+k comparisons.

[0015] As a further improvement to the above scheme, the comparator includes:

[0016] A latch is used to flip and latch the latched 0 / 1 when the input is greater than the flip threshold;

[0017] The preamplifier is used to amplify the difference between the two input signals of the comparator step by step until the amplified difference reaches the latch's toggling threshold.

[0018] As a further improvement to the above scheme, the latch includes: PMOS transistors M15 to M18 and NMOS transistors M19 to M21;

[0019] The gates of M15 and M18 are connected to the two outputs of the last stage preamplifier; the sources of M15 to M18 are connected to a voltage source; the drains of M15, M16, and M19 are connected to the gates of M17 and M20; the drains of M17, M18, and M20 are connected to the gates of M16 and M19; the sources of M19 and M20 are connected to the drain of M21, the source of M21 is grounded, and the gate of M21 is controlled by a comparator clock. The two outputs V of the latch are respectively led out from the drains of M19 and M20. OP and V ON .

[0020] As a further improvement to the above scheme, the latch includes: PMOS transistors M15-M18, M22, and M23, and NMOS transistors M19-M21;

[0021] The gates of M15 and M18 are connected to the two outputs of the last stage preamplifier; the sources of M15-M18, M22, and M23 are connected to a voltage source; the drains of M15, M16, M19, and M23 are connected to the gates of M17 and M20; the drains of M17, M18, M20, and M22 are connected to the gates of M16 and M19; the sources of M19 and M20 are connected to the drain of M21, the source of M21 is grounded, and the gates of M21-M23 are controlled by a comparator clock. The two outputs V of the latch are respectively led out from the drains of M19 and M20. OP and V ON .

[0022] As a further improvement to the above scheme, the preamplifier includes a first-stage preamplifier, which includes: PMOS transistors M24 and M25, and NMOS transistors M26 to M28.

[0023] The gates of M26 and M27 are connected to differential input signals, and the emitters of M26 and M27 are connected to the drain of M28. The gates of M28, M24, and M25 are all controlled by a comparator clock. The source of M28 is grounded; the drains of M26 and M27 are connected to the drains of M24 and M25 respectively; the sources of M24 and M25 are connected to a voltage source; and the two outputs of the first-stage preamplifier are led out from the drains of M26 and M27 respectively.

[0024] Furthermore, the preamplifier also includes at least one secondary preamplifier, which includes: PMOS transistors M29 to M31 and NMOS transistors M32 to M33;

[0025] The gates of M32 and M33 are connected to the drains of M26 and M27, respectively. The sources of M32 and M33 are grounded. The drains of M32 and M33 are connected to the drains of M30 and M31, respectively, and to the gates of M31 and M30, respectively. The sources of M30 and M31 are both connected to the drain of M29. The source of M29 is connected to a voltage source. The gate of M29 is controlled by a clock that is opposite to the comparison clock. The two outputs of the secondary preamplifier are respectively drawn from the drains of M32 and M33.

[0026] As a further improvement to the above scheme, the asynchronous SAR ADC also includes: a clock generator, which is used to output the sampling clock. .

[0027] As a further improvement to the above scheme, the capacitor array DAC uses two opposite digital logic control numbers D P1 ~D Pk D N1 ~D Nk Under the control of the reference signal V ref Adjust VP and VN sequentially from the most significant bit to the least significant bit; the SAR logic outputs D based on the comparison result of the comparator. P1 ~D Pk D N1 ~D Nk Simultaneously output comparison clock .

[0028] (3) Beneficial effects

[0029] This invention connects PMOS transistor M14 and NMOS transistor M4 in parallel to form a transmission gate logic. Even with large input amplitudes of the differential input signal VIN / VIP, it can quickly pull down node VP (the node formed by connecting the drains of PMOS transistor M5 and NMOS transistor M4), thus ensuring the rapid turn-on of PMOS transistor M7. To further reduce the capacitive load on node VG (the node formed by connecting the drain of PMOS transistor M7 and the emitter of NMOS transistor M11), the gate of NMOS transistor M1 is connected to an auxiliary path formed by NMOS transistors M12 and M13. This auxiliary path is activated during sampling to ensure the correct turn-on of NMOS transistor M1. Therefore, this invention reduces the gate-end node capacitance of the sampling transistor in traditional sampling circuits, thereby accelerating sampling. It also increases the pull-down of the switching transistor at node VP, accelerating the voltage boost and turn-on speed of the sampling switch, thus solving the technical problem of slow voltage boost and turn-on speed in existing sampling circuits. The gate voltage enhancement sample-and-hold circuit of this invention is versatile and can be applied to various sampling applications.

[0030] II. This invention adds an additional pre-discharge path (composed of PMOS transistors M22 and M23) to the latch of the last stage of the comparator to speed up the process. The fast reset speed during the low-level period improves the overall logic speed of the SAR logic in the asynchronous SAR ADC. The comparator of this invention is suitable for asynchronous SAR ADCs. Attached Figure Description

[0031] Figure 1 This is a circuit architecture diagram of an existing asynchronous SAR ADC.

[0032] Figure 2 yes Figure 1 The circuit diagrams show two relatively traditional sampling circuits.

[0033] Figure 3 yes Figure 1A circuit diagram of a traditional comparator.

[0034] Figure 4 This is a circuit diagram of the gate voltage enhancement sample-and-hold circuit provided in Embodiment 1 of the present invention.

[0035] Figure 5 This is a circuit diagram of the comparator of the asynchronous SAR ADC provided in Embodiment 2 of the present invention.

[0036] Figure 6 Is adopted Figure 4 Sample-and-hold circuit and Figure 5 The simulation results of the sampling rate of the asynchronous SAR ADC with the comparator are shown in the figure.

[0037] Figure 7 Is adopted Figure 4 Sample-and-hold circuit and Figure 5 Dynamic performance graph of the conversion rate of the asynchronous SAR ADC with comparator.

[0038] Figure 8 Is adopted Figure 4 Sample-and-hold circuit and Figure 5 A graph showing the relationship between the signal-to-noise ratio (SNDR) / spurious-free dynamic range (SFDR) and the sampling frequency for an asynchronous SAR ADC with a mid-range comparator at Nyquist input. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] Example 1

[0041] Please see Figure 4 The gate voltage enhancement sample-and-hold circuit of this embodiment, also known as a gate voltage enhancement bootstrap switch, includes NMOS transistors M0, M1, M3-M4, M8-M12, PMOS transistors M5-M7, M13, M14, and capacitor C. The gate voltage enhancement sample-and-hold circuit of this invention is versatile and can be applied to various sampling scenarios, such as replacing... Figure 1 The two sampling circuits shown are: a gate voltage enhancement sample-and-hold circuit 1, which samples the differential input signals VIP and VIN to obtain the output signal VP; and a gate voltage enhancement sample-and-hold circuit 2, which samples the differential input signals VIN and VIP to obtain the output signal VN.

[0042] A pair of differential input signals are connected to the drains of M0 and M10 respectively. The sources of M0 and M10 are connected together and used as the output terminal of the circuit to obtain the output signal. The gates of M0, M6, M7, M8, and M11 are connected. The drains of M11, M5, M6, and M8 are all connected to the voltage source VDD. The gates of M11, M5, and M4 are all controlled by the sampling clock. The drain of M8 is connected to the drain of M9. The gates of M9, M3, M12, and M14 are all controlled by a clock that is opposite to the sampling clock. The sources of M3, M9, and M12, and the gate of M10 are all grounded. The source of M6 is connected to the sources of M13 and M7 and one end of C. The other end of C is connected to the drains of M1 and M3 and the sources of M4 and M14. The source of M1 is connected to the drain of M0. The gate of M1 is connected to the drains of M12 and M13. The gate of M13 is connected to the drains of M4, M5, and M14 and the gate of M7. The drains of M5 and M4 are connected to form node VP, and the drain of M7 and the gate of M6 are connected to form node VG.

[0043] This invention connects PMOS transistor M14 and NMOS transistor M4 in parallel to form a transmission gate logic. Even with large input amplitudes of the differential input signal VIN / VIP, it can quickly pull down node VP (the node formed by connecting the drains of PMOS transistor M5 and NMOS transistor M4), thus ensuring the rapid turn-on of PMOS transistor M7. To further reduce the capacitive load on node VG (the node formed by connecting the drain of PMOS transistor M7 and the emitter of NMOS transistor M11), the gate of NMOS transistor M1 is connected to an auxiliary path formed by NMOS transistors M12 and M13. This auxiliary path is activated during sampling to ensure the correct turn-on of NMOS transistor M1. Therefore, this invention reduces the gate-end node capacitance of the sampling transistor in traditional sampling circuits, thereby accelerating sampling. It also increases the pull-down of the switching transistor at node VP, accelerating the voltage boost and turn-on speed of the sampling switch, thus solving the technical problem of slow voltage boost and turn-on speed in existing sampling circuits.

[0044] Example 2

[0045] Please see Figure 5 The comparator in this embodiment is suitable for asynchronous SAR ADCs. An additional pre-discharge path (composed of PMOS transistors M22 and M23) is added to the latch of the last stage of the comparator to speed up the process. The reset speed during the low-level period improves the overall logic speed of the asynchronous SAR ADC's SAR logic.

[0046] The comparator includes a preamplifier and a latch. The latch is used to toggle and latch the latched 0 / 1 when the input is greater than a toggle threshold. The preamplifier is used to amplify the difference between the two input signals of the comparator step by step until the amplified difference reaches the toggle threshold of the latch. The preamplifier may include a single-stage preamplifier, or it may include a single-stage preamplifier and at least one second-stage preamplifier. In this embodiment, a three-stage comparator (TTC) is used as an example for illustration.

[0047] The first-stage preamplifier may include: PMOS transistors M24 and M25, and NMOS transistors M26 to M28. The gates of M26 and M27 are connected to the differential input signals, and the emitters of M26 and M27 are connected to the drain of M28. The gates of M28, M24, and M25 are all controlled by a comparator clock. The source of M28 is grounded. The drains of M26 and M27 are connected to the drains of M24 and M25, respectively, and the sources of M24 and M25 are connected to a voltage source. The two outputs of the first-stage preamplifier are led out from the drains of M26 and M27, respectively.

[0048] The secondary preamplifier may include: PMOS transistors M29 to M31, and NMOS transistors M32 to M33. The gates of M32 and M33 are connected to the drains of M26 and M27, respectively, and the sources of M32 and M33 are grounded. The drains of M32 and M33 are connected to the drains of M30 and M31 on one side, and to the gates of M31 and M30 on the other side. The sources of M30 and M31 are both connected to the drain of M29. The source of M29 is connected to a voltage source, and the gate of M29 is controlled by a clock opposite to the comparator clock. The two outputs of the second-stage preamplifier are respectively drawn from the drains of M32 and M33.

[0049] The latch includes: PMOS transistors M15-M18, M22, and M23, and NMOS transistors M19-M21. The gates of M15 and M18 are connected to the two outputs of the last stage preamplifier. The sources of M15-M18, M22, and M23 are connected to a voltage source. The drains of M15, M16, M19, and M23 are connected to the gates of M17 and M20; the drains of M17, M18, M20, and M22 are connected to the gates of M16 and M19. The sources of M19 and M20 are connected to the drain of M21, the source of M21 is grounded, and the gates of M21-M23 are controlled by a comparator clock. The two outputs of the second-stage preamplifier are respectively led out from the drains of M32 and M33, and the drains of M15, M16, and M19 are connected to form the node output V. OP The drain connections of M17, M18, and M20 form the node output V. ON .

[0050] The comparator in this embodiment and Figure 3The difference between this and a traditional comparator is that the comparator in this embodiment adds a preamplifier circuit (such as...) to the third-stage latch. Figure 5 (Within the dashed box). The preamplifier circuit includes symmetrically arranged PMOS transistors M22 and M23. The preamplifier circuit is controlled by a comparator clock. (Because the gates of M22 and M23 are both controlled by the comparator clock) The voltage source is introduced through the source of M22 and M23, and the gate of the latch M16 and M17 is connected through the drain of M22 and M23 respectively.

[0051] Example 3

[0052] This embodiment is to verify whether the performance characteristics of the asynchronous SAR ADC formed by the gate voltage enhancement sample-and-hold circuit of Sampling Embodiment 1 and the comparator of Embodiment 2 have unexpected beneficial effects compared with the conventional ones.

[0053] In addition to the gate voltage enhancement sample-and-hold circuits of two embodiments 1 and a comparator of embodiment 2, the asynchronous SAR ADC also includes a clock generator, a capacitor array DAC, and SAR logic.

[0054] The clock generator is used to output the sampling clock. A capacitor array DAC is used to input VP and VN, utilizing a reference signal V. ref The adjustment proceeds sequentially from the most significant bit to the least significant bit. In this embodiment, the capacitor array DAC uses two opposite digital logic control numbers D. P1 ~D Pk D N1 ~D Nk Under the control of the reference signal V, ref The VP and VN are adjusted sequentially from the most significant bit to the least significant bit. An example using k=7 is provided. The comparator first compares the initial VP and VN once, then compares the adjusted VP and VN k times sequentially. The SAR logic generates a corresponding 1+k-bit digital code based on the results of these 1+k comparisons. In this embodiment, the SAR logic outputs D based on the comparator's comparison results. P1 ~D Pk D N1 ~D Nk Simultaneously output comparison clock The coordination relationship between the capacitor array DAC, comparator, and SAR logic has been described in detail in the background section and will not be repeated here. The focus of this invention is on the structural design of the sampling circuit and comparator.

[0055] Please combine Figure 6 , Figure 7 , Figure 8 , Figure 6 Is adopted Figure 4 Sample-and-hold circuit and Figure 5 The simulation results of the sampling rate of the asynchronous SARADC with comparator are shown in the figure. Figure 7 use Figure 4 Sample-and-hold circuit and Figure 5 Dynamic performance graph of the conversion rate of the asynchronous SAR ADC with comparator. Figure 8 Is adopted Figure 4 Sample-and-hold circuit and Figure 5 The relationship between SNDR / SFDR and sampling frequency of the asynchronous SAR ADC with comparator at Nyquist input.

[0056] Figure 6 The performance of the three architectures under large signal input was compared. The horizontal axis represents sampling time (ps), and the vertical axis represents the signal-to-noise ratio (SNDR) (dB). For the same 60dB SNDR requirement, compared with... Figure 2 Compared to the circuits shown in regions (a) and (b) in the diagram, the sample-and-hold circuit proposed in this invention reduces timing overhead by 20% and 10%, respectively. The gate voltage-enhanced sample-and-hold circuit of this invention reduces the gate node capacitance of the sampling transistor in traditional sampling circuits, accelerating the voltage boost and conduction speed of the sampling switch. Furthermore, it adds a VP node pull-down switch transistor, enabling it to maintain a fast voltage boost even under a large input signal range.

[0057] An additional pre-discharge path was added to the third stage of the three-stage comparator to accelerate the reset speed. Post-layout simulations show that the reset time is reduced by 10 ps compared to a traditional three-stage comparator, thus significantly accelerating the SAR ADC conversion speed. The tested dynamic performance is as follows: Figure 7 As shown. The asynchronous SARADC employs the sample-and-hold circuit of Embodiment 1 and the comparator of Embodiment 2, relative to... Figure 1 The traditional asynchronous SAR ADC architecture also has two bootstrap switches (i.e., sample-and-hold circuits), two monotonically switching capacitor array DACs, asynchronous SAR logic, and a three-stage comparator. However, because the asynchronous SAR ADC in this embodiment has a sample-and-hold circuit with gate voltage enhancement and a comparator with anti-electric comparator, it achieves a higher conversion rate and better energy efficiency.

[0058] Figure 8The plotted relationship between SNDR / SFDR and sampling frequency at Nyquist input shows that this asynchronous SAR ADC significantly improves the conversion rate compared to traditional SAR ADC architectures (sampling rate increases from 1 GS / s to 1.195 GS / s, an improvement of approximately 20%). At a sampling rate of 1.195 GS / s, with Nyquist input, this asynchronous SAR ADC achieves 39.2 dB SNDR and 51.9 dB SFDR. For low-frequency input, the dynamic performance is slightly improved, reaching 39.8 dB SNDR and 52.0 dB SFDR.

[0059] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A gate voltage enhancement sample-and-hold circuit, comprising NMOS transistors M0, M1, M3-M4, M8-M11, PMOS transistors M5-M7, and capacitor C, characterized in that, It also includes NMOS transistor M12 and PMOS transistors M13 and M14; A pair of differential input signals are connected to the drains of M0 and M10 respectively. The sources of M0 and M10 are connected and used as the output terminal of the sample-and-hold circuit to obtain the output signal. The gates of M0, M6, M7, M8, and M11 are connected. The drains of M11, M5, M6, and M8 are all connected to the voltage source VDD. The gates of M11, M5, and M4 are all controlled by the sampling clock. The drain of M8 is connected to the drain of M9. The gates of M9, M3, M12, and M14 are all controlled by a clock that is opposite to the sampling clock. The sources of M3, M9, and M12 and the gate of M10 are all grounded; the source of M6 is connected to the sources of M13 and M7 and one end of C, and the other end of C is connected to the drains of M1 and M3 and the sources of M4 and M14; the source of M1 is connected to the drain of M0; the gate of M1 is connected to the drains of M12 and M13; and the gate of M13 is connected to the drains of M4, M5, and M14 and the gate of M7.

2. An asynchronous SAR ADC, characterized in that, It includes two gate voltage enhancement sample-and-hold circuits as described in claim 1. The first gate voltage enhancement sample-and-hold circuit samples the differential input signals VIP and VIN to obtain the output signal VP; the second gate voltage enhancement sample-and-hold circuit samples the differential input signals VIN and VIP to obtain the output signal VN.

3. The asynchronous SAR ADC according to claim 2, characterized in that, Asynchronous SAR ADCs also include: A capacitor array DAC is used to input VP and VN, utilizing a reference signal V. ref Adjustments were made sequentially from high to low levels. The comparator is used to first compare the initial VP and VN once, and then compare the successively adjusted VP and VN k times in sequence; SAR logic generates a corresponding 1+k bit digital code based on the results of 1+k comparisons.

4. The asynchronous SAR ADC according to claim 3, characterized in that, The comparator includes: A latch is used to flip and latch the latched 0 / 1 when the input is greater than the flip threshold; The preamplifier is used to amplify the difference between the two input signals of the comparator step by step until the amplified difference reaches the latch's toggling threshold.

5. The asynchronous SAR ADC according to claim 4, characterized in that, The latches include: PMOS transistors M15 to M18 and NMOS transistors M19 to M21; The gates of M15 and M18 are connected to the two outputs of the last stage preamplifier; the sources of M15 to M18 are connected to a voltage source; the drains of M15, M16, and M19 are connected to the gates of M17 and M20; the drains of M17, M18, and M20 are connected to the gates of M16 and M19; the sources of M19 and M20 are connected to the drain of M21, the source of M21 is grounded, and the gate of M21 is controlled by a comparator clock. The two outputs V of the latch are respectively led out from the drains of M19 and M20. OP and V ON .

6. The asynchronous SAR ADC according to claim 4, characterized in that, The latches include: PMOS transistors M15-M18, M22, and M23, and NMOS transistors M19-M21; The gates of M15 and M18 are connected to the two outputs of the last stage preamplifier; the sources of M15-M18, M22, and M23 are connected to a voltage source; the drains of M15, M16, M19, and M23 are connected to the gates of M17 and M20; the drains of M17, M18, M20, and M22 are connected to the gates of M16 and M19; the sources of M19 and M20 are connected to the drain of M21, the source of M21 is grounded, and the gates of M21-M23 are controlled by a comparator clock. The two outputs V of the latch are respectively led out from the drains of M19 and M20. OP and V ON .

7. The asynchronous SAR ADC according to claim 4, characterized in that, The preamplifier includes a first-stage preamplifier, which includes PMOS transistors M24 and M25, and NMOS transistors M26 to M28. The gates of M26 and M27 are connected to differential input signals, and the emitters of M26 and M27 are connected to the drain of M28. The gates of M28, M24, and M25 are all controlled by a comparator clock. The source of M28 is grounded; the drains of M26 and M27 are connected to the drains of M24 and M25 respectively; the sources of M24 and M25 are connected to a voltage source; and the two outputs of the first-stage preamplifier are led out from the drains of M26 and M27 respectively.

8. The asynchronous SAR ADC according to claim 7, characterized in that, The preamplifier also includes at least one secondary preamplifier, which includes: PMOS transistors M29 to M31 and NMOS transistors M32 to M33; The gates of M32 and M33 are connected to the drains of M26 and M27, respectively. The sources of M32 and M33 are grounded. The drains of M32 and M33 are connected to the drains of M30 and M31, respectively, and to the gates of M31 and M30, respectively. The sources of M30 and M31 are both connected to the drain of M29. The source of M29 is connected to a voltage source. The gate of M29 is controlled by a clock that is opposite to the comparison clock. The two outputs of the secondary preamplifier are respectively drawn from the drains of M32 and M33.

9. The asynchronous SAR ADC according to claim 3, characterized in that, Asynchronous SAR ADCs also include: Clock generator, which is used to output the sampling clock. .

10. The asynchronous SAR ADC according to claim 3, characterized in that, The capacitor array DAC uses two opposite digital logic control numbers D. P1 ~D Pk D N1 ~D Nk Under the control of the reference signal V, ref Adjust VP and VN sequentially from the most significant bit to the least significant bit; the SAR logic outputs D based on the comparison result of the comparator. P1 ~D Pk D N1 ~D Nk Simultaneously output comparison clock .

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