An adaptive equalization circuit and method based on approximate computation

Abstract

The application provides an adaptive equalization circuit and method based on approximate calculation, and relates to the technical field of approximate circuit.The application constructs a three-level technical architecture: an approximate positive / negative compressor with directional error characteristics is designed, probability optimization logic is used to make the output generate positive and negative bias errors respectively; a Wallace tree array integrated compressor is used to form an 8bit*8bit layered approximate multiplier, low weight bits are truncated, intermediate bits are configured with approximate compressors, high weight bits are configured with full precision, and a mixed adder is used for summation; the approximate equalizer adopts a 15-tap FFE architecture, is based on an LMS algorithm, and divides the taps into front, main and rear taps according to signal energy, the main tap is configured with a low-error approximate negative multiplier, and the front and rear taps are cross-arranged to realize error complementation by using approximate positive / negative multipliers.The design simplifies hardware, realizes system-level error self-cancellation, reduces area, power consumption and delay, guarantees equalization performance, and provides a scheme for breaking through the bottleneck of a high-speed optical interface.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of approximate circuit, in particular to an adaptive equalization circuit and method based on approximate calculation. BACKGROUND

[0002] With the rapid development of cloud computing, big data and 5G communication technology, the data traffic in optical networks presents exponential growth, which puts higher requirements on the transmission rate of short-distance optical interfaces. Four-level pulse amplitude modulation (PAM4) technology has become the mainstream modulation scheme for the next generation of short-distance optical communication because it can double the transmission bandwidth at the same symbol rate. However, compared with traditional non-return-to-zero (NRZ) modulation, the eye diagram of PAM4 signal contains three decision thresholds and four signal levels when transmitted through the channel, and the eye diagram boundary is narrower, and the sensitivity to inter-symbol interference (ISI) is significantly enhanced, which makes high-performance adaptive equalization technology a core requirement for PAM4 system to realize reliable transmission.

[0003] Among the many schemes to suppress ISI, the feedforward equalizer (FFE) based on the least mean square (LMS) algorithm is widely used in high-speed optical communication systems due to its simple structure and stable convergence. LMS-FFE compensates for the front and back edge distortion of the input signal by dynamically adjusting the tap coefficients, and its core operation includes multiplication and accumulation of tap coefficients and input signals, and coefficient update based on error signals. However, with the increase of transmission rate, the hardware overhead of LMS-FFE becomes a key bottleneck restricting system performance. To solve the hardware overhead problem of LMS-FFE equalization circuit, existing research has tried to introduce approximate computing technology to simplify the core operation unit. Xie Wen-zhuo et al. proposed a LMS adaptive filter design based on approximate multiplier and system-level compensation strategy in "A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing", but the current design does not further tap the hardware efficiency improvement space combined with the multi-tap parallel structure characteristics of FFE equalizer, which is difficult to adapt to the "extreme miniaturization" design requirements of optical modules for equalizers. SUMMARY

[0004] The present application relates to the technical field of approximate circuit, in particular to an adaptive equalization circuit and method based on approximate calculation.

[0005] To achieve the above technical purposes, the first aspect of the present application discloses an adaptive equalizer based on approximate calculation, which comprises an input signal interface, an approximate directional compressor structure, an approximate directional multiplier structure, a K-tap approximate feedforward equalizer structure and a specific hardware connection architecture; the input signal interface is used for receiving an 8-bit PAM4 modulated signal and is connected to the K-tap approximate feedforward equalizer structure; the approximate directional compressor structure comprises two types of forward approximate compressors and negative approximate compressors, both of which adopt a 4-input 2-output architecture and realize a directional error generation function through a specific gate circuit connection; the approximate directional multiplier structure is based on a Wallace tree architecture, integrates the approximate directional compressor structure and constitutes an 8-bit×8-bit approximate forward multiplier and an approximate negative multiplier; the K-tap approximate feedforward equalizer structure comprises a delay line unit, an approximate FIR filter module and an approximate tap coefficient update module, and realizes signal processing and coefficient adaptive update under approximate calculation through a specific hardware connection relationship; and the specific hardware connection architecture comprises a physical connection relationship and a data flow path between components, and ensures that the directional errors are cooperatively offset at the system level.

[0006] In further embodiments of the first aspect, the input signal interface is used for receiving an 8-bit PAM4 modulated signal and transmitting it to the delay line unit; the delay line unit is composed of K-1 cascaded 8-bit registers, which are connected in sequence to form a signal delay chain and are used for storing historical data of the input signal; each tap output of the delay line unit is connected to the first input end of the corresponding approximate multiplier module of the K-tap approximate feedforward equalizer, so as to provide a multiplicand signal (A0-A7) for the multiplication operation.

[0007] In further embodiments of the first aspect, the forward approximate compressor comprises four data input ends, a bit and an output end and a bit carry output end, and its logic circuit is only composed of two AND gates, wherein the first AND gate is connected with input ends X1 and X2, the second AND gate is connected with the output of the first AND gate and input end X4, the output result is Sum, and the carry result Carry is always 1.

[0008] In further embodiments of the first aspect, the negative approximate compressor comprises four data input ends, a bit and an output end and a bit carry output end, and its logic circuit is composed of two AND gates and two OR gates, wherein the first AND gate is connected with input ends X1 and X2, the second AND gate is connected with input ends X3 and X4, the first OR gate is connected with input ends X1 and X3 to obtain the output result Sum; and the second OR gate is connected with the outputs of the first AND gate and the second AND gate to output the result Carry.

[0009] In further embodiments of the first aspect, the approximate multiplier module comprises both positive and negative approximate multipliers, both of which employ a Wallace tree structure including three main hardware components: a partial product generation array, a hierarchical partial product compression array, and a final summation unit.

[0010] In further embodiments of the first aspect, the partial product generation array is composed of a logic circuit consisting of 64 AND gates, with 16 inputs connected to 8-bit multiplicand and 8-bit multiplier signal lines respectively, generating 16 columns of partial product signals (P0-P15); the partial product compression layer employs a hierarchical processing structure, with bit weight differentiation achieved through physical layout: low weight bit processing units directly truncate the first 6 bits of partial products and output them to ground; intermediate weight bit processing units employ a 4-input 2-output approximate compressor array, with positive approximate multipliers using positive approximate compressors and negative approximate multipliers using negative approximate compressors, both of which employ different gate-level circuit layouts; high weight bit processing units employ precise 4-2 compressors, full adders, and half adders; the summation layer employs a hybrid structure of carry-save adders and row carry adders for the final summation of compressed partial products.

[0011] In further embodiments of the first aspect, the K-tap approximate feed-forward equalizer structure comprises an approximate FIR filter module and an approximate tap coefficient update module, both of which implement signal processing functions through a specific hardware interconnection architecture.

[0012] The approximate FIR filter module employs a hardware pipeline structure based on shift registers, including K parallel approximate multiplier units and a multi-bit adder tree; the first input of each approximate multiplier unit is directly connected to the corresponding tap output of the delay line unit through an 8-bit data bus, and the second input is connected to the output of the corresponding coefficient register in the approximate tap coefficient update module to receive real-time data for approximate filtering; the multi-bit adder tree employs a Wallace tree structure composed of multiple full adders and half adders, with inputs connected to the 16-bit product output of the K approximate multiplier units, achieving parallel accumulation of partial products through a specific wiring network, and finally outputting a 16-bit filtering result;

[0013] The approximate tap coefficient updating module adopts an error feedback architecture, and comprises an error calculation unit and a coefficient updating unit; the error calculation unit is composed of an accurate subtractor, two input ends of which are connected with a desired signal interface and an approximate FIR filtering module output interface respectively; the coefficient updating unit comprises K coefficient updating channels working in parallel, each channel comprising a step multiplier, an approximate multiplier, an accumulator and a coefficient register; the step multiplier is an accurate multiplier, a first input end of which is connected with an output of the error calculation unit, and a second input end of which is connected with a step factor mu configuration register; a first input end of the approximate multiplier is connected with an error signal output by the error calculation unit, and a second input end thereof is connected with a corresponding tap output end of the delay line unit through an 8-bit data bus; an input end of the accumulator is connected with a 16-bit product output of the approximate multiplier, and an output end thereof is fed back to the input end to realize an accumulation function; the coefficient register is connected with the second input end of the corresponding approximate multiplier unit in the approximate FIR filtering module through an 8-bit coefficient bus, thereby forming a closed-loop control structure.

[0014] In further embodiments of the first aspect, the tap arrangement of the K-tap approximate feed-forward equalizer adopts a specific hardware connection mode, wherein in the first M taps, the approximate multipliers in the approximate FIR filtering module and the approximate tap coefficient updating module adopt an alternating positive and negative physical layout mode; in the middle N taps, all adopt a negative approximate multiplier; in the last P taps, an alternating positive and negative physical layout mode is adopted; the approximate multipliers of each tap adopt a symmetric configuration mode in the approximate FIR filtering module and the approximate tap coefficient updating module, and the same layout and wiring scheme are adopted for the same approximate multipliers in the two modules.

[0015] In the second aspect of the present application, an adaptive equalization method based on approximate calculation is disclosed, which is implemented by using the adaptive equalization circuit based on approximate calculation disclosed in the first aspect, and comprises the following steps:

[0016] Step A: detecting the error characteristics of the approximate positive multiplier and the approximate negative multiplier, and according to the error probability distribution and the output result analysis, the error probability of the positive output of the approximate positive multiplier is larger, and the error probability of the negative output of the approximate negative multiplier is smaller;

[0017] Step B: designing a tap configuration scheme to compensate for the directional error according to the error characteristics of the approximate multiplier, and configuring more approximate negative multipliers in the equalizer system to compensate for the larger error of the approximate positive multiplier; dividing the equalizer taps into three parts, the first M pre-taps adopt an alternating layout scheme of the approximate positive multiplier and the approximate negative multiplier, the middle N taps all adopt a negative approximate multiplier, and the last P post-taps adopt an alternating layout mode of negative and positive;

[0018] Step C: the approximate FIR filter module filters the input signal x(n) under the approximate multiplier tap configuration scheme of error compensation to obtain an output signal y(n):

[0019]

[0020] wherein, is the kth tap coefficient, the total number of taps K = M + N + P, M is the number of pre-taps, N is the number of main taps, and P is the number of post-taps, represents the input signal after k delays; the approximate FIR filter module is actually divided into three approximate filter modules, and the error of the final accumulation result is compensated through the approximate tap configuration scheme;

[0021] Step D: the approximate tap coefficient update module updates the coefficients through the approximate multiplier to realize the approximate update; an ideal reference signal d(n) is obtained, and an error signal e(n) is calculated According to the error signal e(n) and the input signal x(n), the tap weight coefficient at the next moment is obtained through the approximate multiplication by using the LMS algorithm :

[0022]

[0023] wherein, μ is a step factor; the taps of the approximate tap coefficient update module correspond to the taps of the approximate FIR filter module one by one, and the tap configuration adopts the same approximate multiplier error compensation scheme;

[0024] Step E: steps C to D are repeated to realize the adaptive equalization adjustment of the input signal under the approximate calculation through the continuous circulation of the approximate filtering and the approximate tap coefficient update.

[0025] In a further embodiment of the second aspect, in step A, the approximate forward multiplier is an 8-bit x 8-bit multiplier, the partial product generation is implemented through an 8 x 8 AND gate array, the first to sixth low-weight bits are directly truncated during partial product compression, the seventh and eighth intermediate-weight bits use an approximate forward compressor, the ninth to sixteenth high-weight bits use an accurate 4-2 compressor, a full adder and a half adder, and the summation stage uses a mixed structure of a carry-save adder and a carry-propagate adder; the approximate negative multiplier is an 8-bit x 8-bit multiplier, the partial product generation and the summation stage are the same as those of the approximate forward multiplier, and the seventh and eighth intermediate-weight bits use an approximate negative compressor during partial product compression.

[0026] In a further embodiment of the second aspect, the approximate positive compressor is a 4-input 2-output structure, and the probability of the output error being positive is much greater than the probability of the output error being negative; the approximate negative compressor is a 4-input 2-output structure, and the probability of the output error being negative is greater than the probability of the output error being positive. The approximate positive multiplier has a greater probability of positive output error, and the approximate negative multiplier has a smaller probability of negative output error.

[0027] In a further embodiment of the second aspect, in step B, the approximate multiplier tap configuration scheme is designed, and more approximate negative multipliers are configured to compensate for the greater error of the approximate positive multiplier; the approximate positive multipliers and the approximate negative multipliers are arranged in an alternating manner in the first M taps, the approximate negative multipliers are used in the middle N main taps, and the approximate positive multipliers and the approximate negative multipliers are arranged in an alternating manner in the last P taps.

[0028] In view of the hardware resource limitation problem of the adaptive equalizer (LMS-FFE) in high-speed optical communication, the application provides a solution, which replaces the traditional high-precision multiplier with two approximate multipliers with fixed error directions (positive bias and negative bias), thereby reducing the hardware overhead of the compensation circuit. In the specific implementation, the multipliers in the 15 taps are mixedly configured according to a specific proportion, and the systematic superposition of positive and negative errors is used to realize overall error cancellation. Compared with the prior art, the application has the following beneficial effects:

[0029] (1) The application reconfigures the compressor and multiplier architecture innovatively, designs positive / negative error bias compressors based on the probability distribution characteristics of partial products, and performs hierarchical approximation according to the weights of partial products in an 8x8 bit multiplier, thereby effectively simplifying the compressor and multiplier structure and generating the expected error bias, and saving hardware resources.

[0030] (2) The application creatively proposes a three-section tap arrangement strategy to realize system-level error self-cancellation, compensate for the internal error through complementary bias compensation, eliminate the output deviation without increasing additional overhead, and solve the balance problem between precision and efficiency of approximate calculation in the field of adaptive equalization. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 FIG. 1 is a schematic diagram of an adaptive equalization circuit architecture based on approximate calculation in the embodiments.

[0032] Figure 2 FIG. 5 is a Karnaugh map of the approximate positive compressor.

[0033] Figure 3 FIG. 8 is a schematic diagram of a logic gate circuit of the approximate positive compressor.

[0034] Figure 4 FIG. 11 is a Karnaugh map of the approximate negative compressor.

[0035] Figure 5 A schematic diagram of a logic gate circuit for an approximate negative compressor.

[0036] Figure 6 A schematic diagram of an array structure for an approximate multiplier.

[0037] Figure 7 A schematic diagram of a basic architecture of an LMS-FFE system. DETAILED DESCRIPTION

[0038] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art upon

[0039] Embodiment 1

[0040] The adaptive equalization circuit based on approximate calculation disclosed in this embodiment, through three innovative strategies of directional error control, hierarchical approximation optimization and complementary error compensation, ensures the stability of system equalization performance while significantly reducing hardware complexity. The adaptive equalization circuit contains a three-level technical architecture: approximate positive compressors and approximate negative compressors with directional error characteristics; the above compressors are dynamically integrated in the Wallace tree partial product compression array to form an approximate positive multiplier and an approximate negative multiplier with a size of 8 bits x 8 bits; the approximate equalizer adopts an FFE architecture for filtering, selects an LMS algorithm for weight update, and introduces an error-biased approximate multiplier in the approximate FIR filtering module and the approximate tap coefficient update module to implement the tap arrangement strategy of error compensation.

[0041] The approximate compressor is a basic module for controlling the error direction. The design breaks through the limitation of traditional compressors without biased errors and realizes error direction through probability-driven logic optimization. The true value table of the positive compressor is optimized to maximize the probability of positive error: by calculating the error distance of different input combinations, the probability of the output result error being positive is much greater than that of being negative, thereby generating a stable positive biased error;

[0042] The approximate negative compressor adopts the same compressor error biasing idea, so that the probability of the output result error distance being negative is greater than that of being positive, generating a negative biased error;

[0043] The approximate forward multiplier is divided into three stages of partial product generation, partial product compression and summation, and the innovation lies in the processing strategy of hierarchical approximation and key bit precision preservation.

[0044] The approximate negative multiplier adopts the same approximation method, and in the partial product compression part, the approximate negative compressor is used to replace the accurate 4-2 compressor for the middle two bits.

[0045] The equalizer is the top-level design of the system architecture, adopts a K-tap approximate feed-forward equalizer structure, designs an adaptive adjustment mechanism based on a least mean square algorithm for an 8-bit PAM4 input signal, and innovatively proposes an error complementary tap arrangement strategy. The equalizer is the top-level design of the system architecture, adopts a K-tap approximate feed-forward equalizer structure, designs an adaptive adjustment mechanism based on a least mean square algorithm for an 8-bit PAM4 input signal, and innovatively proposes an error complementary tap arrangement strategy.

[0046] To maximize the efficiency of approximate calculation, the approximate multiplier is introduced into the equalizer, and the K taps are classified and differentiated: the taps are divided into front taps, main taps and rear taps, wherein the main taps correspond to the current signal and have the greatest impact on the equalization effect, and are the key to error control; the front and rear taps are mainly used to compensate for the front and rear distortion of the signal, and have relatively small influence on the performance. Based on this classification, the replacement of the approximate multiplier of the tap follows the error complementary principle: the approximate FIR filter module and the approximate tap coefficient update module of the main tap all adopt the approximate negative multiplier, which uses the smaller error probability to ensure the accuracy of the core path; the front and rear taps adopt the forward and negative multipliers in a 1:1 cross arrangement, and the positive and negative errors of adjacent taps are offset to reduce local error accumulation. This configuration realizes precision compensation without additional calibration circuit through global error complementation, and finally reduces the hardware overhead while ensuring system convergence stability and equalization effect.

[0047] To optimize the above technical solutions, the specific measures taken also include:

[0048] ​​The approximate compressors are approximate positive compressors and approximate negative compressors, the compressors are four input data, two output data, and the carry of the present stage and the carry of the next stage, compared with the traditional accurate 4-2 compressor, the carry of the previous stage and the carry of the next stage are discarded. The core basis of this design is the probability characteristics of the input partial product. Based on the probability distribution of the input signal, the compressor adjusts the output logic by optimizing the truth table, so that the error of the output data of the approximate positive compressor is biased to the positive direction, and the error of the output data of the approximate negative compressor is biased to the negative direction, and a simplified logic function is obtained by combining the Carnot diagram.

[0049] The multiplier is an 8bit*8bit multiplier, generating a 16-column partial product array, in the order from low to high, the first to the sixth bit is the low weight bit, the partial product is truncated, the seventh and eighth bit is the intermediate weight bit, the accurate 4-2 compressor is replaced by the approximate compressor, wherein the intermediate weight bit of the approximate positive multiplier is replaced by the approximate positive compressor, and the intermediate weight bit of the approximate negative multiplier is replaced by the approximate negative compressor. The ninth to sixteenth bit is the high weight bit, and the accurate device is used for partial product compression; the summation stage is completed by the mixed structure of the carry save adder and the row carry adder, which not only ensures the accumulation speed, but also avoids the error accumulation in the summation process.

[0050] The approximate equalizer system adopts the FFE equalizer architecture, updates the tap coefficient by using the LMS algorithm, uses the approximate tap error compensation formula arrangement strategy according to the output probability of the approximate positive compressor and the approximate negative compressor and the error distance of the output result of the corresponding multiplier, replaces the multiplier in the FIR filter and the approximate tap coefficient update module in the front tap with the approximate positive multiplier and the approximate negative multiplier in the cross arrangement mode, uses the approximate negative multiplier with lower error probability in the main tap, and also uses the approximate positive multiplier and the approximate negative multiplier in the cross arrangement mode in the post-tap, to constitute the approximate LMS-FFE system.

[0051] Embodiment 2

[0052] Taking an optical communication approximate LMS-FFE system as an example, the system input signal is an 8bit PAM4 signal, and the technical scheme of the application is further described in detail in combination with the drawings:

[0053] Table 1 is the probability distribution of the input partial product of the compressor. The approximate compressor is a 4-input 2-output structure, the input signal is the partial product of the multiplier array, each partial product is generated by an AND gate, the probability of 0 is 3 / 4, and the probability of 1 is 1 / 4. Therefore, the probability of the four inputs x1, x2, x3 and x4 of the compressor is calculated, 16 different input conditions are grouped according to the input probability, and five different input groups are obtained. According to different input probabilities, the output results in the truth table of the compressor are modified.

[0054] Table 1: Probability distribution of partial products of compressor input

[0055]

[0056] Table 2 is the truth table of the approximate positive compressor, according to the input probability and error distance, the probability of error being positive is: , the probability of error being negative is: , so that the output result is more likely to be positive. Figure 2 is the Karnaugh map of the approximate positive compressor, the logic function and is , the carry is , Figure 3 The logic gate circuit structure of the approximate positive compressor is composed of only two AND gates, which efficiently saves hardware resources.

[0057] Table 2: Truth table of approximate positive compressor

[0058]

[0059] Table 3 is the truth table of the approximate negative compressor, according to the same design idea, the probability of error being negative is: , the probability of error being positive is: , so that the output result is more likely to be negative. Figure 4 is the Karnaugh map of the approximate negative compressor, the logic function and is , the carry is . Figure 5 The logic gate circuit structure of the approximate negative compressor is composed of two AND gates and two OR gates.

[0060] Table 3: Truth table of approximate negative compressor

[0061]

[0062] Figure 6This diagram illustrates the structure of an 8-bit × 8-bit approximate multiplier. The multiplier employs a hybrid architecture combining hierarchical approximation and precise key-bit calculation. The multiplier array consists of three parts: partial product generation, partial product compression, and partial product summation. Partial product generation is implemented using an 8×8 AND gate array, consistent with traditional structures. Partial product compression employs a hierarchical processing strategy: the lowest 6 bits are directly truncated, as this part has a relatively small impact on the system's signal-to-noise ratio, and truncating it directly saves on the number of compressors; the middle 2 bits are processed in parallel using the aforementioned approximation compressor, with the positive multiplier configured with a positive compressor and the negative multiplier configured with a negative compressor to obtain an error-biased multiplier; the highest 8 bits are processed using precise 4-2 compressors, full adders, and half adders to ensure the accuracy of signal amplitude calculation, which is crucial for system performance. In the partial product summation stage, a hybrid structure is used, combining a carry-saving adder (CSA) to achieve parallel accumulation of intermediate results, and finally, a row carry adder (RCA) completes the precise summation, balancing computational speed and accuracy.

[0063] Figure 7 The basic architecture of the LMS-FFE system is as follows: the input signal x(n) is filtered to obtain the output signal y(n), where the tap weights are updated using the LMS algorithm, and d(n) is the desired signal. Specifically, the process involves first calculating the error between the output signal and the desired signal. Then, based on the error and the input signal, the tap coefficients for the next time step are updated, i.e. (where μ is the step size factor), through continuous cyclic filtering This enables adaptive equalization and adjustment of the signal.

[0064] The adaptive equalization circuit based on approximation calculation designed in this invention uses a 15-tap system and proposes an innovative approximation multiplier configuration scheme. Figure 1 It is an adaptive equalization circuit architecture based on approximate calculation.

[0065] In this scheme, the approximate FIR filter module filters the input signal x(n) under the error-compensated approximate multiplier tap configuration to obtain the output signal y(n):

[0066]

[0067] in, Let K be the coefficient of the k-th tap. The total number of taps K = M + N + P, where M is the number of preceding taps, N is the number of major taps, and P is the number of following taps. This represents the input signal after k delays.

[0068] For the FFE architecture of 15 taps, the taps are divided into three parts: the first 6 taps as pre-taps, the middle 3 taps as main taps, and the last 6 taps as post-taps. To optimize the system performance, the approximate multiplier is used to replace the accurate multiplier in the FIR module and the approximate tap coefficient update module, and the positive and negative error complementary characteristics of the two approximate multipliers are configured. Since the total error probability of the approximate negative multiplier is , the total error probability of the approximate positive multiplier is , the negative error is smaller, and therefore more negative multipliers need to be configured to compensate for the positive error generated by the positive multiplier. The specific configuration is that in the first 6 taps, the approximate positive multiplier and the approximate negative multiplier are arranged in a 1:1 cross (3 positive and 3 negative), and the local deviation is offset by alternating errors; all the 3 main taps in the middle use approximate negative multipliers, because the main taps have the largest contribution to the signal gain, and arranging more negative multipliers can effectively compensate for larger positive deviation; the last 6 taps also use a 1:1 cross arrangement (3 positive and 3 negative) to balance the overall error distribution. The entire LMS-FFE system realizes a 6:9 approximate positive and negative multiplier ratio, and through this complementary bias offset mechanism, error compensation is achieved without the need for additional calibration circuits, reducing hardware overhead while ensuring system performance.

[0069] As in the above embodiment, to solve the problem of limited hardware resources faced by the adaptive equalizer in the high-speed optical communication scenario, the present application proposes a low-complexity LMS-FFE architecture using approximate multipliers with different error directions, which realizes performance optimization through system-level error compensation. The approximate positive and negative compressors with error bias are designed to construct the corresponding error-biased approximate multipliers, and the hardware complexity is reduced by removing the compensation circuit. At the system level, by strategically configuring the multiplier type in the 15-tap FFE, error offset can be achieved by coordinating the superposition of positive / negative bias. This cooperative method enables the LMS-FFE to save hardware resources by sacrificing part of the precision within the allowed error tolerance range, providing a feasible path for the next generation of high-speed optical interfaces to break through the hardware bottleneck.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for part of the technical features; and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An adaptive equalization circuit based on approximate calculation, characterized in that, include: Input signal interface, approximate directional compressor structure, approximate directional multiplier structure, K-tap approximate feedforward equalizer structure, and predetermined hardware connection architecture. The input signal interface is used to receive an 8-bit PAM4 modulated signal and is connected to the K-tap approximate feedforward equalizer structure. The tap arrangement of the K-tap approximate feedforward equalizer adopts the following hardware connection method: In the first M taps, the approximate multipliers in the approximate FIR filtering module and the approximate tap coefficient update module adopt a physical layout of alternating positive and negative directions; All of the N taps in the middle use negative approximation multipliers; In the last P taps, a physical layout method of alternating negative and positive directions is adopted; the approximate multipliers of each tap are symmetrically configured in the approximate FIR filtering module and the approximate tap coefficient update module, and the same type of approximate multipliers in the two modules adopt the same layout and routing scheme. The approximate directional compressor structure includes a positive approximate compressor and a negative approximate compressor, both of which adopt a 4-input 2-output architecture and are connected through predetermined gate-level circuits to realize the directional error generation function. The approximate oriented multiplier structure is based on the Wallace tree architecture and integrates the approximate oriented compressor structure to form an 8-bit × 8-bit approximate positive multiplier and an approximate negative multiplier. The K-tap approximate feedforward equalizer structure includes a delay line unit, an approximate FIR filter module, and an approximate tap coefficient update module, which realizes signal processing and adaptive coefficient update through predetermined hardware connection relationships. The predetermined hardware connectivity architecture includes the physical connection relationships between the components and the data flow path, ensuring that orientation errors are collaboratively offset at the system level.

2. The adaptive equalization circuit based on approximate calculation according to claim 1, characterized in that, The input signal interface is used to receive an 8-bit PAM4 modulated signal and transmit it to the delay line unit; the delay line unit consists of K-1 cascaded 8-bit registers, which are connected in sequence to form a signal delay chain for storing historical data of the input signal; each tap output of the delay line unit is connected to the first input terminal of the approximate multiplier module corresponding to the K-tap approximate feedforward equalizer, providing multiplicand signals A0-A7 for the multiplication operation; The approximate multiplier module includes two types: positive approximate multipliers and negative approximate multipliers. Both adopt a Wallace tree structure and contain a partial product generation array, a hierarchical partial product compression array, and a final summation unit.

3. The adaptive equalization circuit based on approximate calculation according to claim 1, characterized in that, The forward approximation compressor includes four data input terminals, a local sum output terminal, and a local carry output terminal. Its logic circuit consists of only two AND gates, where the first AND gate is connected to the input terminals X1 and X2, and the second AND gate is connected to the output and input terminal X4 of the first AND gate. The output result is Sum, and the carry result Carry is always 1.

4. The adaptive equalization circuit based on approximate calculation according to claim 1, characterized in that, The negative approximation compressor includes four data input terminals, a local sum output terminal, and a local carry output terminal. Its logic circuit consists of two AND gates and two OR gates. The first AND gate is connected to input terminals X1 and X2, the second AND gate is connected to input terminals X3 and X4, and the first OR gate is connected to input terminals X1 and X3 to obtain the output result Sum. The second OR gate is connected to the outputs of the first AND gate and the second AND gate, and the output result is Carry.

5. The adaptive equalization circuit based on approximate calculation according to claim 2, characterized in that, The partial product generation array consists of 64 AND gates, with its 16 inputs connected to 8-bit multiplicand and 8-bit multiplier signal lines, generating 16 columns of partial product signals P0-P15. The partial product compression layer adopts a layered processing structure, with bit weight differentiation achieved through physical layout: low-weight bit processing units directly truncate the partial product of bits 1-6 and ground their outputs; intermediate-weight bit processing units use a 4-input, 2-output approximation compressor array, where the positive approximation multiplier uses a positive approximation compressor and the negative approximation multiplier uses a negative approximation compressor, with different gate-level circuit layouts for the two types of compressors; high-weight bit processing units use precise 4-2 compressors, full adders, and half adders; the summation layer adopts a hybrid structure of carry-preserving adders and row-carry adders, used to finally sum the compressed partial products.

6. The adaptive equalization circuit based on approximate calculation according to claim 1, characterized in that, The approximate FIR filtering module adopts a shift register-based hardware pipeline structure, comprising K parallel-operating approximate multiplier units and a multi-bit adder tree. The first input of each approximate multiplier unit is directly connected to the corresponding tap output of the delay line unit via an 8-bit data bus, and the second input is connected to the output of the corresponding coefficient register in the approximate tap coefficient update module to receive real-time data for filtering. The multi-bit adder tree adopts a Wallace tree structure, consisting of multiple levels of full adders and half adders. Its inputs are respectively connected to the 16-bit product outputs of the K approximate multiplier units, and the parallel accumulation of partial products is achieved through a wiring network, finally outputting a 16-bit filtered result.

7. The adaptive equalization circuit based on approximate calculation according to claim 6, characterized in that, The approximate tap coefficient update module adopts an error feedback architecture, comprising an error calculation unit and a coefficient update unit. The error calculation unit consists of an accurate subtractor, whose two inputs are connected to the desired signal interface and the output interface of the approximate FIR filter module, respectively. The coefficient update unit contains K parallel coefficient update channels, each containing a step multiplier, an approximate multiplier, an accumulator, and a coefficient register. The step multiplier is an accurate multiplier, with its first input connected to the output of the error calculation unit and its second input connected to the configuration register of the step factor μ. The first input of the approximate multiplier is connected to the error signal output by the error calculation unit, and its second input is connected to the corresponding tap output of the delay line unit via an 8-bit data bus. The input of the accumulator is connected to the 16-bit product output of the approximate multiplier, and its output is fed back to its own input to achieve the accumulation function. The coefficient register is connected to the second input of the corresponding approximate multiplier unit in the approximate FIR filter module via an 8-bit coefficient bus, forming a closed-loop control structure.

8. An adaptive equilibrium method based on approximate calculation, characterized in that, The adaptive equalization circuit based on approximate calculation as described in any one of claims 1 to 7 includes the following steps: Step A: Detect the error characteristics of the approximate positive multiplier and the approximate negative multiplier. The method is as follows: the approximate positive multiplier has a higher probability of positive output error, and the approximate negative multiplier has a lower probability of negative output error. Step B: Design a tap configuration scheme to compensate for orientation error based on the error characteristics: Divide the equalizer taps into three parts. The first M front taps adopt an alternating layout of approximately positive multipliers and approximately negative multipliers; the middle N taps all adopt negative approximate multipliers; and the last P rear taps adopt an alternating layout of negative and positive multipliers. Step C: The approximate FIR filtering module filters the input signal x(n) under the error-compensated approximate multiplier tap configuration scheme to obtain the output signal y(n): in, Let K be the coefficient of the k-th tap. The total number of taps K = M + N + P, where M is the number of preceding taps, N is the number of major taps, and P is the number of following taps. This represents the input signal after k delays; Step D: The approximate tap coefficient update module uses the LMS algorithm to achieve approximate updates of the tap coefficients by configuring an approximate multiplier; it obtains the ideal reference signal d(n) and calculates the error signal. Then, based on the error signal e(n) and the input signal x(n), the tap weight coefficients for the next time step are obtained through approximate multiplication using the LMS algorithm. : Where μ is the step size factor; the taps of the approximate tap coefficient update module correspond one-to-one with the taps of the approximate FIR filter module, and the tap configuration adopts the same approximate multiplier error compensation scheme. Step E: Repeat steps C to D, and through continuous cyclic filtering and approximate tap coefficient updates, achieve adaptive equalization adjustment of the input signal under approximate calculation.

9. The adaptive equilibrium method based on approximate calculation according to claim 8, characterized in that, In step A, the approximate positive multiplier is an 8-bit × 8-bit multiplier. Its partial product generation is achieved through an 8 × 8 AND gate array. During partial product compression, the low-weight bits from the 1st to the 6th bit are directly truncated, the intermediate weight bits of the 7th and 8th bits use an approximate positive compressor, and the high-weight bits from the 9th to the 16th bits use a precise 4-2 compressor, a full adder, and a half adder. The summation stage uses a hybrid structure of carry-preserving adder and row-carry adder. The approximate negative multiplier is also an 8-bit × 8-bit multiplier. Its partial product generation and summation stages are the same as those of the approximate positive multiplier. During partial product compression, the intermediate weight bits of the 7th and 8th bits use an approximate negative compressor. The approximate forward compressor has a 4-input 2-output structure, and the probability that the output error is positive is greater than the probability that the error is negative. The approximate negative compressor has a 4-input, 2-output structure, and the probability of the output error being negative is greater than the probability of the error being positive.

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