Implementation method, system and device of a lightweight stream cipher

Abstract

The present application relates to the field of information security technology, and more particularly to a lightweight sequence cipher implementation method, system and device, comprising obtaining a key and an initial vector, and splitting and isolating independent storage units mapped to a feedback shift register and a linear feedback shift register through a physical isolation mechanism; a driver layer performs multi-round nonlinear iteration reinforcement state confusion in an initialization stage, and switches a cyclic shift operation in a working stage to reduce power consumption; a feedback shift register high bit and a linear feedback shift register fixed bit are extracted through a solidification path to generate reorganized data; a finite state machine three-stage pipeline performs permutation table query, linear diffusion and XOR operation to generate a key stream, wherein the permutation table is preprogrammed, registers are multiplexed, and resource occupation is optimized; and an encryption data stream is output by a bitwise XOR unit. The present application solves the problems of power consumption surge, volume burden, encryption delay and hardware failure caused by resource occupation in industrial control embedded systems, satellite-borne devices and satellite terminals.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of information security, and in particular to a lightweight sequence cipher implementation method, system and device. BACKGROUND

[0002] Lightweight sequence ciphers belong to the branch of cryptography, and are specially designed for resource-constrained environments, such as Internet of Things devices or embedded systems. The core principle is to generate a key stream through an efficient pseudo-random number generator, and combine it with the input data bit by bit to complete the encryption and decryption process. In existing implementations, sequence ciphers require complex logic and large storage resources, but in lightweight versions, by optimizing the algorithm structure, such as integrating linear feedback shift registers and combining nonlinear functions, hardware overhead and energy consumption are greatly reduced, while ensuring the necessary security level and processing speed, thus being suitable for limited computing power scenarios without sacrificing basic encryption strength.

[0003] Sequence ciphers operate based on a layered architecture, including a driving layer responsible for key stream generation, a bit reorganization layer for data extraction, and a finite state machine for nonlinear transformation. The driving layer usually includes linear feedback shift registers and feedback shift registers for generating initial key sequences. The bit reorganization layer extracts specific bit positions from the shift registers for recombination. The finite state machine uses an iterative structure to implement nonlinear confusion operations, such as using permutation tables and linear transformations. Related technologies are designed for regular Internet of Things devices, but do not fully consider the unique operating conditions of industrial embedded systems, spaceborne resource-constrained platforms, or satellite communication portable terminals.

[0004] In application environments such as industrial embedded devices, spaceborne resource-constrained devices, satellite communication portable or miniature terminal devices, the problem of high resource occupation caused by sequence cipher implementation becomes particularly prominent. Algorithm components such as nonlinear permutation tables and complex feedback mechanisms occupy too much logic gate and register space, significantly increasing system power consumption and volume burden. Spaceborne devices face the risk of radiation interference, and intensive operations with high resource occupation can accelerate component aging and reduce error tolerance capabilities; industrial embedded systems are strictly limited in power consumption, and high-energy design can easily lead to heat accumulation and unstable operation, affecting the feasibility of low-power encryption operations; satellite communication terminal miniaturization requirements are high, and resource waste makes small devices unable to balance performance and space constraints. Frequency restrictions cause encryption delays, weakening real-time communication capabilities, while resource-intensive structures increase hardware failure probability, posing a potential threat to key application security. SUMMARY

[0005] In view of the deficiencies of the prior art, the present application provides a lightweight sequence cipher implementation method, system and device, and solves the technical problems of excessive resource occupation of nonlinear permutation tables and complex feedback mechanisms in sequence cipher algorithms, resulting in excessive power consumption, increased volume, significant encryption delay and increased hardware failure probability in industrial embedded systems, satellite-borne resource-limited devices and satellite communication portable terminals.

[0006] To solve the above technical problems, the specific content of the present application is as follows:

[0007] The present application provides a lightweight sequence cipher implementation method, comprising:

[0008] Step 1, obtain the key and the initial vector, split the key into a first key block and a second key block by a physical isolation mechanism, and split the initial vector into a first vector block and a second vector block;

[0009] Step 2, map the split first key block, second key block, first vector block and second vector block to the feedback shift register and linear feedback shift register defined by the hardware layer respectively, the first key block is mapped to the first storage unit of the feedback shift register, the second key block is mapped to the second storage unit of the feedback shift register, the first vector block is mapped to the third storage unit of the linear feedback shift register, and the second vector block is mapped to the fourth storage unit of the linear feedback shift register;[pk1]

[0010] Step 3, in the initialization stage, the driver layer of the hardware layer performs a plurality of rounds of nonlinear iteration operations on the mapped registers to generate confusion state data, and in the working stage, the driver layer performs a cyclic shift operation on the registers to generate shift state data, and from the shift state data, the shift state data is subjected to a bit reorganization operation through a solidification path to generate first reorganization data of the feedback shift register and second reorganization data of the linear feedback shift register;

[0011] Step 4, the extracted first reorganization data and second reorganization data are subjected to three-level processing by the finite state machine of the hardware layer, the first level generates nonlinear transformation data by using a permutation table query, the second level processes the nonlinear transformation data by using a linear diffusion operation to generate diffusion data, and the third level performs an exclusive OR operation on the diffusion data to generate a key stream;

[0012] Step 5, receive the input data to be encrypted, and perform an exclusive OR operation on the key stream and the input data bit by bit through a bit-wise exclusive OR unit to output the generated encrypted data stream.

[0013] Further, the lightweight sequence cipher implementation method of the present application, the step 1 comprises:

[0014] Receive a 128-bit key and a 96-bit initial vector;

[0015] The 128-bit key is divided into four 32-bit key blocks;

[0016] The 96-bit initial vector is divided into three 32-bit vector blocks;

[0017] The four key blocks are respectively mapped to the first storage unit, the second storage unit, the third storage unit and the fourth storage unit of the feedback shift register;

[0018] The three vector blocks are respectively mapped to the fifth storage unit, the sixth storage unit and the seventh storage unit of the linear feedback shift register.

[0019] Further, the implementation method of the lightweight sequence cipher, the step 3 comprises: in the initialization stage, the driving layer performs 32 rounds of composite operations on the feedback shift register and the linear feedback shift register, the 32 rounds of composite operations comprising modulo addition and cyclic shift, reading the storage unit data of the register, performing modulo addition operation to generate intermediate data, and performing cyclic shift on the intermediate data;

[0020] In the working stage, the driving layer performs a single-step cyclic shift operation, reads the shift state data, and performs a single-bit cyclic right shift.

[0021] Further, the implementation method of the lightweight sequence cipher, the step 3 comprises: locating the high 4-bit position from the storage unit of the feedback shift register;

[0022] Extracting the data of the high 4-bit position to generate first reorganization data;

[0023] Locating the fixed bit position determined according to the preset rule from the storage unit of the linear feedback shift register;

[0024] Extracting the data of the preset fixed bit position to generate second reorganization data.

[0025] Further, the implementation method of the lightweight sequence cipher, the step 4 comprises:

[0026] Offline generation of constant data required by the permutation table, and pre-burning the constant data into the read-only memory;

[0027] In the permutation table query stage, the constant data is read from the read-only memory to generate nonlinear transformation data;

[0028] In the linear diffusion operation stage, the same group of registers of the finite state machine is multiplexed to receive the nonlinear transformation data, perform linear diffusion, and store the diffusion data.

[0029] Further, the implementation method of the lightweight sequence cipher, the step 4 further comprises:

[0030] receiving the first reorganized data;

[0031] splitting the first reorganized data into eight 32-bit sub-data segments;

[0032] synchronously accessing the permutation table of the read-only memory through eight independent query channels;

[0033] splicing the eight query results into 256-bit nonlinear transformation data.

[0034] Further, the implementation method of the lightweight sequence cipher further comprises: offline generating 256-bit constant data required by the permutation table;

[0035] pre-storing the constant data to the eighth storage unit of the linear feedback shift register;

[0036] in the initialization stage, the driving layer reads the constant data from the eighth storage unit;

[0037] inputting the read constant data into the permutation table query stage.

[0038] Further, the implementation method of the lightweight sequence cipher further comprises: monitoring the radiation interference signal of the satellite-borne device;

[0039] when the radiation interference is detected, injecting a 4-bit redundancy check bit into the shift state data in the driving layer working stage;

[0040] performing the parity check calculation on the shift state data containing the check bit through the cyclic shift check chain;

[0041] correcting the error bits of the shift state data according to the check result.

[0042] In a second aspect, the present application provides an implementation system of a lightweight sequence cipher, applied to the implementation method of the lightweight sequence cipher, comprising:

[0043] an acquisition device for acquiring a key and an initial vector;

[0044] a splitting device for splitting the key into a first key block and a second key block and splitting the initial vector into a first vector block and a second vector block through a physical isolation mechanism;

[0045] a mapping device for mapping the split key block and vector block to the designated storage unit of the feedback shift register and the linear feedback shift register defined by the hardware layer, respectively;

[0046] The driving device is used for performing a plurality of rounds of nonlinear iteration operation to generate confusion state data in an initialization phase, and performing a cyclic shift operation to generate shift state data in a working phase.

[0047] The recombination device is used for extracting first recombination data of the feedback shift register and second recombination data of the linear feedback shift register from the shift state data through a solidification path.

[0048] The state machine device is used for performing a three-stage pipeline operation on the first recombination data and the second recombination data to generate a key stream.

[0049] The encryption device is used for receiving input data, performing an exclusive OR operation on the input data and the key stream bit by bit through a bit-wise exclusive OR unit, and outputting an encrypted data stream.

[0050] In a third aspect, the present application provides an electronic device, comprising:

[0051] A memory for storing a computer program;

[0052] A processor for implementing the steps of the implementation method of the lightweight stream cipher when executing the computer program.

[0053] Advantages of the present application;

[0054] The present application has the advantages that the key and the initial vector are separated by a physical isolation mechanism and are isolated in different storage units mapped to the registers, the storage resource conflict of the industrial control embedded system is eliminated, and the volume burden is reduced; the double-mode architecture of the driving layer separates the plurality of rounds of nonlinear iteration in the initialization phase and the pure cyclic shift operation in the working phase, the dynamic power consumption of the satellite-borne device is significantly reduced under the premise of maintaining the security strength of the cryptography; the solidification path extracts the high-bit data of the feedback shift register and the fixed-bit data of the linear feedback shift register, the dynamic addressing overhead is eliminated, and the space and energy consumption balance of the satellite communication terminal is optimized; the three-stage pipeline of the finite state machine multiplexes the substitution table pre-burning and the register sharing mechanism, the number of instantiation of the logic unit is reduced, and the resource utilization rate of the embedded system is improved; the offline generation of the constant data pre-storage combined with the fault tolerance check injection mechanism suppresses the soft error probability and the hardware failure risk of the satellite-borne platform; and the overall scheme solves the problems of encryption delay, power consumption surge and reliability decline in the resource-constrained scene. BRIEF DESCRIPTION OF DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed in the embodiments. Obviously, other drawings can also be obtained by those skilled in the art without creative labor under the premise of the drawings.

[0056] Figure 1 The system architecture diagram of the implementation system of the lightweight stream cipher provided by the embodiments of the present application. Detailed Implementation

[0057] To make the technical solution of the present invention clearer, the present invention will be clearly and completely described below with reference to specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The present invention provided by various embodiments will be described in detail below with reference to the accompanying drawings. To better understand the purpose of the present invention, the present invention will be described in further detail below.

[0058] Please see Figure 1 The present invention provides a method for implementing a lightweight stream cipher, comprising:

[0059] Step 1: Obtain the key and initialization vector. Divide the key into a first key block and a second key block using a physical isolation mechanism. Divide the initialization vector into a first vector block and a second vector block.

[0060] Step 2: Map the segmented first key block, second key block, first vector block, and second vector block to the feedback shift register and linear feedback shift register defined in the hardware layer, respectively. The first key block is mapped to the first storage unit of the feedback shift register, the second key block is mapped to the second storage unit of the feedback shift register, the first vector block is mapped to the third storage unit of the linear feedback shift register, and the second vector block is mapped to the fourth storage unit of the linear feedback shift register.

[0061] Step 3: In the initialization phase, the driver layer of the hardware layer performs multiple rounds of nonlinear iterative operations on the mapped register to generate confused state data. In the working phase, the driver layer performs cyclic shift operations on the register to generate shift state data. From the shift state data, the bit recombination operation is performed on the shift state data through the solidified path to generate the first recombined data of the feedback shift register and the second recombined data of the linear feedback shift register.

[0062] Step 4: The extracted first and second recombined data are processed in three levels using a finite state machine at the hardware layer. The first level uses a permutation table to generate nonlinear transformation data. The second level uses a linear diffusion operation to process the nonlinear transformation data and generate diffusion data. The third level reuses the diffusion data to perform an XOR operation and generate a key stream.

[0063] Step 5: Receive the input data to be encrypted, and perform a bitwise XOR operation between the key stream and the input data using a bitwise XOR unit to output the generated encrypted data stream.

[0064] After obtaining the key and the initial vector, a segmentation operation is performed through a physical isolation mechanism. The physical isolation mechanism segments the complete key into independent first and second key blocks, and segments the initial vector into independent first and second vector blocks. The segmentation operation enables different data blocks to be non-overlapping in subsequent mapping processes, eliminating the risk of storage resource contention. The segmented data blocks are used as independent inputs in the register mapping stage, providing isolated data sources for hardware layer processing.

[0065] The segmented data blocks are mapped to the register designated storage units defined by the hardware layer. The first key block is mapped to the first storage unit of the feedback shift register, and the second key block is mapped to the second storage unit of the feedback shift register; the first vector block is mapped to the third storage unit of the linear feedback shift register, and the second vector block is mapped to the fourth storage unit of the linear feedback shift register. The mapping operation establishes a fixed correspondence between the data blocks and the physical storage locations, avoiding dynamic addressing overhead. The registers serve as the basic components of the hardware layer, providing static data storage carriers for the driver layer operations.

[0066] The driver layer performs multiple rounds of nonlinear iteration operations in the initialization stage. The driver layer reads the storage unit data of the mapped registers, performs a composite operation to generate intermediate data, and through a cyclic shift, strengthens the state confusion, and finally outputs the confused state data. The nonlinear iteration operation enhances the initial entropy value, improving the security of cryptography. The confused state data serves as the input for the working stage, supporting subsequent operations in the encryption process.

[0067] The driver layer performs a cyclic shift operation in the working stage. The working stage driver layer reads the shift state data, performs a single-bit cyclic shift to generate updated shift state data. The cyclic shift uses a hardware-level lightweight operation, significantly reducing dynamic power consumption and computation delay. The shift state data is input to the solidification path processing link as a bit reorganization operation.

[0068] The solidification path performs a bit reorganization operation on the shift state data. The high-bit position is located from the storage unit of the feedback shift register, and the specified bits are extracted to generate first reorganization data; the fixed bit position is located according to a preset rule from the storage unit of the linear feedback shift register, and the specified bits are extracted to generate second reorganization data. The solidification path eliminates the dynamic bit shift overhead through a preset hardware rule, ensuring data extraction efficiency. The first and second reorganization data after reorganization are input to the finite state machine processing.

[0069] The finite state machine performs three-stage pipeline processing. The first stage converts reorganized data into nonlinear transformation data through a permutation table query, and the permutation table is generated based on a read-only memory preburn; the second stage processes the nonlinear transformation data using a linear diffusion operation to generate diffusion data, and multiplexes the same group of registers to perform multi-stage operations; and the third stage multiplexes the diffusion data to participate in an exclusive OR operation to directly generate a key stream. The three-stage pipeline realizes layered calculation and hardware multiplexing, optimizing resource utilization.

[0070] The bitwise XOR unit generates an encrypted data stream. The encrypted data stream is generated by receiving input data to be encrypted and a key stream, and performing an exclusive OR operation bit by bit through a hardware-level bitwise XOR unit. The exclusive OR operation outputs an encrypted data stream, completing an end-to-end encryption process. The encrypted data stream is the final output, solving the encryption delay and power consumption problems of resource-constrained devices.

[0071] Specifically, the implementation method of the lightweight sequence cipher comprises the following steps:

[0072] receiving a 128-bit key and a 96-bit initial vector;

[0073] segmenting the 128-bit key into four 32-bit key blocks;

[0074] segmenting the 96-bit initial vector into three 32-bit vector blocks;

[0075] mapping the four key blocks to the first to fourth storage units of the feedback shift register, respectively;

[0076] mapping the three vector blocks to the fifth to seventh storage units of the linear feedback shift register, respectively.

[0077] The physical isolation mechanism receives a 128-bit key and a 96-bit initial vector as input. The key is segmented into four 32-bit key blocks, and the initial vector is segmented into three 32-bit vector blocks. The key blocks are mapped to the first to fourth storage units of the feedback shift register, and the vector blocks are mapped to the fifth to seventh storage units of the linear feedback shift register. The unit mapping establishes physical storage isolation of the key blocks and the vector blocks, eliminating the risk of register space overlap. Independent unit allocation enables parallel storage of multiple data blocks, adapting to the space constraints of resource-constrained devices.

[0078] Specifically, the implementation method of the lightweight sequence cipher comprises the following steps:

[0079] In the working stage, the driving layer performs a single-step cyclic shift operation, reads the shift state data, and performs a single-bit cyclic right shift.

[0080] In the initialization stage, the driving layer reads the storage unit data of the feedback shift register and the linear feedback shift register, performs a modulo addition operation to generate intermediate data. The modulo addition operation combines the characteristics of arithmetic and logical operations, and enhances the non-linear confusion strength. The intermediate data performs a cyclic shift operation to change the bit position distribution. The composite operation is iterated for 32 rounds to generate high-entropy confusion state data. In the working stage, the driving layer reads the shift state data and performs a single-bit cyclic right shift. The single-step shift simplifies the calculation process, reduces dynamic power consumption and clock cycle occupation, and supports real-time encryption requirements.

[0081] Specifically, the step 3 of the implementation method of the lightweight sequence cipher comprises the following steps: Locating the high 4-bit position from the storage unit of the feedback shift register;

[0082] Extracting the data of the high 4-bit position to generate first reorganization data;

[0083] Locating a fixed bit position determined according to a preset rule from the storage unit of the linear feedback shift register;

[0084] Extracting the data of the preset fixed bit position to generate second reorganization data.

[0085] The solidification path locates the high 4-bit position of the feedback shift register storage unit, extracts the high bit data to generate first reorganization data. The high bit position retains the data effective information bit, avoiding low bit redundant calculation. Synchronously locating the fixed bit position of the linear feedback shift register storage unit, extracting the fixed bit data to generate second reorganization data. The fixed bit position is preset according to the hardware architecture, ensuring the stability of data extraction. The solidification path eliminates the dynamic bit displacement addressing operation, reducing the data carrying resource consumption.

[0086] Specifically, the step 4 of the implementation method of the lightweight sequence cipher comprises the following steps:

[0087] Offline generation of constant data required for the permutation table, and pre-burning the constant data to the read-only memory;

[0088] In the permutation table query stage, the constant data is read from the read-only memory to generate nonlinear transformation data;

[0089] In the linear diffusion operation stage, the same group of registers of the finite state machine is multiplexed to receive the nonlinear transformation data, perform linear diffusion, and store the diffusion data.

[0090] Constant data required for generating the substitution table offline is pre-recorded to a read-only memory. The pre-recording operation fixes the content of the substitution table, saving real-time calculation circuits. The substitution table query stage reads constant data from the read-only memory, and combines reorganization data to generate nonlinear transformation data. The linear diffusion operation stage multiplexes the same set of registers of the finite state machine, receives nonlinear transformation data to perform linear transformation. The register sharing mechanism reduces the number of instances of logic units, and optimizes the utilization rate of hardware resources. The transformation result is stored as diffusion data and transmitted to the next level of processing.

[0091] Specifically, the implementation method of the lightweight sequence cipher provided by the present application, the step 4 further comprises:

[0092] receiving first reorganization data;

[0093] splitting the first reorganization data into eight 32-bit sub-data segments;

[0094] synchronously accessing the substitution table of the read-only memory through eight independent query channels;

[0095] splicing the eight query results into 256-bit nonlinear transformation data.

[0096] The first reorganization data is received and split into eight 32-bit sub-data segments. Data segmentation is adapted to a parallel processing architecture to improve query throughput. Eight independent query channels synchronously access the substitution table of the read-only memory, and output eight query results. Parallel operation eliminates serial query delay and reduces encryption response time. The query results are spliced into 256-bit nonlinear transformation data, which is completely transmitted to the linear diffusion stage.

[0097] Specifically, the implementation method of the lightweight sequence cipher provided by the present application, the step 3 further comprises: offline generating 256-bit constant data required for the substitution table;

[0098] pre-storing the constant data to the eighth storage unit preset in the linear feedback shift register;

[0099] In the initialization stage, the driving layer reads the constant data from the eighth storage unit;

[0100] The read constant data is input to the substitution table query stage.

[0101] Offline generation of 256-bit substitution table constant data is pre-stored to the eighth storage unit of the linear feedback shift register. The special storage unit isolates the constant storage area to avoid data conflict in the initialization stage. In the initialization stage, the driving layer reads the constant data from the eighth storage unit and directly calls the pre-stored data. The constant data is input to the substitution table query stage, which eliminates the real-time generation calculation burden. The pre-storage mechanism reduces dynamic power consumption and improves the long-term operation stability of the spaceborne device.

[0102] Specifically, the implementation method of the lightweight sequence cipher, the step 3 further comprises: monitoring the radiation interference signal of the spaceborne device;

[0103] When the radiation interference is detected, 4-bit redundant check bits are injected into the shift state data in the driving layer working stage;

[0104] The shift state data with the check bits is subjected to the parity check calculation through the cyclic shift check chain;

[0105] According to the check result, the error bits of the shift state data are corrected.

[0106] The radiation interference signal of the spaceborne device is monitored, and the high-energy particle impact event is detected in real time. When the radiation interference is detected, 4-bit redundant check bits are injected into the shift state data in the driving layer working stage. The check bits enhance the data integrity verification capability and identify potential bit errors. The data is subjected to the parity check calculation through the cyclic shift check chain, and the error bit position is located. According to the check result, the error bits of the shift state data are corrected, and the data consistency of the encryption process is restored. The fault tolerance processing improves the anti-radiation capability in the spaceborne environment.

[0107] In a second aspect, the present application provides a lightweight sequence cipher implementation system, applied to the lightweight sequence cipher implementation method, comprising:

[0108] An acquisition device is configured to acquire a key and an initial vector;

[0109] A segmentation device is configured to segment the key into a first key block and a second key block through a physical isolation mechanism, and segment the initial vector into a first vector block and a second vector block;

[0110] A mapping device is configured to map the segmented key blocks and vector blocks to designated storage units of a feedback shift register and a linear feedback shift register defined by a hardware layer, respectively;

[0111] A driving device is configured to generate confusion state data by performing a plurality of rounds of nonlinear iteration operations in an initialization stage, and generate shift state data by performing a cyclic shift operation in a working stage;

[0112] A recombination device is configured to extract first recombination data of the feedback shift register and second recombination data of the linear feedback shift register from the shift state data through a solidification path;

[0113] A state machine device is configured to generate a key stream by performing a three-stage pipeline operation on the first recombination data and the second recombination data;

[0114] An encryption device is configured to receive input data, perform an exclusive OR operation on the key stream and the input data bit by bit through a bit-wise exclusive OR unit, and output an encrypted data stream.

[0115] In a third aspect, the present application provides an electronic device comprising:

[0116] a memory storing a computer program;

[0117] a processor implementing the steps of the implementation method of the lightweight stream cipher when executing the computer program.

[0118] The technical scheme of the present application solves the resource occupation pain point through multi-level collaborative optimization. The physical isolation mechanism divides the key and the initial vector into independent data blocks, and isolates them to different storage units of the feedback shift register and the linear feedback shift register. This mechanism eliminates the risk of register space overlap, reduces the storage conflict of multi-task encryption of industrial control embedded systems, and reduces the volume burden.

[0119] The driving layer adopts a dual-mode architecture to separate security strength and operational efficiency. In the initialization phase, multiple rounds of nonlinear iteration are performed to strengthen state confusion, ensuring the security benchmark of cryptography; in the working phase, it is switched to pure cyclic shift operation, significantly reducing the logic gate trigger frequency. The dual-mode design adapts to the low-power requirements of the anti-radiation scene of satellite devices, while meeting the real-time response requirements of industrial control systems.

[0120] The solidification path extraction eliminates the overhead of dynamic displacement. The preset hardware rule locates the high-bit feedback shift register and the fixed-bit linear feedback shift register, and directly extracts and reorganizes the data. The solidification operation eliminates the dynamic addressing calculation load, compressing the space occupation and transmission energy consumption of satellite communication terminals.

[0121] The finite state machine three-stage pipeline realizes hardware reuse. The substitution table is pre-burned into the read-only memory to eliminate real-time calculation circuits; the linear diffusion stage reuses the same group of registers to perform multi-stage operations; and the substitution table eight-way parallel query improves throughput. The reuse mechanism reduces the number of instances of logic units, optimizing the resource utilization rate of embedded systems.

[0122] In the key stream synthesis stage, the diffusion data is reused to participate in the XOR operation, avoiding redundant state machine calculation. The single-step update mechanism of the driving layer adapts to low-frequency clock synchronization, maintaining the timing stability of satellite terminals in harsh environments. Constant data generated offline is pre-stored in a dedicated register unit, suppressing the soft error probability of satellite platforms.

[0123] The fault-tolerant mechanism enhances the reliability in extreme environments. When radiation interference is triggered, redundant check bits are injected, and parity check is performed through a cyclic shift check chain. The check result real-time corrects the error bits of the shift state data, improving the single event upset resistance of satellite devices. The pre-burned substitution table combined with the register sharing design simultaneously reduces the heat dissipation pressure and hardware failure risk of industrial control devices.

Claims

1. A method of implementing a lightweight stream cipher, characterized by, The method comprises the following steps: Step 1, obtaining a key and an initial vector, splitting the key into a first key block and a second key block through a physical isolation mechanism, and splitting the initial vector into a first vector block and a second vector block; Step 2, mapping the split first key block, second key block, first vector block and second vector block to feedback shift registers and linear feedback shift registers defined by a hardware layer respectively, mapping the first key block to a first storage unit of the feedback shift registers, mapping the second key block to a second storage unit of the feedback shift registers, mapping the first vector block to a third storage unit of the linear feedback shift registers, and mapping the second vector block to a fourth storage unit of the linear feedback shift registers; Step 3, in the initialization stage, performing a plurality of rounds of nonlinear iteration operations on the mapped registers through a driver layer of the hardware layer to generate confusion state data, and in the working stage, performing a cyclic shift operation on the registers through the driver layer to generate shift state data, and from the shift state data, performing a bit reorganization operation on the shift state data through a solidification path to generate first reorganization data of the feedback shift registers and second reorganization data of the linear feedback shift registers; Step 4, performing three-level processing on the extracted first reorganization data and second reorganization data through a finite state machine of the hardware layer, the first level generating nonlinear transformation data by querying a permutation table, the second level processing the nonlinear transformation data by linear diffusion operation to generate diffusion data, and the third level performing exclusive or operation on the diffusion data to generate a key stream; Step 5, receiving input data to be encrypted, performing exclusive or operation on the key stream and the input data bit by bit through a bit-wise exclusive or unit, and outputting generated encrypted data stream.

2. The method of claim 1, wherein, The step 1 comprises: receiving a 128-bit key and a 96-bit initial vector; splitting the 128-bit key into four 32-bit key blocks; splitting the 96-bit initial vector into three 32-bit vector blocks; mapping the four key blocks to the first storage unit, the second storage unit, the third storage unit and the fourth storage unit of the feedback shift registers respectively; mapping the three vector blocks to the fifth storage unit, the sixth storage unit and the seventh storage unit of the linear feedback shift registers respectively.

3. The method of claim 1, wherein, The step 3 comprises: in the initialization stage, the driver layer performs 32 rounds of composite operations on the feedback shift registers and the linear feedback shift registers, the 32 rounds of composite operations including modulo addition and cyclic shift, reading the storage unit data of the registers, performing modulo addition operation to generate intermediate data, and performing cyclic shift on the intermediate data; in the working stage, the driver layer performs a single-step cyclic shift operation, reads the shift state data, and performs a single-bit cyclic right shift.

4. The method of claim 1, wherein, The step 3 comprises: locating a high 4-bit position from the storage unit of the feedback shift registers; extracting data at the high 4-bit position to generate first reorganization data; locating a fixed bit position determined according to a preset rule from the storage unit of the linear feedback shift registers; extracting data at the preset fixed bit position to generate second reorganization data.

5. The method of claim 1, wherein, The step 4 comprises: generating constant data required by the permutation table offline, and pre-burning the constant data to a read-only memory; In the permutation table query stage, constant data is read from the read-only memory to generate nonlinear transformation data; In the linear diffusion operation stage, the same set of registers of the finite state machine is multiplexed to perform, receive nonlinear transformation data, line diffusion, and store diffusion data.

6. The implementation method of a lightweight stream cipher according to claim 5, wherein, The step 4 further comprises: Receiving first reorganization data; Splitting the first reorganization data into eight 32-bit sub-data segments; Synchronously accessing the permutation table of the read-only memory through eight independent query channels; Splicing the eight query results into 256-bit nonlinear transformation data.

7. The method of claim 1, wherein, The step 3 further comprises: Generating 256-bit constant data required by the permutation table offline; Pre-storing the constant data to the eighth storage unit of the linear feedback shift register preset; In the initialization stage, the driving layer reads the constant data from the eighth storage unit; Inputting the read constant data for use in the permutation table query stage.

8. The method of claim 1, wherein, The step 3 further comprises: Monitoring the radiation interference signal of the spaceborne device; When detecting the radiation interference, injecting a 4-bit redundancy check bit into the shift state data in the driving layer working stage; Performing parity check calculation on the shift state data containing the check bit through the cyclic shift check chain; Correcting the error bits of the shift state data according to the check result.

9. A system for implementing a lightweight stream cipher, applied to the method for implementing a lightweight stream cipher according to any one of claims 1 to 8, characterized in that, Comprise: An acquisition device for acquiring a key and an initial vector; A segmentation device for segmenting the key into a first key block and a second key block and segmenting the initial vector into a first vector block and a second vector block through a physical isolation mechanism; A mapping device for mapping the segmented key blocks and vector blocks to the designated storage units of the feedback shift register and the linear feedback shift register defined by the hardware layer, respectively; A driving device for performing multiple rounds of nonlinear iteration operations in the initialization stage to generate confusion state data and performing cyclic shift operations in the working stage to generate shift state data, the cyclic shift operation comprising modulo addition and cyclic shift; A reorganization device for extracting first reorganization data of the feedback shift register and second reorganization data of the linear feedback shift register from the shift state data through a solidification path; A state machine device for performing three-stage pipeline operations on the first reorganization data and the second reorganization data to generate a keystream; An encryption device for receiving input data, performing XOR operation between the keystream and the input data bit by bit through a bitwise XOR unit, and outputting an encrypted data stream.

10. An electronic device, comprising: Comprise: A memory for storing a computer program; A processor for implementing the steps of the implementation method of the lightweight stream cipher as claimed in any one of claims 1 to 8 when executing the computer program.

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