Electronic device and manufacturing method thereof

Abstract

The invention provides an electronic device and a manufacturing method thereof. The manufacturing method of the electronic device comprises the following steps of: (a) providing a circuit substrate which comprises a substrate; a plurality of electronic units disposed on the substrate; and a first bonding member disposed on the substrate, where the first bonding member surrounds the electronic unit in a plan view direction of the circuit substrate; (b) a plurality of cover plates are respectively arranged on at least one part of the electronic units, a bonding material is arranged on the first bonding piece, one of the cover plates comprises a second bonding piece, the second bonding piece is overlapped with at least one part of the first bonding piece in the plan view direction of the circuit substrate, and the bonding material is not overlapped with the second bonding piece; and (c) melting the bonding material so that the bonding material flows between the first bonding member and the second bonding member.

Description

Technical Field

[0001] This disclosure relates to an electronic device and a method of manufacturing the same, specifically an electronic device comprising a cover plate and a method of manufacturing the same. Background Technology

[0002] In the manufacturing process of electronic devices, such as during packaging, a cover plate is typically assembled with a circuit substrate, and then cut to form multiple independent electronic units. Traditional processes often use bonding materials to achieve the assembly of the cover plate and the circuit substrate.

[0003] However, in traditional processes, bonding materials can easily overflow or be squeezed out of the bonding area. This can cause bonding materials to flow into the sealed space, affecting the function of the electronic unit and causing it to operate poorly, or resulting in poor vacuum after assembly, or material waste due to abnormal packaging of electronic units.

[0004] Therefore, there is an urgent need to provide an electronic device and its manufacturing method in order to improve the defects. Summary of the Invention

[0005] This disclosure provides a method for manufacturing an electronic device, characterized by comprising the following steps: (a) providing a circuit substrate comprising: a substrate; a plurality of electronic units disposed on the substrate; and a first bonding member disposed on the substrate, wherein, in a plan view of the circuit substrate, the first bonding member surrounds the electronic units; (b) respectively disposing of a plurality of cover plates on at least a portion of the electronic units, and disposing of a bonding material on the first bonding member, wherein one of the cover plates includes a second bonding member, in a plan view of the circuit substrate, the second bonding member overlaps with at least a portion of the first bonding member, and the bonding material does not overlap with the second bonding member; and (c) melting the bonding material, causing a portion of the bonding material to flow between the first bonding member and the second bonding member.

[0006] This disclosure further provides an electronic device, characterized in that it comprises: a circuit substrate, the circuit substrate comprising: a substrate; an electronic unit disposed on the substrate; and a first bonding member disposed on the substrate and surrounding the electronic unit; a cover plate disposed on the first bonding member, wherein the cover plate comprises a second bonding member, the cover plate overlapping the electronic unit in a top view of the circuit substrate, and the second bonding member overlapping at least a portion of the first bonding member; and a bonding material comprising a first portion and a second portion, the first portion being disposed between the first bonding member and the second bonding member, the second portion being disposed on the first bonding member, wherein, in a top view of the circuit substrate, the second portion does not overlap with the second bonding member; wherein the thickness of the first portion of the bonding material is less than the thickness of the second portion. One objective of this invention is to provide a method for manufacturing a high-density terminal module, which can set multiple sets of terminals on multiple carrier areas of a tooling plate through a batch terminal aligning process and cut the tooling plate through a batch cutting process to produce multiple terminal modules, thereby efficiently meeting the pin mounting requirements of multiple circuit units on a wafer or a circuit board. Attached Figure Description

[0007] Figure 1 A flowchart illustrating a method for manufacturing an electronic device according to an embodiment of the present disclosure is shown.

[0008] Figures 2A to 2F A schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present disclosure is shown.

[0009] Figures 3A to 3F A schematic diagram of a method for manufacturing an electronic device according to another embodiment of the present disclosure is shown.

[0010] Figure 4 A cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0011] Figure 5A and Figure 5B An enlarged schematic diagram of a portion of the electronic device according to an embodiment of the present disclosure is shown.

[0012] Figure 6 A schematic diagram of an electronic unit according to an embodiment of the present disclosure is shown.

[0013] Figure 7A and Figure 7B A schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present disclosure is shown.

[0014] Figure 8 A cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0015] Symbol Explanation

[0016] a, b, c, d Step a, step b, step c, step d

[0017] 1 Circuit substrate

[0018] 11 Substrate

[0019] 12 Circuit Layers

[0020] 12s sidewall

[0021] 121 Connection Unit

[0022] 13 First joint

[0023] 13e1 Edge

[0024] 13s sidewall

[0025] 14 Limiting components

[0026] 14s sidewall

[0027] 2. Cover plate

[0028] 21 Ontology

[0029] 21s1 side

[0030] 21s2 sidewall

[0031] 22 Second joint

[0032] 22e1 Edge

[0033] 22e2 Another edge

[0034] 23 Anti-reflective layer

[0035] 3. Bonding materials

[0036] 31 Part One

[0037] 31e1 edge

[0038] 32 Part Two

[0039] 32s surface

[0040] 4 lenses

[0041] 4s side

[0042] D1 First Driver

[0043] D2 Second Drive

[0044] E and E' electronic units

[0045] E1 Electronic Components

[0046] H1 and H2 openings

[0047] L1 First conductor

[0048] L2 Second wire

[0049] L3 and L4 wires

[0050] M monomer

[0051] P element

[0052] R1 Overlapping Area

[0053] SP sealed space

[0054] T1 First Thickness

[0055] T2 Second Thickness

[0056] W1 First Width

[0057] W2 Second Width

[0058] X and Y directions

[0059] Z (Top view) Detailed Implementation

[0060] The following describes the implementation of this disclosure through specific embodiments. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed for different viewpoints and applications without departing from the spirit of the embodiments of this disclosure.

[0061] It should be noted that, unless otherwise specified herein, the presence of an element "a" is not limited to having a single element, but may include one or more of the elements. Furthermore, the ordinal numbers used in the specification and claims, such as "first" and "second," to modify elements of a claim, do not in themselves indicate or represent any prior ordinal number for that claimed element, nor do they represent the order of one claimed element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely for the purpose of clearly distinguishing one claimed element with a given name from another claimed element with the same name.

[0062] Throughout this disclosure and in the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as “comprising,” “containing,” and “having” are open-ended terms and should therefore be interpreted as “containing but not limited to…”. Thus, when the terms “comprising,” “containing,” and / or “having” are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0063] In this text, the terms "about," "approximately," "substantially," and "roughly" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantity is an approximate quantity; that is, even without specific mention of "about," "approximately," "substantially," or "roughly," the meaning of these terms is implied. Furthermore, the phrases "range from the first value to the second value" or "range between the first value and the second value" indicate that the range includes the first value, the second value, and other values ​​in between.

[0064] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined herein.

[0065] Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one element to another in the figures. It is understood that if the apparatus in the figures is flipped upside down, the element described as being on the "below" side will become the element on the "above" side. When a corresponding component (e.g., a membrane or region) is referred to as "on another component," it can be directly on the other component, or there may be other components between them. On the other hand, when a component is referred to as "directly on another component," there are no components between them. Additionally, when a component is referred to as "on another component," there is a vertical relationship between them in the top view, and this component can be above or below the other component, depending on the orientation of the apparatus.

[0066] In this disclosure, the distance, width, length, and thickness can be measured using an optical microscope, or they can be measured from cross-sectional images in an electron microscope, but this disclosure is not limited to these methods. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error of approximately 10% between the two values; if the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions may be between 0 and 10 degrees.

[0067] It should be noted that the technical solutions provided in the different embodiments below can be substituted for, combined or mixed with each other to constitute another embodiment without violating the spirit of this disclosure.

[0068] The electronic devices disclosed herein may include, for example, display devices, sensing devices, antenna devices, touch devices, splicing devices, or other suitable electronic devices, but are not limited thereto. The display devices disclosed herein may be non-emissive display devices or emissive display devices, such as liquid crystal displays, cholesteric liquid crystal displays, electrophoretic displays, organic light-emitting diode displays, and light-emitting diode displays, but are not limited thereto. The display devices may include light-emitting diodes, light conversion layers, or other suitable materials, or combinations thereof, but are not limited thereto. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs (including QLEDs and QDLEDs), but are not limited thereto. The light conversion layer may include wavelength conversion materials and / or filter materials. The light conversion layer may include, for example, fluorescence, phosphorescence, quantum dots (QD), other suitable materials, or combinations thereof, but is not limited thereto. The sensing device may include, for example, biosensors, touch sensors, fingerprint sensors, infrared sensors, temperature sensors, other suitable sensors, or combinations of the above types of sensors. The antenna device may be, for example, a liquid crystal antenna or other types of antennas, but is not limited thereto. The splicing device may include, for example, a splicing display device or a splicing antenna device, but is not limited thereto. The electronic device may include electronic components, which may include passive components, active components, or combinations thereof, such as capacitors, resistors, inductors, varactor diodes, variable capacitors, filters, diodes, transistors, sensors, microelectromechanical systems (MEMS) components, chips, etc., but is not limited thereto. It should be noted that the electronic device disclosed herein may be various combinations of the above devices, but is not limited thereto.

[0069] Figure 1 This is a flowchart illustrating a method for manufacturing an electronic device according to an embodiment of the present disclosure. Figures 2A to 2F This is a schematic diagram illustrating a method for manufacturing an electronic device according to an embodiment of the present disclosure. Wherein, Figures 2A to 2FThe upper part of the diagram is a top view, and the lower part is a cross-sectional view. For ease of explanation, some components have been omitted from the diagram.

[0070] In one embodiment of this disclosure, such as Figure 1 and Figure 2A As shown, a method for manufacturing an electronic device may include: step a, providing a circuit substrate 1. The circuit substrate 1 may include: a substrate 11; a plurality of electronic units E disposed on the substrate 11; and a first bonding member 13 disposed on the substrate 11, wherein the first bonding member 13 includes a plurality of openings H1, and in the top view Z direction of the circuit substrate 1, the first bonding member 13 surrounds the plurality of electronic units E, and the openings H1 of the first bonding member 13 expose the electronic units E respectively.

[0071] More in detail, such as Figure 2A As shown, the circuit substrate 1 may include a circuit layer 12 disposed on the substrate 11. The circuit layer 12 may include a plurality of electronic units E. A first bonding member 13 is disposed on the circuit layer 12, and in the top view Z direction of the circuit substrate 1, the first bonding member 13 may be disposed around the electronic unit E. Therefore, in the top view Z direction of the circuit substrate 1, the projected area of ​​the opening H1 of the first bonding member 13 on the substrate 11 may be approximately equal to the projected area of ​​the electronic unit E on the substrate 11, and in the top view Z direction of the circuit substrate 1, the opening H1 may expose the electronic unit E. More specifically, as... Figure 2A As shown, circuit layer 12 may include multiple regions. The region exposed by opening H1 is the electronic unit E, and the region covered by the first bonding member 13 is the connection unit 121, wherein the electronic unit E is surrounded by the connection unit 121. The connection unit refers, for example, to a portion of circuit layer 12 that does not have wires or does not have the function of releasing or receiving signals.

[0072] In this disclosure, the material of the substrate 11 may include glass, quartz, sapphire, ceramic, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polymethyl methacrylate (PMMA), other suitable materials or combinations thereof, but this disclosure is not limited thereto.

[0073] In this disclosure, the material of the first bonding member 13 may include aluminum, nickel, gold, palladium (Pd), copper, titanium, the aforementioned alloys, or combinations thereof. In this disclosure, the first bonding member 13 may have a single-layer or multi-layer structure, and the layers may be made of the same or different materials. For example, the first bonding member 13 may have a multi-layer structure of aluminum / nickel / copper, aluminum / nickel / palladium / gold, copper / nickel / gold, copper / gold / palladium / gold, or titanium / copper, but this disclosure is not limited thereto. In this disclosure, the thickness of the first bonding member 13 may be from 0.1 μm to 500 μm, for example, from 50 μm to 500 μm, but this disclosure is not limited thereto. When the material of the first bonding member 13 includes gold (Au), the thickness of the gold (Au) layer may be from 10 nm to 100 nm or from 100 nm to 2000 nm, but this disclosure is not limited thereto; the gold layer can be used to provide a good bonding effect. When the material of the first bonding member 13 contains palladium (Pd), the thickness of the palladium (Pd) layer can be from 10 nm to 500 nm, but this disclosure is not limited to this. The palladium layer can be used to prevent diffusion of the metal materials in the upper and lower layers, which could lead to abnormalities in subsequent steps. In this disclosure, the thickness of the first bonding member 13 refers, for example, to the distance between the side of the first bonding member 13 away from the substrate 11 and the side of the first bonding member 13 adjacent to the substrate 11.

[0074] In this disclosure, circuit layer 12 may further include wires, pads, sensors, drive circuits, other suitable components, or combinations thereof. Suitable components may include passive components, active components, or combinations thereof, such as capacitors, resistors, inductors, diodes, transistors, etc., but this disclosure is not limited thereto. Diodes may include light-emitting diodes or photodiodes. Light-emitting diodes include organic light-emitting diodes (OLEDs), miniLEDs, microLEDs, or quantum dot LEDs (QDs, such as QLEDs, QDLEDs), or other suitable materials or any arrangement and combination of the above materials, but this disclosure is not limited thereto. In this disclosure, the size of the electronic units E in circuit layer 12 is not particularly limited, and the size of each electronic unit E can be adjusted as needed, for example... Figure 2A In this disclosure, the size of the central electronic unit E may be larger than the size of the electronic units E on the left or right, but this disclosure is not limited thereto. The size of the electronic unit refers, for example, to the maximum width or length of the electronic unit E in a direction (e.g., the X direction).

[0075] Then, as Figure 1 , Figure 2B-1 and Figure 2CAs shown, the manufacturing method of the electronic device may include: step b, respectively, setting a plurality of cover plates 2 on at least a portion of the electronic unit E, and setting a bonding material 3 on the first bonding member 13. One of the cover plates 2 includes a second bonding member 22, which overlaps with at least a portion of the first bonding member 13 in the top view Z direction of the circuit substrate 1, and the bonding material 3 does not overlap with the second bonding member 22.

[0076] More in detail, such as Figure 2B-1 and Figure 2B-2 As shown, where, Figure 2B-2 This is a top view of the cover plate 2. The cover plate 2 may include a body 21 and a second connecting member 22. The second connecting member 22 is disposed on one side 21s1 of the body 21. The second connecting member 22 forms an annular structure adjacent to the edge of the body 21, and the edge of the annular structure is approximately aligned with the edge of the body 21. An opening H2 surrounded by the annular structure exposes a portion of that side 21s1 of the body 21, and the area of ​​the opening H2 surrounded by the annular structure is approximately the same as the area of ​​the opening H1 of the first connecting member 13. In this disclosure, as... Figure 2B-1 As shown, one cover plate 2 corresponds to one electronic unit E, and the area of ​​the opening H1 of the first bonding member 13 is approximately equal to the area of ​​the opening H2 of the second bonding member 22. The second bonding member 22 is disposed on the side 21s1 of the body 21 facing the circuit substrate 1, so that the cover plate 2 and the circuit substrate 1 can be assembled using the first bonding member 13 and the second bonding member 22. In one embodiment of this disclosure, in the top view Z direction of the circuit substrate 1, the projected area of ​​the body 21 of the cover plate 2 on the substrate 11 is greater than the projected area of ​​the opening H of the first bonding member 13 on the substrate 11. Furthermore, as Figure 2C As shown, in the top view Z direction of the circuit substrate 1, the first bonding member 13 has an overlapping region R1 that overlaps with the second bonding member 22, and the bonding material 3 is disposed on the first bonding member 13 outside the overlapping region R1, wherein, in the top view Z direction, the overlapping region R1 surrounds the electronic unit E.

[0077] In this disclosure, there are no particular restrictions on the order in which the cover plate 2 and the coupling material 3 are arranged, for example, in this embodiment, as shown in Figure 2B and Figure 2C As shown, multiple cover plates 2 are first set on at least a portion of the electronic unit E, and then bonding material 3 is set on the first bonding member 13. However, this disclosure is not limited to this. In other embodiments of this disclosure, bonding material 3 may be set on the first bonding member 13 first, and then multiple cover plates 2 may be set on at least a portion of the electronic unit E.

[0078] In one embodiment of this disclosure, in the top view Z direction of the circuit substrate 1, the bonding material 3 can be placed or formed between two adjacent electronic units E. More specifically, in the top view of the circuit substrate 1, as shown... Figure 2CAs shown, the bonding material 3 may be placed or formed between two adjacent electronic units E, but this disclosure is not limited thereto. In other embodiments of this disclosure, although not shown in the figures, the bonding material 3 may be placed or formed on one side of the electronic unit E, for example, in a top view of the circuit substrate 1, the bonding material 3 may be placed or formed on the upper side of the electronic unit E; or the bonding material 3 may be placed or formed on the lower side of the electronic unit E; or the bonding material 3 may be placed or formed on the upper and lower sides of the electronic unit E, but this disclosure is not limited thereto.

[0079] In this disclosure, the material of the body 21 may include silicon, germanium (Ge), zinc sulfide (ZnS), zinc selenide (ZnSe), gallium arsenide (GaAs), chalcogenides, or combinations thereof, but this disclosure is not limited thereto. In one embodiment of this disclosure, the body 21 may be composed of, for example, a silicon substrate that allows light of a specific wavelength (e.g., light with a wavelength of 5 μm to 15 μm) to pass through, but this disclosure is not limited thereto. In this disclosure, the second bonding member 22 may be fabricated using the same or different materials as the first bonding member 13, and the material of the second bonding member 22 may be as described for the first bonding member 13, and will not be repeated here. In this disclosure, the thickness of the second bonding member 22 may be from 0.1 μm to 500 μm, for example, from 50 μm to 500 μm, but this disclosure is not limited thereto. In this disclosure, the thickness of the second bonding member 22 may be greater than or equal to the thickness of the first bonding member 13.

[0080] In this disclosure, the bonding material 3 may comprise solder, solder paste, or a combination thereof, but this disclosure is not limited thereto. In this disclosure, the bonding material 3 may comprise tin, tin alloys, or a combination thereof, but this disclosure is not limited thereto. Because tin has a low melting point, when the bonding material 3 contains tin, the temperature of the subsequent melting of the bonding material 3 can be reduced, thereby reducing damage to the circuit substrate 1 caused by excessive temperature.

[0081] After that, as Figure 1 and Figure 2D As shown, a method for manufacturing an electronic device may include: step c, melting and bonding material 3, causing a portion of the bonding material 3 to flow between the first bonding member 13 and the second bonding member 22. More specifically, as... Figure 2D As shown, the bonding material 3 can be heated to melt it into a liquid or semi-liquid state and flow into the overlapping area R1 of the first bonding member 13 and the second bonding member 22, thereby bonding the first bonding member 13 and the second bonding member 22 through the bonding material 3, achieving the purpose of assembling the cover plate 2 and the circuit substrate 1. Therefore, a sealed space SP can be formed between the cover plate 2 and the circuit substrate 1, and the electronic unit E exists in the sealed space SP.

[0082] In this disclosure, by heating and melting the bonding material 3, the cover plate 2 and the circuit substrate 1 can be assembled. Therefore, when manufacturing electronic devices using the method of this disclosure, the overflow or extrusion of the bonding material 3 into the sealing space SP between the cover plate 2 and the circuit substrate 1 can be reduced, thereby reducing interference with the electronic unit E (e.g., sensing sensitivity) and improving the yield rate of the electronic device. Furthermore, in other embodiments, other process conditions, such as pressure, can be added as needed to assist in the assembly effect.

[0083] In one embodiment of this disclosure, the temperature of the heating bonding material 3 may be greater than or equal to the melting temperature of the bonding material 3, for example, it may be 90°C to 450°C, 150°C to 450°C, or 200°C to 400°C, but this disclosure is not limited thereto. In this disclosure, the pressurization refers to the application of a pressure, for example, greater than 0.1 MPa, during the process of melting the bonding material 3.

[0084] In this disclosure, because the first joining member 13 has an affinity with the joining material 3, after the joining material 3 is melted, the joining material 3 will flow along the position of the first joining member 13. Therefore, as Figure 2D As shown, in the top view Z direction of the circuit substrate 1, the bonding material 3 overlaps with at least a portion of the first bonding member 13. In one embodiment of this disclosure, the projected area of ​​the bonding material 3 on the substrate 11 may be approximately equal to the projected area of ​​the first bonding member 13 on the substrate 11. In one embodiment of this disclosure, as... Figure 2D As shown, the bonding material 3 may include a first portion 31 and a second portion 32, the first portion 31 being connected to the second portion 32. The first portion 31 is disposed between the first bonding member 13 and the second bonding member 22, and the second portion 32 is disposed on the first bonding member 13. In the top view Z direction of the circuit substrate 1, the second portion 32 does not overlap with the second bonding member 22. In other words, the first portion 31 of the bonding material 3 is disposed within the overlapping region R1, and the second portion 32 of the bonding material 3 is disposed on the first bonding member 13 outside the overlapping region R1.

[0085] In one embodiment of this disclosure, before step c, the method may further include placing the circuit substrate 1 in a cavity (not shown) and evacuating the cavity. In this disclosure, the evacuation step can be performed at any stage before step c. For example, after performing step a, the circuit substrate 1 can be placed in the cavity and the cavity evacuated, followed by subsequent steps such as step b; or in step b, after setting multiple cover plates 2 on at least a portion of the electronic unit E, the circuit substrate 1 can be placed in the cavity and the cavity evacuated, followed by subsequent steps such as setting the bonding material 3 on the first bonding member 13; or after performing steps a and b, the circuit substrate 1 can be placed in the cavity and the cavity evacuated, followed by subsequent steps such as step c, but this disclosure is not limited to these methods. In this disclosure, the vacuum refers to a pressure within the cavity, for example, less than or equal to 1 torr. For example, the pressure within the cavity can be 10⁻³ torr to 1 torr or 10⁻⁷ torr to 1 torr, but this disclosure is not limited to these methods. In this disclosure, since multiple cover plates 2 are used in combination with a circuit substrate 1, it is less likely that the vacuum level of the center and the edge of the circuit substrate 1 will be inconsistent during the vacuuming step, thereby improving the vacuum effect in the sealed space SP.

[0086] Then, as Figure 1 , Figure 2E and Figure 2F As shown, a method for manufacturing an electronic device may include: step d, cutting a circuit substrate 1 and a bonding material 3 to form a plurality of monomers M. More specifically, this may be achieved, for example, along... Figure 2E The dashed lines in the diagram represent cuts made of the bonding material 3, the first bonding member 13, the circuit layer 12, and the substrate 11, respectively, to form a monomer M of appropriate size, as shown below. Figure 2F As shown. In this embodiment, Figure 2E The dashed lines in the diagram roughly represent cuts along the dimensions of circuit layer 1-2. Therefore, as shown... Figure 2F As shown, the projected area of ​​the circuit layer 12 in the monomer M can be approximately equal to the projected area of ​​the substrate 11. However, in other embodiments of this disclosure, the projected area of ​​the substrate 11 in the monomer M can be larger than the projected area of ​​the circuit layer 12. In this disclosure, the method of cutting the circuit substrate 1 and the bonding material 3 can be performed, for example, by laser cutting, rotary cutting, or a combination thereof. In one embodiment of this disclosure, the monomer M can be an electronic device, or in other embodiments, the electronic device can include multiple monomers M, but this disclosure is not limited thereto. In this disclosure, the monomer M can have the function of receiving or emitting signals, such as sensing temperature or emitting light, but this disclosure is not limited thereto.

[0087] Figures 3A to 3F This is a schematic diagram illustrating a method for manufacturing an electronic device according to another embodiment of the present disclosure. Wherein, Figures 3A to 3F Manufacturing method and Figures 2A to 2F The manufacturing methods are similar, except for the following differences.

[0088] In one embodiment of this disclosure, such as Figure 3A As shown, a method for manufacturing an electronic device may include: step a, providing a circuit substrate 1. Details of the circuit substrate 1 are as previously described and will not be repeated here. Next, as... Figure 3B and Figure 3C As shown, the manufacturing method of the electronic device may include: step b, respectively setting a plurality of cover plates 2 on at least a portion of the electronic unit E, and setting a bonding material 3 on the first bonding member 13. More specifically, step b includes: detecting the electronic unit E on the circuit substrate 1 and determining whether the electronic unit E is normal or defective; and respectively setting cover plates 2 on normal electronic units E, but not setting cover plates 2 on defective electronic units E'. The details of the cover plates 2 and the bonding material 3 are as described above and will not be repeated here. In the figure, the defective electronic unit E' is represented by a black filled pattern. In this embodiment, Figure 3A The example uses two normal electronic units E and one abnormal electronic unit E', but this disclosure is not limited thereto.

[0089] In one embodiment of this disclosure, electronic unit E can be first detected to determine whether it is normal or defective, and then cover plate 2 can be placed on normal electronic unit E, thereby reducing the waste of cover plate 2 and achieving the effect of reducing manufacturing costs. In this disclosure, a normal electronic unit refers to electronic unit E whose appearance, electrical properties, etc., are normal and can be operated. An "abnormal electronic unit" refers to electronic unit E' whose appearance, electrical properties, or a combination thereof are abnormal. In this disclosure, detecting electronic unit E includes performing electrical testing, electrostatic discharge testing, appearance testing, other suitable testing, or combinations thereof on electronic unit E, but this disclosure is not limited to these.

[0090] After that, as Figure 3D As shown, the manufacturing method of the electronic device may include: step c, melting and bonding material 3, so that a portion of the bonding material 3 flows between the first bonding member 13 and the second bonding member 22. The details of the step of melting and bonding material 3 are as previously described and will not be repeated here.

[0091] In one embodiment of this disclosure, the step c may further include: placing the circuit substrate 1 in a cavity (not shown) and evacuating the cavity. In this disclosure, the aforementioned vacuuming step can be performed at any stage before step c. For example, after performing step a, the circuit substrate 1 can be placed in the cavity and the cavity can be evacuated, followed by subsequent steps such as step b; or in step b, after detecting and determining the electronic unit E on the circuit substrate 1, the circuit substrate 1 can be placed in the cavity and the cavity can be evacuated, then cover plates 2 can be set on normal electronic units E respectively, but not on defective electronic units E', followed by subsequent steps such as setting bonding material 3 on the first bonding member 13; or in step b, after setting cover plates 2 on normal electronic units E respectively, but not on defective electronic units E', the circuit substrate 1 can be placed in the cavity and the cavity can be evacuated, followed by subsequent steps such as setting bonding material 2 on the first bonding member 13; or after performing steps a and b, the circuit substrate 1 can be placed in the cavity and the cavity can be evacuated, followed by subsequent steps such as step c, but this disclosure is not limited to these. In this disclosure, the vacuum refers to a pressure within the cavity, for example, less than or equal to 1 torr, such as 10⁻³ to 1 torr or 10⁻⁷ to 1 torr, but this disclosure is not limited thereto.

[0092] Then, as Figure 3E and Figure 3F As shown, the method for manufacturing an electronic device may include: step d, cutting the circuit substrate 1 and the bonding material 3 to form a plurality of monomers M. The details of the cutting step are as previously described and will not be repeated here. In one embodiment of this disclosure, as... Figure 3F As shown, since it is not necessary to assemble the cover plate 2 for the abnormal electronic unit E', the cost can be reduced.

[0093] The electronic device manufactured by the above method can be as follows: Figures 4 to 5B As shown, the following will provide a detailed explanation.

[0094] Figure 4 This is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 5A and Figure 5B This is an enlarged schematic diagram of a portion of the electronic device according to an embodiment of the present disclosure. Figure 5A and Figure 5B They are respectively Figure 4 Enlarged view of the area indicated by the dotted line.

[0095] In one embodiment of this disclosure, such as Figure 4As shown, the electronic device includes: a circuit substrate 1, comprising: a substrate 11; an electronic unit E disposed on the substrate 11; and a first bonding member 13 disposed on the substrate 11 and surrounding the electronic unit E; a cover plate 2 disposed on the first bonding member 13, wherein the cover plate 2 includes a second bonding member 22, which overlaps with the electronic unit E in the top view Z direction of the circuit substrate 1, and the second bonding member 22 overlaps with at least a portion of the first bonding member 13; and a bonding material 3, comprising a first portion 31 and a second portion 32, the first portion 31 being disposed between the first bonding member 13 and the second bonding member 22, and the second portion 32 being disposed on the first bonding member 13, wherein the second portion 32 does not overlap with the second bonding member 22 in the top view Z direction of the circuit substrate 1; wherein the thickness of the first portion 31 of the bonding material 3 (i.e., the first thickness T1) is less than the thickness of the second portion 32 (i.e., the second thickness T2).

[0096] More specifically, the circuit substrate 1 may include a circuit layer 12 disposed on the substrate 11. The circuit layer 12 may include an electronic unit E. A first bonding member 13 is disposed on the circuit layer 12, and in the top view Z direction of the circuit substrate 1, the first bonding member 13 may be disposed around the electronic unit E. The first bonding member 13 may include an opening H, and in the top view Z direction of the circuit substrate 1, the opening H of the first bonding member 13 corresponds to the electronic unit E. In one embodiment of this disclosure, in the top view Z direction of the circuit substrate 1, the projected area of ​​the opening H of the first bonding member 13 on the substrate 11 may be approximately equal to the projected area of ​​the electronic unit E on the substrate 11. In this disclosure, the cover plate 2 may include a body 21 and a second bonding member 22. The second bonding member 22 is disposed on the body 21, wherein the second bonding member 22 is disposed on the side of the body 21 facing the circuit substrate 1; in other words, the second bonding member 22 is closer to the circuit substrate 1 than the body 21. The first connector 13 and the second connector 22 can be joined by the connector material 3 to form a sealed space SP between the cover plate 2 and the electronic unit E.

[0097] In this disclosure, such as Figures 4 to 5B As shown, in one direction (e.g., the X direction), the first joint 13 has a first width W1, and the second joint 22 has a second width W2, wherein the first width W1 is greater than the second width W2. In this disclosure, as... Figure 4As shown, in the top view Z direction of the circuit substrate 1, the first bonding member 13 has an overlapping region R1 that overlaps with the second bonding member 22. More specifically, a first portion 31 of the bonding material 3 is disposed within the overlapping region R1, and a second portion 32 of the bonding material 3 is disposed on the first bonding member 13 outside the overlapping region R1. In this disclosure, the first portion 31 of the bonding material 3 has a first thickness T1, and the second portion 32 of the bonding material 3 has a second thickness T2, wherein the first thickness T1 is less than the second thickness T2. In one embodiment of this disclosure, the second thickness T2 may be from 50 μm to 500 μm. When the first thickness T1 and the second thickness T2 conform to the above design, the bonding material 3 can provide a good bonding effect and prevent unwanted substances (e.g., moisture, air, dust, or a combination thereof) from entering the sealed space SP.

[0098] In this disclosure, the "first width" refers, for example, to the maximum distance between an edge 13e1 of the first bonding member 13 and the opening H in a direction (e.g., the X direction). The second width refers, for example, to the maximum distance between an edge 22e1 of the second bonding member 22 and another edge 22e2 in a direction (e.g., the X direction), wherein the edge 22e1 of the second bonding member 22 is farther from the opening H than the other edge 22e2. In this disclosure, the "first thickness T1" refers, for example, to the maximum dimension of the first portion 31 of the bonding material 3 in the top view Z direction of the circuit substrate 1, or, for example, to the maximum height of the bonding material 3 between the first bonding member 13 and the second bonding member 22 in the overlapping region R1. The "second thickness" refers, for example, to the maximum dimension of the second portion 32 of the bonding material 3 in the top Z direction of the circuit substrate 1, or, since the second portion 32 of the bonding material 3 may have an uneven surface 32s, the second thickness T2 refers, for example, to the distance between the portion of the surface 32s of the second portion 32 furthest from the first bonding member 13 and the surface of the first bonding member 13 in a cross-section in a direction perpendicular to the substrate 11 (e.g., the Z direction). In one embodiment of this disclosure, since the bonding material 3 has an affinity with the second bonding member 22, the second portion 32 of the bonding material 3 may contact the edge 22e1 of the second bonding member 22.

[0099] In one embodiment of this disclosure, such as Figure 5A As shown, the first portion 31 of the bonding material 3 may have a recess, and the second portion 32 of the bonding material 3 may have an arcuate surface. The recess, for example, refers to an edge 31e1 of the first portion 31 of the bonding material 3 being recessed or close to the second portion 32 of the bonding material 3. The arcuate surface, for example, refers to a surface 32s of the second portion 32 of the bonding material 3 being an uneven surface.

[0100] In another embodiment of this disclosure, such as Figure 5BAs shown, the first portion 31 of the bonding material 3 may have a protrusion, and the second portion 32 of the bonding material 3 may have an arcuate surface. The protrusion, for example, refers to an edge 31e1 of the first portion 31 of the bonding material 3 protruding away from the second portion 32 of the bonding material 3. The arcuate surface, for example, refers to a surface 32s of the second portion 32 of the bonding material 3 being an uneven surface.

[0101] In one embodiment of this disclosure, such as Figure 4 As shown, the cover plate 2 may further include an anti-reflective layer 23 disposed on the body 21. More specifically, the cover plate 2 includes the body 21, a second bonding member 22, and the anti-reflective layer 23, wherein the second bonding member 22 is disposed on the side of the body 21 facing the circuit substrate 1, and the anti-reflective layer 23 is disposed on the side of the body 21 away from the circuit substrate 1. In other words, the body 21 of the cover plate 2 is located between the second bonding member 22 and the anti-reflective layer 23. In one embodiment of this disclosure, the anti-reflective layer 23 may be disposed on the side of the body 21 away from the circuit substrate 1. In another embodiment (not shown), the anti-reflective layer 23 may be disposed on the side of the body 21 away from the circuit substrate 1 and on the sidewall 21s2 of the body 21 of the cover plate 2, but is not limited thereto. The anti-reflective layer 23 can be used to reduce the reflection of light within a specified wavelength range and / or block light outside the specified wavelength range from entering, thereby improving the transmittance of light within the specified wavelength range. In one embodiment of this disclosure, the light within the specified wavelength range is, for example, light with a wavelength of 5 μm to 15 μm, but this disclosure is not limited thereto.

[0102] In one embodiment of this disclosure, the material of the antireflective layer 23 may include silicon, germanium (Ge), zinc sulfide (ZnS), zinc selenide (ZnSe), magnesium fluoride (MgF2), beryllium fluoride (BeF2), potassium chloride, arsenic trisulfide (As2S3), silicon oxide, silicon nitride, silicon oxynitride, indium tin oxide (ITO), aluminum zinc oxide (AZO), indium gallium zinc oxide (IGZO), antimony tin oxide (ATO), fluorine-doped tin oxide (FTO), or combinations thereof, but this disclosure is not limited thereto. In one embodiment of this disclosure, the antireflective layer 23 may include multiple high-refractive-index layers and multiple low-refractive-index layers, wherein the high-refractive-index layers and low-refractive-index layers are stacked alternately. Through the layer stacking design of different refractive indices, the antireflective layer 23 can achieve the effect of reducing reflected light. The high refractive index layer refers, for example, a film made of a material with a refractive index greater than or equal to 1.38 and less than or equal to 1.48. The low refractive index layer refers, for example, a film made of a material with a refractive index greater than or equal to 1.8 and less than or equal to 2.1.

[0103] Figure 6 This is a schematic diagram of an electronic unit according to an embodiment of the present disclosure. Wherein, Figure 6 The right side is a partial enlarged view of the left side, and for ease of explanation, some components, such as substrate 11 and cover plate 2, are omitted in the right figure.

[0104] In one embodiment of this disclosure, such as Figure 6As shown, the electronic unit E may include multiple electronic components E1; a first driver D1; and a second driver D2, wherein the first driver D1 and the second driver D2 are electrically connected to the multiple electronic components E1 respectively. More specifically, the first driver D1 and the second driver D2 may be electrically connected to each electronic component E1 via a first wire L1 and a second wire L2 respectively to transmit or receive signals. For example, the first driver D1 may transmit control signals via the first wire L1 to control the electronic component E1; or the second driver D2 may receive signals generated by the electronic component E1 via the second wire L2, but this disclosure is not limited thereto. In this disclosure, the electronic component E1 may include multiple transistors, wherein the transistors may further include semiconductors, gates, sources, and drains. In addition, the electronic component E1 may also include one or more sensing units (not shown), such as sensors or material structures that can absorb light wavelengths, wherein the multiple transistors may be electrically connected to one or more sensing units, but this disclosure is not limited thereto. Furthermore, the components within the electronic unit E may be fabricated using the same or different process methods, such as thin-film technology or by bonding the required components.

[0105] In one embodiment of this disclosure, such as Figure 6 As shown, the electronic device may further include a component P, electrically connected to a first driver D1 (e.g., a gate driver) and a second driver D2 (e.g., a data controller), wherein the first driver D1 and the second driver D2 can be manufactured using thin film processing, photolithography, or etching methods, but are not limited thereto. More specifically, component P can be electrically connected to the first driver D1 via wire L3 and to the second driver D2 via wire L4, and can be used, for example, to control or process signals transmitted to the first driver D1 or to receive signals from the second driver D2. In one embodiment of this disclosure, component P may be an integrated circuit (IC), but this disclosure is not limited thereto. Furthermore, although Figure 6 Taking one first driver D1 and one second driver D2 as an example, but in other embodiments of this disclosure, the electronic unit E may include multiple first drivers D1 and / or multiple second drivers D2, which can be electrically connected to the element P through multiple wires L3 and / or wires L4 respectively.

[0106] Figure 7A and Figure 7B A schematic diagram illustrating a method for manufacturing an electronic device according to an embodiment of the present disclosure is shown. Wherein, Figure 7A and Figure 7B The upper part of the diagram is a top view, and the lower part is a cross-sectional view. For ease of explanation, some components have been omitted from the diagram. Figure 7A and Figure 7B Manufacturing method and Figures 2C to 2D Similar, except for the following differences.

[0107] In one embodiment of this disclosure, such as Figure 7A and Figure 7B As shown, the circuit substrate 1 may further include a limiting member 14 disposed on the first bonding member 13, wherein, in the top view Z direction of the circuit substrate 1, the limiting member 14 is located around the electronic unit E. More specifically, the limiting member 14 is disposed on the substrate 11, the circuit layer 12 and the first bonding member 13, and the limiting member 14 may cover a portion of the circuit layer 12 and the first bonding member 13. In one embodiment of this disclosure, in a cross-sectional view, the limiting member 14 may contact the sidewall 12s of the circuit layer 12 and / or the sidewall 13s of the first bonding member 13.

[0108] In this disclosure, the material of the limiting member 14 may include organic materials, such as polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polybenzoxazole (PBO), benzocyclobutene (ECB), polyfluoroalkoxy (PFA), epoxy resin, photoresist, polymer or combinations thereof, but this disclosure is not limited thereto.

[0109] In one embodiment of this disclosure, after performing steps a and b, as follows: Figure 7A As shown, in the top view Z direction of the circuit substrate 1, the cover plate 2 and the limiting member 14 do not overlap, and the bonding material 3 and the limiting member 14 do not overlap. The limiting member 14 can be used to position the relative position of the cover plate 2 and / or the bonding material 3 with the circuit substrate 1, reducing displacement caused by external forces during the assembly of the circuit substrate 1 and the cover plate 2, and reducing the possibility of assembly tolerances or errors. In this disclosure, the details of the circuit substrate 1, the cover plate 2 and the bonding material 3 are as described above, and will not be repeated here.

[0110] Next, proceed with step c, melting and bonding material 3, as follows: Figure 7B As shown, the bonding material 3 is disposed between the limiting members 14. In one embodiment of this disclosure, as... Figure 7B As shown, the bonding material 3 can contact the sidewall 14s of the limiting member 14. Then, although not shown in the figure, refer to... Figure 2E and Figure 2FAs shown, the electronic device then undergoes step d, which involves cutting the circuit substrate 1 and the bonding material 3 to form a single unit. The details of the cutting step are as previously described and will not be repeated here. Therefore, in one embodiment of this disclosure, the electronic device may include a limiting member 14 disposed on the first bonding member 13. In one embodiment of this disclosure, step d may optionally include cutting the limiting member 14.

[0111] Furthermore, in one embodiment of this disclosure, step b may include: detecting electronic units E on the circuit substrate 1 and determining whether the electronic units E are normal or defective; and respectively setting cover plates 2 on normal electronic units E, but not setting cover plates 2 on defective electronic units E'. The details of the above-described steps for detecting electronic units E are as described above and will not be repeated here.

[0112] Figure 8 This is a schematic cross-sectional view of an electronic device according to an embodiment of the present disclosure. Figure 8 The electronic device shown is Figure 4 Similar, except for the following differences.

[0113] In one embodiment of this disclosure, the method of manufacturing the electronic device may further include the step of setting a lens 4 on the monomer M. Therefore, as... Figure 8 As shown, the electronic device may include a lens 4 disposed on the cover plate 2. More specifically, the lens 4 is disposed on the side of the body 21 of the cover plate 2 away from the circuit substrate 1. The lens 4 allows light of a specific wavelength range to pass through and be focused, thereby improving the transmittance of light within that specific wavelength range. In one embodiment of this disclosure, the electronic device may also include an anti-reflective layer 23 (such as...). Figure 4 As shown), it is positioned on the side of lens 4 away from cover plate 2, 4s; or, in other embodiments, refer to... Figure 8 Anti-reflective layer 23 (e.g.) Figure 4 (As shown) can be set on the side 4s of the lens 4 away from the cover plate 2 and on the side wall 21s2 of the body 21 of the cover plate 2.

[0114] In this disclosure, the material of lens 4 may include silicon, germanium (Ge), chalcogenide glass, gallium arsenide (GaAs), zinc sulfide (ZnS), zinc selenide (ZnSe), or combinations thereof, but this disclosure is not limited thereto. Other details of the circuit substrate 1, cover plate 2, and bonding material 3 in this disclosure are as previously described and will not be repeated here.

[0115] This disclosure, by providing a first bonding member 13, a second bonding member 22, and a bonding material 3, and in conjunction with the manufacturing method of this disclosure, can reduce the overflow or extrusion of the bonding material 3 into the sealed space SP between the cover plate 2 and the circuit substrate 1, thereby improving the yield rate of electronic devices. Furthermore, by using multiple cover plates 2 paired with a circuit substrate 1, this disclosure can improve the vacuum effect within the sealed space SP or reduce costs.

[0116] The specific embodiments described above should be interpreted as merely illustrative and not as limiting the remainder of this disclosure in any way.

Claims

1. A method for manufacturing an electronic device, characterized in that, Includes the following steps: (a) A circuit substrate is provided, the circuit substrate comprising: a substrate; a plurality of electronic units disposed on the substrate; and a first bonding member disposed on the substrate, wherein, in a plan view of the circuit substrate, the first bonding member surrounds the electronic units; (b) A plurality of cover plates are respectively disposed on at least a portion of the electronic units, and a bonding material is disposed on the first bonding member, wherein one of the cover plates includes a second bonding member, which overlaps at least a portion of the first bonding member in a plan view of the circuit substrate, and the bonding material does not overlap with the second bonding member; and (c) Melt the bonding material so that a portion of the bonding material flows between the first joint and the second joint.

2. The manufacturing method according to claim 1, characterized in that, It also includes the step of cutting the circuit substrate and the bonding material to form a plurality of monomers.

3. The manufacturing method according to claim 2, characterized in that, It also includes the step of setting multiple lenses on these individual units respectively.

4. The manufacturing method according to claim 1, characterized in that, Step (b) includes: The electronic units on the circuit substrate are inspected, and it is determined whether the electronic units are normal or defective; and These covers are respectively set on the normal electronic units, but not on the defective electronic units.

5. The manufacturing method according to claim 1, characterized in that, The procedure before step (c) further includes placing the circuit substrate in a cavity and evacuating the cavity.

6. The manufacturing method according to claim 1, characterized in that, In the top view of the circuit substrate, the bonding material is formed between two adjacent electronic units.

7. An electronic device, characterized in that, Include: A circuit substrate comprising: A substrate; An electronic unit is disposed on the substrate; and A first bonding member is disposed on the substrate and surrounds the electronic unit; A cover plate is disposed on the first bonding member, wherein the cover plate includes a second bonding member, and in a plan view of the circuit substrate, the cover plate overlaps with the electronic unit, and the second bonding member overlaps at least partially with the first bonding member; and A bonding material includes a first portion and a second portion, the first portion being disposed between the first bonding member and the second bonding member, and the second portion being disposed on the first bonding member, wherein, in the top view of the circuit substrate, the second portion does not overlap with the second bonding member; The thickness of the first part of the bonding material is less than the thickness of the second part.

8. The electronic device according to claim 7, characterized in that, The circuit substrate also includes a limiting member disposed on the first bonding member, wherein, in a top view of the circuit substrate, the limiting member is located around the electronic unit.

9. The electronic device according to claim 7, characterized in that, The thickness of the second portion of the bonding material is between 50 μm and 500 μm.

10. The electronic device according to claim 7, characterized in that, In a cross-sectional view, the width of the first joint is greater than the width of the second joint.

11. The electronic device according to claim 7, characterized in that, The bonding material contains solder.

12. The electronic device according to claim 7, characterized in that, The material of the first joint includes aluminum, nickel, gold, palladium, copper, titanium, the aforementioned alloys, or combinations thereof.

13. The electronic device according to claim 7, characterized in that, The cover plate includes a body and an anti-reflective layer disposed on the body.

14. The electronic device according to claim 13, characterized in that, The material of the body includes silicon, germanium, zinc sulfide, zinc selenide, gallium arsenide, chalcogenides, or combinations thereof.

15. The electronic device according to claim 13, characterized in that, The anti-reflective layer comprises multiple high-refractive-index layers and multiple low-refractive-index layers, wherein the high-refractive-index layers and the low-refractive-index layers are stacked alternately on top of each other.

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