Circuit board and electronic device

Abstract

The application relates to the technical field of integrated circuits, and discloses a circuit board and an electronic device. The circuit board comprises a core board and a differential capacitor pair. The core board comprises a signal layer, an insulating layer and a reference layer which are sequentially distributed along a third direction. The core board is provided with at least two core boards, and the two core boards are respectively a first core board and a second core board. The first core board and the second core board are sequentially stacked along the third direction. The reference layer of the first core board is provided with a hollow region. The differential capacitor pair comprises a first capacitor and a second capacitor. The first capacitor and the second capacitor are sequentially distributed along a second direction. The first capacitor and the second capacitor are connected with the signal layer of the first core board through a pair of pads which are sequentially distributed along a first direction. The hollow region corresponds to the pads in position along the third direction. One end of the pad along the second direction is provided with a tapered region. The size of the tapered region along the first direction gradually decreases in the direction away from the pad. The application can reduce the influence of the PCB layer offset on the impedance of the capacitor.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a circuit board and electronic device. Background Technology

[0002] In the design of high-speed digital circuits, any tiny impedance fluctuation can cause signal reflection, jitter and inter-symbol interference. Therefore, in high-speed links, a series capacitor is usually required to achieve DC isolation.

[0003] To compensate for the impedance drop at the capacitor pads, the industry generally adopts the method of merging or independently hollowing out the reference layer below the differential capacitor pads to achieve a local increase in impedance value.

[0004] However, interlayer alignment errors (layer misalignment) are unavoidable in the PCB multilayer lamination process, causing the cutout area of ​​the actual product to deviate from the design pattern. This misalignment results in asymmetry in the cutout shape on both sides of the differential pair, or changes in the effective reference area of ​​a single pad, thus introducing unpredictable impedance mismatch. This impedance discontinuity caused by manufacturing deviations severely reduces the quality and reliability of signal transmission. Summary of the Invention

[0005] This application provides a circuit board and electronic device to solve the problem of the influence of PCB layer offset on capacitor impedance.

[0006] In a first aspect, this application provides a circuit board having intersecting first direction, second direction, and third direction, comprising:

[0007] A core board includes a signal layer, an insulating layer, and a reference layer distributed sequentially along a third direction. At least two core boards are provided, namely a first core board and a second core board. The first core board and the second core board are stacked sequentially along the third direction. A cut-out area is provided on the reference layer of the first core board.

[0008] The differential capacitor pair includes a first capacitor and a second capacitor, which are distributed sequentially along the second direction. The first capacitor and the second capacitor are respectively connected to the signal layer of the first core board through a pair of pads distributed sequentially along the first direction. The cutout area corresponds to the position of the pads along the third direction.

[0009] Wherein, one end of the pad along the second direction is set as a tapered region, and the size of the tapered region along the first direction gradually decreases in the direction away from the pad.

[0010] Beneficial Effects: By setting a pad structure with a tapered region, the effective size of the pad in the second direction is effectively reduced. This reduces the relative area change between the pad and the reference layer cutout area when interlayer alignment errors occur during PCB manufacturing, thereby reducing impedance discontinuities caused by layer misalignment. This design achieves fault tolerance for manufacturing errors through simple structural improvements, enhancing the impedance stability and signal integrity of high-speed differential signal transmission. This application reduces the maximum effective size of the pad in the second direction by setting a tapered region on the pad. The tapered region makes the change in reference area caused by layer misalignment slow and gradual, reducing the pad's sensitivity to layer misalignment. This application transforms the impedance abrupt change caused by layer misalignment into a slow, gradual change, so that even if layer misalignment occurs, the amount of impedance change is reduced, thus always keeping the impedance value within an acceptable continuous range.

[0011] In one optional embodiment, the pad connected to the first capacitor is a first pad, and the pad connected to the second capacitor is a second pad, wherein the tapered area of ​​the first pad and the tapered area of ​​the second pad are opposite to each other along the second direction.

[0012] Beneficial effects: By setting the tapered areas of the first and second pads to be mutually opposite, this design ensures the symmetry of the positive and negative signal paths in the differential pair. Even under layer offset, the impedance change trends of the two signal paths can be kept consistent, effectively avoiding the increase of common-mode noise and signal distortion caused by asymmetrical impedance changes, and further improving the transmission quality and anti-interference capability of differential signals.

[0013] In one optional embodiment, the tapering region has a first plane and a second plane that are opposite each other, the first plane and the second plane are arranged opposite each other along the first direction, the distance between the first plane and the second plane is the size of the tapering region along the first direction, the first plane and the second plane are both arranged at an angle to the second direction, and the first plane and the second plane are symmetrical about the plane containing the second direction.

[0014] Beneficial Effects: The use of symmetrically arranged inclined planes to form the tapered region ensures that the pad structure maintains symmetry in both mechanical and electrical characteristics. This not only facilitates manufacturing but, more importantly, ensures that the electromagnetic field distribution remains symmetrical when the signal passes through the pad, avoiding signal phase deviation caused by geometric asymmetry and providing a more balanced and predictable transmission path for high-speed signals. Specifically, both the first and second planes are set at an angle to the second direction, making the tapered region of the pad form a trapezoidal structure, i.e., a trapezoidal structure is formed on the outer side of the offset. For pads with a tapered region of trapezoidal structure, the change in reference area caused by layer offset is slow and gradual, reducing the pad's sensitivity to layer offset. This application transforms the impedance abrupt change caused by layer offset into a slow gradient, so that even if layer offset occurs, the amount of impedance change is reduced, thereby always keeping the impedance value within an acceptable continuous range. Since the physical size of the capacitor pad area is much larger than the transmission line width, by changing the outer edge of the pad in the layer offset sensitive direction to a bevel at a specific angle, the effective sensitive size of the pad in that direction is actively reduced. This design transforms the effective area of ​​the misalignment between the pads and the cutout area during layer offset from a rectangular area that is linearly related to the amount of layer offset. Instead, it converts this area into a trapezoidal or triangular area that is related to the angle of the hypotenuse and has a much lower rate of change. This design changes the impact of layer offset from abrupt to gradual, effectively buffering its effect on impedance continuity.

[0015] In one alternative implementation, the angle between the first plane and the second direction is A, where 40°≤A≤50°.

[0016] Beneficial effects: By controlling the included angle of the inclined plane within the range of 40° to 50°, this angle range can provide sufficient tapering effect to resist the influence of layer offset, while avoiding the tip effect caused by too small an angle or the size redundancy caused by too large an angle, thus ensuring the optimization of impedance compensation effect.

[0017] In one optional implementation, the length of the tapered region along the second direction is B, where 5mil ≤ B ≤ 8mil; the length of the pad along the second direction is C, where 16mil ≤ C ≤ 24mil.

[0018] Beneficial effects: By precisely defining the dimensional range of the tapered zone length and the total length of the pads, sufficient tapering effect is ensured to cope with layer offset errors within the expected range, while also ensuring that the pads have sufficient area to meet the soldering process requirements and current carrying capacity.

[0019] In one optional embodiment, the signal layer of the first core board is provided with a first line and a second line. The first line is provided with a first blank area, and a pair of first pads are both located in the first blank area. The end of the first pad away from the tapered area is connected to the first line. The second line is provided with a second blank area, and a pair of second pads are both located in the second blank area. The end of the second pad away from the tapered area is connected to the second line.

[0020] Beneficial effects: By setting blank areas on the lines to accommodate pads and placing the connection points between the pads and the lines at the end furthest from the tapered area, a smooth transition of the signal transmission path is ensured, impedance fluctuations caused by structural abrupt changes are reduced, and stable mechanical support and electrical connection are provided for the pads.

[0021] In one alternative implementation, the first line extends along the first direction at least in a portion near the first pad, and the second line extends along the first direction at least in a portion near the second pad.

[0022] Beneficial effects: By requiring the local area of ​​the trace near the pad to extend along the first direction, impedance discontinuities and signal reflections caused by trace bends or crossings are reduced, further improving the integrity of signal transmission. By connecting the end of the first pad furthest from the tapered area to the first trace, and the end of the second pad furthest from the tapered area to the second trace, combined with the constraint that the first and second traces extend along the first direction, differential signals can use horizontal traces closest to the inner side of the pad. This ensures that the link symmetry is maintained as much as possible while minimizing the trace spacing from the normal spacing, eliminating the asymmetry between the first and second traces that might be caused by layer offset due to oblique capacitor traces.

[0023] In one optional embodiment, both the first core board and the second core board are provided with ground holes extending along the third direction. The ground holes on the first core board and the second core board are correspondingly arranged along the third direction. There are multiple ground holes, and the multiple ground holes are distributed at intervals along the circumference of the differential capacitor pair. The distance from the center of the ground hole to the center of the differential capacitor pair is D, where 25mil≤D≤35mil.

[0024] Beneficial Effects: By strategically placing ground vias on each core board and distributing them circumferentially along the differential capacitor pairs, the shortest return path for the signal is provided, significantly reducing the return loop area, lowering loop inductance, effectively suppressing electromagnetic radiation, and improving signal quality. Multiple ground vias are evenly distributed around the center of the differential capacitor pair, with a radius of 25mil to 35mil, ensuring the symmetry of the return path. By using multiple ground vias, the signal return can find the nearest via entrance within a very short distance in either the first or second direction, forming a minimized, symmetrical loop. This ensures that the signal receives the same high-quality electrical performance regardless of the angle from which it enters the capacitor area. Furthermore, even if one ground via has a slight manufacturing defect, the other three can still function excellently, providing redundancy for the design and improving yield and consistency in mass production.

[0025] In one alternative implementation, the projections of the two first pads onto the cutout area along the third direction have a pair of first edges, the pair of first edges being located at both ends of the projection along the first direction, and the pair of first edges coinciding with two opposite edges of the cutout area along the first direction; the projections of the two second pads onto the cutout area along the third direction have a pair of second edges, the pair of second edges being located at both ends of the projection along the first direction, and the pair of second edges coinciding with two opposite edges of the cutout area along the first direction.

[0026] Beneficial effect: Since the first direction is the outgoing direction, the cutout will cause the trace to cross the split, resulting in higher impedance of bidirectional traces in the via area. Therefore, the cutout in the first direction is the same size as the pad.

[0027] Secondly, this application also provides an electronic device, including the circuit board.

[0028] Beneficial effects: Since electronic devices include circuit boards and have the same effects as circuit boards, they will not be elaborated further here. By including circuit boards, electronic devices can improve the reliability and stability of data transmission. Attached Figure Description

[0029] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the structure of a circuit board according to an embodiment of this application;

[0031] Figure 2 This is a schematic diagram of the structure of the first plane and the second plane in the embodiments of this application;

[0032] Figure 3 This is a schematic diagram of the core board structure in an embodiment of this application.

[0033] Explanation of reference numerals in the attached figures:

[0034] 1. Core board; 101. Signal layer; 1011. First line; 1012. Second line; 102. Insulating layer; 103. Reference layer; 104. Cutout area; 105. Ground via; 2. Differential capacitor pair; 201. First pad; 2011. First edge; 202. Second pad; 2021. Second edge; 203. Tapered area; 2031. First plane; 2032. Second plane; X, First direction; Y, Second direction; Z, Third direction. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0036] It should be noted that the terms "center," "longitudinal," "lateral," "length," "dimension," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "installed," "connected," and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements. The terms "parallel," "perpendicular," and "equal" include the described situation and situations similar to the described situation, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism can be, for example, within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity can also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality can be, for example, a difference between the two equal items being less than or equal to 5% of either one. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.

[0037] The following is combined Figures 1 to 3 This describes an embodiment of the present application.

[0038] According to an embodiment of this application, a circuit board is provided, having intersecting first direction X, second direction Y, and third direction Z, including a core board 1 and differential capacitor pairs 2. The core board 1 includes a signal layer 101, an insulating layer 102, and a reference layer 103 sequentially distributed along the third direction Z. At least two core boards 1 are provided, namely a first core board 1 and a second core board 1, which are stacked sequentially along the third direction Z. A cutout area 104 is provided on the reference layer 103 of the first core board 1. The differential capacitor pair 2 includes a first capacitor and a second capacitor, which are sequentially distributed along the second direction Y. The first capacitor and the second capacitor are respectively connected to the signal layer 101 of the first core board 1 through a pair of pads sequentially distributed along the first direction X. The cutout area 104 corresponds to the position of the pads along the third direction Z. One end of the pad along the second direction Y is designated as a tapered region 203, and the size of the tapered region 203 along the first direction X gradually decreases in the direction away from the pad.

[0039] It should be noted that due to manufacturing errors in the circuit board, the cutout area 104 of the reference layer 103 on the second layer will be offset relative to the pads of the signal layer 101 on the surface. This offset causes a change in the relative overlap area between the pads and the cutout area 104. For rectangular pads, even a small offset can cause a large linear change in the area of ​​the pad exposed outside the cutout area 104. Below this exposed pad is the complete reference layer 103, which can cause a sudden drop in local impedance, thereby disrupting the overall impedance continuity. This application reduces the maximum effective size of the pad in the second direction Y by providing a tapered region 203 on the pad. For rectangular pads, the change in reference area caused by layer offset is sudden and linear, while for trapezoidal pads, the change in reference area caused by layer offset is slow and gradual, reducing the sensitivity of the pad to layer offset. This application transforms the impedance abrupt change caused by layer offset into a slow gradient, so that even if layer offset occurs, the amount of impedance change is reduced, thereby always keeping the impedance value within an acceptable continuous range.

[0040] Furthermore, unlike the method of bonding two independent substrates using prepreg (PP), this application employs a core (Laminated Core) stack-up design. Specifically, the surface layer (i.e., signal layer 101) and the reference layer 103 located in the second layer, which require high-precision alignment, are integrated onto both sides of the same substrate (i.e., insulating layer 102) instead of being two independent substrates bonded together using PP. Since the patterns on both sides of the same core are simultaneously etched using photolithography, interlayer alignment errors (layer misalignment) caused by material slippage during subsequent multilayer lamination are avoided. Therefore, the layer misalignment between the surface layer and the second layer can be reduced from ±3.5mil in the PP bonding method to within ±1.5mil, providing a stable and accurate alignment basis for subsequent impedance optimization design, and fundamentally improving the performance consistency and reliability of high-speed signal links.

[0041] Understandably, since signal layer 101 and reference layer 103 are on the same substrate, the sliding motion between the two substrates during PCB manufacturing significantly reduces layer offset differences, thus lowering layer offset. Signal layer 101, also known as the device layer, is where series capacitors, other components, and signal traces are placed.

[0042] In this embodiment, by setting a pad structure with a tapered region 203, the effective size of the pad in the second direction Y is effectively reduced. This reduces the relative area change between the pad and the cut-out area 104 of the reference layer 103 when interlayer alignment errors occur during PCB manufacturing, thereby reducing impedance discontinuities caused by layer misalignment. This design achieves fault tolerance for manufacturing errors through simple structural improvements, enhancing the impedance stability and signal integrity of high-speed differential signal transmission.

[0043] In one embodiment, the pad connected to the first capacitor is the first pad 201, and the pad connected to the second capacitor is the second pad 202. The tapered area 203 of the first pad 201 and the tapered area 203 of the second pad 202 are opposite to each other along the second direction Y.

[0044] In this embodiment, by setting the tapered regions 203 of the first pad 201 and the second pad 202 to be arranged opposite to each other, this design ensures the symmetry of the positive and negative signal paths in the differential pair. Even in the case of layer offset, the impedance change trend of the two signal paths can be kept consistent, effectively avoiding the increase of common-mode noise and signal distortion caused by asymmetrical impedance changes, and further improving the transmission quality and anti-interference capability of differential signals.

[0045] In one embodiment, the tapered region 203 has a first plane 2031 and a second plane 2032 that are opposite each other. The first plane 2031 and the second plane 2032 are arranged opposite each other along a first direction X. The distance between the first plane 2031 and the second plane 2032 is the size of the tapered region 203 along the first direction X. The first plane 2031 and the second plane 2032 are both arranged at an angle to the second direction Y. The first plane 2031 and the second plane 2032 are symmetrically arranged about the plane containing the second direction Y.

[0046] It should be noted that both the first plane 2031 and the second plane 2032 are set at an angle to the second direction Y, so that the tapered area 203 of the pad forms a trapezoidal structure, that is, a trapezoidal structure is formed on the outer side of the offset.

[0047] Understandably, for pads with a trapezoidal tapered region 203, the change in reference area due to layer offset is slow and gradual, reducing the pad's sensitivity to layer offset. This application transforms the impedance abrupt change caused by layer offset into a slow, gradual change, so that even if layer offset occurs, the amount of impedance change is reduced, thereby always keeping the impedance value within an acceptable continuous range. Because the physical size of the capacitor pad area is much larger than the transmission line width, by changing the outer edge of the pad in the layer offset sensitive direction to a bevel at a specific angle, the effective sensitive size of the pad in that direction is actively reduced. This means that when layer offset occurs, the effective area of ​​the misalignment between the pad and the cutout area 104 is no longer a rectangular area linearly related to the amount of layer offset, but is transformed into a trapezoidal or triangular area related to the bevel angle with a much lower rate of change. This design transforms the impact of layer offset from abrupt to gradual, effectively buffering its impact on impedance continuity.

[0048] In this embodiment, the tapered region 203 is formed by symmetrically arranged inclined planes, which makes the pad structure symmetrical in both mechanical and electrical characteristics. This not only facilitates manufacturing, but more importantly, ensures that the electromagnetic field distribution of the signal remains symmetrical when passing through the pad, avoiding signal phase deviation caused by geometric asymmetry, and providing a more balanced and predictable transmission path for high-speed signals.

[0049] In one embodiment, the angle between the first plane 2031 and the second direction Y is A, where 40°≤A≤50°.

[0050] It should be noted that the first plane 2031 and the second plane 2032 are both set at an angle to the second direction Y, and the first plane 2031 and the second plane 2032 are symmetrically set about the plane containing the second direction Y, so that the tapered area 203 of the pad can form an isosceles trapezoidal structure.

[0051] Optionally, the angle between the first plane 2031 and the second direction Y is 45°.

[0052] In this embodiment, the included angle of the inclined plane is controlled within the range of 40° to 50°. This angle range can provide sufficient tapering effect to resist the influence of layer offset, while avoiding the tip effect caused by too small an angle or the size redundancy caused by too large an angle, thus ensuring the optimization of the impedance compensation effect.

[0053] In one embodiment, the length of the tapered region 203 along the second direction Y is B, where 5mil≤B≤8mil; the length of the pad along the second direction Y is C, where 16mil≤C≤24mil.

[0054] It should be noted that the length of the tapered region 203 along the second direction Y is one-third of the length of the pad along the second direction Y.

[0055] In this embodiment, by precisely defining the size range of the tapered region 203 and the total length of the pads, both sufficient tapering effect is ensured to cope with layer offset errors within the expected range, and the pads are ensured to have sufficient area to meet the welding process requirements and current carrying capacity.

[0056] In one embodiment, the signal layer 101 of the first core board 1 is provided with a first line 1011 and a second line 1012. The first line 1011 is provided with a first blank area, and a pair of first pads 201 are both located in the first blank area. The end of the first pad 201 away from the tapered area 203 is connected to the first line 1011. The second line 1012 is provided with a second blank area, and a pair of second pads 202 are both located in the second blank area. The end of the second pad 202 away from the tapered area 203 is connected to the second line 1012.

[0057] It should be noted that the first circuit 1011, the second circuit 1012, and the pads are all integrally formed copper foils, created by etching the copper foil on the top layer of the PCB. The pads are widened areas of the traces to facilitate component soldering.

[0058] In this embodiment, by setting a blank area on the line to accommodate the pads, and setting the connection point between the pads and the line at the end away from the tapered area 203, a smooth transition of the signal transmission path is ensured, impedance fluctuations caused by structural abrupt changes are reduced, and stable mechanical support and electrical connection are provided for the pads.

[0059] In one embodiment, the first line 1011 extends along the first direction X at least in a portion near the first pad 201, and the second line 1012 extends along the first direction X at least in a portion near the second pad 202.

[0060] It should be noted that the first line 1011 and the second line 1012 are signal lines on the signal layer 101, namely P (positive phase) line and N (negative phase) line, respectively. Positive and negative signals have their own independent and completely parallel traces on the PCB.

[0061] Understandably, since capacitor pads are much wider than signal lines, the center distance between two pads is also larger than the normal spacing between two signal lines. If a signal line originates from the outside or center of the pad, it needs to bend abruptly after leaving the pad to return to the normal differential spacing. The impedance in this bend is discontinuous, causing signal reflection. Therefore, this application connects the end of the first pad 201 furthest from the tapered region 203 to the first line 1011, and the end of the second pad 202 furthest from the tapered region 203 to the second line 1012. Combined with the limitation that the first line 1011 and the second line 1012 extend along the first direction X, the differential signal can be routed horizontally closest to the inner side of the pad. This ensures that the trace spacing is as small as possible compared to the normal spacing, maintaining the symmetry of the link and eliminating the asymmetry of the first line 1011 and the second line 1012 that might be caused by layer offset due to the angled capacitor routing.

[0062] In this embodiment, the local area of ​​the line near the pad is required to extend along the first direction X, which reduces impedance discontinuities and signal reflections caused by line bends or intersections, and further improves the integrity of signal transmission.

[0063] In one embodiment, both the first core board 1 and the second core board 1 are provided with ground holes 105 extending along the third direction Z. The ground holes 105 on the first core board 1 and the second core board 1 are correspondingly arranged along the third direction Z. Multiple ground holes 105 are provided, and the multiple ground holes 105 are distributed at intervals along the circumference of the differential capacitor pair 2. The distance from the center of the ground hole 105 to the center of the differential capacitor pair 2 is D, where 25mil≤D≤35mil.

[0064] It should be noted that the ground via 105 is a through-hole installed on the PCB. The ground via 105 is drilled from the top layer to the bottom layer of the PCB, connecting all the internal ground planes it passes through. After drilling, the inner wall of the through-hole is chemically plated with copper to make it conductive. The copper plating automatically makes electrical connections with all copper-plated layers it passes through during the drilling process. Specifically, the ground via 105 provides a low-impedance vertical channel for high-speed return current, efficiently guiding it from the deep reference layer 103 to the shallow reference layer 103 near the interruption point, thereby minimizing the area of ​​the entire return loop.

[0065] Optionally, four ground vias 105 are provided, evenly distributed on a circle with a radius of 30 mil centered on the center of the differential capacitor pair 2. This ensures the symmetry of the return path by positioning the four vias 105 at 0°, 90°, 180°, and 270° respectively. By using four ground vias 105, the signal return path can find the nearest ground via 105 entrance within a very short distance (<30 mil) regardless of whether it's in the first direction X or the second direction Y, forming a minimized, symmetrical loop. This ensures that the signal receives the same high-quality electrical performance regardless of the angle from which it enters the capacitor region. Furthermore, even if one ground via 105 has a slight manufacturing defect, the other three can still function excellently, providing redundancy for the design and improving yield and consistency in mass production.

[0066] In this embodiment, by providing ground holes 105 on each core board 1 and distributing them circumferentially along the differential capacitor pair 2, the shortest return path for the signal is provided, which significantly reduces the return loop area, reduces the loop inductance, effectively suppresses electromagnetic radiation, and improves signal quality.

[0067] In one embodiment, the projections of the two first pads 201 along the third direction Z onto the cutout region 104 have a pair of first edges 2011, which are located at the two ends of the projection along the first direction X, and the pair of first edges 2011 coincide with the two opposite edges of the cutout region 104 along the first direction X; the projections of the two second pads 202 along the third direction Z onto the cutout region 104 have a pair of second edges 2021, which are located at the two ends of the projection along the first direction X, and the pair of second edges 2021 coincide with the two opposite edges of the cutout region 104 along the first direction X.

[0068] It should be noted that the cutout area 104 can be set as a whole cutout or as two independent cutout areas 104. The two cutout areas 104 correspond to the first pad 201 and the second pad 202, respectively. When two cutout areas 104 are set, the spacing between the PN junctions of the differential capacitors must be greater than 12mil due to the DFM (actual manufacturing constraints). Since this value is much larger than the PCB layer offset range (3.5mil in the conventional case and 1.5mil in the same substrate), it can be extended outward by an additional 1.5mil along the second direction Y at the cutout boundary of each pad in the direction towards the other pad.

[0069] Understandably, in the signal output direction (first direction X), the size of the cutout area 104 is consistent with the size of the pad itself, without any additional expansion. This is to avoid situations where expanding the cutout area 104 would result in a copper-free area directly below both signal lines. This would cause the reference plane of the signal line to no longer be the complete reference layer 103 of the first core board 1, but rather the reference layer 103 of the second core board 1, leading to a sudden change in the reference plane of different areas below the signal line, resulting in a drastic change in impedance and strong signal reflection.

[0070] In this embodiment, since the first direction X is the outgoing direction, the cutout will cause the trace to cross the segment, resulting in the bidirectional trace having a higher impedance in the via area. Therefore, the cutout in the first direction X is the same size as the pad.

[0071] In one embodiment, this solution places the signal layer 101 containing the capacitor and its direct reference layer 103 on two surfaces of the same core board 1, allowing their patterns to be simultaneously completed using the same film, the same photoplotting equipment, and in a single exposure imaging and etching process. This achieves high alignment accuracy between the signal layer 101 and the reference layer 103, reducing layer misalignment. The effectiveness of the irregularly shaped pads in this application, particularly those with trapezoidal or tapered structures, does not stem from material changes but from modifications to their mechanical structure. In high-speed differential signal transmission, the capacitor pad area is much larger than the transmission linewidth. The tapered irregularly shaped pads used in this solution actively reduce the effective sensitive size of the pad in the layer misalignment sensitive direction (second direction Y) by changing the outer edge of the pad to a bevel at a specific angle. This means that when layer misalignment occurs, the effective area of ​​the misalignment between the pad and the cutout area 104 is no longer a rectangular area linearly related to the amount of layer misalignment, but rather a trapezoidal or triangular area related to the bevel angle with a much lower rate of change. This design transforms the impact of layer offset from abrupt change to a gradual change, effectively buffering its impact on impedance continuity. Secondly, the asymmetrical geometry of the pads has a clear directional focus, precisely compensating for layer offset in a specific direction (second direction Y), while minimizing the impedance impact on the signal output direction (first direction X), thus maximizing the effect without introducing additional complexity.

[0072] In one embodiment, multiple vias 105 positioned at a specific distance (e.g., 30 mil) around the capacitor provide the shortest return path. These vias offer a shortcut for deep return currents to the reference layer 103 near the interruption point, compressing the horizontal loop into a vertical path and minimizing the return loop area. Simultaneously, the parallel connection of multiple vias 105 results in a significantly lower total inductance than a single via 105, providing a return path for high-speed signals. Furthermore, the symmetrical arrangement of the vias 105 along the capacitor's circumference ensures symmetrical return paths for the differential pair's P and N signals, avoiding common-mode noise introduced by asymmetrical return. The irregularly shaped pads and core stack-up ensure correct impedance of the signal path, while the via 105 system ensures that the signal energy (in the form of an electromagnetic field) is delivered completely, with low loss and low radiation.

[0073] According to an embodiment of this application, another aspect provides an electronic device, including a circuit board.

[0074] In this embodiment, since the electronic device includes a circuit board and has the same effect as a circuit board, it will not be described again here. By including a circuit board, the electronic device can improve the reliability and stability of data transmission.

[0075] The circuit board and electronic device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A circuit board having a first direction (X), a second direction (Y), and a third direction (Z) intersecting each other in pairs, characterized in that, include: The core board (1) includes a signal layer (101), an insulating layer (102) and a reference layer (103) distributed sequentially along a third direction (Z). At least two core boards (1) are provided, namely a first core board (1) and a second core board (1). The first core board (1) and the second core board (1) are stacked sequentially along the third direction (Z). A cutout area (104) is provided on the reference layer (103) of the first core board (1). The differential capacitor pair (2) includes a first capacitor and a second capacitor. The first capacitor and the second capacitor are distributed sequentially along the second direction (Y). The first capacitor and the second capacitor are respectively connected to the signal layer (101) of the first core board (1) through a pair of pads distributed sequentially along the first direction (X). The cutout area (104) corresponds to the position of the pad along the third direction (Z). Wherein, one end of the pad along the second direction (Y) is set as a tapered region (203), and the size of the tapered region (203) along the first direction (X) gradually decreases in the direction away from the pad; The pad connected to the first capacitor is the first pad (201), and the pad connected to the second capacitor is the second pad (202). The tapered area (203) of the first pad (201) and the tapered area (203) of the second pad (202) are opposite to each other along the second direction (Y). The tapered region (203) has a first plane (2031) and a second plane (2032) that are opposite each other. The first plane (2031) and the second plane (2032) are arranged opposite each other along the first direction (X). The distance between the first plane (2031) and the second plane (2032) is the size of the tapered region (203) along the first direction (X). The first plane (2031) and the second plane (2032) are both arranged at an angle to the second direction (Y).

2. The circuit board according to claim 1, characterized in that, The first plane (2031) and the second plane (2032) are symmetrically arranged about the plane containing the second direction (Y).

3. The circuit board according to claim 2, characterized in that, The angle between the first plane (2031) and the second direction (Y) is A, where 40°≤A≤50°.

4. The circuit board according to claim 2, characterized in that, The length of the tapered region (203) along the second direction (Y) is B, where 5mil≤B≤8mil; the length of the pad along the second direction (Y) is C, where 16mil≤C≤24mil.

5. The circuit board according to claim 1, characterized in that, The signal layer (101) of the first core board (1) is provided with a first line (1011) and a second line (1012). The first line (1011) is provided with a first blank area. A pair of first pads (201) are both located in the first blank area. The end of the first pad (201) away from the tapered area (203) is connected to the first line (1011). The second line (1012) is provided with a second blank area. A pair of second pads (202) are both located in the second blank area. The end of the second pad (202) away from the tapered area (203) is connected to the second line (1012).

6. The circuit board according to claim 5, characterized in that, The first line (1011) extends along the first direction (X) at least in a portion near the first pad (201), and the second line (1012) extends along the first direction (X) at least in a portion near the second pad (202).

7. The circuit board according to claim 1, characterized in that, Both the first core plate (1) and the second core plate (1) are provided with ground holes (105) extending along the third direction (Z). The ground holes (105) on the first core plate (1) and the second core plate (1) are correspondingly provided along the third direction (Z). There are multiple ground holes (105), and the multiple ground holes (105) are distributed at intervals along the circumference of the differential capacitor pair (2). The distance from the center of the ground hole (105) to the center of the differential capacitor pair (2) is D, where 25mil≤D≤35mil.

8. The circuit board according to claim 1, characterized in that, The projections of the two first pads (201) onto the cutout area (104) along the third direction (Z) have a pair of first edges (2011), the pair of first edges (2011) being located at both ends of the projection along the first direction (X), and the pair of first edges (2011) coinciding with the two opposite edges of the cutout area (104) along the first direction (X); the projections of the two second pads (202) onto the cutout area (104) along the third direction (Z) have a pair of second edges (2021), the pair of second edges (2021) being located at both ends of the projection along the first direction (X), and the pair of second edges (2021) coinciding with the two opposite edges of the cutout area (104) along the first direction (X).

9. An electronic device, characterized in that, include: The circuit board according to any one of claims 1 to 8.

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