Semiconductor device

Abstract

There is provided a semiconductor device including: a gate trench on a substrate between a source region and a drain region; the first gate insulating layer covers the lower surface and the side wall of the gate trench; a second insulating layer in the gate trench in contact with an upper region of a sidewall of the first gate insulating layer; and a gate electrode in the gate trench, the gate electrode including a lower buried portion in contact with the first gate insulating layer in a lower region of the gate trench and an upper buried portion on the lower buried portion in an upper region of the gate trench, where the lower buried portion includes a first conductive layer in contact with a sidewall surface of the first gate insulating layer and the lower region, and the upper buried portion includes a second conductive layer in contact with a sidewall surface of the first gate insulating layer. The upper buried portion includes a work function adjustment layer on the second insulating layer and a second conductive layer in an upper region of the gate trench, where the second conductive layer is in contact with the work function adjustment layer and the first conductive layer, and the second conductive layer includes a transition metal.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2024-0061428, filed on May 9, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor devices. Background Technology

[0004] Semiconductor devices are core components in electronic devices used to control or amplify electrical signals, and various types of semiconductor devices can be manufactured. For example, memory devices are primarily used to store and retrieve data, while non-memory devices are used to control or amplify electrical signals. In recent years, the demands for the performance and functionality of electronic devices have become stronger than ever before, essentially requiring semiconductor devices to possess high-performance characteristics. To meet this requirement, the integration density of semiconductor devices is constantly increasing. Researchers are exploring various methods to create high-performance, highly integrated semiconductor devices.

[0005] In particular, buried channel array transistors (BCATs) are used in DRAM products, providing higher integration density while ensuring sufficient effective spacing. A BCAT consists of a gate electrode filled in a trench formed between the source and drain regions on a substrate. Using this BCAT increases the integration density of integrated circuit devices, leading to an abnormally reduced depth of the gate electrode filling the trench between the source and drain regions. This can result in gate electrode loss and degraded electrical characteristics. Summary of the Invention

[0006] This disclosure provides a semiconductor device with improved electrical characteristics and reliability.

[0007] According to some aspects, a semiconductor device may include: a gate trench on a substrate between a source region and a drain region; a first gate insulating layer covering a lower surface and sidewalls of the gate trench; a second insulating layer in the gate trench contacting an upper region of the sidewalls of the first gate insulating layer; and a gate electrode in the gate trench, wherein the gate electrode includes a lower buried portion in the lower region of the gate trench contacting the first gate insulating layer and an upper buried portion in the upper region of the gate trench on the lower buried portion, wherein the lower buried portion includes a first conductive layer contacting the sidewalls and the lower region of the first gate insulating layer, and the upper buried portion includes a work function adjustment layer on the second insulating layer and a second conductive layer in the upper region of the gate trench, wherein the second conductive layer contacts the work function adjustment layer and the first conductive layer, and the second conductive layer includes a transition metal.

[0008] According to some aspects, a semiconductor device may include: a source region and a drain region on a substrate, the source region and the drain region being spaced apart from each other by a gate trench; a first gate insulating layer covering the lower surface and sidewalls of the gate trench; a second insulating layer in the gate trench contacting an upper region of the sidewalls of the first gate insulating layer; and a gate electrode including a lower buried portion surrounded by the first gate insulating layer and in the lower region of the gate trench, and an upper buried portion on the lower buried portion and in the upper region of the gate trench, wherein the lower buried portion includes a first conductive layer surrounded by the sidewalls and lower region of the first gate insulating layer, the second insulating layer is on the upper surface of the first conductive layer and the upper region of the sidewalls of the first gate insulating layer, the upper buried portion includes a work function adjustment layer surrounded by the second insulating layer and a second conductive layer surrounded by the work function adjustment layer, and the second conductive layer includes a transition metal.

[0009] According to some aspects, a memory device may include a semiconductor device and a capacitor electrically connected to the semiconductor device. The memory device or semiconductor device may be a semiconductor chip. The semiconductor device may include: a gate trench on a substrate between a source region and a drain region; a first gate insulating layer covering a lower surface and sidewalls of the gate trench; a second insulating layer in the gate trench contacting an upper region of the sidewalls of the first gate insulating layer; and a gate electrode in the gate trench, wherein the gate electrode includes a lower buried portion in the lower region of the gate trench contacting the first gate insulating layer and an upper buried portion in the upper region of the gate trench on the lower buried portion, wherein the lower buried portion includes a first conductive layer contacting the sidewalls and lower region of the first gate insulating layer, and the upper buried portion includes a work function adjustment layer on the second insulating layer and a second conductive layer in the upper region of the gate trench, wherein the second conductive layer contacts the work function adjustment layer and the first conductive layer, and the second conductive layer includes a transition metal.

[0010] In semiconductor devices according to some aspects of this disclosure, leakage current can be reduced and word line continuity can be ensured.

[0011] According to some aspects of this disclosure, the work function of the gate electrode can be reduced by the work function adjustment layer in the upper region of the gate electrode of the semiconductor device, thereby reducing the leakage current caused by the gate-induced drain leakage (GIDL) phenomenon.

[0012] According to some aspects of this disclosure, a portion of the conductive layer in the upper region of the gate electrode of a semiconductor device is buried in another conductive layer in the lower region of the gate electrode, thereby improving the problem of word line resistance disconnection due to loss of conductive layer, even when the gate trench is formed at a lower depth. Attached Figure Description

[0013] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary aspects of this disclosure with reference to the accompanying drawings, in which:

[0014] Figure 1 This is a diagram illustrating an example of a semiconductor device;

[0015] Figure 2 It is along Figure 1 A cross-sectional view taken from line AA;

[0016] Figure 3 This is a cross-sectional view of another example of a semiconductor device;

[0017] Figure 4 This is a cross-sectional view of another example of a semiconductor device;

[0018] Figure 5 This is a cross-sectional view of another example of a semiconductor device;

[0019] Figure 6 This is a cross-sectional view of another example of a semiconductor device;

[0020] Figure 7 This is a cross-sectional view of another example of a semiconductor device;

[0021] Figure 8 This is a diagram illustrating an example configuration of a storage device array;

[0022] Figure 9 It is along Figure 8 A cross-sectional view of line BB; and

[0023] Figures 10 to 18 It shows the manufacturing process. Figure 2 The diagram shows a cross-sectional view of the process of the semiconductor device. Detailed Implementation

[0024] In the following description, when referring to an element as being “above” or “on top of” another element, it may mean that the element is not only directly above or on top of and in contact with the other element, but also that the element is located above the other element without contact. For ease of description, this document may use spatial relative terms such as “above,” “upper,” and “lower” to describe positional relationships, for example, as shown in the accompanying figures. It will be understood that spatial relative terms cover different orientations of the devices in addition to those shown in the figures. These spatial relative terms used herein (e.g., “above” and “below”) have their usual broad meaning; for example, element A may be above element B even if the two elements do not overlap when viewed from above (just as an object in the sky is usually above an object on the ground, even if it is not directly above it).

[0025] Singular expressions include plural expressions, as shown in the attached figure, for example. Therefore, unless the context clearly specifies otherwise, a description of a single item provided in plural form should be understood to apply to the remaining multiple items.

[0026] Throughout this specification, when a component is described as "comprising" or "including" a particular element or group of elements, it should be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with other elements to form the component, unless the context otherwise requires. On the other hand, the term "composed of" indicates that the component is formed solely by the listed elements.

[0027] As used herein, the terms “surrounding” and “surrounded” are intended to indicate that an element is outside another element. These elements may or may not be in contact. An element that is surrounded may completely surround an inner element or may not completely surround an inner element. However, an element that is wrapped around does not need to completely surround an inner element. As used herein, the term “cover” is intended to indicate that an element is above, on top of, or beside another element. These elements may or may not be in contact. Furthermore, a top element does not need to cover the entire top surface of the element below to be considered a “cover.” The term is intended to encompass an element that covers all or any part of the element below it.

[0028] Unless the order of the steps of the method is explicitly stated or stated to the contrary, the steps may be performed in any suitable order, and are not necessarily limited to the order stated.

[0029] It will be understood that when referring to an element as "connected" or "coupled" to another element or "on top of" another element, the element may be directly connected or coupled to the other element or directly on top of the other element, or there may be an intermediate element. In contrast, when referring to an element as "directly connected" or "directly coupled" to another element, or "contacting" or "in contact" with another element (or any form of using the word "contact"), there is no intermediate element at the point of contact.

[0030] The connecting lines or connecting members between the components shown in the figure are provided to illustrate functional connections and / or physical or circuit connections, and may be replaced or represented in actual devices as various additional functional connections, physical connections or circuit connections.

[0031] A “semiconductor chip” can be a semiconductor device that is monolithically (e.g., cut off) from a wafer.

[0032] All examples or illustrative terms used herein are for the purpose of describing technical ideas in detail only, and aspects of the invention are not limited to the scope of these examples or illustrative terms unless limited by the claims.

[0033] The semiconductor device and the method of manufacturing the semiconductor device will be described in detail below with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same or similar components, and the dimensions of each component may be enlarged for clarity and convenience. Furthermore, the aspects described herein are merely illustrative and various modifications may be made to them.

[0034] In the following description, in Figures 1 to 18 In the diagram, the first direction D1, the second direction D2, the fourth direction D4, and the fifth direction D5 represent the same plane, and the third direction D3 is perpendicular to the first direction D1, the second direction D2, the fourth direction D4, and the fifth direction D5. The first direction D1 and the second direction D2 are perpendicular to each other, and the fourth direction D4 and the fifth direction D5 are perpendicular to each other.

[0035] Figure 1 This is a diagram showing an example of a semiconductor device, and Figure 2 It is along Figure 1 The image shows a cross-sectional view taken from line AA. The semiconductor device can be a storage device. For example, a storage device or semiconductor device can be a semiconductor chip. The semiconductor device can be dynamic random access memory (DRAM), but is not limited to this.

[0036] refer to Figure 1 and Figure 2 The semiconductor device 10 may include: a source region 122 and a drain region 124 on a substrate 100 and spaced apart from each other; a gate trench T1 formed on the substrate 100 between the source region 122 and the drain region 124; a gate insulating layer 220 (also referred to herein interchangeably as a "first gate insulating layer" to distinguish it from a "second insulating layer" or "additional insulating layer") covering the lower surface and sidewalls of the gate trench T1; a gate electrode 210 in the gate trench T1 including a lower buried portion (LBP) that contacts and fills the lower region of the gate trench T1, and an upper buried portion (UBP) on the lower buried portion (LBP) that fills the upper region of the gate trench T1; and a capping layer 240 on the gate electrode 210.

[0037] As used herein, the term "fill" is intended to indicate that a component is within a space or area. Within the scope of the term "fill," a component may completely fill a space or area or partially fill a space or area.

[0038] Substrate 100 may include a semiconductor substrate. Substrate 100 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof. Substrate 100 is a III-V group semiconductor substrate, such as a binary, ternary, or quaternary compound formed by combining at least one of group III elements aluminum (Al), gallium (Ga), or indium (In) with at least one of group V elements phosphorus (P), arsenic (As), or antimony (Sb).

[0039] A gate trench T1, formed by etching a portion of the substrate 100 onto a third direction D3, can be located on the substrate 100. The source region 122 and drain region 124 are horizontally spaced apart from each other (e.g., in the first direction D1) by the gate trench T1 on the substrate 100. The source region 122 and drain region 124 can be parallel to each other in the horizontal direction (e.g., in the first direction D1) relative to the upper region of the gate trench T1. For example, the upper surfaces of the source region 122 and drain region 124 can be coplanar with the upper surface of the substrate 100. Furthermore, the lower surfaces of the source region 122 and drain region 124 can be located above the lower surface of the gate trench T1. Additionally, the source region 122 and drain region 124 can contact the sidewalls of the gate trench T1.

[0040] The source region 122 and the drain region 124 can be formed by doping impurities on a portion of the substrate 100. For example, the source region 122 and the drain region 124 can be formed by doping a portion of the substrate 100 with any one of phosphorus (P), arsenic (As), antimony (Sb) or boron (B).

[0041] A gate electrode 200 may be located within a gate trench T1. The gate electrode 200 may include a gate electrode 210, a gate insulating layer 220, an additional (or "second") insulating layer 230, and a capping layer 240. The gate electrode 210 may partially fill the interior of the gate trench T1. The gate insulating layer 220 may contact the lower surface and sidewalls of the gate trench T1. The gate electrode 210 may partially fill the interior of the gate trench T1, and the gate insulating layer 220 may be located between the substrate 100 and the gate electrode 210 to surround the gate electrode 210. Accordingly, the gate electrode 210 may not directly contact the lower surface and sidewalls of the gate trench T1. The second / additional insulating layer 230 may contact the upper region of the sidewalls of the gate insulating layer 220 in the gate trench T1. The capping layer 240 may be located on the gate electrode 210. The second / additional insulating layer 230 may increase the thickness of the side insulating layer of the semiconductor device 10, thereby reducing gate-induced drain leakage (GIDL).

[0042] The gate electrode 210 may include a lower buried portion (LBP) and an upper buried portion (UBP). The lower buried portion (LBP) may include a first conductive layer 212. The first conductive layer 212 may fill the lower region of the gate trench T1 and may contact the lower surface of the gate insulating layer 220 and the lower region of the sidewall of the gate trench T1. Furthermore, since the lower buried portion (LBP) is located in the lower region of the gate trench T1, it may not overlap with the source region 122 and the drain region 124 in the horizontal direction (e.g., the first direction D1 and the second direction D2), which are parallel to the upper region of the gate trench T1.

[0043] The first conductive layer 212 may include a transition metal material. For example, the first conductive layer 212 may include at least one of molybdenum (Mo), ruthenium (Ru), rhodium (Rh), titanium (Ti), cobalt (Co), tantalum (Ta), or tungsten (W). However, the aspects are not limited thereto, and the first conductive layer 212 may include not only at least one of molybdenum (Mo), ruthenium (Ru), rhodium (Rh), titanium (Ti), cobalt (Co), tantalum (Ta), or tungsten (W), but may also include other transition metal materials that can be deposited by atomic layer deposition (ALD). The first conductive layer 212 may include a compound containing a transition metal material. For example, the first conductive layer 212 may include a transition metal nitride. In some aspects, the first conductive layer 212 may include at least one of titanium nitride (TiN) or tungsten nitride (WN), but is not limited thereto. Furthermore, the first conductive layer 212 may include a material or a p-type material having a mid-bandgap work function that is thermally stable at high temperatures (about 1000°C or higher).

[0044] The upper buried portion UBP may include a work function adjustment layer 216 and a second conductive layer 214. The work function adjustment layer 216 may contact an additional insulating layer 230 in the upper region of the sidewall of the gate insulating layer 220 in the gate trench T1. Correspondingly, the work function adjustment layer 216 and the gate insulating layer 220 may not contact each other. The second conductive layer 214 may contact the first conductive layer 212 and the work function adjustment layer 216, while filling the upper region of the gate trench T1. For example, the lower portion of the second conductive layer 214 may pass through the upper portion of the first conductive layer 212 and be buried. Correspondingly, the lower surface of the second conductive layer 214 may be located below the upper surface of the first conductive layer 212. In embodiments where a portion of the second conductive layer 214 is buried in the first conductive layer 212, the problem of word line resistance breakage due to the loss of the first conductive layer 212 can be improved even when the gate trench T1 is formed at a lower depth. Furthermore, the work function adjustment layer 216 may surround the second conductive layer 214, but may not cover the upper and lower surfaces of the second conductive layer 214. Additionally, since the upper buried portion (UBP) is disposed in the upper region of the gate trench T1, at least a portion of the upper buried portion (UBP) may overlap with the source region 122 and drain region 124 parallel to the upper region of the gate trench T1 in the horizontal direction (e.g., the first direction D1 and the second direction D2). Accordingly, at least a portion of the work function adjustment layer 216 and at least a portion of the second conductive layer 214 may overlap with the source region 122 and drain region 124 in the horizontal direction (e.g., the first direction D1 and the second direction D2).

[0045] The second conductive layer 214 may include a transition metal. For example, the second conductive layer 214 may include at least one of molybdenum (Mo), ruthenium (Ru), rhodium (Rh), titanium (Ti), cobalt (Co), tantalum (Ta), or tungsten (W). However, the aspects are not limited thereto, and the second conductive layer 214 may include not only at least one of molybdenum (Mo), ruthenium (Ru), rhodium (Rh), titanium (Ti), cobalt (Co), tantalum (Ta), or tungsten (W), but may also include other transition metal materials that can be deposited by atomic layer deposition (ALD). The second conductive layer 214 may include compounds containing transition metal materials. For example, the second conductive layer 214 may include transition metal nitrides. In some aspects, the second conductive layer 214 may include at least one of titanium nitride (TiN) or tungsten nitride (WN), but is not limited thereto. Furthermore, the second conductive layer 214 may include a material or a p-type material having a mid-bandgap work function that is thermally stable at high temperatures (e.g., about 1000°C or higher).

[0046] The second conductive layer 214 may include a transition metal that is the same as or different from the transition metal of the first conductive layer 212. Furthermore, the second conductive layer 214 may include a transition metal compound that is the same as or different from the transition metal compound of the first conductive layer 212. Alternatively, the second conductive layer 214 may include a material that is the same as or different from the material having a medium band gap work function or a p-type material of the first conductive layer 212.

[0047] The work function adjustment layer 216 may include a material with a lower work function than the first conductive layer 212 and the second conductive layer 214. For example, the work function adjustment layer 216 may include n-type doped polysilicon or a metal (e.g., aluminum (Al)). Furthermore, the work function adjustment layer 216 may include a material that is thermally stable at high temperatures (e.g., 1000°C or higher) in subsequent processes. The work function of the gate electrode 210 can be reduced by the work function adjustment layer 216. Therefore, leakage current due to gate-induced drain leakage (GIDL) can be reduced. A capping layer 240 may be located on the upper surface of the second conductive layer 214 and the work function adjustment layer 216.

[0048] At least a portion of the additional insulating layer 230 may be located between the lower end of the work function adjustment layer 216 and at least a portion of the first conductive layer 212. For example, the end of the additional insulating layer 230 between the gate insulating layer 220 and the work function adjustment layer 216 may extend in a horizontal direction (e.g., a first direction D1 and a second direction D2). In this case, the portion of the additional insulating layer 230 between the work function adjustment layer 216 and the first conductive layer 212 (e.g., a portion of the additional insulating layer 230 that bends or protrudes in the first direction D1) may contact the second conductive layer 214. In this case, the portion of the additional insulating layer 230 between the lower end of the work function adjustment layer 216 and at least a portion of the first conductive layer 212 may have a thickness of 10 Å or greater. The GIDL phenomenon can be reduced by using the additional insulating layer 230 located between the lower end of the work function adjustment layer 216 and at least a portion of the first conductive layer 212.

[0049] The gate insulating layer 220 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. The high-k material may include a material with a dielectric constant greater than that of silicon oxide. For example, the high-k material may include a material with a dielectric constant greater than 3.9. In another example, the high-k material may include a material with a dielectric constant greater than 10. The high-k material may include at least one metallic element. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. The high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. Other known high-k materials may be used as high-k materials.

[0050] The additional insulating layer 230 may include silicon oxide, silicon nitride, silicon oxynitride, high-k materials, or combinations thereof. For example, the additional insulating layer 230 may include the same material as the gate insulating layer 220.

[0051] The capping layer 240 may include an insulating material. For example, the capping layer 240 may include silicon nitride, silicon oxynitride, or a combination thereof. Alternatively, the capping layer 240 may include a combination of silicon nitride and silicon oxide. For example, after lining with silicon nitride, a spin-on dielectric (SOD) may be filled to form the capping layer 240. The capping layer 240 may be located above the second conductive layer 214 and the work function adjustment layer 216. An additional insulating layer 230 may extend in the third direction D3 to the side surface of the capping layer 240. Accordingly, the side surface of the capping layer 240 may be surrounded by the additional insulating layer 230.

[0052] Figure 3 This is a cross-sectional view of another example of a semiconductor device.

[0053] Figure 3 Semiconductor device 10a can be used with Figure 2 The semiconductor device 10 is essentially the same, but in this case, at least a portion of the additional insulating layer 230a is not located between the lower end of the work function adjustment layer 216 and the first conductive layer 212. (In the description...) Figure 3 At that time, and Figure 1 and Figure 2 Overlapping elements or operations are briefly described or not described, as it is understood that similar elements and operations have similar descriptions in all figures.

[0054] The additional insulating layer 230a can contact the upper region of the sidewall of the gate insulating layer 220 in the gate trench T1. The second conductive layer 214 can partially fill the upper region in the gate trench T1, and the work function adjustment layer 216 can be located between at least a portion of the second conductive layer 214 and at least a portion of the gate insulating layer 220, such that the side surface of at least a portion of the second conductive layer 214 can contact the work function adjustment layer 216. Accordingly, the second conductive layer 214 may not directly contact the gate insulating layer 220. Furthermore, at least a portion of the upper surface of the first conductive layer 212 can contact the lower surface of the additional insulating layer 230a and the lower surface of the work function adjustment layer 216. For example, the lower surface of the additional insulating layer 230a on the gate insulating layer 220 and the lower surface of the work function adjustment layer 216 can sequentially contact at least a portion of the upper surface of the first conductive layer 212.

[0055] Figure 4 This is a cross-sectional view of another example of a semiconductor device.

[0056] Figure 4 Semiconductor device 10b can be used with Figure 2The semiconductor device 10 is basically the same as that of semiconductor device 10b, except that it may also include a dipole layer 250. In the description Figure 4 At that time, and Figure 1 and Figure 2 Overlapping elements or operations are briefly described or not described at all.

[0057] refer to Figure 4 The semiconductor device 10b may further include a dipole layer 250 between the work function adjustment layer 216 and the additional insulating layer 230. For example, at the boundary between the work function adjustment layer 216 and the additional insulating layer 230, one side surface of the dipole layer 250 may contact the work function adjustment layer 216, and the opposite side surface and lower surface of the dipole layer 250 may contact the additional insulating layer 230.

[0058] The dipole layer 250 may include an oxide of the dipole element. For example, the dipole layer 250 may include at least one of zinc oxide, lanthanum aluminate, barium titanate, or lead zirconate titanate. However, the material forming the dipole layer 250 is not limited to the above materials and may include compounds of dipole elements having a low work function. The dipole layer 250 may reduce the effective work function between the upper buried portion UBP and the source region 122 and / or between the upper buried portion UBP and the drain region 124.

[0059] Figures 5 to 7 This is a cross-sectional view of another example of a semiconductor device.

[0060] Figures 5 to 7 Semiconductor devices 10c, 10d, and 10e can be used with Figure 2 The semiconductor devices 10 are basically the same, except that they may also include barrier layers 260a, 260b, and 260c. In the description... Figures 5 to 7 At that time, and Figure 1 and Figure 2 Overlapping elements or operations are briefly described or not described at all.

[0061] refer to Figure 5 The semiconductor device 10c may further include a barrier layer 260a between the first conductive layer 212 and the additional insulating layer 230. Alternatively or additionally, refer to... Figure 6 The semiconductor device 10d may further include a barrier layer 260b above the work function adjustment layer 216 and the second conductive layer 214. Alternatively or additionally, see reference. Figure 7 The semiconductor device 10e may also include a barrier layer 260c between the additional insulating layer 230 and the work function adjustment layer 216. The barrier layers 260a, 260b and 260c may be used to block impurities diffusing from the low-resistivity material or to prevent interdiffusion and reaction between different materials.

[0062] Barrier layers 260a, 260b, and 260c may comprise nitrides or metals. For example, barrier layers 260a, 260b, and 260c may comprise at least one of titanium nitride (TiN), tungsten nitride (WN), aluminum nitride (AlN), or silicon nitride (SiN). Alternatively, barrier layers 260a, 260b, and 260c may comprise at least one of titanium (Ti) or tantalum (Ta).

[0063] Figure 8 This is a diagram illustrating an example configuration of a storage device array. Furthermore, Figure 9 It is along Figure 8 The image shows a cross-sectional view taken from line BB. The storage device can be dynamic random access memory (DRAM), but is not limited to it.

[0064] The memory device array MA may include a plurality of active patterned APs. Each of the plurality of active patterned APs may have a stripe extending in a first direction D1. Each of the plurality of active patterned APs may have an isolation shape. The plurality of active patterned APs may be defined by a device isolation film 110 on a substrate 100. The device isolation film 110 may be a shallow trench isolation (STI) region formed by trench etching. The device isolation film 110 may include silicon oxide, silicon nitride, or a combination thereof. Source region (e.g., Figure 2 The source region 122) and the drain region (e.g., Figure 2 The drain region 124 can be in each active pattern AP and adjacent to the gate electrode 210.

[0065] A memory device array MA can include multiple word lines WL. Each of the multiple word lines WL can represent a gate electrode ( Figure 2 (Gate electrode 210). Each of the multiple word lines WL may intersect at least a portion of the multiple active patterns AP. Each of the multiple word lines WL may extend in a fifth direction D5 and may be spaced apart from each other in a fourth direction D4. Each of the multiple word lines WL may be in a trench formed in the substrate 100. For example, as Figure 9 As shown, the gate electrode 210 can be in the gate trench T1 formed in the substrate 100.

[0066] The memory device array MA may include multiple bit lines BL. Each of the multiple bit lines BL can be electrically connected to the source region of the memory device (e.g., ) via a first contact 400. Figure 2 The source region 122). Each of the multiple bit lines BL may intersect at least a portion of the multiple active patterns AP. Each of the multiple bit lines BL may extend in the fourth direction D4 and may be spaced apart from each other in the fifth direction D5.

[0067] The array of multiple storage devices MA may include multiple capacitors CA. Each of the multiple capacitors may be electrically connected to the drain region of the storage device (e.g., drain region 124) via a second contact 600.

[0068] Figure 9 It shows the formation Figure 8 Example of storage device 1 in storage device array MA.

[0069] refer to Figure 9 The storage device 1 may include a semiconductor device 10, a bit line BL, and a capacitor CA. Figure 9 The storage device 1 is shown to include Figure 2 The semiconductor device 10 shown may include the memory device 1, but the memory device 1 may include the semiconductor device 1. Figures 3 to 7 Any one of the semiconductor devices 10a, 10b, 10c, 10d, and 10e shown. Furthermore, Figure 9 A semiconductor device comprising a source region 122 and two drain regions 124 is shown, wherein a capacitor CA is connected to each drain region 124, but this is for illustrative purposes only and the aspects are not limited thereto.

[0070] The storage device 1 may also include interlayer insulating films 300 and 500 on the substrate 100 of the semiconductor device 10, the interlayer insulating films 300 and 500 covering the source region 122, the drain region 124 and the gate 200.

[0071] The first interlayer insulating film 300 may be on the substrate 100 and the device isolation film 110. The first interlayer insulating film 300 may include a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0072] Bit lines BL can be on the first interlayer insulating film 300. Bit lines BL can include various conductive materials. For example, bit lines BL can include at least one of polycrystalline silicon, titanium nitride (TiN), tungsten (W), titanium (Ti), ruthenium (Ru), or tungsten nitride (WN).

[0073] The first via may be located in a portion of the first interlayer insulating film 300. The storage device 1 may also include a first contact 400 filled in the first via. For example, the first via may be formed to expose the source region 122, and the first contact 400 may contact the source region 122. A bit line BL may be located on the first interlayer insulating film 300 to contact the first contact 400. Accordingly, the bit line BL may be electrically connected to the source region 122 via the first contact 400. The shape and configuration of the first contact 400 may be varied, and the first contact 400 may comprise various conductive materials.

[0074] The second interlayer insulating film 500 may be on the first interlayer insulating film 300 and the bit line BL. The second interlayer insulating film 500 may include a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The second interlayer insulating film 500 may be formed to bury the bit line BL.

[0075] A second via may be formed in a portion of the second interlayer insulating film 500. The storage device 1 may also include a second contact 600 filled in the second via. The second via may extend to the lower surface of the first interlayer insulating film 300. For example, the second via may be formed to expose the drain region 124, and the second contact 600 may contact the drain region 124. A capacitor CA may be on the second interlayer insulating layer 500 to contact the second contact 600. Accordingly, the capacitor CA may be electrically connected to the drain region 124 through the second contact 600. The shape and configuration of the second contact 600 may be varied, and the second contact 600 may include various conductive materials.

[0076] The capacitor CA can be located on the second interlayer insulating film 500. The capacitor CA may include a first electrode 820, a second electrode 840, and a dielectric layer 830 between the first electrode 820 and the second electrode 840. The first electrode 820 may have a cylindrical shape with its lower portion blocked. The second electrode 840 may cover the first electrode 820.

[0077] The first electrode 820 and the second electrode 840 may comprise various conductive materials. The first electrode 820 and the second electrode 840 may comprise at least one of polycrystalline silicon, titanium nitride (TiN), tungsten (W), titanium (Ti), ruthenium (Ru), or tungsten nitride (WN). The dielectric layer 830 may comprise various insulating materials. For example, the dielectric layer 830 may comprise at least one high dielectric constant material, such as zirconium oxide (ZrO2), aluminum oxide (Al2O3), or hafnium oxide (Hf2O3).

[0078] The support layer 700 may be located between the second electrode 840 and the second interlayer insulating film 500. The support layer 700 may also be located on the outer wall of the first electrode 820 to prevent the first electrode 820 from falling off. The support layer 700 may include an insulating material.

[0079] In the semiconductor device 10, the second conductive layer 214 forming the upper buried portion (UBP) and the first conductive layer 212 forming the lower buried portion (LBP) of the word line (WL) extend in the third direction D3, so that even when the gate trench T1 is formed at a lower depth, the problem of word line resistance disconnection due to the loss of the first conductive layer 212 can be improved. Furthermore, due to the work function adjustment layer 216 between the second conductive layer 214 and the additional insulating layer 230, the work function of the gate electrode 210 can be reduced. Accordingly, the leakage current to the source region 122 and the drain region 124 caused by the GIDL phenomenon generated by the word line WL can be reduced. Consequently, the electrical characteristics of the semiconductor device 10 can be improved.

[0080] Figures 10 to 18 It shows the manufacturing process. Figure 2 The diagram shows a cross-sectional view of the process of the semiconductor device.

[0081] refer to Figure 10 A portion of the substrate 100 can be patterned to form a gate trench T1.

[0082] refer to Figure 11 A gate insulating layer 220 covering the lower surface and sidewalls of the gate trench T1 can be formed on the substrate 100. The gate insulating layer 220 can be formed by a thermal oxidation process. Alternatively, the gate insulating layer 220 can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). If the gate insulating layer 220 comprises a silicon oxide film, it can have a thickness of 35 Å or greater. A preliminary first conductive layer 212_P filling the gate trench T1 can be formed on the gate insulating layer 220.

[0083] refer to Figure 12 The initial first conductive layer 212_P can be patterned to form a lower buried portion (LBP), which contacts the lower region of the sidewall of the gate insulating layer 220 in the gate trench T1. The lower buried portion (LBP) may include the first conductive layer 212 that fills the lower region of the gate trench T1 and contacts the lower surface and the lower region of the sidewall of the gate insulating layer 220.

[0084] refer to Figure 13 A preliminary additional insulating layer 230_P can be formed, covering a portion of the upper surface of the first conductive layer 212 and the gate insulating layer 220. The preliminary additional insulating layer 230_P can have a thickness of 10 Å or greater. On the other hand, prior to the formation of the preliminary additional insulating layer 230_P, a barrier layer (e.g., Figure 5 The barrier layer 260a) can be formed on the upper surface of the first conductive layer 212.

[0085] refer to Figure 14A preliminary work function adjustment layer 216_P can be formed, covering the preliminary additional insulating layer 230_P. The preliminary work function adjustment layer 216_P can be formed using atomic layer deposition (ALD). On the other hand, prior to the formation of the preliminary work function adjustment layer 216_P, a barrier layer (e.g., Figure 7 The barrier layer 260c can be formed on the initial additional insulating layer 230_P. On the other hand, before the formation of the initial work function adjustment layer 216_P, the dipole layer (e.g., Figure 4 The dipole layer 250 can be formed on the initial additional insulating layer 230_P.

[0086] refer to Figure 15 The initial additional insulating layer 230_P and the initial work function adjustment layer 216_P can be patterned to form an additional insulating layer 230 that contacts the upper region of the sidewall of the gate insulating layer 220 and a work function adjustment layer 216 on the additional insulating layer 230. During this process, a portion of the upper part of the first conductive layer 212 can also be patterned. Therefore, an upper trench T2 exposing a portion of the first conductive layer 212 can be formed.

[0087] refer to Figure 16 The initial second conductive layer 214_P that fills the trench T2 can be formed on a portion of the upper part of the first conductive layer 212 and the work function adjustment layer 216.

[0088] refer to Figure 17 The initial second conductive layer 214_P and the work function adjustment layer 216 can be patterned to form an upper buried portion UBP that fills the upper region of the gate trench T1. The upper buried portion UBP may include the work function adjustment layer 216 on the additional insulating layer 230, and a second conductive layer 214 that partially fills the upper trench T2 and contacts a portion of the upper part of the first conductive layer 212 and the work function adjustment layer 216. The lower part of the second conductive layer 214 may penetrate the upper part of the first conductive layer 212 to be buried. For example, the lower surface of the second conductive layer 214 may be located below the upper surface of the first conductive layer 212. In this process, a capping trench T3 that exposes a portion of the additional insulating layer 230 can be formed.

[0089] refer to Figure 18 This can form a capping layer 240 that fills the capping layer trench T3. On the other hand, prior to forming the capping layer 240, a barrier layer (e.g., Figure 6 The barrier layer 260b can be formed on the upper surface of the second conductive layer 214 and the work function adjustment layer 216.

[0090] Accordingly, according to aspects of the technical concept of the present invention, a semiconductor device with reduced leakage current and improved word line conductivity can be provided.

[0091] Although the invention has been described herein by way of certain aspects and figures, the invention is not limited thereto, and those skilled in the art can make various changes and modifications within the scope of the technical concept and the equivalent of the claims of the invention.

Claims

1. A semiconductor device, comprising: A source region and a drain region on a substrate, wherein the source region and the drain region are spaced apart from each other; The substrate has a gate trench between the source region and the drain region; A first gate insulating layer covers the lower surface and sidewalls of the gate trench; The second insulating layer in the gate trench that contacts the upper region of the sidewall of the first gate insulating layer; and The gate electrode in the gate trench includes a lower buried portion in the lower region of the gate trench that contacts the first gate insulating layer, and an upper buried portion in the upper region of the gate trench on the lower buried portion. in, The lower buried portion includes a first conductive layer that contacts the sidewalls and lower region of the first gate insulating layer. The upper buried portion includes a work function adjustment layer on the second insulating layer and a second conductive layer in the upper region of the gate trench, wherein the second conductive layer is in contact with the work function adjustment layer and the first conductive layer, and The second conductive layer comprises a transition metal.

2. The semiconductor device according to claim 1, wherein, The lower part of the second conductive layer is buried in the upper part of the first conductive layer.

3. The semiconductor device according to claim 1, wherein, The first conductive layer comprises the same transition metal as the second conductive layer.

4. The semiconductor device according to claim 3, wherein, The transition metal includes at least one selected from the group consisting of molybdenum (Mo), ruthenium (Ru), rhodium (Rh), titanium (Ti), cobalt (Co), tantalum (Ta), and tungsten (W).

5. The semiconductor device according to claim 1, wherein, The work function adjustment layer comprises a material whose work function is lower than that of the first conductive layer and lower than that of the second conductive layer.

6. The semiconductor device according to claim 5, wherein, The work function adjustment layer comprises n-type doped polycrystalline silicon or metal.

7. The semiconductor device of claim 1, wherein the second insulating layer comprises at least one material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and high-k materials.

8. The semiconductor device of claim 1, wherein at least a portion of the second insulating layer is located between the lower end of the work function adjustment layer and the first conductive layer.

9. The semiconductor device according to claim 8, wherein, The thickness of the portion of the second insulating layer located between the lower end of the work function adjustment layer and the first conductive layer is 10 Å or greater.

10. The semiconductor device of claim 1, further comprising a dipole layer located between the work function adjustment layer and the second insulating layer.

11. The semiconductor device according to claim 10, wherein, The dipole layer comprises at least one material selected from the group consisting of zinc oxide, lanthanum aluminate, barium titanate, and lead zirconate titanate.

12. The semiconductor device of claim 1, further comprising a barrier layer, wherein the barrier layer: Between the first conductive layer and the second insulating layer Between the second insulating layer and the work function adjustment layer, or Above the work function adjustment layer and the second conductive layer.

13. The semiconductor device according to claim 12, wherein, The barrier layer comprises at least one material selected from the group consisting of titanium nitride (TiN), tungsten nitride (WN), aluminum nitride (AlN), silicon nitride (SiN), titanium, and tantalum.

14. A semiconductor device, comprising: A source region and a drain region on a substrate, wherein the source region and the drain region are spaced apart from each other by a gate trench; A first gate insulating layer covers the lower surface and sidewalls of the gate trench; The second insulating layer in the gate trench that contacts the upper region of the sidewall of the first gate insulating layer; and The gate electrode includes a lower buried portion surrounded by the first gate insulating layer and located in the lower region of the gate trench, and an upper buried portion on the lower buried portion and located in the upper region of the gate trench. in, The lower buried portion includes a first conductive layer surrounded by the sidewalls of the first gate insulating layer and a lower region. The second insulating layer is located on the upper surface of the first conductive layer and in the upper region of the sidewall of the first gate insulating layer. The upper buried portion includes a work function adjustment layer surrounded by the second insulating layer and a second conductive layer surrounded by the work function adjustment layer, and The second conductive layer comprises a transition metal.

15. The semiconductor device according to claim 14, wherein, The lower part of the second conductive layer is buried in the upper part of the first conductive layer.

16. The semiconductor device according to claim 14, wherein, The first conductive layer comprises the same transition metal as the second conductive layer.

17. The semiconductor device according to claim 15, wherein, The transition metal includes at least one selected from the group consisting of molybdenum (Mo), ruthenium (Ru), rhodium (Rh), titanium (Ti), cobalt (Co), tantalum (Ta), and tungsten (W).

18. The semiconductor device according to claim 14, wherein, The work function adjustment layer comprises a material whose work function is lower than that of the first conductive layer and lower than that of the second conductive layer.

19. The semiconductor device according to claim 18, wherein, The work function adjustment layer comprises n-type doped polycrystalline silicon or metal.

20. A storage device, comprising: Semiconductor devices; as well as A capacitor, electrically connected to the semiconductor device, The semiconductor device includes: Source and drain regions spaced apart from each other on the substrate; The substrate has a gate trench between the source region and the drain region; A first gate insulating layer covers the lower surface and sidewalls of the gate trench; The second insulating layer in the gate trench that contacts the upper region of the sidewall of the first gate insulating layer; and The gate electrode in the gate trench includes a lower buried portion in the lower region of the gate trench that contacts the first gate insulating layer, and an upper buried portion in the upper region of the gate trench on the lower buried portion. in, The lower buried portion includes a first conductive layer that contacts the sidewalls and lower region of the first gate insulating layer. The upper buried portion includes a work function adjustment layer on the second insulating layer and a second conductive layer in the upper region of the gate trench, wherein the second conductive layer is in contact with the work function adjustment layer and the first conductive layer, and The second conductive layer comprises a transition metal.

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