Semiconductor device

Abstract

A semiconductor device includes: a substrate and a peripheral circuit region; and a cell array region at a distance from the substrate different from a distance of the peripheral circuit region from the substrate, and electrically connected to the peripheral circuit region through a bonding pad, in which the cell array region includes: a molded structure extending in a first horizontal direction; an active semiconductor layer on a sidewall of the molding structure and including a first oxide semiconductor; a word line on a sidewall of the active semiconductor; a unit capacitor on an upper surface of the active semiconductor layer; a bit line on a bottom surface of the active semiconductor layer and extending in a second horizontal direction; and an intermediate line between the bottom surface of the active semiconductor layer and the bit line, extending in the second horizontal direction, and including a second oxide semiconductor.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0060759, filed on May 8, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to semiconductor devices, and more specifically, to semiconductor devices including vertical channel transistors. Background Technology

[0003] As the size of semiconductor devices shrinks, the size of dynamic random access memory (DRAM) devices is also shrinking. In DRAM devices with a 1T-1C structure where one capacitor is connected to another, leakage current through the channel region becomes increasingly large due to the smaller size of the device. To reduce leakage current, vertical channel transistors using oxide semiconductor materials as the channel layer have been proposed. Summary of the Invention

[0004] The inventive concept provides a semiconductor device with excellent electrical performance.

[0005] According to some embodiments of the inventive concept, a semiconductor device is provided, the semiconductor device comprising: a substrate; a peripheral circuit region on the substrate; and a cell array region electrically connected to the peripheral circuit region via bonding pads at a distance different from the distance of the peripheral circuit region from the substrate. The cell array region includes: a molded structure extending in a first horizontal direction; an active semiconductor layer on a sidewall of the molded structure, comprising a first oxide semiconductor; a word line on the sidewall of the active semiconductor; a cell capacitor on an upper surface of the active semiconductor layer; a bit line on a bottom surface of the active semiconductor layer and extending in a second horizontal direction intersecting the first horizontal direction; and a center line between the bottom surface of the active semiconductor layer and the bit line, the center line extending along the second horizontal direction and comprising a second oxide semiconductor.

[0006] According to some embodiments of the inventive concept, a semiconductor device is provided, the semiconductor device comprising: a substrate; a peripheral circuit region on the substrate; and a cell array region on the peripheral circuit region, wherein the cell array region comprises: a plurality of molded structures extending in a first horizontal direction; a plurality of active semiconductor layers spaced apart from each other in the first direction, one of the plurality of active semiconductor layers extending between adjacent molded structures in the plurality of molded structures and in a vertical direction intersecting the first horizontal direction; a first word line and a second word line spaced apart from each other between adjacent molded structures in the plurality of molded structures and extending in the first horizontal direction; a plurality of bit lines at a first distance from the substrate less than a second distance from the plurality of active semiconductor layers to the substrate and less than a third distance from the plurality of molded structures to the substrate, the plurality of bit lines extending in a second horizontal direction intersecting the first horizontal direction and the vertical direction; and a plurality of intermediate lines between a corresponding active semiconductor layer in the plurality of active semiconductor layers and a corresponding bit line in the plurality of bit lines, and between the plurality of molded structures and the plurality of bit lines, and extending in a second horizontal direction.

[0007] According to some embodiments of the inventive concept, a semiconductor device is provided, the semiconductor device comprising: a peripheral circuit region including a substrate and peripheral circuit transistors; and a cell array region on the peripheral circuit region, wherein the cell array region comprises: a molded structure extending in a first horizontal direction; an active semiconductor layer on a sidewall of the molded structure and including a first oxide semiconductor; a word line on a sidewall of the active semiconductor layer; a gate insulating layer between the sidewall of the active semiconductor layer and the word line; a pad on an upper surface of the active semiconductor layer; a cell capacitor on the pad; a middle line on a bottom surface of the active semiconductor layer and a bottom surface of the molded structure, the middle line extending in a second horizontal direction and including a second oxide semiconductor; a bit line on the bottom surface of the middle line and extending in a second horizontal direction; a bit line insulating layer on the bit line and on a sidewall of the middle line; and a shielding metal layer at a side of the bit line, the bit line insulating layer being between the shielding metal layer and the side of the bit line. Attached Figure Description

[0008] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 This is a schematic diagram illustrating a semiconductor device according to an embodiment.

[0010] Figure 2 yes Figure 1 An enlarged layout diagram of the cell array region.

[0011] Figure 3 yes Figure 2The layout is a sectional view taken along line A1-A1'.

[0012] Figure 4 yes Figure 2 A sectional view taken along line A2-A2'.

[0013] Figure 5 yes Figure 3 A magnified view of region CX1.

[0014] Figure 6 yes Figure 4 A magnified view of region CX2.

[0015] Figure 7 and Figure 8 This is a cross-sectional view showing a semiconductor device according to an embodiment.

[0016] Figure 9 yes Figure 8 A magnified view of region CX2.

[0017] Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C ,as well as Figures 22 to 24 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0018] Figure 1 This is a schematic diagram illustrating a semiconductor device 100 according to an embodiment. Figure 2 yes Figure 1 An enlarged layout diagram of the MCA portion of the cell array region. Figure 3 yes Figure 2The layout is a sectional view taken along line A1-A1'. Figure 4 yes Figure 2 A sectional view taken along line A2-A2'. Figure 5 yes Figure 3 A magnified view of region CX1. Figure 6 yes Figure 4 A magnified view of region CX2.

[0019] Reference Figures 1 to 6 The semiconductor device 100 may include a peripheral circuit region PCA and a cell array region MCA at a vertical height higher than the peripheral circuit region PCA.

[0020] In some embodiments, the cell array region MCA can be a memory cell region of a dynamic random access memory (DRAM) device, and the peripheral circuit region PCA can be a core region or a peripheral circuit region of the DRAM device. For example, the peripheral circuit region PCA may include peripheral circuit transistors (PTRs) for transmitting signals and / or power to the memory cell array included in the cell array region MCA. In embodiments, the peripheral circuit transistors (PTRs) may be configured with various circuits, such as command decoders, control logic, address buffers, row decoders, column decoders, sense amplifiers, or data input / output circuitry.

[0021] like Figure 2 As shown, multiple word lines WL extending in the first horizontal direction X and multiple bit lines BL extending in the second horizontal direction Y can be arranged in the cell array region MCA. Multiple cell transistors CTR can be located at the intersection points of the multiple word lines WL and the multiple bit lines BL. Multiple cell capacitors CAP can be respectively disposed on the multiple cell transistors CTR.

[0022] Multiple word lines WL may include first word lines WL1 and second word lines WL2 alternately arranged in the second horizontal direction Y, and multiple unit transistors CTR may include first unit transistors CTR1 and second unit transistors CTR2 alternately arranged in the second horizontal direction Y. First unit transistors CTR1 may be arranged adjacent to the first word line WL1, and second unit transistors CTR2 may be arranged adjacent to the second word line WL2. First unit transistors CTR1 and second unit transistors CTR2 may have a structure that is mirror-symmetrical about each other. For example, first unit transistors CTR1 and second unit transistors CTR2 may have a structure that is mirror-symmetrical about a center line extending in the first horizontal direction X between first unit transistors CTR1 and second unit transistors CTR2.

[0023] In an embodiment, the pitch of the multiple bit lines BL (e.g., the sum of the width of one bit line BL and the gap between two adjacent bit lines BL) can be 2F, the pitch of the first word line WL1 can be 2F (or the pitch of the second word line WL2 can be 2F), and the cell area used to form a unit transistor CTR can be 4F. 2 Therefore, since the unit transistor CTR can have a cross-point type that requires a relatively small unit area, it is beneficial to improve the integration density of the semiconductor device 100.

[0024] Although not shown, an edge region may be arranged around the cell array region MCA. The edge region may be a region where electrical connection members for word lines WL and / or for bit lines BL can be arranged, and may also be a region where electrical connection members that realize electrical connections between the cell array region MCA and the peripheral circuit region PCA can be arranged.

[0025] Below, as Figure 3 and Figure 4 As shown, the cell array region MCA is depicted at a higher vertical height (e.g., when the cell array region MCA is positioned on the peripheral circuit region PCA). However, the semiconductor device 100 may be arranged upside down such that the cell array region MCA is at a lower vertical height than the peripheral circuit region PCA. In this case, it should be understood that in the following description, the term "upper surface" or "bottom surface" of an element may also refer to the "bottom surface" or "upper surface" of the element, respectively; an element described as "above" or "below" the element may also refer to "below" or "above" the element, respectively; and an element described as "at a higher vertical height" may also refer to "at a lower vertical height."

[0026] The substrate 110 may include, for example, monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, the substrate 110 may include at least one selected from germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the substrate 110 may include conductive regions (e.g., impurity-doped wells or impurity-doped structures).

[0027] In the peripheral circuit region PCA, the active region AC can be defined in the substrate 110, and the peripheral circuit transistor PTR can be disposed on the active region AC. The peripheral circuit transistor PTR may include a gate electrode PTG, a gate insulating layer PTI, and a source / drain region PTS.

[0028] A peripheral circuit transistor (PTR) and a peripheral circuit line structure 120 may be disposed on a substrate 110. The peripheral circuit line structure 120 may include a peripheral circuit line 122, a peripheral circuit contact 124, and a peripheral circuit insulating layer 126. The peripheral circuit line 122 and the peripheral circuit contact 124 may be electrically connected to the peripheral circuit transistor PTR and / or the substrate 110, and on the substrate 110, the peripheral circuit insulating layer 126 may cover the peripheral circuit transistor PTR, the peripheral circuit line 122, and the peripheral circuit contact 124, or be stacked with the peripheral circuit transistor PTR, the peripheral circuit line 122, and the peripheral circuit contact 124. The peripheral circuit insulating layer 126 may include an oxide film, a nitride film, a low-k dielectric film, or a combination thereof, and may be formed by a stacked structure of multiple insulating layers.

[0029] The peripheral circuit region PCA can be attached to the cell array region MCA via a bonding method. In an embodiment, the boundary between the peripheral circuit region PCA and the cell array region MCA may be referred to as the bonding interface BIF. For example, Figure 3 The portion of the semiconductor device 100 shown that is lower in vertical height than the bonding interface BIF relative to the substrate 110 can be referred to as the peripheral circuit region PCA, and the portion that is higher in vertical height than the bonding interface BIF relative to the substrate 110 can be referred to as the cell array region MCA.

[0030] In this embodiment, the peripheral circuitry structure 120 and the unit wiring structure 160 may be in contact with each other, and the bonding interface BIF is located between the peripheral circuitry structure 120 and the unit wiring structure 160. The unit wiring structure 160 may include a unit wiring layer 162, a unit contact 164, and a unit insulating layer 166.

[0031] The bonding pad BP may be located at the interface between the unit wiring structure 160 and the peripheral circuitry structure 120 (e.g., at the bonding interface BIF). The bonding pad BP may include a first bonding pad BP1 and a second bonding pad BP2. The upper surface of the second bonding pad BP2 may be at the same height as the upper surface of the peripheral circuitry insulating layer 126, the bottom surface of the first bonding pad BP1 may be at the same height as the bottom surface of the unit insulation layer 166, and the upper surface of the second bonding pad BP2 may contact the bottom surface of the first bonding pad BP1.

[0032] In an embodiment, the unit wiring structure 160 and the peripheral circuit line structure 120 can be attached to each other by a metal-oxide mixture bonding method. In this case, the interface between the peripheral circuit insulating layer 126 and the unit insulating layer 166 can be coplanar with the interface between the first bonding pad BP1 and the second bonding pad BP2 (for example, the interface between the peripheral circuit insulating layer 126 and the unit insulating layer 166 and the interface between the first bonding pad BP1 and the second bonding pad BP2 can be arranged along the bonding interface BIF).

[0033] In other embodiments, the unit wiring structure 160 and the peripheral circuit line structure 120 may be attached to each other by an oxide bonding method (in which case the bonding pad BP may be omitted).

[0034] Multiple bit lines BL can be disposed on the cell wiring structure 160, cell transistors CTR can be disposed on the multiple bit lines BL, and cell capacitors CAP can be disposed on the cell transistors. In an embodiment, the bit lines BL can be arranged closer to the bonding interface BIF than the cell transistors CTR or the cell capacitors CAP. Therefore, the vertical distance between the bit lines BL and the peripheral circuit transistors PTR can be smaller than the vertical distance between the cell capacitors CAP and the peripheral circuit transistors PTR.

[0035] In this embodiment, multiple bit lines BL can extend in a second horizontal direction Y, and a shielding metal layer SS can be disposed in the space between the multiple bit lines BL. For example, the multiple bit lines BL can be arranged to extend in the second horizontal direction Y, a portion of the shielding metal layer SS can be arranged to extend in the second horizontal direction Y and fill the space between the multiple bit lines BL, and another portion of the shielding metal layer SS can be disposed between the bottom surface of the multiple bit lines BL and the upper surface of the unit wiring structure 160. The sidewalls and bottom surface of the bit lines BL can be covered by or superimposed with the first bit insulation layer 152 and the second bit insulation layer 154, and the first bit insulation layer 152 and the second bit insulation layer 154 can be disposed between the sidewalls of the bit lines BL and the shielding metal layer SS, and between the bottom surface of the bit lines BL and the shielding metal layer SS.

[0036] In embodiments, the bit line BL may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), titanium silicide (TiSi), titanium nitride silicon (TiSiN), tungsten silicide (WSi), tungsten nitride silicon (WSiN), tantalum silicide (TaSi), tantalum nitride silicon (TaSiN), ruthenium titanium nitride (RuTiN), cobalt silicide (CoSi), nickel silicide (NiSi), polycrystalline silicon, or combinations thereof. In embodiments, the shielding metal layer SS may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, copper (Cu), aluminum (Al), TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, or combinations thereof.

[0037] The bit line contact 156 can be disposed between the bottom surface of the bit line BL and the unit wiring layer 162, and the sidewall of the bit line contact 156 can be surrounded by the bit line contact spacer 158. The bit line contact 156 can be electrically insulated from the shielding metal layer SS through the bit line contact spacer 158.

[0038] Multiple intermediate lines BUL can be respectively disposed on the upper surface of multiple bit lines BL. The multiple intermediate lines BUL can be arranged to extend in the second horizontal direction Y, and each of the multiple intermediate lines BUL can cover or overlap with the corresponding upper surface of the multiple bit lines BL. The sidewalls BULa of the multiple intermediate lines BUL can be covered by or overlapped by the first line insulation layer 152.

[0039] In an embodiment, the multiple intermediate lines BUL may comprise an oxide semiconductor, for example, the oxide semiconductor may comprise zinc tin oxide (ZnO). x Sn y O), Indium zinc oxide (In) x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn zO), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O) and zirconium zinc tin oxide (Zr) x Zn y Sn z At least one of (O). In embodiments, the multiple intermediate line BULs may comprise semiconductor materials (such as silicon, germanium, or silicon-germanium). In embodiments, the multiple intermediate line BULs may also comprise n-type impurity ions. For example, n-type impurity ions may be doped into the multiple intermediate line BULs by means of an ion implantation process or the like.

[0040] In an embodiment, the sidewall BULa of each of the plurality of intermediate lines BUL may be aligned with the sidewall BLa of each of the plurality of bit lines BL. In an embodiment, each of the plurality of intermediate lines BUL may have a first width w1 in a first horizontal direction X, each of the plurality of bit lines BL may have a second width w2 in the first horizontal direction X, and the first width w1 may be equal to or similar to the second width w2. Here, the first width w1 being equal to or similar to the second width w2 may mean that the second width w2 has a value within the tolerance range of the first width w1 (e.g., the first width w1 has a value within a range that takes into account tolerances or errors in the manufacturing process (such as a value within ±5% or ±10% of the first width w1)).

[0041] In this embodiment, multiple intermediate line BULs can be patterned together in a patterning process for multiple bit lines BL. For example, intermediate line layer BULp (see Figure 19A and Figure 19B ) and bitline layer BLp (see Figure 19A and Figure 19B ) can be sequentially formed on the molded structure 130 and the unit transistor CTR, and then the intermediate line layer BULp (see Figure 19A and Figure 19B ) and bitline layer BLp (see Figure 19A and Figure 19B It can be patterned as a line type to form multiple intermediate lines BUL and multiple bit lines BL. In this case, the sidewalls BULa of each of the multiple intermediate lines BUL and the sidewalls BLa of each of the multiple bit lines BL can be aligned with each other.

[0042] In some embodiments, during the patterning process for forming multiple intermediate lines BUL and multiple bit lines BL, portions of the multiple bit lines BL may be exposed to an etching atmosphere for a longer period of time, in which case the sidewalls BLa of the multiple bit lines BL may be tilted at a specific angle.

[0043] In an embodiment, the bit line BL may have a flat top surface (or a uniform top height) and a flat bottom surface (or a uniform bottom height). For example, the bit line BL may have a uniform thickness in the vertical direction Z along its entire length along the second horizontal direction Y. Furthermore, the intermediate line BUL may have a flat top surface (or a uniform top height) and a flat bottom surface (or a uniform bottom height). For example, the intermediate line BUL may have a uniform thickness in the vertical direction Z along its entire length along the second horizontal direction Y.

[0044] Multiple molded structures 130 and multiple unit transistors CTRs may be disposed on the upper surface of multiple center lines BUL. For example, each of the multiple molded layers 130 may extend in a first horizontal direction X, and the multiple unit transistors CTRs may be disposed on opposite sidewalls of each of the molded structures 130.

[0045] Each of the plurality of molding structures 130 may include a first molding layer 132, a second molding layer 134, and a third molding layer 136 disposed in the vertical direction Z. For example, the third molding layer 136 may be disposed on the center line BUL and the first line insulation layer 152, and for example, the third molding layer 136 may be arranged to contact the center line BUL and the first line insulation layer 152. The second molding layer 134 may be disposed on the third molding layer 136, and the first molding layer 132 may be disposed on the second molding layer 134.

[0046] In some embodiments, each of the first molding layer 132, the second molding layer 134, and the third molding layer 136 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material. In some embodiments, the first molding layer 132 and the third molding layer 136 may include silicon nitride or silicon oxynitride, and the second molding layer 134 may include silicon oxide or a low-k dielectric material.

[0047] In an embodiment, the unit transistor CTR may include an active semiconductor layer AP, a gate insulating layer GI, and a word line WL sequentially disposed on the sidewall of the molded structure 130.

[0048] In this embodiment, the active semiconductor layer AP may extend in the vertical direction Z and may have an upper surface configured to be coplanar with the upper surface of the molding structure 130 and a bottom surface configured to be coplanar with the bottom surface of the molding structure 130. The bottom surface of the active semiconductor layer AP and the bottom surface of the molding structure 130 may contact the upper surface of the centerline BUL.

[0049] In this embodiment, the active semiconductor layer AP may include Zn. x Sn y O、In x Zn y O, ZnO x Inx Ga y Zn z O、In x Ga y Si z O、In x W y O、In x O、Sn x O, Ti x O, Zn x ON z Mg x Zn y O、Zr x In y Zn z O、Hf x In y Zn z O、Sn x In y Zn z O, Al x Sn y In z Zn a O, Si x In y Zn z O, Al x Zn y Sn z O.Ga x Zn y Sn z O and Zr x Zn y Sn z At least one of O. In an embodiment, the active semiconductor layer AP may further include n-type impurity ions. For example, n-type impurity ions may be doped into the active semiconductor layer AP by means of an ion implantation process or the like.

[0050] The gate insulating layer GI may be further disposed on the sidewall of the active semiconductor layer AP. In an embodiment, the gate insulating layer GI may include at least one high-k dielectric material selected from those having a higher dielectric constant than silicon oxide and ferroelectric materials. In some embodiments, the gate insulating layer GI may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconium titanium oxide (PbZrTiO), strontium bismuth tantalate (SrTaBiO, STB), bismuth iron oxide (BiFeO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0051] Word lines WL may be disposed on the sidewalls of the gate insulating layer GI. In some embodiments, word lines WL may comprise Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or combinations thereof. For example, two word lines WL may be spaced apart from each other between two adjacent molding structures 130 and may extend in a first horizontal direction X. For example, a first word line WL1 and a second word line WL2 may be spaced apart from each other between two adjacent molding structures 130. The upper surface of the word lines WL may be covered by or stacked with the gate insulating layer GI, and the bottom surface of the word lines WL may be at a vertical height higher than the bottom surface of the active semiconductor layer AP.

[0052] An insulating liner 142 and a buried insulating layer 144 may be disposed between the first word line WL1 and the second word line WL2. The insulating liner 142 may be conformally disposed on the sidewalls and bottom surfaces of the first word line WL1 and the second word line WL2, and may be disposed between the word line WL1 and the buried insulating layer 144.

[0053] Multiple landing pads (LPs) may be disposed on multiple unit transistors (CTRs), and a unit capacitor (CAP) may be disposed on each of the landing pads (LPs). The multiple landing pads (LPs) may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or combinations thereof. The unit capacitor (CAP) may have a metal-insulator-metal type capacitor structure. For example, the unit capacitor (CAP) may include a first electrode, a second electrode, and a capacitor dielectric layer disposed between the first electrode and the second electrode. An insulating layer 176 may be disposed on at least a portion of the unit capacitor (CAP) and on the sidewalls of the landing pads (LPs).

[0054] In a semiconductor device including an oxide semiconductor channel, according to a comparative example, after an active semiconductor layer AP is formed on the sidewall of a molded structure, a recess is formed by removing a portion of the active semiconductor, and a bit line is formed by burying a portion of the bit line BL within the recess (i.e., the location where the portion of the active semiconductor layer AP is removed). In this case, the bit line BL may include a first portion disposed within the recess and a second portion connected to the first portion and extending linearly. In other words, the vertical distance between the first portion of the bit line BL and the shielding metal layer SS can be relatively large.

[0055] In the semiconductor device according to the comparative example, because the second portion of the bit line is shielded by the shielding metal layer SS, the capacitance caused by bit line coupling is small. However, because the first portion of the bit line BL is not shielded by the shielding metal layer SS, the capacitance caused by bit line coupling can be relatively large. For example, in the semiconductor device according to the comparative example, the capacitance caused by bit line coupling can correspond to 21% of the total capacitance.

[0056] On the other hand, according to the embodiment, the process of forming the recess by removing a portion of the active semiconductor layer AP may not be performed, and the bit line BL can be arranged linearly with the intermediate line BUL disposed between the bit line BL and the active semiconductor layer AP. Therefore, according to the embodiment, the first portion of the bit line BL formed in the comparative example can be omitted, and the bit line BL may only include the second portion. Furthermore, the vertical distance between the bit line BL and the shielding metal layer SS can be relatively small. Because the entire area of ​​the bit line BL can be shielded by the shielding metal layer SS, the capacitance caused by bit line coupling in the semiconductor device according to the embodiment can correspond to 4.2% of the total capacitance. Therefore, according to the embodiment, a significantly lower coupling capacitance can be obtained compared to the comparative example.

[0057] Furthermore, when the intermediate line BUL is positioned between the bit line and the active semiconductor layer AP, it has been confirmed that the resistance between the bit line BL and the active semiconductor layer AP can be significantly reduced, and the operating current is increased by approximately 10% compared to the comparative example. Therefore, the semiconductor device 100 can have excellent electrical performance.

[0058] Figure 7 and Figure 8 This is a cross-sectional view showing a semiconductor device 100A according to an embodiment. Figure 9 yes Figure 8 A magnified view of region CX2.

[0059] Reference Figures 7 to 9Multiple intermediate lines BUL may have a first width w1, and multiple bit lines BL may have a second width w2, wherein the second width w2 may be greater than the first width w1. For example, the sidewalls BULa and bottom surfaces of the multiple intermediate lines BUL may be covered by or superimposed with bit lines BL, thus increasing the contact area between each of the multiple intermediate lines BUL and its corresponding bit line BL. The sidewalls BULa of the multiple intermediate lines BUL may be covered by or superimposed with bit lines BL, and may not be in direct contact with the first bit insulation layer 152.

[0060] Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C ,as well as Figures 22 to 24 This is a schematic diagram illustrating a method for manufacturing a semiconductor device 100 according to an embodiment. Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A ,as well as Figures 22 to 24 yes Figure 2 A sectional view taken along line A1-A1'. Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B and Figure 21B yes Figure 2 A sectional view taken along line A2-A2', and Figure 10B , Figure 11B , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 20C and Figure 21C They are respectively with Figure 10A , Figure 11A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 20A and Figure 21A The sectional view corresponds to the plan view.

[0061] Reference Figure 10A and Figure 10B A unit capacitor CAP can be formed on the carrier substrate 210, and a pad LP can be formed on the unit capacitor CAP.

[0062] In an embodiment, such as Figure 10B As shown, the unit capacitor CAP and the pad LP can be arranged in a matrix shape. In other embodiments, the unit capacitor CAP and the pad LP can be arranged in a hexagonal shape.

[0063] In some embodiments, a capacitor molding insulating layer may be formed on the carrier substrate 210, and a capacitor opening extending in the vertical direction Z may be formed in the capacitor molding insulating layer. A unit capacitor CAP may be formed in the capacitor opening.

[0064] In some embodiments, an insulating layer 176 may be formed around the sidewalls of the pad LP in a plan view. In some embodiments, an insulating layer 176 may first be formed covering or overlapping the sidewalls and top surface of the unit capacitor CAP, and then an opening may be formed in the insulating layer 176 to expose the top surface of the unit capacitor CAP. The pad LP may be formed in the opening.

[0065] Reference Figure 11A and Figure 11B A molded structure 130 extending in a first horizontal direction X can be formed on the pad LP and the insulating layer 176. The molded structure 130 may include a first molded layer 132, a second molded layer 134, and a third molded layer 136 sequentially disposed on the pad LP and the insulating layer 176. The molded structure 130 may have a sidewall 130H extending in the first horizontal direction X.

[0066] In an embodiment, the width of the molded structure 130 in the second horizontal direction Y can be determined such that two pads LP are exposed in the second horizontal direction Y between two adjacent molded structures 130. For example, in Figure 2 In a cross-sectional view taken along the second horizontal direction Y (e.g., line A1-A1'), two pads LP are exposed between two adjacent molded structures 130.

[0067] Reference Figure 12A and Figure 12B An active semiconductor layer APL can be formed on the sidewall 130H of the molded structure 130. The active semiconductor layer APL can be conformally disposed on the sidewall 130H and the upper surface of the molded structure 130, the upper surface of the pad LP, and the upper surface of the insulating layer 176. For example, the thickness of the active semiconductor layer APL disposed on the sidewall 130H of the molded structure 130 can be equal to or similar to the thickness of the active semiconductor layer APL disposed on the upper surface of the molded structure 130, the upper surface of the pad LP, and the upper surface of the insulating layer 176.

[0068] Reference Figure 13A , Figure 13B and Figure 13C The portion of the prepared active semiconductor layer APL disposed on the upper surface of the molded structure 130 and the upper surface of the insulating layer 176 can be removed by performing an anisotropic etching process or an etch-back process, so that the portion of the prepared active semiconductor layer APL disposed only on the sidewall 130H of the molded structure 130 can be retained.

[0069] Due to anisotropic etching or etch-back processes, the upper surface of the molded structure 130 (e.g., the upper surface of the third molding layer 136) can be exposed again. The upper surface of the molded structure 130 (e.g., the upper surface of the third molding layer 136) can be at the same vertical height as the upper surface of the prepared active semiconductor layer APL. Furthermore, as... Figure 13A As shown, the bottom surface of the prepared active semiconductor layer APL can contact the upper surface of the pad LP. The prepared active semiconductor layer APL can extend in a first horizontal direction X on the sidewall 130H of the molded structure 130.

[0070] Reference Figure 14A , Figure 14B and Figure 14C A mask pattern M10 extending in the second horizontal direction Y can be formed on the molded structure 130 and the prepared active semiconductor layer APL.

[0071] In an embodiment, the mask pattern M10 may include a lower mask layer M14 that partially or completely fills the space between two adjacent pre-existing active semiconductor layers APL, and an upper mask layer M12 on the lower mask layer M14. For example, the lower mask layer M14 may include silicon-on-hardmask, and the upper mask layer M12 may include silicon oxynitride.

[0072] Reference Figure 15A , Figure 15B and Figure 15C The portion of the prepared active semiconductor layer APL that is not covered or stacked by the mask pattern M10 can be removed. Another portion of the prepared active semiconductor layer APL that is covered or stacked by the mask pattern M10 can be retained without removal and may be referred to as the active semiconductor layer AP. Two active semiconductor layers AP may be spaced apart from each other in a first horizontal direction X between two adjacent molding structures 130, and one active semiconductor layer AP may be disposed on a pad LP.

[0073] Reference Figure 16A , Figure 16B and Figure 16C A gate insulating layer GI and a word line WL can be formed on the sidewall of the active semiconductor layer AP.

[0074] In an embodiment, the gate insulating layer GI may be conformally formed on the upper surface of the molded structure 130, the sidewalls and upper surface of the active semiconductor layer AP, the upper surface of the pad LP, and the upper surface of the insulating layer 176.

[0075] Subsequently, a word line WL can be formed on the sidewall of the active semiconductor layer AP, with the gate insulating layer GI between the sidewall of the active semiconductor layer AP and the word line WL. In an example process for forming the word line WL, the word line WL can be conformally formed on the upper surface and sidewall of the gate insulating layer GI, and then an anisotropic etching or recessing process can be performed on the word line WL so that the word line WL can be retained only between two molded structures 130 arranged adjacent to each other.

[0076] like Figure 16C As shown, between two molded structures 130 arranged adjacent to each other, a first letter line WL1 can be provided on the side wall of the upper molded structure 130, and a second letter line WL2 can be provided on the side wall of the lower molded structure 130.

[0077] Reference Figure 17A and Figure 17B An insulating liner 142 and a buried insulating layer 144 can be sequentially formed on the word line WL.

[0078] Reference Figure 18A and Figure 18BA portion of the insulating liner 142 (which is disposed on the upper surface of the molded structure 130) and a portion of the gate insulating layer GI (which is disposed on the upper surface of the molded structure 130) can be removed, so that the upper surface of the molded structure 130 and the upper surface of the active semiconductor layer AP can be exposed again.

[0079] The process for removing this portion of the insulating liner 142 and this portion of the gate insulating layer GI can be a grinding process or a chemical mechanical polishing (CMP) process, and after the grinding process or CMP process, the upper surface of the buried insulating layer 144, the upper surface of the active semiconductor layer AP and the upper surface of the molded structure 130 can be configured to be coplanar with each other.

[0080] Reference Figure 19A and Figure 19B An intermediate line layer BULp can be formed on the upper surface of the buried insulating layer 144, the upper surface of the active semiconductor layer AP, and the molding structure 130.

[0081] In one embodiment, the intermediate line layer BULp may include an oxide semiconductor and may include, for example, the same material as the active semiconductor layer AP. In other embodiments, the intermediate line layer BULp may include an oxide semiconductor and may include, for example, a material different from the material of the active semiconductor layer AP.

[0082] Subsequently, a bit line layer BLp can be formed on the intermediate line layer BULp. In embodiments, the bit line layer BLp may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polysilicon, or combinations thereof.

[0083] Reference Figure 20A , Figure 20B and Figure 20C It can be done in the bitline layer BLp (see Figure 19A A mask pattern extending in the second horizontal direction Y is formed on the surface, and the bit line layer BLp and the intermediate line layer BULp can be patterned by using the mask pattern as an etch mask, so that the bit line BL and the intermediate line BUL can be formed.

[0084] In an embodiment, bit line BL and intermediate line BUL can be formed sequentially in the same process, so that the sidewalls of bit line BL can be aligned with the sidewalls of intermediate line BUL.

[0085] like Figure 20AAs shown, the intermediate line BUL may have a linear shape extending in the second horizontal direction Y, a portion of the bottom surface of the intermediate line BUL may contact the upper surface of the active semiconductor layer AP, and the entire upper surface of the intermediate line BUL may contact the entire bottom surface of the bit line BL.

[0086] Reference Figure 21A , Figure 21B and Figure 21C A first bit insulation layer 152 and a second bit insulation layer 154 may be sequentially formed on the intermediate bit line BUL and the bit line BL, and a shielding metal layer SS may be formed on the second bit insulation layer 154.

[0087] Reference Figure 22 A unit wiring structure 160 can be formed on the shielding metal layer SS. The unit wiring structure 160 may include a unit wiring layer 162, unit contacts 164, and a unit insulating layer 166. Furthermore, bit line contacts 156 connecting the unit wiring layer 162 and the bit lines BL to each other can be further formed. The sidewalls of the bit line contacts 156 may be surrounded by bit line contact spacers 158 in a plan view, and the bit line contacts 156 may be electrically insulated from the shielding metal layer SS by the bit line contact spacers 158.

[0088] A first bonding pad BP1 may be provided within the unit insulating layer 166 of the unit wiring structure 160. The first bonding pad BP1 may be electrically connected to the unit wiring layer 162. The upper surface of the unit insulating layer 166 may be configured to be coplanar with the upper surface of the first bonding pad BP1, and the upper surface of the unit insulating layer 166 may be referred to as the bonding interface BIF.

[0089] Reference Figure 23 An active region AC can be formed on the substrate 110, and a peripheral circuit transistor PTR can be formed on the active region AC. For example, the peripheral circuit transistor PTR may include a gate electrode PTG, a gate insulating layer PTI, and a source / drain region PTS.

[0090] Subsequently, peripheral circuit lines 122 and peripheral circuit contacts 124 electrically connected to the substrate 110 and the peripheral circuit transistor PTR can be formed, and a peripheral circuit insulating layer 126 covering or superimposed on the peripheral circuit lines 122 and peripheral circuit contacts 124 can be formed on the substrate 110. The peripheral circuit insulating layer 126 can be formed using an oxide film, a nitride film, a low-k dielectric film, or a combination thereof.

[0091] The second bonding pad BP2 may be disposed within the peripheral circuit insulation layer 126. The second bonding pad BP2 may be electrically connected to the peripheral circuit line 122. The upper surface of the peripheral circuit insulation layer 126 may be configured to be coplanar with the upper surface of the second bonding pad BP2, and the upper surface of the peripheral circuit insulation layer 126 may be referred to as the bonding interface BIF.

[0092] Reference Figure 24 The peripheral circuit region PCA and the cell array region MCA can be coupled to each other, so that the cell wiring structure 160 and the peripheral circuit line structure 120 are in contact with each other. In an embodiment, the first bonding pad BP1 and the second bonding pad BP2 can be in contact with each other at the bonding interface BIF, and the cell insulating layer 166 and the peripheral circuit insulating layer 126 can be in contact with each other at the bonding interface BIF.

[0093] After this, the carrier substrate 210 can be removed.

[0094] By performing the above process, semiconductor device 100 can be completed.

[0095] According to an embodiment, the peripheral circuit region PCA and the cell array region MCA can be fabricated using separate wafers and bonded to each other using bonding pads BP. Furthermore, when the cell array region MCA is formed, it can be formed first, and the cell capacitor CAP can be formed subsequently. Therefore, thermal damage to the cell transistor CTR can be avoided or minimized.

[0096] In a semiconductor device including an oxide semiconductor channel, according to a comparative example, after an active semiconductor layer is formed on the sidewall of a molded structure, a recess is formed by removing a portion of the active semiconductor, and a bit line is formed by burying a portion of the bit line within the recess (i.e., at the location where the portion of the active semiconductor layer is removed). In this case, the coupling capacitance caused by the portion of the bit line arranged within the recess can be relatively high.

[0097] According to the embodiment, the process of forming the recess by removing a portion of the active semiconductor layer AP can be omitted. Therefore, since the entire area of ​​the bit line BL can be shielded by the shielding metal layer SS, a significantly lower coupling capacitance can be exhibited compared to the comparative example.

[0098] Furthermore, when the intermediate line BUL is positioned between the bit line BL and the active semiconductor layer AP, the resistance between the bit line BL and the active semiconductor layer AP can be significantly reduced, and the semiconductor device 100 can have excellent electrical performance.

[0099] In the above embodiments, reference is made to Figure 18A , Figure 18B , Figure 19A and Figure 19B The description describes how bit lines BL and intermediate lines BUL can be patterned in the same process. However, in other embodiments, the intermediate line layer BULp is formed first, a mask pattern is formed on the intermediate line layer BULp, and the intermediate line layer BULp is patterned so that the intermediate line BUL can be formed. Subsequently, the bit line layer BLp is formed to cover or overlap the intermediate line BUL, a mask pattern is formed on the bit line layer BLp, and the bit line layer BLp is patterned so that the bit line layer BLp can be formed. In this embodiment, the second width w2 of the bit line BL may be different from the first width w1 of the intermediate line BUL. For example, the second width w2 of the bit line may be greater than the first width w1 of the intermediate line BUL, thus the contact area between the bit line BL and the intermediate line BUL can be further increased. In this case, refer to... Figures 7 to 9 The described semiconductor device 100A can be manufactured.

[0100] According to the present invention, coupling between bit lines can be reduced, and contact resistance can be reduced by increasing the contact area between the bit lines and the channel layer. Therefore, the semiconductor device can have excellent electrical performance.

[0101] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: Base; The peripheral circuit region is on the substrate; as well as The cell array region is located at a different distance from the substrate than the peripheral circuit region, wherein the cell array region is electrically connected to the peripheral circuit region via bonding pads. The cell array region includes: A molded structure extending in the first horizontal direction; An active semiconductor layer is located on the sidewall of the molded structure and includes a first oxide semiconductor. Word lines are located on the sidewalls of the active semiconductor layer. A single-unit capacitor is located on the upper surface of the active semiconductor layer. Bit lines extend on the bottom surface of the active semiconductor layer and in a second horizontal direction intersecting the first horizontal direction; and The intermediate line, between the bottom surface of the active semiconductor layer and the bit line, extends in the second horizontal direction and includes the second oxide semiconductor.

2. The semiconductor device of claim 1, wherein, The upper surface of the active semiconductor layer is coplanar with the upper surface of the molded structure, and In this structure, the bottom surface of the active semiconductor layer is coplanar with the bottom surface of the molded structure.

3. The semiconductor device as claimed in claim 1, wherein, The center line is located between the bottom surface of the molded structure and the part line.

4. The semiconductor device of claim 1, wherein, The position line has a flat top surface and a flat bottom surface, and The bit line has a uniform thickness along its length.

5. The semiconductor device of claim 1, wherein, The first oxide semiconductor includes at least one of zinc tin oxide, indium zinc oxide, zinc oxide, indium gallium zinc oxide, indium gallium silicon oxide, indium tungsten oxide, indium oxide, tin oxide, titanium oxide, zinc oxynitride, magnesium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, aluminum zinc tin oxide, gallium zinc tin oxide, and zirconium zinc tin oxide.

6. The semiconductor device of claim 1, wherein, The second oxide semiconductor includes at least one of zinc tin oxide, indium zinc oxide, zinc oxide, indium gallium zinc oxide, indium gallium silicon oxide, indium tungsten oxide, indium oxide, tin oxide, titanium oxide, zinc oxynitride, magnesium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, aluminum zinc tin oxide, gallium zinc tin oxide, and zirconium zinc tin oxide.

7. The semiconductor device of claim 1, further comprising: Shielding metal layer, on the mounting line; as well as The bit line insulation layer is located on the sidewall of the bit line and on the sidewall of the intermediate line, between the shielding metal layer and the bit line, and between the shielding metal layer and the intermediate line.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The sidewalls of the center line are aligned with the sidewalls of the position line.

9. The semiconductor device of claim 8, wherein, The centerline has a first width in the first horizontal direction. The bit line has a second width in the first horizontal direction, and The second width is equal to the first width.

10. The semiconductor device according to any one of claims 1 to 7, wherein, The position line is on the side wall of the center line.

11. The semiconductor device of claim 10, wherein, The centerline has a first width in the first horizontal direction. The bit line has a second width in the first horizontal direction, and The second width is greater than the first width.

12. A semiconductor device, comprising: Base; The peripheral circuit region is on the substrate; as well as The cell array region, on the peripheral circuit region, The cell array region includes: Multiple molded structures extend in the first horizontal direction; Multiple active semiconductor layers are spaced apart from each other in a first horizontal direction, wherein the active semiconductor layers are between adjacent molded structures in the multiple molded structures and extend in a vertical direction intersecting the first horizontal direction. The first letter line and the second letter line are spaced apart from each other in adjacent molded structures among the plurality of molded structures, wherein the first letter line and the second letter line extend in a first horizontal direction. Multiple bit lines, at a first distance from the substrate, the first distance being less than a second distance between the multiple active semiconductor layers and the substrate and less than a third distance between the multiple molded structures and the substrate, wherein the multiple bit lines extend in a second horizontal direction intersecting a first horizontal direction and a vertical direction; and Multiple intermediate lines extend in a second horizontal direction between the multiple active semiconductor layers and the multiple bit lines, and between the multiple molded structures and the multiple bit lines.

13. The semiconductor device of claim 12, wherein, The multiple intermediate lines are respectively on the upper surface of the multiple bit lines, and The upper surfaces of the multiple intermediate lines are in contact with the bottom surfaces of the multiple active semiconductor layers, respectively.

14. The semiconductor device of claim 12, wherein, The upper surfaces of the plurality of active semiconductor layers are respectively coplanar with the corresponding upper surfaces of the plurality of molded structures, and The bottom surfaces of the plurality of active semiconductor layers are coplanar with the corresponding bottom surfaces of the plurality of molded structures.

15. The semiconductor device of claim 12, further comprising: A shielding metal layer is located in the space between adjacent bit lines among the plurality of bit lines and extends in a second horizontal direction.

16. The semiconductor device according to any one of claims 12 to 15, wherein, The sidewalls of the multiple intermediate lines are respectively aligned with the sidewalls of the multiple position lines. Each of the plurality of intermediate lines has a first width in the first horizontal direction. Each of the plurality of bit lines has a second width in the first horizontal direction, and The second width is equal to the first width.

17. The semiconductor device according to any one of claims 12 to 15, wherein, The multiple position lines are on the corresponding sidewalls of the multiple intermediate lines. Each of the plurality of intermediate lines has a first width in the first horizontal direction. Each of the plurality of bit lines has a second width in the first horizontal direction. The second width is greater than the first width.

18. A semiconductor device, comprising: The peripheral circuit region includes the substrate and peripheral circuit transistors; as well as The cell array region, on the peripheral circuit region, The cell array region includes: A molded structure extending in the first horizontal direction; An active semiconductor layer is located on the sidewall of the molded structure and includes a first oxide semiconductor. Word lines are located on the sidewalls of the active semiconductor layer. A gate insulating layer is located between the sidewall of the active semiconductor layer and the word line; The pad is located on the upper surface of the active semiconductor layer; Unit capacitor, on the pad; The intermediate line extends in a second horizontal direction and includes a second oxide semiconductor on the bottom surface of the active semiconductor layer and on the bottom surface of the molded structure. The position line extends on the bottom surface of the middle line and in the second horizontal direction; The bit line insulation layer is on the bit line and on the sidewall of the intermediate line; and A shielding metal layer is located on the side of the bit line, and a bit line insulating layer is located between the shielding metal layer and the side of the bit line.

19. The semiconductor device of claim 18, wherein, The first oxide semiconductor and the second oxide semiconductor each include at least one of zinc tin oxide, indium zinc oxide, zinc oxide, indium gallium zinc oxide, indium gallium silicon oxide, indium tungsten oxide, indium oxide, tin oxide, titanium oxide, zinc oxynitride, magnesium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, aluminum zinc tin oxide, gallium zinc tin oxide, and zirconium zinc tin oxide.

20. The semiconductor device of claim 18 or 19, wherein, The upper surface of the active semiconductor layer is coplanar with the upper surface of the molded structure. In this structure, the bottom surface of the active semiconductor layer is coplanar with the bottom surface of the molded structure, and The bit line has a flat top surface and a flat bottom surface.

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