Semiconductor device

Abstract

According to the semiconductor device, an interlayer dielectric layer located on a semiconductor substrate comprises a plurality of first lines, a plurality of second lines and asymmetric sawtooth-shaped edges, the first lines and the second lines perpendicularly intersect and partially overlap, and the formation position of a contact plug is limited and isolated through an interlayer cut-off layer. Therefore, the contact plugs within the asymmetric zigzag edge can be uniformly distributed, and the contact plugs on the asymmetric zigzag edge are distributed depending on the zigzag distribution of the asymmetric zigzag edge, so that no contact plug exists above a part of the active region at the boundary of the core region. And contact plugs are arranged above other active regions at the boundary of the core region and the active region in the core region, so that the problem that the semiconductor device cannot pass related tests due to the problem of an electrical structure at the boundary of the core region can be avoided, and the performance and the qualified rate of the semiconductor device are improved.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of the parent application with application number CN201910925253.2, application date September 27, 2019, and invention title "Mask Assembly and Contact Plug Manufacturing Method, Semiconductor Device and Manufacturing Method Thereof". Technical Field

[0003] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a photomask assembly and contact plugs, a semiconductor device, and a method for manufacturing the same. Background Technology

[0004] Various techniques have been used to integrate more circuit patterns within the limited area of ​​a semiconductor substrate or wafer. Due to differences in circuit pattern spacing, integrated circuits are generally classified into dense, sparse, and isolated regions. Dense regions are areas with high device density (i.e., relatively densely packed devices), sparse regions are areas with low device density (i.e., relatively sparsely packed devices), and isolated regions are areas set separately from the dense and sparse regions. As the critical dimensions of semiconductor devices continue to decrease, the density of circuit patterns and / or device height also continuously increase. Influenced by the resolution limits of optical exposure tools and the density difference effect between dense and sparse regions (i.e., the dense / sparse effect of circuit patterns), the difficulties in performing photolithography and / or etching processes increase significantly (e.g., reduced process allowance), thereby affecting the performance of the manufactured semiconductor devices.

[0005] For example, in the case of a dynamic random access memory (DRAM) device, a large number of memory cells are clustered to form an array memory region. Next to the array memory region exists a peripheral circuit region, which contains other transistor components and contact structures. The array memory region, as the device-dense area of ​​the DRAM, is used to store data, while the peripheral circuit region, as the device-sparse area of ​​the DRAM, is used to provide the input / output signals required by the array memory region. Each memory cell in the array memory region can be composed of a metal-oxide-semiconductor (MOS) transistor and a capacitor structure connected in series. The capacitor is located within the array memory region, stacked above the bit line and electrically coupled to the corresponding memory node contact. The memory node contact is electrically coupled to the active region below it. With the continuous development of semiconductor technology, the critical size of devices is constantly decreasing, and the gap between memory cells in DRAM devices is becoming narrower. When forming the memory node contact part through the self-aligned contact (SAC) process, the resolution limit of the optical exposure equipment and the density difference effect between the dense and sparse areas of the device are affected. After connecting the capacitor on the contact plug of the array memory area, the capacitor at the boundary of the array memory area is prone to collapse or partial failure. These problems affect the performance of the fabricated DRAM device and are very likely to cause the fabricated DRAM device to fail the relevant tests, thereby reducing the yield of the produced DRAM device. Summary of the Invention

[0006] The purpose of this invention is to provide a method for fabricating a photomask assembly and contact plugs, a semiconductor device, and a method for manufacturing the same, so as to improve the performance and yield of the manufactured semiconductor device.

[0007] To solve the above-mentioned technical problems, the present invention provides a mask assembly for fabricating contact plugs, the mask assembly comprising:

[0008] The first mask has multiple parallel first light-blocking stripes, and the area between two adjacent first light-blocking stripes is the first light-transmitting area;

[0009] The second mask has multiple parallel second light-blocking stripes that intersect with each of the first light-blocking stripes, and the area between two adjacent second light-blocking stripes is a second light-transmitting area.

[0010] The third mask has a light-shielding block and a third light-transmitting area complementary to the light-shielding block. The light-shielding block covers at least one first light-shielding stripe at the boundary of the first mask and the portion of the first light-transmitting area adjacent to the first light-shielding stripe. It also covers at least two second light-shielding stripes at the boundary of the second mask and the portion of the second light-transmitting area between the two second light-shielding stripes. The overlapping area of ​​the third light-transmitting area, the first light-transmitting area, and the second light-transmitting area is the area for forming a contact plug.

[0011] Based on the same inventive concept, the present invention also provides a method for manufacturing a contact plug, which uses the mask template assembly described in the present invention to manufacture the contact plug. The method for manufacturing the contact plug includes:

[0012] A semiconductor substrate having multiple active regions is provided, and an interlayer dielectric layer and a first mask layer are sequentially formed on the semiconductor substrate;

[0013] A process combining photolithography and etching is used to transfer the pattern on the first mask in the mask assembly onto the first mask layer, so as to form a plurality of first lines in the first mask layer. Each first line corresponds to a corresponding first light-blocking stripe on the first mask, and the groove between adjacent first lines corresponds to a corresponding first light-transmitting area on the first mask and exposes the corresponding interlayer dielectric layer.

[0014] A second mask layer is covered on the interlayer dielectric layer and the first mask layer, and a photolithography combined with etching process is used to transfer the pattern on the second mask in the mask assembly onto the second mask layer to form a plurality of corresponding second lines. Each second line corresponds to a corresponding second light-blocking stripe on the second mask, and the groove between adjacent second lines corresponds to a corresponding second light-transmitting area on the second mask and exposes the corresponding first line and the interlayer dielectric layer in the first light-transmitting area.

[0015] A third mask layer is covered on the first mask layer, the second mask layer, and the interlayer dielectric layer. The pattern on the third mask in the mask assembly is transferred to the third mask layer using photolithography. The remaining third mask layer corresponds to the light-shielding block of the third mask. The interlayer dielectric layer exposed by the remaining third mask layer, the first mask layer, and the second mask layer is the area to be formed as the contact plug.

[0016] Using the first mask layer, the second mask layer, and the third mask layer as masks, the exposed interlayer dielectric layer is etched to form contact holes that expose the corresponding active regions;

[0017] Contact plugs are formed in the contact holes, and the bottom of each contact plug contacts the corresponding active area.

[0018] Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, comprising: forming contact plugs on a semiconductor substrate having a core region using the method for manufacturing contact plugs described in the present invention, wherein the bottom of each contact plug is in contact with the active region of a corresponding core element in the core region.

[0019] Based on the same inventive concept, the present invention also provides a semiconductor device manufactured using the semiconductor device manufacturing method described in the present invention, comprising:

[0020] A semiconductor substrate having a core region formed therein, wherein the core region has an active region having a plurality of core elements;

[0021] An interlayer dielectric layer is formed on the semiconductor substrate;

[0022] Multiple contact plugs are formed in the interlayer dielectric layer and make contact with the active areas of the corresponding core components;

[0023] Among them, there is no contact plug above the active area at the boundary of the core area.

[0024] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0025] By using the mask combination provided by this invention to define the formation position of the contact plugs, the top of some active areas at the core region boundary is free of contact plugs, while other active areas at the core region boundary and active areas inside the core region are covered by contact plugs. Thus, when subsequent electrical structures are formed inside and at the boundary of the core region using existing processes, some electrical structures at the core region boundary become virtual structures because there are no contact plugs below them that contact the active areas. This avoids the problem of the manufactured semiconductor device failing relevant tests due to the electrical structure at the core region boundary, thereby improving the performance and yield of the manufactured semiconductor device. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of the first mask template in a specific embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram of the structure of the second mask template in a specific embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the structure of the first mask template in a specific embodiment of the present invention;

[0029] Figure 4A This is a schematic diagram of the structure after the patterns of the first mask and the active area of ​​the core region are aligned and overlapped in a specific embodiment of the present invention (some layers that affect the observation of the pattern alignment and overlap effect are omitted).

[0030] Figure 4B This is a schematic diagram of the structure after the patterns of the second mask, the first mask, and the active area of ​​the core region are aligned and overlapped according to a specific embodiment of the present invention (some layers that affect the observation of the pattern alignment and overlap effect are omitted).

[0031] Figure 4C This is a schematic diagram of the structure after the patterns of the third mask, the second mask, the first mask, and the active area of ​​the core region are aligned and overlapped according to a specific embodiment of the present invention (some layers that affect the observation of the pattern alignment and overlap effect are omitted).

[0032] Figure 5 This is a schematic diagram of the distribution of contact plugs made on the core region using a mask assembly in a specific embodiment of the present invention, wherein there are no contact plugs above a portion of the active region at the boundary of the core region;

[0033] Figure 6 This is a specific embodiment of the present invention. Figure 5 A schematic diagram of the cross-sectional structure at the boundary of the central core area along line aa';

[0034] Figure 7 This is a cross-sectional structural diagram of a semiconductor device at the boundary of the core region according to a specific embodiment of the present invention. Detailed Implementation

[0035] The memory and its formation method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0036] Please refer to Figures 1-3 An embodiment of the present invention provides a mask template assembly for fabricating contact plugs, the mask template assembly comprising: a first mask template 10, a second mask template 20 and a third mask template 30.

[0037] Please refer to Figure 1The first photomask 10 has multiple parallel first light-shielding stripes, and the area between two adjacent first light-shielding stripes is a first light-transmitting area 102. In this embodiment, the first first light-shielding stripe 101a at the boundary of the first photomask 10 (i.e., the boundary extending along the length of the first light-shielding stripe) has a first width W1, the width of the second first light-shielding stripe 101b is less than W1, and the remaining first light-shielding stripes 101c have a second width W2. The first width W1 is greater than the second width W2, for example, W1 > 1.5 * W2, and the width of the second first light-shielding stripe 101b is greater than W2. Thus, in the photolithography and etching process of transferring the pattern on the first photomask 10 to the corresponding film layer, the width gradient of the first first light-shielding stripe 101a, the second first light-shielding stripe 101b, and the remaining first light-shielding stripes 101c in the first photomask 10 can be used to improve the pattern density / sparseness effect between the core area and the peripheral area of ​​the semiconductor device, thereby improving the pattern transfer effect of the first photomask 10. In other embodiments of the present invention, the width of the second first light-shielding stripe 101b may be equal to that of the first first light-shielding stripe 101a. Alternatively, the width of the first light-transmitting area 102 between the first first light-shielding stripe 101a and the second first light-shielding stripe 101b may be greater than the width of the remaining first light-transmitting areas 102, thereby providing sufficient process margin for the fabrication of contact plugs at the boundary of the core region of the semiconductor device.

[0038] Please refer to Figure 2 The second mask template 20 has multiple parallel second light-blocking stripes 201 that intersect each of the first light-blocking stripes 101a, 101b, and 101c perpendicularly, and the area between two adjacent second light-blocking stripes 201 is a second light-transmitting area 202. Figure 2The widths of the second light-shielding stripes 201 shown are substantially the same. However, in other embodiments of the present invention, optionally, at least one second light-shielding stripe (not shown) at the boundary of the second mask 20 (i.e., the boundary extending along the length of the second light-shielding stripe) has a third width (not shown), and the remaining second light-shielding stripes have a fourth width (not shown). The third width is greater than the fourth width, for example, the third width is greater than 1.5 times the fourth width. Thus, in the photolithography and etching processes that transfer the pattern on the second mask 20 to the corresponding film layer, the width gradient of the second light-shielding stripes in the second mask 20 can be used to improve the pattern density / sparseness effect between the core region and the peripheral region of the semiconductor device, thereby improving the pattern transfer effect of the second mask 20. In other embodiments of the present invention, optionally, the width of the second light-transmitting area 202 between the first and second light-blocking stripes at the boundary of the second mask 20 (i.e., the boundary extending along the length of the first light-blocking stripe) is greater than the width of the remaining second light-transmitting areas 202, thereby providing sufficient process margin for the fabrication of the contact plug at the boundary of the core region of the semiconductor device.

[0039] Please refer to Figure 3 The third mask 30 has a light-shielding block 301 and a third light-transmitting area 302 that is complementary to the light-shielding block 301. The light-shielding block 301 may have a serrated edge facing the core area to mask part of the area where the contact hole is to be formed at the boundary of the core area.

[0040] It should be noted that, Figures 1-3 Only a corner area of ​​the first mask 10, the second mask 20, and the third mask 30 is shown respectively. Those skilled in the art should be able to... Figures 1 to 3 The displayed area is extended accordingly to obtain a complete mask that is essentially rectangular. Furthermore, the light-shielding block 301 has a closed ring structure or a non-closed ring structure with at least one opening on the complete third mask 30. The serrated edges of the light-shielding block 301 facing the center of the third mask 30 are asymmetrical, that is, the light-shielding blocks 301 on the upper and lower sides of the third mask 30 are asymmetrical, and the light-shielding blocks 301 on the left and right sides of the third mask 30 are asymmetrical.

[0041] Please refer to Figure 4C and Figure 5When the photomask assembly of this embodiment is used to fabricate a contact plug on a semiconductor substrate having a core region I, a boundary region III, and a peripheral region II, the light-shielding block 301 covers at least one first light-shielding stripe at the boundary of the first photomask 10 and a portion of the first light-transmitting area adjacent to that first light-shielding stripe, and covers at least two second light-shielding stripes 201 at the boundary of the second photomask 20 and a portion of the second light-transmitting area 202 between the two second light-shielding stripes. Furthermore, the overlapping area of ​​the third light-transmitting area 302, the first light-transmitting area 102, and the second light-transmitting area 202 with the core region I constitutes the contact plug forming area CT. Optionally, depending on the shape of the first light-shielding stripe and the shape of the second light-shielding stripe, the shape of the contact plug forming area CT includes at least one of a square, a circle, an ellipse, a triangle, a rectangle, a polygon, and a heart shape.

[0042] In addition, in order to take into account device density, performance, and yield as much as possible, the number of second light-shielding stripes 201 covered by the light-shielding block 301 is 2 to 5 times the number of first light-shielding stripes covered by the light-shielding block 301.

[0043] Please refer to Figures 1-3 , Figures 4A-4C as well as Figures 5-6 An embodiment of the present invention also provides a method for manufacturing a contact plug, wherein the method for manufacturing the contact plug is implemented using the mask template combination described in the present invention, and specifically includes the following steps:

[0044] First, please refer to Figure 4A and Figure 6 A semiconductor substrate 400 having multiple active regions AA1 is provided. An interlayer dielectric layer 500 and a first mask layer P1 are sequentially formed on the semiconductor substrate 400. The semiconductor substrate 400 also has a core region I, a peripheral region II, and a boundary region III located between the core region I and the peripheral region II. A shallow trench isolation structure 400b defining each active region AA1 is formed in the core region I, and a shallow trench isolation structure 400a defining the core region I and the peripheral region II is formed in the boundary region III. The material of the first mask layer P1 can be silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0045] Next, please refer to Figure 1 , Figure 4A and Figure 6By employing a photolithography-etching process, the pattern on the first mask in the mask assembly is transferred to the first mask layer P1, i.e., the first mask layer P1 is patterned using the first mask 10. Specifically, a bottom anti-reflective layer (not shown) and a photoresist layer (not shown) are first sequentially covered on the first mask layer P1, and the photoresist layer is exposed and developed using the first mask 10 to transfer the pattern on the first mask 10 to the first mask layer P1. Afterward, the bottom anti-reflective layer and the photoresist layer can be removed. The patterned first mask layer P1 has multiple first lines, each corresponding to a first light-blocking stripe on the first mask 10. The grooves (not shown) between adjacent first lines correspond to the corresponding first light-transmitting areas 102 on the first mask 10 and expose the corresponding interlayer dielectric layer 500. Specifically, for example, the outermost first line P11 at the boundary of the core area I (i.e., the boundary of the core area I extending along the length direction of the first line) corresponds to the first first light-shielding stripe 101a at the boundary of the first mask template 10, the second first line P12 corresponds to the second first light-shielding stripe 101b at the boundary of the first mask template 10, and the remaining first lines P10 correspond to the remaining first light-shielding stripes 101c inside the first mask template 10.

[0046] Then, please refer to Figure 2 , Figure 4B and Figure 6 A second mask layer P2 is covered on the first mask layer P1 and the interlayer dielectric layer 500. A photolithography-etching process is used to transfer the pattern on the second mask 20 in the mask assembly onto the second mask layer P2, forming multiple corresponding second lines P20. In other words, the second mask layer P2 is patterned using the second mask 20. The specific process is basically the same as the process of patterning the first mask layer P1 using the first mask, and will not be described in detail here. Each second line P20 corresponds to a corresponding second light-blocking stripe 201 on the second mask 20. The grooves (not shown) between adjacent second lines P20 correspond to corresponding second light-transmitting areas 202 on the second mask 20. Each second line P20 intersects all first lines P11, P12, and P10 perpendicularly and covers the corresponding portions of the grooves between these first lines P11, P12, and P10 and adjacent first lines within its linewidth region. The grooves between adjacent second lines P20 expose the interlayer dielectric layer 500 within the corresponding first lines P11, P12, and P10 and the grooves between adjacent first lines within the width region of that groove. At this time, all the first and second lines overlap, defining a checkerboard-shaped arrangement of grooves CTa (not shown). The material of the second mask layer P2 is different from that of the first mask layer P1, so that the etching process described above can preserve the first lines between adjacent second lines.

[0047] Next, please refer to Figure 3 , Figure 4C and Figure 6 A third mask layer P3 is covered on the second mask layer P2, the first mask layer P1, and the interlayer dielectric layer 500. The material of the third mask layer P3 is different from the material of the second mask layer P2 and the first mask layer P1, so that the first and second lines exposed can be retained after the third mask layer P3 is patterned. Optionally, the material of the third mask layer P3 is photoresist. The pattern on the third mask 30 in the mask assembly is transferred to the third mask layer P3 using a photolithography process, that is, the third mask layer P3 is patterned using the third mask 30. The remaining third mask layer P3 (i.e., the patterned third mask layer P3) corresponds to the light-shielding block 301 of the third mask 30. The trench CTa region (i.e., the exposed interlayer dielectric layer 500 region) exposed by the remaining third mask layer P3, the remaining second mask layer P2, and the first mask layer P1 is the region to be formed as a contact plug. The remaining third mask layer P3 covers all the grooves defined by the intersection of the first and second lines on the boundary region III, and covers the outermost grooves defined by the intersection of the first and second lines at the boundaries in each direction of the core region I. Furthermore, it should be noted that in this embodiment, the word line WL can overlap with the second line P20, and the first lines P10 to P12 can correspondingly overlap with the bit line BL. Therefore, the first mask 10 can be a bit line mask, and the second mask 20 can be a word line mask.

[0048] Next, please refer to Figure 4C , Figure 5 and Figure 6 Using the remaining third mask layer P3, second mask layer P2, and first mask layer P1 as masks, the exposed interlayer dielectric layer 500 is etched until the active region AA1 in the semiconductor substrate 400 is exposed, thereby forming contact holes that expose the corresponding active region AA1. In this embodiment, due to the masking effect of the third mask layer P3, contact holes (such as...) are present on a portion of the active region AA1 at the boundary of the core region I extending along the length direction of the first line. Figure 5 The solid-line border of the square CT on line aa' is shown, and the other part of the active area AA1 has no contact hole (as shown in the image). Figure 5 The square dCT with a dashed border on line aa' is shown.

[0049] Next, please refer to Figure 5 and Figure 6 Contact plugs (CTs) are formed in each of the contact holes, and the bottom of each contact plug (CT) contacts the corresponding active region (AA1). Figure 6As can be seen, there is no contact plug above the active region AA1 at the boundary of the core region I along the length of the first or second line, such as... Figure 6 As shown in dCT. Furthermore, in some embodiments, the contact plugs CT at the boundaries of the core region I on both sides are asymmetrically distributed, for example, the contact plugs at the upper and lower boundaries of the core region I are asymmetrically distributed, and / or, the contact plugs at the left and right boundaries of the core region I are asymmetrically distributed. From the contact plug manufacturing method of the present invention, it can be seen that by adjusting the shape and size of the light-shielding block of the third mask, the position of the groove defined by the intersection of the first and second lines covered by the patterned third mask layer can be adjusted, thereby achieving the requirement that there are no contact plugs above the active area at certain special locations at the boundary of the core region. Therefore, in actual production, areas prone to problems at the boundary of the core region can be collected based on historical production data, so that contact plugs no longer form in these areas. This makes the electrical structures (e.g., capacitors or resistors) connected to the original contact plug positions in these areas virtual structures, which do not participate in subsequent yield tests, thereby improving the test pass rate and ultimately achieving the goal of improving the product qualification rate.

[0050] The following example uses semiconductor devices as dynamic random access memory, and combines... Figures 1-3 , Figures 4A-4C as well as Figure 5 and Figure 7 This section details how to fabricate the semiconductor device of the present invention using the aforementioned contact plug fabrication method. Specifically, the fabrication method of the semiconductor device of the present invention includes the following steps:

[0051] First, please refer to Figure 4A and Figure 7A semiconductor substrate 400 with multiple core elements (i.e., storage transistors) is provided. The specific process includes: First, a semiconductor substrate 400a is provided, comprising a core region I, a peripheral region II, and a boundary region III. In this embodiment, the core region I is a storage region. The core elements to be formed on the core region I include selection elements, and data storage elements are subsequently connected above the core elements. The selection elements are, for example, MOS transistors or diodes, and the data storage elements are, for example, capacitors, variable resistors, etc. A selection element and a corresponding data storage element constitute a storage cell. Peripheral circuits (e.g., NMOS transistors and PMOS transistors, diodes, or resistors) can be formed in the peripheral region II to control the storage cell. Multiple shallow trench isolation structures 401b are formed in the semiconductor substrate 400a of the core region I, and a shallow trench isolation structure 401a is formed in the semiconductor substrate 400a of the boundary region III. The shallow trench isolation structures 401a define the boundary between the core region I and the peripheral region II on a two-dimensional plane, and the shallow trench isolation structures 401b define the active regions AA1 corresponding to each core element in the core region I. The active regions AA1 are distributed in a strip shape on the two-dimensional plane and all extend along the first direction. The active regions AA1 can be arranged in a staggered manner on the surface of the semiconductor substrate 400a. Then, embedded word lines WL are formed in the semiconductor substrate 400a. The embedded word lines WL are generally embedded at a predetermined depth in the semiconductor substrate 400a, extending along the second direction (i.e., the row direction) and passing through the shallow trench isolation structure 401b and the active regions AA1. The second direction is not perpendicular to the first direction of the active regions AA1. The embedded word lines WL serve as gates to control the switching of memory cells. Typically, the sidewalls and bottom of the embedded word lines WL are surrounded by a gate dielectric layer (not shown), and the top of the embedded word lines WL is buried within a gate capping layer 402. Since the embedded word lines WL are not the focus of this invention, their related manufacturing processes can be found in known technical solutions in the art and will not be detailed here. Furthermore, the gate dielectric layer may include silicon oxide or other suitable dielectric materials, the buried word line WL may include aluminum, tungsten, copper, titanium-aluminum alloy, polysilicon, or other suitable conductive materials, and the gate cap layer 402 may include silicon nitride, silicon oxynitride, silicon carbide, or other suitable insulating materials. Moreover, a second type of dopant, such as P-type or N-type dopant, may be incorporated into the active regions AA1 on both sides of the buried word line WL to form source and drain regions (collectively defined as S / D). One of the AA1 regions on both sides of the buried word line WL is located at the center of AA1 corresponding to a predetermined bit line contact structure, and the other is located at the end of the active region AA1 at a predetermined memory node contact structure. The word line WL and S / D can constitute or define multiple MOS memory transistors formed on the core region I of the semiconductor device. Furthermore, while forming S / D, the source and drain regions corresponding to the peripheral transistors (not shown) may also be formed simultaneously in the peripheral region II.After forming the S / D, an etch stop layer 303 can be further formed on the semiconductor substrate 400a. The etch stop layer 303 covers the S / D and the shallow trench isolation structures 401a and 401b, and its material includes, for example, silicon nitride (SiN) and / or silicon oxide (SiO2). Then, a plurality of bitline contacts (not shown) and bit lines BL located above the bitline contacts are formed on the S / D serving as the drain region in the core region I. The bitline contacts can be formed by first etching the S / D between two adjacent WLs formed in an active region AA1 to form a groove, and then forming metal silicide in the groove. The plurality of bit lines BL are parallel to each other and extend along a third direction (i.e., column direction) perpendicular to the buried word lines WL, and simultaneously cross the active region AA1 and the buried word lines WL. Each line BL may include, for example, a semiconductor layer (e.g., polysilicon, not shown), a barrier layer (e.g., including Ti or TiN, not shown), a metal layer (e.g., tungsten, aluminum or copper, not shown) and a mask layer (e.g., including silicon oxide, silicon nitride or silicon carbonitride, not shown) stacked in sequence.

[0052] Then, please refer to Figure 4A and Figure 7 After providing a semiconductor substrate 400 with bit lines BL, source regions and drain regions S / D of core elements, an interlayer dielectric layer 500 is formed on the semiconductor substrate 400. The material of this interlayer dielectric layer includes silicon oxide, silicon nitride, or a low-k dielectric. Specifically, the interlayer dielectric layer 500 is first deposited onto the semiconductor substrate 400 to completely cover it, filling the spaces between the bit lines BL and burying the bit lines BL within them. Then, the interlayer dielectric layer 500 is planarized using processes such as chemical mechanical polishing to form an interlayer dielectric layer 500 with an overall flat top surface. The top surface of the planarized interlayer dielectric layer 500 is at least higher than the top surface of each bit line BL.

[0053] Next, please refer to Figures 1-3 , Figures 4A to 4C , Figure 5 as well as Figure 7Using the aforementioned method for fabricating contact plugs, a first mask layer P1 with a pattern of a first mask template 10, a second mask layer P2 with a pattern of a second mask template 10, and a third mask layer P3 with a pattern of a third mask template 30 are sequentially formed on the interlayer dielectric layer 500. Specific processes can be found above and will not be detailed here. The second mask layer P2 is formed on the first mask layer P1 and the exposed interlayer dielectric layer 500, while the third mask layer P3 is formed on the second mask layer P2 and the exposed first mask layer P1 and interlayer dielectric layer 500. The first lines in the first mask layer P1 and the second lines in the second mask layer P2 intersect perpendicularly, defining a series of checkerboard-shaped grooves. The third mask layer P3 masks all the grooves in the boundary region III and some of the grooves at the boundary of the core region I, thereby defining the positions of each effective memory node contact structure.

[0054] Then, please continue to refer to Figure 4C , Figure 5 as well as Figure 7 Using the third mask layer P3, the second mask layer P2, and the first mask layer P1 as masks, the interlayer dielectric layer 500 is anisotropically etched to form contact holes that penetrate the interlayer dielectric layer 500 and expose the corresponding S / D source regions below. Contact holes (not shown) exposing corresponding areas in the peripheral region II can also be formed simultaneously. The size of the contact holes at the boundary of the core region I can be larger than the size of the contact holes inside the core region I. In other embodiments of the invention, contact holes can also be formed in the region of the boundary region III near the boundary of the core region I, and the contact plugs in the contact holes in the subsequent boundary region III can be connected to the top of the corresponding contact plugs at the boundary of the core region I.

[0055] Next, please continue to refer to Figure 5 and Figure 7After the contact holes are formed, an ashing process, wet cleaning, or other suitable process can be performed to remove the third mask layer P3, the second mask layer P2, and the first mask layer P1 above the interlayer dielectric layer 500, and to sequentially fill each contact hole with a barrier metal layer (not shown) and a conductive metal layer (not shown). The barrier metal layer can cover the inner wall of the contact hole and the top surface of the interlayer dielectric layer 500 with a uniform thickness. The barrier metal layer can reduce or prevent the diffusion of metal material disposed in the contact hole into the interlayer dielectric layer 500. It can be formed of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or any combination thereof, and can be formed using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (e.g., sputtering). The conductive metal layer can be formed of one or more refractory metals (e.g., cobalt, iron, nickel, tungsten, and / or molybdenum). Alternatively, a deposition process with good step coverage properties can be used to form the conductive metal layer, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (e.g., sputtering). The formed conductive metal layer also covers the surface of the interlayer dielectric layer 500 around the contact hole. Subsequently, the top surface of the deposited conductive metal layer can be chemically and mechanically polished (CMP) until the top surface of the interlayer dielectric layer 500 is exposed to form the contact plug CT located in the interlayer dielectric layer 500. Figure 7 The image shows that there are no contact plugs above the active region AA1 at the boundary of the core region I (in the prior art, contact plugs would be formed at these locations, but not in this invention, i.e., in...). Figure 7 (The dashed box column dCT is used to form a contrast), and above the other part of the active region AA1 is a contact plug CT. The contact plug CT serves as the contact structure for the storage node in the core region I, and is used to connect to the capacitor subsequently formed above the core region I.

[0056] After that, please continue to refer to Figure 7The corresponding capacitors can be fabricated on the core region I using conventional capacitor fabrication methods in the art, and the specific process will not be detailed here. A capacitor 705 is formed above each S / D in the core region I. At the boundary of the core region I, the capacitor 705 whose bottom is electrically connected to the corresponding S / D via a corresponding contact plug CT is an effective capacitor and participates in subsequent testing and device operation. The capacitors whose bottom is not connected to the corresponding S / D without a contact plug CT are virtual capacitors and do not participate in subsequent device-related testing and device operation, thereby improving the product yield. In this embodiment, each capacitor 705 includes a lower electrode layer 701, a capacitor dielectric layer 702, and an upper electrode layer 703. The capacitors 705 are laterally supported and stacked in a spaced manner by a bottom support layer 600, a middle support layer 601, and a top support layer 602. The bottom support layer 600 serves to support the subsequently formed lower electrode layer and also isolates the internal components of the semiconductor substrate 400 from the capacitors and other components above. The formation process of the bottom support layer 600 can also be a thermal oxidation process. The bottom support layer 600, intermediate support layer 601, and top support layer 602 are made of materials including, but not limited to, silicon nitride. In other embodiments of the present invention, to better support the lower electrode layer, two or more intermediate support layers 601 may be stacked between the bottom support layer 600 and the top support layer 602. Optionally, all capacitors 705 may be arranged in a hexagonal close-packed configuration. Further, the lower electrode layer 701 has a cylindrical structure and may be a polycrystalline silicon electrode or a metal electrode. When the lower electrode layer 701 is a metal electrode, a titanium nitride (TiN) and Ti stacked structure may also be used. When the lower electrode layer 701 is a polycrystalline silicon electrode, it may be formed using undoped and / or doped polycrystalline silicon materials. The capacitor dielectric layer 702 covers the inner and outer surfaces of the cylindrical structure of the lower electrode layer 701 to fully utilize the two opposing surfaces of the lower electrode layer 701 and form a capacitor with a large electrode surface area. Preferably, the capacitor dielectric layer 702 may be a high-k dielectric layer such as a metal oxide. Furthermore, the capacitor dielectric layer 702 has a multilayer structure, such as a two-layer structure of halooxide and zirconium oxide. The upper electrode layer 703 can be a single-layer structure or a multilayer structure. When the upper electrode layer 703 is a single-layer structure, it can be, for example, a polycrystalline silicon electrode or a metal electrode. When the upper electrode layer 703 is a metal electrode, it can be formed, for example, using titanium nitride (TiN). The upper electrode layer 703 can form a capacitor with the capacitor dielectric layer 702 and the lower electrode layer 701 both inside and outside the cylindrical structure.Furthermore, in the edge region of core region I (i.e., the boundary region of the capacitor aperture array), due to the presence of the lateral support layers (i.e., the intermediate support layer 601 and the top support layer 602), both the capacitor dielectric layer 702 and the upper electrode layer 703 have uneven sidewall structures. The uneven sidewall structures correspond to the intermediate support layer 601 and the top support layer 602 outside the cylindrical structure of the lower electrode layer 701. As a result, the portion of the upper electrode layer 703 in the edge region of core region I (i.e., the boundary region of the capacitor aperture array) protrudes in a direction away from the lower electrode layer 701, corresponding to the intermediate support layer 601 and the top support layer 602, making the boundary of the capacitor array in core region I uneven. Furthermore, in this embodiment, the capacitor dielectric layer 702 and the upper electrode layer 703 extend sequentially to cover the surface of the underlying support layer 600 retained on the peripheral region II. Additionally, an upper electrode filling layer 704 covers the surface of the upper electrode layer 703, filling the gaps between the upper electrode layers 703. That is, the upper electrode filling layer 704 fills the gaps between adjacent cylindrical structures and covers the aforementioned structure. Preferably, the upper electrode filling layer 704 is made of undoped or boron-doped polycrystalline silicon.

[0057] Please refer to Figure 7 The present invention also provides a semiconductor device manufactured using the above-described semiconductor device manufacturing method, comprising: a semiconductor substrate 400, an interlayer dielectric layer 500, and a plurality of contact plugs CT. The semiconductor substrate 400 has a core region I, a peripheral region II, and a boundary region III located between the core region I and the peripheral region II. A shallow trench isolation structure 400b defining each active region AA1 is formed in the core region I, and a shallow trench isolation structure 400a defining the core region I and the peripheral region II is formed in the boundary region III. The interlayer dielectric layer 500 is formed on the semiconductor substrate 400 and may be silicon dioxide, silicon nitride, or a low-k dielectric (dielectric constant K less than 3). A plurality of contact plugs CT are formed in the interlayer dielectric layer 500 and contact the active region AA1 of the corresponding core element. Notably, no contact plugs are present above a portion of the active region AA1 at the boundary of the core region I. Furthermore, in some embodiments, the contact plugs CT at the opposite boundaries of the core region I are asymmetrically distributed, for example, the contact plugs at the upper and lower boundaries of the core region I are asymmetrically distributed, and / or the contact plugs at the left and right boundaries of the core region I are asymmetrically distributed.

[0058] Optionally, the semiconductor device may be a memory, which further includes multiple word lines WL, source and drain regions S / D, bit line contacts (not shown), and multiple bit lines BL (not shown). Each word line WL is a buried word line, formed in the semiconductor substrate 400, and intersects with the active region AA1. The source and drain regions S / D are formed in the active regions AA1 on both sides of the word lines. Bit line contacts are formed on the drain regions, and each bit line is formed on the corresponding bit line contact and intersects with each word line. The interlayer dielectric layer 500 buries the semiconductor substrate 400, word lines WL, source and drain regions S / D, bit line contacts, and bit lines within it. At the boundary of the core region I, at least the portion of the active region between the two outermost bit lines BL has no contact plug above it, and / or (one or both), at least the portion of the active region between the two word lines WL has no contact plug above it.

[0059] In summary, the technical solution of this invention defines the formation position of the contact plugs by using the mask combination provided by this invention. This ensures that there are no contact plugs above the active areas at the boundary of the core region, while contact plugs are present above the other active areas at the boundary of the core region and the active areas inside the core region. Consequently, when existing processes are used to form corresponding electrical structures inside and at the boundary of the core region, the electrical structures at the boundary of the core region become virtual structures because there are no contact plugs below them that contact the active areas. This avoids the problem of the manufactured semiconductor devices failing relevant tests due to the electrical structure at the boundary of the core region, thereby improving the performance and yield of the manufactured semiconductor devices.

[0060] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Furthermore, the above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope claimed by the present invention.

[0061] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first," "second," and "third," etc., in this specification are used only to distinguish the various components, elements, and steps within the specification, and not to indicate any logical or sequential relationships between them. The term "and / or" in this document indicates a choice between two options or both.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate having a shallow trench isolation structure and a plurality of active regions defined by the shallow trench isolation structure; An interlayer dielectric layer is located on the semiconductor substrate and includes multiple first lines, multiple second lines, and an asymmetric serrated edge, wherein the first lines and the second lines intersect perpendicularly and partially overlap. Contact plugs are formed in the interlayer dielectric layer and connected to the active region. The contact plugs are arranged alternately with the first line and also alternately with the second line. A capacitor is formed on the active region, and a portion of the capacitor is electrically connected to the active region below via a corresponding contact plug.

2. The semiconductor device as claimed in claim 1, characterized in that, The asymmetrical serrated edge includes a portion that intersects perpendicularly with the second line and another portion that intersects perpendicularly with the first line.

3. The semiconductor device as described in claim 1, characterized in that, The semiconductor device further includes: Multiple word lines are formed in the semiconductor substrate and intersect with the active region, and the word lines overlap with the second line; The source region and the drain region are respectively formed in the active regions on both sides of the word line; Bit line contact portion, formed on the drain region; and Multiple bit lines are formed on the bit line contact portion, the bit lines intersect with the word lines, and the first line overlaps with the bit lines.

4. The semiconductor device as described in claim 3, characterized in that, There is no contact plug above the portion of the active region between the two bit lines, and there is no contact plug above the portion of the active region between the two word lines.

5. A semiconductor device, characterized in that, include: A semiconductor substrate having a shallow trench isolation structure and a plurality of active regions defined by the shallow trench isolation structure; An interlayer dielectric layer is located on the semiconductor substrate and includes multiple first lines, multiple second lines, and an asymmetric serrated edge, wherein the first lines and the second lines intersect perpendicularly and partially overlap. Several contact plugs are formed in the interlayer dielectric layer and connected to the active region; A portion of the contact plugs are formed in the interlayer dielectric layer within the asymmetric serrated edge, and are surrounded by the first line and the second line, and are arranged alternately with the first line and the second line. Another portion of the contact plug is formed in the interlayer dielectric layer of the asymmetric serrated edge, and is arranged alternately with the serrations of the asymmetric serrated edge; A capacitor is formed on the active region, and a portion of the capacitor is electrically connected to the active region below via a corresponding contact plug.

6. The semiconductor device as claimed in claim 5, characterized in that, The semiconductor device further includes: Multiple word lines are formed in the semiconductor substrate and intersect with the active region, and the word lines overlap with the second line; The source region and the drain region are respectively formed in the active regions on both sides of the word line; Bit line contact portion, formed on the drain region; and Multiple bit lines are formed on the bit line contact portion, the bit lines intersect with the word lines, and the first line overlaps with the bit lines.

7. The semiconductor device as claimed in claim 6, characterized in that, There is no contact plug above the portion of the active region between the two bit lines, and there is no contact plug above the portion of the active region between the two word lines.

8. A semiconductor device, characterized in that, include: A semiconductor substrate having a shallow trench isolation structure and a plurality of active regions defined by the shallow trench isolation structure; Multiple trenches are located on the semiconductor substrate and arranged in a checkerboard pattern; Multiple contact plugs are located within the trench and are in electrical contact with the corresponding active areas; A capacitor is formed on the active region, and a portion of the capacitor is electrically connected to the active region below via a corresponding contact plug; An interlayer dielectric layer is located between adjacent contact plugs; In this embodiment, at least one of the grooves adjacent to the contact plug is filled with the interlayer dielectric layer.

9. The semiconductor device as claimed in claim 8, characterized in that, The interlayer dielectric layer includes multiple first lines, multiple second lines, and an asymmetrical serrated edge, wherein the first lines intersect perpendicularly with the second lines and partially overlap.

10. A semiconductor device, characterized in that, include: A semiconductor substrate having a shallow trench isolation structure and a plurality of active regions defined by the shallow trench isolation structure; An interlayer dielectric layer is located on the semiconductor substrate; Multiple first lines are spaced apart along a first direction, and the first lines have misaligned ends; Multiple second lines are spaced apart along a second direction, and the second lines have misaligned ends; The first line and the second line together define a checkerboard-shaped arrangement of contact plugs, wherein the contact plugs are connected to the active area; The overlapping area between the end of the first line and the second line has an asymmetrical serrated edge; A capacitor is formed on the active region, and a portion of the capacitor is electrically connected to the active region below via a corresponding contact plug.

11. The semiconductor device as claimed in claim 10, characterized in that, The overlapping area between the end of the second line and the first line also has an asymmetrical serrated edge.

12. The semiconductor device as claimed in claim 10, characterized in that, The asymmetrical serrated edges are arranged alternately with the contact plugs.

13. A semiconductor device, characterized in that, include: A semiconductor substrate having a core region, a peripheral region, and a boundary region between the core region and the peripheral region; Contact plugs are located on the substrate and are distributed in a checkerboard pattern; An interlayer dielectric layer is located between adjacent contact plugs and covers the junction area; Among them, the contact plugs closest to the boundary area are asymmetrically distributed.

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