Semiconductor structure and manufacturing method thereof

Abstract

The semiconductor structure includes a substrate and a word line structure. The substrate is provided with a groove. The word line structure is located in the substrate. The word line structure includes a first spacer, a word line conductive layer, a barrier layer, and a second spacer. The first spacer is disposed on a sidewall of the trench. And the character line conductive layer is filled at the bottom of the groove. The barrier layer is disposed between the first spacer and the word line conductive layer. And a second spacer disposed on the barrier layer and the word line conductive layer, the second spacer including a low-K dielectric material, in which a thickness of the second spacer is gradually reduced along a first direction from the first spacer to the word line conductive layer. The semiconductor structure can reduce the parasitic capacitance between the word line and the bit line implantation region and the parasitic capacitance between the word line and the contact implantation region.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] In recent decades, with the continuous improvement of electronic products, the demand for storage capacity has been increasing. To increase the storage capacity of storage devices (such as DRAM devices), more storage cells need to be integrated. As integration increases, parasitic capacitance may also increase. Summary of the Invention

[0003] According to one aspect of the present invention, a method for manufacturing a semiconductor structure is provided. A substrate is provided, wherein the substrate has trenches. A first spacer is formed in the trenches. A barrier layer is formed on the first spacer. A word line conductive layer is formed to fill the trenches. A first portion of the word line conductive layer and a first portion of the barrier layer are removed. A second portion of the word line conductive layer and a second portion of the barrier layer are removed to form a groove near the first spacer, wherein the groove has a first end and a second end, the first end being near the first spacer and the second end being near the top surface of the word line conductive layer, the depth of the groove gradually decreasing from the first end to the second end. A second spacer is formed to fill the groove, wherein the second spacer has a first portion, a second portion, and a third portion, the first portion being located on a sidewall of the first spacer, the second portion being located on the top surface of the word line conductive layer, and the third portion being located within the groove, wherein the second spacer comprises a low-k material. The first and second portions of the second spacer are removed. A capping layer is formed to fill the trenches.

[0004] According to some embodiments, after removing a first portion of the character line conductive layer and a first portion of the barrier layer, the first distance from the top surface of the character line conductive layer to the top surface of the substrate is 50 to 60 nanometers.

[0005] According to some embodiments, after the groove is formed, the second distance from the bottom surface of the first end of the groove to the top surface of the character line conductive layer is 5 to 10 nanometers.

[0006] According to some embodiments, after the groove is formed, the third distance from the sidewall of the first spacer to the second end of the groove is 5 to 10 nanometers.

[0007] According to some embodiments, the second distance is the same as the third distance.

[0008] According to some embodiments, the thickness of the first portion of the second spacer is 1 to 10 nanometers.

[0009] According to some embodiments, the grooves are formed by a dry etching process.

[0010] According to some embodiments, the method further includes forming a first implantation region and a second implantation region in a substrate after forming a cover layer.

[0011] According to one aspect of the present invention, a semiconductor structure is provided. The semiconductor structure includes a substrate and a word line structure. The substrate has a trench. The word line structure is located in the substrate. The word line structure includes a first spacer, a word line conductive layer, a barrier layer, and a second spacer. The first spacer is disposed on the sidewall of the trench. The word line conductive layer fills the bottom of the trench. The barrier layer is disposed between the first spacer and the word line conductive layer. The second spacer is disposed on the barrier layer and the word line conductive layer, and the second spacer includes a low-k dielectric material, wherein the thickness of the second spacer gradually decreases along a first direction from the first spacer to the word line conductive layer, and the top surface of the second spacer is coplanar with the top surface of the word line conductive layer.

[0012] According to some embodiments, the semiconductor structure further includes a capping layer. The capping layer is located on the word line conductive layer, wherein the top surface of the capping layer is coplanar with the top surface of the substrate.

[0013] According to some embodiments, the semiconductor structure further includes a first implantation region and a second implantation region. The first implantation region and the second implantation region are located in the substrate and adjacent to the word line structure.

[0014] According to some embodiments, the first implantation region and the second implantation region contain N-type dopants.

[0015] According to some embodiments, the second spacer comprises silicon carbonitride.

[0016] According to some embodiments, the first spacer comprises an oxide.

[0017] According to some embodiments, the barrier layer comprises titanium oxide.

[0018] It should be understood that the foregoing general description and the following detailed description are provided by way of example and are intended to further explain the scope of the claimed invention. Attached Figure Description

[0019] A more complete understanding of the present invention can be obtained by reading the following detailed description of the embodiments and referring to the accompanying drawings:

[0020] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure according to some embodiments.

[0021] Figure 2 This is a schematic cross-sectional view of a semiconductor structure after a first spacer and a barrier layer have been formed in a trench, according to some embodiments.

[0022] Figure 3This is a schematic cross-sectional view of a semiconductor structure after a character line conductive layer has been formed to fill the trench, according to some embodiments.

[0023] Figure 4 This is a schematic cross-sectional view of a semiconductor structure after removing a portion of the character line conductive layer and the barrier layer, according to some embodiments.

[0024] Figure 5 This is a schematic cross-sectional view of a semiconductor structure after the formation of a groove, according to some embodiments.

[0025] Figure 6 This is a schematic cross-sectional view of a semiconductor structure after a second spacer has been formed to fill the groove, according to some embodiments.

[0026] Figure 7 This is a schematic cross-sectional view of a semiconductor structure after a portion of the second spacer has been removed, according to some embodiments.

[0027] Figure 8 This is a schematic cross-sectional view of a semiconductor structure after the capping layer has been formed, according to some embodiments.

[0028] Figure 9 This is a cross-sectional schematic diagram of a semiconductor structure forming a first implantation region and a second implantation region, according to some embodiments. Detailed Implementation

[0029] Reference will now be made in detail to embodiments of the invention, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0030] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific embodiments or examples of components and configurations are described below to simplify the invention. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or symbols may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, for ease of description, the present invention may use spatially relative terms, such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship of an element or feature to one or more other elements or features, as shown in the accompanying drawings. The spatially relative terms are intended to cover not only the orientation illustrated in the drawings but also different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0032] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be directly connected to or coupled to another component or layer, or there can be intermediate components or layers.

[0033] Figures 1 to 9 This is a schematic diagram illustrating various intermediate stages in the formation of a semiconductor structure 100 according to some embodiments. The semiconductor structure 100 can be applied to an integrated circuit (IC) or a portion thereof, such as logic circuits, resistors, capacitors, sensors, and storage devices (e.g., dynamic random access memory (DRAM)). It should be understood that, for the sake of simplicity, [the accompanying drawings are omitted]. Figures 1 to 9 Some components of the semiconductor structure 100 are not shown, and other embodiments of the semiconductor structure 100 may include other components.

[0034] refer to Figure 1 The semiconductor structure 100 includes a substrate 102. In some embodiments, the substrate 102 may be a semiconductor substrate, such as a host semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., wherein the insulator may be a buried oxide (BOX) layer, a silicon oxide layer, etc. In some embodiments, the substrate 102 may be doped (e.g., containing p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the substrate 102 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors, or combinations thereof. The substrate 102 may also be formed of other materials, such as sapphire, indium tin oxide, etc. Trench 104 may then be formed in the substrate 102. The trench 104 may be formed by a suitable wet etching process or other suitable isotropic etching process. As shown, the trench 104 may have a circular bottom surface 104B and vertical sidewalls 104S.

[0035] refer to Figure 2A first spacer 110 is formed in trench 104, and a barrier layer 120 is formed on the first spacer 110. Specifically, the first spacer 110 may be formed conformally to cover the bottom surface 104B and sidewalls 104S of trench 104. The barrier layer 120 may be formed conformally to cover the first spacer 110. In other words, the barrier layer 120 may have a similar cross-sectional profile. In some embodiments, the first spacer 110 comprises a suitable dielectric material, such as an oxide. In some embodiments, the barrier layer 120 comprises a suitable material for preventing metal diffusion, such as titanium nitride, tantalum nitride, tungsten nitride, silicon dioxide, silicon nitride, etc. In some embodiments, suitable deposition processes may be used to form the first spacer 110 and the barrier layer 120, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0036] refer to Figure 3 A character line conductive layer 130 is formed in the trench 104. Specifically, the character line conductive layer 130 may fill the trench 104. After forming the character line conductive layer 130, a selective chemical mechanical polishing (CMP) process may be performed. After the CMP process, the top surface 130T of the character line conductive layer 130 is coplanar with the top surface 102T of the substrate 102. In some embodiments, the character line conductive layer 130 includes a suitable conductive material, such as a metal. For example, the character line conductive layer 130 may include tungsten. In some embodiments, the character line conductive layer 130 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0037] refer to Figure 4 The first portion 130-1 of the character line conductive layer 130 and the first portion 120-1 of the barrier layer 120 are removed. After removing the character line conductive layer 130 and a portion of the barrier layer 120, the top surface 130T of the character line conductive layer 130 is lower than the top surface 102T of the substrate 102. The first distance D1 between the top surface 130T of the character line conductive layer 130 and the top surface 102T of the substrate 102 is 50 to 60 nanometers (nm). A portion of the character line conductive layer 130 and a portion of the barrier layer 120 can be removed by a suitable etching process.

[0038] refer to Figure 5The second portion 130-2 of the character line conductive layer 130 and the second portion 120-2 of the barrier layer 120 are removed to form a groove 132. In other words, the peripheral portion of the character line conductive layer 130 and the exposed portion of the barrier layer 120 are removed. The groove 132 has a triangular cross-sectional profile. The groove 132 has a first end E1 and a second end E2, wherein the first end E1 of the groove 132 is close to the first spacer 110, and the second end E2 of the groove 132 is close to the top surface 130T of the character line conductive layer 130.

[0039] The groove 132 has a second distance D2, which is 5-10 nm. The second distance D2 refers to the depth between the top surface 130T of the character line conductive layer 130 and the first end E1 of the groove 132. The groove 132 also has a third distance D3, which is 5-10 nm. The third distance D3 refers to the width between the second end E2 of the groove 132 and the inner wall 110S of the first spacer 110. The second distance D2 and the third distance D3 can be the same or different. After the groove 132 is formed, the first spacer 110 remains unetched. After the groove 132 is formed, the central portion of the character line conductive layer 130 is higher than the peripheral portion. After the groove 132 is formed, the barrier layer 120 is closer to the top surface of the first spacer 110 than the barrier layer 120 is closer to the top surface of the character line conductive layer 130. The groove 132 can be formed using a suitable directional dry etching process, such as plasma reactive etching or ion beam etching.

[0040] refer to Figure 6 A second spacer 140 is formed to fill the groove 132. The second spacer 140 has a first portion 140-1, a second portion 140-2, and a third portion 140-3. As shown, the first portion 140-1 is located on the sidewall 110S of the first spacer 110, the second portion 140-2 is located on the top surface 130T of the character line conductive layer 130, and the third portion 140-3 is located within the groove 132. The second spacer 140 has a fourth distance D4, which is 1 to 10 nm, and the fourth distance D4 refers to the thickness of the first portion 140-1 located on the sidewall 110S of the first spacer 110. In some embodiments, the second spacer 140 may include a low-k (K < 3.9) material, such as silicon oxycarbide (SiCO). In some embodiments, the second spacer 140 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0041] refer to Figure 7The first portion 140-1 and the second portion 140-2 of the second spacer 140 are removed, exposing the top surface 130T of the character line conductive layer 130. As shown, the third portion 140-3 of the second spacer 140 remains in the groove 132, and the top surface of the third portion 140-3 of the second spacer 140 can be coplanar with the top surface 130T of the character line conductive layer 130. The first portion 140-1 and the second portion 140-2 of the second spacer 140 can be removed using a suitable directional dry etching process, such as plasma reactive etching, ion beam etching, etc.

[0042] refer to Figure 8 A capping layer 150 is formed to fill the trench 104. After the capping layer 150 is formed, an optional chemical mechanical polishing (CMP) process can be performed. After the CMP process, the top surface 150T of the capping layer 150 is coplanar with the top surface 102T of the substrate 102. The capping layer 150 has a fifth distance D5, which is 50-60 nm, and the fifth distance D5 refers to the thickness of the capping layer 150. In some embodiments, the first distance D1 is the same as the fifth distance D5. In some embodiments, the capping layer 150 may include a suitable dielectric material, such as silicon nitride (SiN). In some embodiments, a suitable deposition process can be used to form the capping layer 150, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0043] See Figure 9 A first implantation region 160 and a second implantation region 170 may be formed in the substrate 102. In some embodiments, the first implantation region 160 and the second implantation region 170 may include an N-type dopant. In other embodiments, the first implantation region 160 and the second implantation region 170 may include a P-type dopant. In some embodiments, the first implantation region 160 and the second implantation region 170 may include the same or different dopants. For example, the first implantation region 160 is a contact implantation region, while the second implantation region 170 is a bitline implantation region.

[0044] like Figure 9 As shown, the semiconductor structure 100 includes a word line structure WL. The word line structure WL is located in the substrate 102. The word line structure WL includes a first spacer 110, a word line conductive layer 130, a barrier layer 120, a second spacer 140, and a capping layer 150. The first spacer 110 is disposed on the sidewall of the trench 104 (e.g., ...). Figure 2A character line conductive layer 130 is filled into the bottom of trench 104. A barrier layer 120 is located between the first spacer 110 and the character line conductive layer 130. A second spacer 140 is located on the barrier layer 120 and the character line conductive layer 130, wherein it extends from the first spacer 110 to the character line conductive layer 130 along a first direction FD. The second spacer 140 has a gradually decreasing thickness T1, and its top surface 140T is coplanar with the top surface 130T of the character line conductive layer 130. A capping layer 150 is located on the character line conductive layer 130, wherein the top surface 150T of the capping layer 150 is coplanar with the top surface 102T of the substrate 102. A first implantation region 160 and a second implantation region 170 are located on the substrate 102 and adjacent to the character line structure WL.

[0045] This invention provides a semiconductor structure and a method for manufacturing the same. By forming a second spacer, the parasitic capacitance between the word line and the bit line implantation region, as well as the parasitic capacitance between the word line and the contact implantation region, can be reduced.

[0046] Although the invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are also possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0047] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, this invention is intended to cover any modifications and variations of the invention that fall within the scope of the appended claims.

[0048] [Symbol Explanation]

[0049] 100: Semiconductor Structure

[0050] 102:Substrate

[0051] 102T: Top surface

[0052] 104: Trench

[0053] 104B: Bottom surface

[0054] 104S: Sidewall

[0055] 110: First spacer

[0056] 110S: Sidewall

[0057] 120: Barrier Layer

[0058] 120-1: Part One

[0059] 120-2: Part Two

[0060] 130: Character line conductive layer

[0061] 130-1: Part One

[0062] 130-2: Part Two

[0063] 130T: Top surface

[0064] 132: Groove

[0065] 140: Second spacer

[0066] 140-1: Part One

[0067] 140-2: Part Two

[0068] 140-3: Part Three

[0069] 140T: Top surface

[0070] 150: Covering layer

[0071] 150T: Top surface

[0072] 160: First Implantation Zone

[0073] 170: Second Implantation Zone

[0074] D1: First Distance

[0075] D2: Second distance

[0076] D3: Third Distance

[0077] D4: Fourth Distance

[0078] D5: Fifth Distance

[0079] E1: First end

[0080] E2: Second end

[0081] FD: First Direction

[0082] T1: Thickness

[0083] WL: Character line structure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate has trenches; A first spacer is formed in the trench; A barrier layer is formed on the first spacer; A character line conductive layer is formed to fill the trench; Remove the first portion of the character line conductive layer and the first portion of the blocking layer; Remove the second portion of the character line conductive layer and the second portion of the barrier layer to form a groove near the first spacer, wherein the groove has a first end and a second end, the first end being near the first spacer and the second end being near the top surface of the character line conductive layer, and the depth of the groove gradually decreases from the first end to the second end. A second spacer is formed to fill the groove, wherein the second spacer has a first portion, a second portion and a third portion, the first portion is located on the sidewall of the first spacer, the second portion is located on the top surface of the character line conductive layer, and the third portion is located in the groove, wherein the second spacer contains a low-K material; Remove the first portion and the second portion of the second spacer; and A capping layer is formed to fill the trench.

2. The method according to claim 1, characterized in that, After removing the first portion of the character line conductive layer and the first portion of the barrier layer, the first distance from the top surface of the character line conductive layer to the top surface of the substrate is 50 to 60 nanometers.

3. The method according to claim 1, characterized in that, After the groove is formed, the second distance from the bottom surface of the first end of the groove to the top surface of the character line conductive layer is 5 to 10 nanometers.

4. The method according to claim 3, characterized in that, After the groove is formed, the third distance from the sidewall of the first spacer to the second end of the groove is 5 to 10 nanometers.

5. The method according to claim 4, characterized in that, The second distance is the same as the third distance.

6. The method according to claim 1, characterized in that, The thickness of the first portion of the second spacer is 1 to 10 nanometers.

7. The method according to claim 1, characterized in that, The groove is formed by a dry etching process.

8. The method according to claim 1, characterized in that, Further includes: After the cover layer is formed, a first implantation area and a second implantation area are formed in the substrate.

9. A semiconductor structure, characterized in that, include: The substrate has grooves; and The character line structure, located in the substrate, includes: The first spacer is disposed on the side wall of the trench; The character line conductive layer fills the bottom of the trench; A barrier layer is disposed between the first spacer and the character line conductive layer; and A second spacer is disposed on the barrier layer and the character line conductive layer. The second spacer comprises a low-k dielectric material. The thickness of the second spacer gradually decreases along a first direction from the first spacer to the character line conductive layer, and the top surface of the second spacer is coplanar with the top surface of the character line conductive layer.

10. The semiconductor structure according to claim 9, characterized in that, Further includes: A capping layer is located on the character line conductive layer, wherein the top surface of the capping layer is coplanar with the top surface of the substrate.

11. The semiconductor structure according to claim 9, characterized in that, Further includes: The first implantation area and the second implantation area are located in the substrate and are adjacent to the character line structure.

12. The semiconductor structure according to claim 11, characterized in that, The first implantation region and the second implantation region contain N-type dopants.

13. The semiconductor structure according to claim 9, characterized in that, The second spacer contains silicon carbonitride.

14. The semiconductor structure according to claim 9, characterized in that, The first spacer contains oxides.

15. The semiconductor structure according to claim 9, characterized in that, The barrier layer contains titanium oxide.

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