Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. The semiconductor device may include: a peripheral circuit; a first gate structure on the peripheral circuit; a first stack at a level corresponding to the first gate structure; a source bonding structure on the first gate structure; a first contact bonding structure on the first stack; a first channel structure extending through the first gate structure into the source junction structure; a first contact plug extending through the first stack into the first contact bonding structure; a second gate structure on the source bonding structure; a second stack on the first contact bonding structure; a second channel structure extending through the second gate structure into the source junction structure; and a second contact plug extending through the second stack into the first contact bonding structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to electronic devices and methods of manufacturing electronic devices, and more specifically, to semiconductor devices and methods of manufacturing semiconductor devices. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices where memory cells are formed as a single layer on a substrate has reached its limit, three-dimensional semiconductor devices with memory cells stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0003] According to embodiments of the present disclosure, a semiconductor device may include: a peripheral circuit; a first gate structure located above the peripheral circuit and including alternating layers of a first insulating layer and a first conductive layer; a first stack located at a level corresponding to the first gate structure and including alternating layers of a first insulating layer and a first sacrificial layer; a source junction structure located on the first gate structure; a first contact junction structure located on the first stack; a first channel structure extending partially through the first gate structure into the source junction structure; a first contact plug extending through the first stack into the first contact junction structure; a second gate structure located on the source junction structure and including alternating layers of a second insulating layer and a second conductive layer; a second stack located on the first contact junction structure and including alternating layers of a second insulating layer and a second sacrificial layer; a second channel structure extending through the second gate structure into the source junction structure; and a second contact plug extending through the second stack into the first contact junction structure.

[0004] According to embodiments of the present disclosure, a method of manufacturing a semiconductor device may include: forming a first stack on a first substrate; forming a first channel structure extending through the first stack into the first substrate; forming a first contact plug extending through the first stack; removing the first substrate; forming a first dielectric bonding layer on the first stack; forming a first opening exposing the first channel structure by partially removing the first dielectric bonding layer; forming a second opening exposing the first contact plug by partially removing the first dielectric bonding layer; forming a first source bonding pattern in the first opening; and forming a first contact bonding pattern in the second opening. Attached Figure Description

[0005] Figure 1A and Figure 1B This is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0006] Figures 2A to 2CThis is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0007] Figures 3 to 7 This is a simplified diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 8 This is a simplified diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 9 This is a simplified diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 10 This is a simplified diagram illustrating a memory system according to an embodiment of the present disclosure.

[0011] Figure 11 This is a simplified diagram illustrating a memory system according to an embodiment of the present disclosure.

[0012] Figure 12 This is a simplified diagram illustrating a memory system according to an embodiment of the present disclosure.

[0013] Figure 13 This is a simplified diagram illustrating a memory system according to an embodiment of the present disclosure.

[0014] Figure 14 This is a simplified diagram illustrating a memory system according to an embodiment of the present disclosure.

[0015] Figure 15 This is a simplified structural diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0016] According to embodiments of this disclosure, a semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device has a stable structure and exhibits improved characteristics and reliability.

[0017] Hereinafter, embodiments based on the technical concept of this disclosure will be described with reference to the accompanying drawings.

[0018] Figure 1A and Figure 1B This is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1A It is a floor plan, and Figure 1B It is along Figure 1A A cross-sectional view taken from line A-A'.

[0019] Reference Figure 1A and Figure 1BAccording to embodiments, a semiconductor device may include a first stack 120S, a first gate structure 120G, a second stack 180S, a second gate structure 180G, a first channel structure 130, a second channel structure 190, a first contact plug CTP1, a second contact plug CTP2, a source junction structure 140, a first contact junction structure 150, a second contact junction structure 160, and a dielectric junction structure 170. The semiconductor device may also include a substrate 100, peripheral circuitry PC, peripheral circuitry junction structure 110, a first interconnect structure IC1, a second interconnect structure IC2, a third interconnect structure IC3, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, a third interlayer insulating layer IL3, a first contact via CTV1, and a second contact via CTV2.

[0020] The peripheral circuit PC can be located on or above the substrate 100. The peripheral circuit PC can include at least one transistor 1, which includes junctions 1A and 1B, a gate electrode 1D, and a gate insulating layer 1C located between the gate electrode 1D and the substrate 100. An isolation layer ISO can be located in the substrate 100 and can define an active region. The aforementioned at least one transistor 1 can be located in the active region.

[0021] The first interlayer insulating layer IL1 may be located on the substrate 100. The first interconnect structure IC1 may be located within the first interlayer insulating layer IL1. More specifically, the first interconnect structure IC1 may be located on or above the substrate 100. The first interconnect structure IC1 may include at least one first via ICA extending in the stacking direction (i.e., perpendicular to the top surface of the substrate), and at least one first line ICB extending in a direction parallel to the top surface of the substrate. The first interconnect structure IC1 may be connected to a peripheral circuit PC. For example, at least one of the first via ICAs may be connected to a transistor 1. The first via ICAs may connect the first lines ICBs to each other. The first lines ICBs may connect the first via ICAs to each other. The first interconnect structure IC1 may include a suitable conductive material, such as tungsten. The first interlayer insulating layer IL1 may include a suitable insulating material, such as an oxide or nitride.

[0022] The peripheral circuit bonding structure 110 may be located on the first interconnect structure IC1. The peripheral circuit bonding structure 110 may include a first peripheral circuit bonding pad 110A and a second peripheral circuit bonding pad 110B. The first peripheral circuit bonding pad 110A may be located in a first interlayer insulating layer IL1. The second peripheral circuit bonding pad 110B may be located on the first peripheral circuit bonding pad 110A and may also be located in a second interlayer insulating layer IL2. Here, the second interlayer insulating layer IL2 may be located on the first interlayer insulating layer IL1. The peripheral circuit bonding structure 110 may include a suitable conductive material, such as copper, and the second interlayer insulating layer IL2 may include a suitable insulating material, such as an oxide.

[0023] The second interconnect structure IC2 may be located on the peripheral circuit bonding structure 110. The second interconnect structure IC2 may be disposed within the second interlayer insulating layer IL2 above the peripheral circuit bonding structure 110. More specifically, the second interconnect structure IC2 may be located on and contact the peripheral circuit bonding structure 110. The second interconnect structure IC2 may include at least one second via ICC and at least one second line ICD. Some of the second line ICDs may serve as bit lines. For example, a second line ICD connected to the first channel structure 130 may serve as a bit line. The second interconnect structure IC2 may be connected to the peripheral circuit bonding structure 110. For example, at least one of the second via ICCs may be connected to the second peripheral circuit bonding pad 110B. The second interconnect structure IC2 may include a suitable conductive material, such as tungsten. The second interlayer insulating layer IL2 may include a suitable insulating material, such as an oxide or nitride.

[0024] The first gate structure 120G may be located above the peripheral circuit PC. For example, the first gate structure 120G may be located above the peripheral circuit junction structure 110. The first gate structure 120G may include alternating layers of a first insulating layer 120A and a first conductive layer 120C. Here, the first conductive layer 120C may be a gate line. The gate line may include at least one of a word line, a source select line, and a drain select line. The first stack 120S may be located at a level corresponding to the first gate structure 120G and may include alternating layers of a first insulating layer 120A and a first sacrificial layer 120B. The first stack 120S may be a remaining structure not replaced by the first gate structure 120G. Here, the first insulating layer 120A may include an insulating material such as an oxide, the first sacrificial layer 120B may include a sacrificial material such as a nitride, and the first conductive layer 120C may include a suitable conductive material, such as tungsten, polysilicon, or molybdenum.

[0025] The first gate structure 120G may include a first step structure SS1. For example, the first gate structure 120G may include a first step structure SS1 that exposes the upper surface of each of the first conductive layers 120C. Here, the first step structure SS1 may have an inverted step shape.

[0026] Source junction structure 140 may be located on first gate structure 120G. Source junction structures 140 may be spaced apart from each other in a second direction II intersecting the first direction I. Source junction structure 140 may include a first source junction pattern 140A and a second source junction pattern 140B located on the first source junction pattern 140A. In a process for manufacturing a semiconductor device, the first source junction pattern 140A and the second source junction pattern 140B may be bonded. Source junction structure 140 may include a conductive material such as polysilicon.

[0027] The first contact bonding structure 150 may be located on the first stack 120S. The first contact bonding structure 150 may be located at the layer corresponding to the source bonding structure 140. The first contact bonding structure 150 may be located between source bonding structures 140 separated in the second direction II. For example, the first contact bonding structure 150 may be located in the dielectric bonding structure 170. In this case, the first contact bonding structures 150 may be insulated from each other through the dielectric bonding structure 170.

[0028] The first contact bonding structure 150 may be arranged along a first direction I and a second direction II. The first contact bonding structure 150 may include a first contact bonding pattern 150A and a second contact bonding pattern 150B located on the first contact bonding pattern 150A. In a process for manufacturing a semiconductor device, the first contact bonding pattern 150A and the second contact bonding pattern 150B may be bonded. The first contact bonding structure 150 may comprise the same or substantially the same material as the source bonding structure 140. For example, the first contact bonding structure 150 may comprise a conductive material such as polysilicon.

[0029] The second contact bonding structure 160 may be located on the first gate structure 120G. The second contact bonding structure 160 may be located at a layer corresponding to the source bonding structure 140. For example, the second contact bonding structure 160 may be located in the dielectric bonding structure 170. In this case, the second contact bonding structures 160 may be insulated from each other through the dielectric bonding structure 170.

[0030] The second contact bonding structure 160 may be arranged along a first direction I and a second direction II. The second contact bonding structure 160 may include a third contact bonding pattern 160A and a fourth contact bonding pattern 160B located on the third contact bonding pattern 160A. In the process of manufacturing a semiconductor device, the third contact bonding pattern 160A and the fourth contact bonding pattern 160B may be bonded to each other. The second contact bonding structure 160 may comprise the same or substantially the same material as the source bonding structure 140. For example, the second contact bonding structure 160 may comprise a conductive material such as polysilicon.

[0031] The dielectric bonding structure 170 may be located at a layer corresponding to at least one of the source bonding structure 140, the first contact bonding structure 150, and the second contact bonding structure 160. For example, the dielectric bonding structure 170 may be located at a layer corresponding to the source bonding structure 140 and the first contact bonding structure 150. The dielectric bonding structure 170 may be located between adjacent source bonding structures 140. The dielectric bonding structure 170 may include a first dielectric bonding pattern 170A and a second dielectric bonding pattern 170B located on the first dielectric bonding pattern 170A. In the process of manufacturing a semiconductor device, the first dielectric bonding pattern 170A and the second dielectric bonding pattern 170B may be bonded to each other. The dielectric bonding structure 170 may include a dielectric material.

[0032] According to embodiments of this disclosure, a semiconductor device may include a source bonding structure 140, a first contact bonding structure 150, a second contact bonding structure 160, and a dielectric bonding structure 170 as bonding structures. In the process of manufacturing the semiconductor device, the source bonding structure 140, the first contact bonding structure 150, the second contact bonding structure 160, and the dielectric bonding structure 170 can be used as bonding structures without forming additional bonding pads for bonding unit wafers to each other. The first source bonding pattern 140A and the second source bonding pattern 140B can be directly bonded, the first contact bonding pattern 150A and the second contact bonding pattern 150B can be directly bonded, the third contact bonding pattern 160A and the fourth contact bonding pattern 160B can be directly bonded, and the first dielectric bonding pattern 160A and the second dielectric bonding pattern 160B can be directly bonded.

[0033] Furthermore, the source junction structure 140, the first contact junction structure 150, and the second contact junction structure 160 may comprise the same or substantially the same material. For example, the source junction structure 140, the first contact junction structure 150, and the second contact junction structure 160 may comprise polysilicon. The manufacturing cost of a semiconductor device can be reduced by integrating the fabrication of the source junction structure 140, the first contact junction structure 150, and the second contact junction structure 160 into a single, simultaneous operation.

[0034] The second gate structure 180G may be located on the source junction structure 140. The second gate structure 180G may include alternating layers of a second insulating layer 180A and a second conductive layer 180C. Here, the second conductive layer 180C may be a gate line. The gate line may include at least one of a word line, a source select line, and a drain select line. The second stack 180S may be located on the first contact junction structure 150 and may include alternating layers of a second insulating layer 180A and a second sacrificial layer 180B. The second stack 180S may be the remaining structure not replaced by the second gate structure 180G. Here, the second insulating layer 180A may include an insulating material such as an oxide, the second sacrificial layer 180B may include a sacrificial material such as a nitride, and the second conductive layer 180C may include a suitable conductive material, such as tungsten, polysilicon, or molybdenum.

[0035] The second gate structure 180G may include a second step structure SS2. For example, the second gate structure 180G may include a second step structure SS2 that exposes the upper surface of each of the second conductive layers 180C. For example, the second step structure SS2 may have a shape symmetrical to the first step structure SS1, wherein the plane of symmetry extends parallel to the top surface of the substrate 100 and through the bonding interface of the second contact bonding structure 160. That is, the first step structure SS1 and the second step structure SS2 may be mirror images of each other.

[0036] The first channel structure 130 may extend partially through the first gate structure 120G into the source junction structure 140. Each of the first channel structures 130 may include at least one of a first channel layer 130A, a first memory layer 130B surrounding the first channel layer 130A, and a first insulating core 130C located in the first channel layer 130A.

[0037] The second channel structure 190 may extend partially through the second gate structure 180G into the source junction structure 140. Each of the second channel structures 190 may include at least one of a second channel layer 190A, a second memory layer 190B surrounding the second channel layer 190A, and a second insulating core 190C located in the second channel layer 190A.

[0038] The first channel structure 130 and the second channel structure 190 may share the source junction structure 140. For example, the first channel structure 130 and the second channel structure 190 may share a source junction structure 140.

[0039] The first contact plug CTP1 may extend partially through the first stack 120S into the first contact engagement structure 150. The first contact plug CTP1 may extend through the first stack 120S and may be electrically connected to the peripheral circuit PC. The first contact plug CTP1 may comprise a suitable conductive material, such as tungsten.

[0040] The second contact plug CTP2 may extend partially through the second stack 180S into the first contact engagement structure 150. The second contact plug CTP2 may include a suitable conductive material, such as tungsten.

[0041] The first contact plug CTP1 and the second contact plug CTP2 can share the first contact engagement structure 150. For example, the first contact plug CTP1 and the second contact plug CTP2 can be electrically connected through the first contact engagement structure 150. A first contact plug CTP1 and a second contact plug CTP2 can share a first contact engagement structure 150. In this case, the second contact plug CTP2 can be electrically connected to the peripheral circuit PC through the first contact engagement structure 150 and the first contact plug CTP1.

[0042] The first contact via CTV1 may extend through the first stepped structure SS1 of the first gate structure 120G and may be connected to the first conductive layer 120C. The first contact via CTV1 may be connected to at least one of the first conductive layers 120C via a protrusion CTVP of the first contact via CTV1. For example, the first contact via CTV1 may be connected via the protrusion CTVP to the first conductive layer 120C exposed on its upper surface through the first stepped structure SS1. The first contact via CTV1 may extend through the first stepped structure SS1 and may be electrically connected to the peripheral circuit PC. An insulating spacer SP may be located between the first contact via CTV1 and the first conductive layer 120C. The first contact via CTV1 may include a suitable conductive material, such as tungsten. The insulating spacer SP may include an insulating material such as oxide.

[0043] The second contact via CTV2 may extend through the second stepped structure SS2 of the second gate structure 180G and may be connected to the second conductive layer 180C. The second contact via CTV2 may be connected to at least one of the second conductive layers 180C via a protrusion CTVP. For example, the second contact via CTV2 may be connected to the second conductive layer 180C exposed on its upper surface through the second stepped structure SS2 via the protrusion CTVP. An insulating spacer SP may be located between the second contact via CTV2 and the second conductive layer 180C. The second contact via CTV2 may comprise a suitable conductive material, such as tungsten.

[0044] The first contact via CTV1 and the second contact via CTV2 can share the second contact engagement structure 160. For example, the first contact via CTV1 and the second contact via CTV2 can be electrically connected through the second contact engagement structure 160. A first contact via CTV1 and a second contact via CTV2 can share a second contact engagement structure 160. In this case, the second contact via CTV2 can be electrically connected to the peripheral circuit PC through the second contact engagement structure 160 and the first contact via CTV1.

[0045] The third interconnect structure IC3 may be located on the second gate structure 180G and / or the second stack 180S. The third interconnect structure IC3 may be disposed within the third interlayer insulating layer IL3. Here, the third interlayer insulating layer IL3 may be located on the second gate structure 180G. The third interconnect structure IC3 may include at least one third via ICE and at least one third line ICF. The third interconnect structure IC3 may include a suitable conductive material, such as tungsten. The third interlayer insulating layer IL3 may include a suitable insulating material, such as an oxide or nitride.

[0046] According to the above structure, the source junction structure 140 can be a source structure connected to the first channel structure 130 and the second channel structure 190, and can be used as a junction structure. The first contact junction structure 150 can be a contact structure electrically connecting the first contact plug CTP1 and the second contact plug CTP2, and can be used as a junction structure. The second contact junction structure 160 can be a contact structure electrically connecting the first contact via CTV1 and the second contact via CTV2, and can be used as a junction structure.

[0047] Figures 2A to 2C This is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 2A It is a floor plan, and Figure 2B and Figure 2C It is along Figure 2A The cross-sectional view taken by line B-B'.

[0048] Reference Figures 2A to 2CThe semiconductor device may include a first stack 220S1, a first gate structure 220G, a second stack 280S1, a second gate structure 280G, a third stack 220S2, a fourth stack 280S2, a first channel structure 230, a second channel structure 290, a first contact plug CTP1, a second contact plug CTP2, a source junction structure 240, a first contact junction structure 250, a third contact junction structure 260, and a dielectric junction structure 270. The semiconductor device may include a substrate 200, peripheral circuitry PC, peripheral circuitry junction structure 210, a first interconnect structure IC1, a second interconnect structure IC2, a third interconnect structure IC3, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, a third interlayer insulating layer IL3, a first contact via CTV1, and a second contact via CTV2.

[0049] The peripheral circuit PC can be located on or above the substrate 200. The peripheral circuit PC can include a transistor 1. The transistor 1 can include junctions 1A and 1B, a gate electrode 1D, and a gate insulating layer 1C. An isolation layer ISO can be located in the substrate 200, and the active region can be defined by the isolation layer ISO. The transistor 1 can be located in the active region.

[0050] The first interconnect structure IC1 may be located on or above the substrate 200. The first interconnect structure IC1 may be located within a first interlayer insulating layer IL1. Here, the first interlayer insulating layer IL1 may be located on the substrate 200. The first interconnect structure IC1 may include at least one first via ICA and at least one first line ICB. The first interconnect structure IC1 may be connected to a peripheral circuit PC.

[0051] The peripheral circuit bonding structure 210 may be located on the first interconnect structure IC1. The peripheral circuit bonding structure 210 may include a first peripheral circuit bonding pad 210A and a second peripheral circuit bonding pad 210B. The first peripheral circuit bonding pad 210A may be located in the first interlayer insulating layer IL1. The second peripheral circuit bonding pad 210B may be located on the first peripheral circuit bonding pad 210A and may also be located in the second interlayer insulating layer IL2. Here, the second interlayer insulating layer IL2 may be located on the first interlayer insulating layer IL1.

[0052] The second interconnect structure IC2 may be located on the peripheral circuit bonding structure 210. The second interconnect structure IC2 may be located in the second interlayer insulating layer IL2. The second interconnect structure IC2 may include at least one second via ICC and at least one second line ICD. Some of the second line ICDs may be used as bit lines. For example, a second line ICD connected to the first channel structure 230 may be used as a bit line. The second interconnect structure IC2 may be connected to the peripheral circuit bonding structure 210.

[0053] The first gate structure 220G may be located on or above the peripheral circuit bonding structure 210. The first gate structure 220G may include alternating layers of a first insulating layer 220A and a first conductive layer 220C. Here, the first conductive layer 220C may be a gate line. The gate line may include at least one of a word line, a source select line, and a drain select line. The first stack 220S1 may be located at the layer corresponding to the first gate structure 220G and may include alternating layers of a first insulating layer 220A and a first sacrificial layer 220B. The third stack 220S2 may be located at the layer corresponding to the first stack 220S1 and may include alternating layers of a first insulating layer 220A and a first sacrificial layer 220B. The first stack 220S1 and the third stack 220S2 may be remaining structures not replaced by the first gate structure 220G.

[0054] Reference Figure 2B The first gate structure 220G may include a first stepped structure SS1. For example, the first gate structure 220G may include a first stepped structure SS1 exposing the upper surface of each of the first conductive layers 220C. The first stepped structure SS1 may have an inverted stepped shape. (See reference...) Figure 2C The first gate structure 220G may not include the first step structure SS1.

[0055] Source bonding structure 240 may be located on first gate structure 220G. Source bonding structures 240 may be spaced apart from each other in a second direction II intersecting the first direction I. Source bonding structure 240 may include a first source bonding pattern 240A and a second source bonding pattern 240B located on the first source bonding pattern 240A. In the process of manufacturing a semiconductor device, the first source bonding pattern 240A and the second source bonding pattern 240B may be bonded. Source bonding structure 240 may include a conductive material such as polysilicon.

[0056] The first contact bonding structure 250 may be located on the first stack 220S1. The first contact bonding structure 250 may be located at a layer corresponding to the source bonding structure 240. The first contact bonding structure 250 may be located between source bonding structures 240 separated in a second direction II. The first contact bonding structure 250 may be arranged along a first direction I and a second direction II. The first contact bonding structure 250 may include a first contact bonding pattern 250A and a second contact bonding pattern 250B located on the first contact bonding pattern 250A. In a process for manufacturing a semiconductor device, the first contact bonding pattern 250A and the second contact bonding pattern 250B may be bonded. The first contact bonding structure 250 may comprise the same or substantially the same material as the source bonding structure 240. For example, the first contact bonding structure 250 may comprise a conductive material such as polysilicon.

[0057] The third contact bonding structure 260 may be located on the third stack 220S2. The third contact bonding structure 260 may be located at a layer corresponding to the source bonding structure 240. The third contact bonding structure 260 may be arranged along a first direction I and a second direction II. The third contact bonding structure 260 may include a fifth contact bonding pattern 260A and a sixth contact bonding pattern 260B located on the fifth contact bonding pattern 260A. In the process of manufacturing a semiconductor device, the fifth contact bonding pattern 260A and the sixth contact bonding pattern 260B may be bonded. The third contact bonding structure 260 may comprise the same or substantially the same material as the source bonding structure 240. For example, the third contact bonding structure 260 may comprise a conductive material such as polysilicon.

[0058] The dielectric bonding structure 270 may be located at a layer corresponding to at least one of the source bonding structure 240, the first contact bonding structure 250, and the third contact bonding structure 260. The dielectric bonding structure 270 may include a first dielectric bonding pattern 270A and a second dielectric bonding pattern 270B located on the first dielectric bonding pattern 270A. In the process of manufacturing a semiconductor device, the first dielectric bonding pattern 270A and the second dielectric bonding pattern 270B may be bonded. The dielectric bonding structure 270 may include a dielectric material.

[0059] The second gate structure 280G may be located on the source junction structure 240. The second gate structure 280G may include alternating layers of a second insulating layer 280A and a second conductive layer 280C. Here, the second conductive layer 280C may be a gate line. The gate line may include at least one of a word line, a source select line, and a drain select line. The second stack 280S1 may be located on the first contact junction structure 250 and may include alternating layers of a second insulating layer 280A and a second sacrificial layer 280B. The fourth stack 280S2 may be located at a level corresponding to the second stack 280S1 and may include alternating layers of a second insulating layer 280A and a second sacrificial layer 280B. The second stack 280S1 and the fourth stack 280S2 may be remaining structures not replaced by the second gate structure 280G.

[0060] Reference Figure 2B The second gate structure 280G may include a second stepped structure SS2. For example, the second gate structure 280G may include a second stepped structure SS2 exposing the upper surface of each of the second conductive layers 280C. Here, the second stepped structure SS2 may have a shape symmetrical to the first stepped structure SS1. (Refer to...) Figure 2C The second gate structure 280G may not include the second step structure SS2.

[0061] The support member SPS can be located between the first gate structure 220G and the third stack 220S2, and between the second gate structure 280G and the fourth stack 280S2. The support member SPS can distinguish the regions where the third contact plug CTP3 and the fourth contact plug CTP4 are located, as well as the regions where the first contact via CTV1 and the second contact via CTV2 are located. One end of the first support member SPS can contact the first gate structure 220G or the second gate structure 280G, and the other end can contact the third stack 220S2 or the fourth stack 280S2. The support member SPS can include an insulating material such as an oxide.

[0062] The first channel structure 230 may extend partially through the first gate structure 220G into the source junction structure 240. Each of the first channel structures 230 may include at least one of a first channel layer 230A, a first memory layer 230B surrounding the first channel layer 230A, and a first insulating core 230C located in the first channel layer 230A.

[0063] The second channel structure 290 may extend partially through the second gate structure 280G into the source junction structure 240. Each of the second channel structures 290 may include at least one of a second channel layer 290A, a second memory layer 290B surrounding the second channel layer 290A, and a second insulating core 290C located in the second channel layer 290A.

[0064] The first channel structure 230 and the second channel structure 290 may share the source junction structure 240. For example, the first channel structure 230 and the second channel structure 290 may share a single source junction structure 240.

[0065] The first contact plug CTP1 can extend partially through the first stack 220S1 into the first contact engagement structure 250. The first contact plug CTP1 can extend through the first stack 220S1 and can be electrically connected to the peripheral circuit PC. The second contact plug CTP2 can extend partially through the second stack 280S1 into the first contact engagement structure 250.

[0066] The first contact plug CTP1 and the second contact plug CTP2 can share the first contact engagement structure 250. The second contact plug CTP2 can be electrically connected to the peripheral circuit PC through the first contact engagement structure 250 and the first contact plug CTP1.

[0067] The third contact plug CTP3 can extend through the third stack 220S2 into the third contact engagement structure 260. The third contact plug CTP3 can extend through the third stack 220S2 and can be electrically connected to the peripheral circuit PC.

[0068] The fourth contact plug CTP4 may be located on the third contact engagement structure 260 and may extend through the fourth stack 280S2 into the third contact engagement structure 260. The third contact plug CTP3 and the fourth contact plug CTP4 may share the third contact engagement structure 260. For example, the third contact plug CTP3 and the fourth contact plug CTP4 may be electrically connected through the third contact engagement structure 260. One third contact plug CTP3 and one fourth contact plug CTP4 may share a third contact engagement structure 260. In this case, the fourth contact plug CTP4 may be electrically connected to the peripheral circuit PC through the third contact engagement structure 260 and the third contact plug CTP3.

[0069] Reference Figure 2B The first contact via CTV1 can be directly connected to the upper surface of the first conductive layer 220C exposed through the first stepped structure SS1 of the first gate structure 220G. Here, the first contact via CTV1 can have a different height. The second contact via CTV2 can be directly connected to the upper surface of the second conductive layer 280C exposed through the second stepped structure SS2 of the second gate structure 280G. Here, the second contact via CTV2 can have a different height.

[0070] Reference Figure 2C The first contact via CTV1 can extend through the first gate structure 220G and can be connected to the first conductive layer 220C. Here, the first contact via CTV1 can have a different height. The second contact via CTV2 can extend through the second gate structure 280G and can be connected to the second conductive layer 280C. Here, the second contact via CTV2 can have a different height. An insulating spacer SP can be located on the sidewall of the first contact via CTV1 to insulate the remaining first conductive layer 220C except for the first conductive layer 220C connected to the first contact via CTV1. Similarly, the insulating spacer SP can be located on the sidewall of the second contact via CTV2.

[0071] Compare Figure 1B , Figure 2B and Figure 2C , Figure 1B The first contact via CTV1 and the second contact via CTV2 can share the second contact bonding structure 160. Here, the second contact bonding structure 160 can be located between the first step structure SS1 and the second step structure SS2. The second contact via CTV2 can be electrically connected to the second contact bonding structure 160 through the second step structure SS2 of the second gate structure 180G. Therefore, the second contact via CTV2 can be electrically connected to the peripheral circuit PC through the second contact bonding structure 160 and the first contact via CTV1.

[0072] However, Figure 2B and Figure 2C The first contact via CTV1 and the second contact via CTV2 cannot be shared. Figure 1B The second contact bonding structure 160. In this case, the second contact bonding structure 160 may not exist between the first gate structure 220G and the second gate structure 280G, and the second contact via CTV2 may not pass through the second gate structure 280G.

[0073] The third contact plug CTP3 and the fourth contact plug CTP4 can electrically connect the second contact via CTV2 to the peripheral circuit PC. Here, the third contact engagement structure 260 can be located between the third stack 220S2 and the fourth stack 280S2. Therefore, the second contact via CTV2 can be electrically connected to the peripheral circuit PC through the fourth contact plug CTP4, the third contact engagement structure 260, and the third contact plug CTP3.

[0074] The third interconnect structure IC3 can be located on the second gate structure 280G, the second stack 280S1, and the fourth stack 280S2. The third interconnect structure IC3 can be located in the third interlayer insulating layer IL3. Here, the third interlayer insulating layer IL3 can be located on the second gate structure 280G. The third interconnect structure IC3 may include a third via ICE and a third line ICF.

[0075] According to the above structure, the heights of the first contact vias CTV1 and CTV2 can be different from each other. In this case, the first contact vias CTV1 can be directly connected to the peripheral circuit PC, and the second contact vias CTV2 can be electrically connected to the peripheral circuit PC through the fourth contact plug CTP4, the third contact engagement structure 260, and the third contact plug CTP3.

[0076] Figures 3 to 7 This is a simplified diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. In the following text, content overlapping with the above description is omitted.

[0077] Reference Figure 3 A peripheral circuit wafer (PWF) can be formed. The peripheral circuit PC can be formed on or above the first substrate 300. The peripheral circuit PC can include a transistor 1. The transistor 1 can include junctions 1A and 1B, a gate electrode 1D, and a gate insulating layer 1C. Here, the gate insulating layer 1C can be formed between the gate electrode 1D and the first substrate 300. An isolation layer ISO can be located in the first substrate 300, and the active region can be defined by the isolation layer ISO. The transistor 1 can be formed in the active region.

[0078] The first interconnect structure IC1 may be formed on or above the first substrate 300. Here, the first interconnect structure IC1 may be formed in the first interlayer insulating layer IL1. The first interlayer insulating layer IL1 may be formed on the first substrate 300. The first interconnect structure IC1 may include at least one first via ICA and at least one first line ICB. The first interconnect structure IC1 may be connected to a peripheral circuit PC. For example, at least one of the first vias ICA may be connected to a transistor 1. The first vias ICA can connect the first lines ICB to each other. The first lines ICB can connect the first vias ICA to each other. The first interconnect structure IC1 may include a suitable conductive material, such as tungsten, copper, or aluminum. The first interlayer insulating layer IL1 may include a suitable insulating material, such as an oxide or a nitride.

[0079] The first peripheral circuit bonding pad 310 can be formed on the first interconnect structure IC1. The first peripheral circuit bonding pad 310 may include a suitable conductive material, such as copper. Therefore, the peripheral circuit wafer PWF can be formed to include a first substrate 300, a peripheral circuit PC, a first interlayer insulating layer IL1, the first interconnect structure IC1, and the first peripheral circuit bonding pad 310.

[0080] Reference Figure 4 A first unit wafer CWF1 can be formed. A first stack 410S can be formed by alternately stacking a first material layer 410A and a second material layer 410B on or above a second substrate 400. The first stack 410S may include a first step structure SS1. The upper surface of each of the second material layers 410B in the first stack 410S can be exposed through the first step structure SS1. Here, the first material layer 410A may include an insulating material such as an oxide, and the second material layer 410B may include a sacrificial material such as a nitride. Alternatively, the second material layer 410B may include a conductive material such as molybdenum.

[0081] A first channel structure 420 may be formed that extends partially through the first stack 410S into the second substrate 400. For example, the first channel structure 420 may include at least one of a first channel layer 420A, a first memory layer 420B surrounding the first channel layer 420A, and a first insulating core 420C in the first channel layer 420A.

[0082] A first contact plug CTP1 may be formed extending through the first stack 410S. For example, a first contact plug CTP1 may be formed extending partially through the first stack 410S into the second substrate 400. The first contact plug CTP1 may comprise a suitable conductive material, such as tungsten.

[0083] A first contact via CTV1 extending through the first stack 410S can be formed. The first contact via CTV1 can be formed to extend through the first stepped structure SS1 and each connect to the second material layer 410B. The first contact via CTV1 may include protrusions and can contact the upper surface of the second material layer 410B exposed through the first stepped structure SS1. To prevent contact between the first contact via CTV1 and the remaining second material layer 410B except for the second material layer 410B contacted by the protrusions of the first contact via CTV1, an insulating spacer SP can be formed on the sidewall of the first contact via CTV1. The first contact via CTV1 may include a suitable conductive material, such as tungsten. The insulating spacer SP may include an insulating material such as an oxide. The insulating spacer SP can be formed between the first contact via CTV1 and the second material layer 410B.

[0084] The second material layer 410B of the first stack 410S can be replaced by a fifth material layer 410C. For example, the second material layer 410B can be replaced by the fifth material layer 410C by extending through a first slit (not shown) of the first stack 410S. Thus, a first gate structure 410G in which the first material layer 410A and the fifth material layer 410C are alternately stacked can be defined. Certain regions of the first stack 410S may not be replaced by the fifth material layer 410C. For example, in the region of the first stack 410S where the first contact plug CTP1 is formed, the second material layer 410B may be retained without being replaced by the fifth material layer 410C. Here, the fifth material layer 410C may comprise a suitable conductive material, such as tungsten, molybdenum, or polysilicon.

[0085] For reference, when the second material layer 410B comprises a conductive material, the process of replacing the second material layer 410B with a fifth material layer 410C can be omitted. In this case, the first stack 410S can be used as the first gate structure 410G.

[0086] The second interconnect structure IC2 can be formed on the first stack 410S. Here, the second interconnect structure IC2 can be formed in the second interlayer insulating layer IL2. The second interlayer insulating layer IL2 can be formed on the first step structure SS1 of the first stack 410S. The second interconnect structure IC2 may include at least one second via ICC and at least one second line ICD. The second interconnect structure IC2 can be connected to at least one of the first channel structure 420, the first contact plug CTP1, and the first contact via CTV1. The second interconnect structure IC2 may include a suitable conductive material, such as tungsten, copper, or aluminum. The second interlayer insulating layer IL2 may include a suitable insulating material, such as an oxide or nitride.

[0087] The second peripheral circuit bonding pad 430 can be formed on the second interconnect structure IC2. The second peripheral circuit bonding pad 430 may include a conductive material such as copper. Therefore, the first unit chip CWF1 is formed to include a second substrate 400, a first stack 410S, a first gate structure 410G, a first channel structure 420, a first contact plug CTP1, a first contact via CTV1, a second interlayer insulating layer IL2, the second interconnect structure IC2, and the second peripheral circuit bonding pad 430.

[0088] Reference Figure 5A It can bond the peripheral circuit chip PWF and the first unit chip CWF1. For example, the first peripheral circuit bonding pad 310 of the peripheral circuit chip PWF and the second peripheral circuit bonding pad 430 of the first unit chip CWF1 can be directly bonded.

[0089] Subsequently, the second substrate 400 can be removed, and the first channel structure 420, the first contact plug CTP1, and the first contact via CTV1 can be exposed by removing the second substrate 400. Subsequently, the first channel layer 420A can be exposed by partially removing the first memory layer 420B of the first channel structure 420.

[0090] Subsequently, a first dielectric bonding layer 510 may be formed on the first stack 410S in the region where the second substrate 400 has been removed. The first dielectric bonding layer 510 may include a dielectric material.

[0091] Reference Figure 5B A first opening OP1 exposing the first channel structure 420 can be formed by partially removing the first dielectric bonding layer 510. A second opening OP2 exposing the first contact plug CTP1 can be formed by partially removing the first dielectric bonding layer 510. A third opening OP3 exposing the first contact via CTV1 can be formed by partially removing the first dielectric bonding layer 510. The second opening OP2 can be formed while forming the first opening OP1. The third opening OP3 can be formed while forming the first opening OP1.

[0092] Subsequently, a conductive bonding layer 520 can be formed to fill the first opening OP1, the second opening OP2, and the third opening OP3. For example, the conductive bonding layer 520 can be formed on the first channel structure 420 to fill the first opening OP1. Here, the conductive bonding layer 520 can include a conductive material such as polysilicon. Subsequently, the conductive bonding layer 520 can be annealed.

[0093] Reference Figure 5CA first source bonding pattern 530 can be formed in the first opening OP1. For example, the conductive bonding layer 520 can be planarized by using the first dielectric bonding layer 510 as a planarization barrier, and the first source bonding pattern 530 can be formed in the first opening OP1. In this case, the first channel layer 420A of the first channel structure 420 can be connected to the first source bonding pattern 530.

[0094] The first contact bonding pattern 540 can be formed in the second opening OP2. The first contact bonding pattern 540 can be formed when the first source bonding pattern 530 is formed. The first contact plugs CTP1 can be connected to the corresponding first contact bonding patterns 540 one by one. Therefore, one first contact plug CTP1 can be connected to one first contact bonding pattern 540. Adjacent first contact bonding patterns 540 can be insulated from each other through the first dielectric bonding layer 510.

[0095] The second contact bonding pattern 550 can be formed in the third opening OP3. The second contact bonding pattern 550 can be formed when the first source bonding pattern 530 is formed. The first contact vias CTV1 can be connected to the corresponding second contact bonding patterns 550 one by one. Therefore, one first contact via CTV1 can be connected to one second contact bonding pattern 550. Adjacent second contact bonding patterns 550 can be insulated from each other through the first dielectric bonding layer 510.

[0096] According to embodiments of this disclosure, when a first source bonding pattern 530 is formed by patterning the conductive bonding layer 520, a first contact bonding pattern 540 and a second contact bonding pattern 550 can be formed simultaneously. In this case, the manufacturing cost of the semiconductor device can be reduced by integrating the processes for forming the first source bonding pattern 530, the first contact bonding pattern 540, and the second contact bonding pattern 550.

[0097] Reference Figure 6A For example, Figure 4 The method for forming the first unit wafer CWF1 is used to form the second unit wafer CWF2. For example, the second unit wafer CWF2 can be formed to include a third substrate 600, a second stack 610S, a second gate structure 610G, a second channel structure 620, a second contact plug CTP2, a second contact via CTV2, a third interlayer insulating layer IL3, and a third interconnect structure IC3.

[0098] Here, the second stack 610S may include alternating layers of a third material layer 610A and a fourth material layer 610B. The second stack 610S may include a second step structure SS2. The upper surface of each of the fourth material layers 610B may be exposed through the second step structure SS2. The second stack 610S may be replaced by a second gate structure 610G, and the second gate structure 610G may include alternating layers of a third material layer 610A and a sixth material layer 610C.

[0099] The second channel structure 620 may extend through the second gate structure 610G, and each of the second channel structures 620 may include a second channel layer 620A, a second memory layer 620B, and a second insulating core 620C. The second contact plug CTP2 may extend through the second stack 610S. The second contact via CTV2 may extend through the second gate structure 610G. For example, the second contact via CTV2 may extend through the second step structure SS2 of the second gate structure 610G and may be connected to the sixth material layer 610C.

[0100] Reference Figure 6B The second unit wafer CWF2 can be rotated. First, a dummy bonding layer 630 can be formed on the second unit wafer CWF2. Subsequently, the dummy bonding layer 630 and the dummy substrate 640 can be bonded. In this case, the second unit wafer CWF2 can be rotated so that the lower surface of the third substrate 600 is exposed.

[0101] Then, it can be used Figures 5A to 5C The method of forming the first dielectric bonding layer 510, the first source bonding pattern 530, the first contact bonding pattern 540 and the second contact bonding pattern 550 of the first unit wafer CWF1 is used to form the second dielectric bonding layer 650, the second source bonding pattern 660, the third contact bonding pattern 670 and the fourth contact bonding pattern 680 of the second unit wafer CWF2.

[0102] A second dielectric bonding layer 650 can be formed on the second stack 610S. A second source bonding pattern 660 can be formed on the second gate structure 610G. A third contact bonding pattern 670 and a fourth contact bonding pattern 680 can be formed at the layer corresponding to the second source bonding pattern 660. The second channel layer 620A of the second channel structure 620 can be connected to the second source bonding pattern 660. A second contact plug CTP2 can be connected to a third contact bonding pattern 670. Here, one second contact plug CTP2 can be connected to one third contact bonding pattern 670. Adjacent third contact bonding patterns 670 can be insulated from each other through the second dielectric bonding layer 650. A second contact via CTV2 can be connected to a fourth contact bonding pattern 680. Here, one second contact via CTV2 can be connected to one fourth contact bonding pattern 680. Adjacent fourth contact bonding patterns 680 can be insulated from each other through the second dielectric bonding layer 650.

[0103] Reference Figure 7 The first unit wafer CWF1 and the second unit wafer CWF2 can be bonded. For example, the first unit wafer CWF1 and the second unit wafer CWF2 can be bonded to connect the first source bonding pattern 530 and the second source bonding pattern 660, the first contact bonding pattern 540 and the third contact bonding pattern 670, the second contact bonding pattern 550 and the fourth contact bonding pattern 680, and the first dielectric bonding layer 510 and the second dielectric bonding layer 650.

[0104] According to embodiments of this disclosure, additional bonding pads may not be formed to bond the first unit wafer CWF1 and the second unit wafer CWF2. For example, a conductive bonding layer 520 may be formed on a first dielectric bonding layer 510 of the first unit wafer CWF1. A first source bonding pattern 530, a first contact bonding pattern 540, and a second contact bonding pattern 550 may be formed by patterning the conductive bonding layer 520 using the first dielectric bonding layer 510 as a planarization barrier. Similarly, a second dielectric bonding layer 650, a second source bonding pattern 660, a third contact bonding pattern 670, and a fourth contact bonding pattern 680 may be formed for the second unit wafer CWF2.

[0105] In this configuration, the first channel structure 420 and the second channel structure 620 can share the second source bonding pattern 660 and the first source bonding pattern 530. The second contact plug CTP2 can be electrically connected to the third contact bonding pattern 670, the first contact bonding pattern 540, and the first contact plug CTP1, and can also be electrically connected to the peripheral circuit PC. The second contact via CTV2 can be electrically connected to the fourth contact bonding pattern 680, the second contact bonding pattern 550, and the first contact via CTV1, and can also be electrically connected to the peripheral circuit PC.

[0106] According to the above manufacturing method, the second channel structure 620 of the second unit chip CWF2 can share the second source bonding pattern 660 and the first source bonding pattern 530 with the first channel structure 420. The second contact plug CTP2 of the second unit chip CWF2 can be electrically connected to the peripheral circuit PC through the first contact plug CTP1, and the second contact via CTV2 of the second unit chip CWF2 can be electrically connected to the peripheral circuit PC through the first contact via CTV1.

[0107] Furthermore, by integrating the processes of the source bonding patterns 530 and 660, contact bonding patterns 540 and 670, and contact bonding patterns 550 and 680 of the forming unit wafers CWF1 and CWF2, the manufacturing cost of semiconductor devices can be advantageously reduced.

[0108] Figure 8 This is a simplified diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. In the following text, content overlapping with the above description is omitted.

[0109] Reference Figure 8 This can be used to form peripheral circuit wafers (PWF). For example, it can be used... Figure 3 The method for forming a peripheral circuit wafer (PWF) is described above. Here, the peripheral circuit wafer (PWF) may include a first substrate 800, a peripheral circuit PC, a first interlayer insulating layer IL1, a first interconnect structure IC1, and a first peripheral circuit bonding pad 810A.

[0110] For example, you can use Figures 4 to 5C The method for forming the first unit wafer CWF1 is described above. Here, the first unit wafer CWF1 may include a second peripheral circuit bonding pad 810B, a second interlayer insulating layer IL2, a second interconnect structure IC2, a first stack 820S1, a third stack 820S2, a first gate structure 820G, a first channel structure 830, a first source bonding pattern 840A, a first contact bonding pattern 850A, a fifth contact bonding pattern 860A, a first dielectric bonding layer 870A, a first contact plug CTP1, a third contact plug CTP3, and a first contact via CTV1.

[0111] Here, the first stack 820S1 may include alternating layers of first material layer 820A and second material layer 820B. The first stack 820S1 may include a first stepped structure SS1 exposing the upper surface of each of the second material layers 820B. The first stack 820S1 may be replaced by a first gate structure 820G. A first contact via CTV1 may be directly connected to the upper surface of each of the fifth material layers 820C exposed by the first stepped structure SS1 of the first gate structure 820G. The first contact via CTV1 may have different heights. The first contact via CTV1 may be electrically connected to an external circuit PC.

[0112] The fifth contact bonding pattern 860A can be formed at the layer corresponding to the first source bonding pattern 840A. The third contact plug CTP3 can extend through the third stack 820S2 into the fifth contact bonding pattern 860A. Here, the third stack 820S2 can be formed at the layer corresponding to the first stack 820S1. The third contact plug CTP3 can be electrically connected to the peripheral circuit PC.

[0113] A second unit wafer, CWF2, can be formed. For example, it can be used... Figure 6A and Figure 6B The method for forming a second cell wafer CWF2 is described above. Here, the second cell wafer CWF2 may include a second source bonding pattern 840B, a second contact bonding pattern 850B, a sixth contact bonding pattern 860B, a second dielectric bonding layer 870B, a second stack 880S1, a fourth stack 880S2, a second gate structure 880G, a second channel structure 890, a second contact plug CTP2, a fourth contact plug CTP4, a second contact via CTV2, a support SPS, a third interconnect structure IC3, and a third interlayer insulating layer IL3.

[0114] Here, the second stack 880S1 may include alternately stacked third material layer 880A and fourth material layer 880B. The second stack 880S1 may include a second stepped structure SS2 exposing the upper surface of each of the fourth material layers 880B. The second stack 880S1 may be replaced by a second gate structure 880G. The second contact via CTV2 may be directly connected to the upper surface of each of the sixth material layers 880C exposed by the second stepped structure SS2 of the second gate structure 880G. The second contact via CTV2 may have different heights.

[0115] The sixth contact bonding pattern 860B can be formed at the layer corresponding to the second source bonding pattern 840B. The fourth contact plug CTP4 can extend through the fourth stack 880S2 into the sixth contact bonding pattern 860B. Here, the fourth stack 880S2 can be formed at the layer corresponding to the second stack 880S1. The fourth contact plug CTP4 can be electrically connected to the peripheral circuit PC via the third contact plug CTP3.

[0116] The first source bonding pattern 840A can be bonded to the second source bonding pattern 840B, the first contact bonding pattern 850A can be bonded to the second contact bonding pattern 850B, and the fifth contact bonding pattern 860A can be bonded to the sixth contact bonding pattern 860B.

[0117] The second contact via CTV2 can be connected to the fourth contact plug CTP4 through the third interconnect structure IC3. Therefore, the second contact via CTV2 can be electrically connected to the fourth contact plug CTP4, the sixth contact bonding pattern 860B and the fifth contact bonding pattern 860A, and can be connected to the peripheral circuit PC.

[0118] According to the above manufacturing method, the fifth contact bonding pattern 860A and the sixth contact bonding pattern 860B can be formed between the third stack 820S2 and the fourth stack 880S2. The third contact plug CTP3 can extend into the fifth contact bonding pattern 860A, and the fourth contact plug CTP4 can extend into the sixth contact bonding pattern 860B. Here, the fifth contact bonding pattern 860A and the sixth contact bonding pattern 860B can be joined, and the third contact plug CTP3 and the fourth contact plug CTP4 can be electrically connected.

[0119] Furthermore, a first contact via CTV1 can be formed directly connected to the upper surface of the fifth material layer 820C, with the upper surface of the fifth material layer 820C exposed through the first step structure SS1 of the first gate structure 820G. A second contact via CTV2 can also be formed directly connected to the upper surface of the sixth material layer 880C, with the upper surface of the sixth material layer 880C exposed through the second step structure SS2 of the second gate structure 880G. In this configuration, the first contact via CTV1 can be directly connected to the peripheral circuit PC, and the second contact via CTV2 can be electrically connected to the peripheral circuit PC through the fourth contact plug CTP4, the sixth contact bonding pattern 860B, and the fifth contact bonding pattern 860A.

[0120] Figure 9 This is a simplified diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. In the following text, content overlapping with the above description is omitted.

[0121] It can be used to form peripheral circuit chips (PWF). For example, it can be used... Figure 3 The method for forming a peripheral circuit wafer (PWF) is described above. Here, the peripheral circuit wafer (PWF) may include a first substrate 900, a peripheral circuit PC, a first interlayer insulating layer IL1, a first interconnect structure IC1, and a first peripheral circuit bonding pad 910A.

[0122] The first unit wafer CWF1 can be formed. For example, it can be used... Figures 4 to 5C The method for forming the first unit wafer CWF1 is described above. Here, the first unit wafer CWF1 may include a second peripheral circuit bonding pad 910B, a second interlayer insulating layer IL2, a second interconnect structure IC2, a first stack 920S1, a third stack 920S2, a first gate structure 920G, a first channel structure 930, a first source bonding pattern 940A, a first contact bonding pattern 950A, a fifth contact bonding pattern 960A, a first dielectric bonding layer 970A, a first contact plug CTP1, a third contact plug CTP3, and a first contact via CTV1.

[0123] Here, the first stack 920S1 may include alternately stacked first material layer 920A and second material layer 920B. Figure 8 In contrast, the first stack 920S1 may not include the first step structure. The first contact via CTV1 may extend through the first stack 920S1 and may connect to the second material layer 920B. The first contact via CTV1 may have different heights. The first contact via CTV1 may be electrically connected to the peripheral circuit PC.

[0124] The fifth contact bonding pattern 960A can be formed at the layer corresponding to the first source bonding pattern 940A. The third contact plug CTP3 can extend through the third stack 920S2 into the fifth contact bonding pattern 960A. Here, the third stack 920S2 can be formed at the layer corresponding to the first stack 920S1. The third contact plug CTP3 can be electrically connected to the peripheral circuit PC.

[0125] For example, by using Figure 6A and Figure 6BThe method for forming a second cell wafer CWF2 is described above. Here, the second cell wafer CWF2 may include a second source bonding pattern 940B, a second contact bonding pattern 950B, a sixth contact bonding pattern 960B, a second dielectric bonding layer 970B, a second stack 980S1, a fourth stack 980S2, a second gate structure 980G, a second channel structure 990, a second contact plug CTP2, a fourth contact plug CTP4, a second contact via CTV2, a support SPS, a third interconnect structure IC3, and a third interlayer insulating layer IL3.

[0126] Here, the second stack 980S1 may include alternating layers of a third material layer 980A and a fourth material layer 980B. Figure 8 In contrast, the second stack 980S1 may not include the second step structure. The second contact via CTV2 may extend through the second stack 980S1 and may connect to the fourth material layer 980B. The second contact via CTV2 may have a different height.

[0127] The sixth contact bonding pattern 960B can be formed at the layer corresponding to the second source bonding pattern 940B. The fourth contact plug CTP4 can extend through the fourth stack 980S2 into the sixth contact bonding pattern 960B. The fourth stack 980S2 can be formed at the layer corresponding to the second stack 980S1. The fourth contact plug CTP4 can be electrically connected to the peripheral circuit PC through the third contact plug CTP3.

[0128] The first source bonding pattern 940A can be bonded to the second source bonding pattern 940B, the first contact bonding pattern 950A can be bonded to the second contact bonding pattern 950B, and the fifth contact bonding pattern 960A can be bonded to the sixth contact bonding pattern 960B.

[0129] The second contact via CTV2 can be connected to the fourth contact plug CTP4 through the third interconnect structure IC3. Therefore, the second contact via CTV2 can be electrically connected to the fourth contact plug CTP4, the sixth contact bonding pattern 960B and the fifth contact bonding pattern 960A, and can be connected to the peripheral circuit PC.

[0130] According to the manufacturing method described above, the fifth contact bonding pattern 960A and the sixth contact bonding pattern 960B can be formed between the third stack 920S2 and the fourth stack 980S2. The third contact plug CTP3 can extend into the fifth contact bonding pattern 960A, and the fourth contact plug CTP4 can extend into the sixth contact bonding pattern 960B. Here, the fifth contact bonding pattern 960A and the sixth contact bonding pattern 960B can be joined to each other, and the third contact plug CTP3 and the fourth contact plug CTP4 can be electrically connected.

[0131] Furthermore, a first contact via CTV1 can be formed that extends through the first gate structure 920G and is directly connected to the fifth conductive layer 920C, and a second contact via CTV2 can be formed that extends through the second gate structure 980G and is directly connected to the sixth conductive layer 980C. In this case, the first contact via CTV1 can be directly connected to the peripheral circuit PC, and the second contact via CTV2 can be electrically connected to the peripheral circuit PC through the fourth contact plug CTP4, the sixth contact bonding pattern 960B, and the fifth contact bonding pattern 960A.

[0132] Figure 10 This is a simplified diagram illustrating a memory system according to an embodiment of the present disclosure.

[0133] Reference Figure 10 The memory system 1000 may include a memory device 1200 therein for storing data, and a controller 1100 for communicating between the memory device 1200 and the host 2000.

[0134] The host 2000 can be a device or system that stores data in or retrieves data from the memory system 1000. The host 2000 can generate requests for various operations and can output these requests to the memory system 1000. Requests may include programming requests for programming operations, read requests for read operations, erase requests for erase operations, etc. The host 2000 can communicate with the memory system 1000 via various communication standards or interfaces, such as Peripheral Component Interconnect High Speed ​​(PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory High Speed ​​(NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Panel Interface (ESDI), or Integrated Drive Electronic Device (IDE).

[0135] The host 2000 may include at least one of a computer, portable digital device, tablet computer, digital camera, digital audio player, television, wireless communication device or cellular phone, but the embodiments disclosed herein are not limited thereto.

[0136] Generally, controller 1100 can control the operation of memory system 1000. Controller 1100 can control memory device 1200 according to requests from host 2000. Controller 1100 can control memory device 1200 so that it can perform programming operations, read operations, erase operations, etc., according to requests from host 2000. Alternatively, even if no request from host 2000 is received, controller 1100 can perform background operations, etc., to improve the performance of memory system 1000.

[0137] The controller 1100 can transmit control signals and data signals to the memory device 1200 to control the operation of the memory device 1200. Control signals and data signals can be transmitted to the memory device 1200 through different input / output lines. Data signals may include commands, addresses, or data. Control signals can be used to segment the input data signals.

[0138] The memory device 1200 can perform programming operations, reading operations, erasing operations, etc., under the control of the controller 1100. The memory device 1200 can be implemented as a volatile memory device in which the stored data is destroyed when the power is cut off, or as a non-volatile memory device in which the stored data is maintained even when the power is cut off.

[0139] The memory device 1200 may be a previously referenced Figure 1A , Figure 1B and Figures 2A to 2C The semiconductor device described has a specific structure. The memory device 1200 can be a semiconductor device using the previously referenced... Figures 3 to 7 , Figure 8 and Figure 9 A semiconductor device manufactured using the described manufacturing method. In an embodiment, a semiconductor device may include: a peripheral circuit; a first gate structure located above the peripheral circuit and including alternating layers of a first insulating layer and a first conductive layer; a first stack located at a level corresponding to the first gate structure and including alternating layers of a first insulating layer and a first sacrificial layer; a source junction structure located on the first gate structure; a first contact junction structure located on the first stack; a first channel structure extending through the first gate structure into the source junction structure; a first contact plug extending through the first stack into the first contact junction structure; a second gate structure located on the source junction structure and including alternating layers of a second insulating layer and a second conductive layer; a second stack located on the first contact junction structure and including alternating layers of a second insulating layer and a second sacrificial layer; a second channel structure extending through the second gate structure into the source junction structure; and a second contact plug extending through the second stack into the first contact junction structure.

[0140] Figure 11This is a simplified diagram illustrating a memory system according to an embodiment of the present disclosure.

[0141] Reference Figure 11 The memory system 30000 can be implemented as a cellular phone, smartphone, tablet computer, personal computer (PC), personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 2200 and a controller 2100 capable of controlling the operation of the memory device 2200.

[0142] The controller 2100 can control the data access operations of the memory device 2200 under the control of the processor 3100, such as programming operations, erasing operations, and reading operations.

[0143] The data programmed in the memory device 2200 can be output through the display 3200 under the control of the controller 2100.

[0144] The radio transceiver 3300 can transmit and receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed by the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and transmit the processed signals to the controller 2100 or the display 3200. The controller 2100 can transmit the signals processed by the processor 3100 to the memory device 2200. Furthermore, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the converted radio signals to an external device via the antenna ANT. The input device 3400 can be a device capable of inputting control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100, and can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200, so that data output from the controller 2100, data output from the radio transceiver 3300, or data output from the input device 3400 is output through the display 3200.

[0145] According to the implementation, the controller 2100 that can control the operation of the memory device 2200 can be implemented as part of the processor 3100 or as a chip separate from the processor 3100.

[0146] Figure 12 This is a simplified diagram illustrating a memory system according to an embodiment of the present disclosure.

[0147] Reference Figure 12The memory system 40000 can be implemented as a personal computer (PC), tablet computer, laptop computer, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player or MP4 player.

[0148] The memory system 40000 may include a memory device 2200 and a controller 2100 capable of controlling the data processing operations of the memory device 2200.

[0149] The processor 4100 can output data stored in the memory device 2200 via the display 4300 based on data input through the input device 4200. For example, the input device 4200 can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard.

[0150] The processor 4100 can control the overall operation of the memory system 40000 and control the operation of the controller 2100. According to the embodiment, the controller 2100, which is capable of controlling the operation of the memory device 2200, can be implemented as part of the processor 4100 or as a chip separate from the processor 4100.

[0151] Figure 13 This is a simplified diagram illustrating a memory system according to an embodiment of the present disclosure.

[0152] Reference Figure 13 The memory system 50000 can be implemented as an image processing device, such as a digital camera, a mobile phone equipped with a digital camera, a smartphone equipped with a digital camera, or a tablet computer equipped with a digital camera.

[0153] The memory system 50000 includes a memory device 2200 and a controller 2100 capable of controlling data processing operations (e.g., programming operations, erasing operations, or reading operations) of the memory device 2200.

[0154] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals and transmit the converted digital signals to the processor 5100 or the controller 2100. Under the control of the processor 5100, the converted digital signals can be output through the display 5300 or stored in the memory device 2200 through the controller 2100. Furthermore, data stored in the memory device 2200 can be output through the display 5300 under the control of the processor 5100 or the controller 2100.

[0155] According to the implementation, the controller 2100, which is capable of controlling the operation of the memory device 2200, may be implemented as part of the processor 5100 or as a chip separate from the processor 5100.

[0156] Figure 14 This is a simplified diagram illustrating a memory system according to an embodiment of the present disclosure.

[0157] Reference Figure 14 The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 2200, a controller 2100, and a card interface 7100.

[0158] The controller 2100 controls the data exchange between the memory device 2200 and the card interface 7100. According to embodiments, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but the embodiments are not limited to these.

[0159] Card interface 7100 can interface for data exchange between host 60000 and controller 2100 according to the protocol of host 60000. Depending on the implementation, card interface 7100 can support Universal Serial Bus (USB) protocol and IC-USB protocol. Here, card interface 7100 can refer to hardware, software installed in the hardware, or signal transmission method capable of supporting protocols used by host 60000.

[0160] When the memory system 70000 is connected to the host interface 6200 of a host 60000 such as a PC, tablet computer, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box, the host interface 6200 can perform data communication with the memory device 2200 through the card interface 7100 and the controller 2100 under the control of the microprocessor 6100.

[0161] Figure 15 This is a simplified structural diagram of a semiconductor device according to an embodiment of the present disclosure.

[0162] Reference Figure 15 The semiconductor device may include a substrate SUB, peripheral circuitry PC, bonding structure BS, and memory cell array CA. Here, the peripheral circuitry PC and memory cell array CA may be formed on separate substrates and then bonded together. The semiconductor device may also include a support base SP_B.

[0163] The substrate SUB may include a semiconductor material. In this embodiment, the semiconductor material may include at least one of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Here, group IV semiconductors may include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. Group II-VI compound semiconductors may include ZnS, ZnO, or CdS.

[0164] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include organic materials. In one embodiment, the substrate SUB may include graphene.

[0165] The substrate SUB can be a bulk wafer or an epitaxial layer grown using a selective epitaxial growth (SEG) method. The substrate SUB can be a layer formed using a metal-induced lateral crystallization (MILC) method and can locally include metal. The substrate SUB can have a single-crystal, polycrystalline, or amorphous state. The substrate SUB can include group II, III, IV, V, or VI impurities. In an embodiment, the substrate SUB can include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0166] The substrate SUB can serve as a support in the process of forming the peripheral circuit PC. Here, the peripheral circuit PC may include row decoders, column decoders, page buffers, logic circuits, control circuits, sense amplifiers, input / output circuits, etc. In embodiments, the peripheral circuit PC may include NMOS transistors, PMOS transistors, resistors, capacitors, etc. The peripheral circuit PC may also include interconnect structures. The interconnect structures can serve as paths for transmitting operating voltages and may include contact plugs, wires, etc.

[0167] The support base SP_B can be used as a support in the process of forming the memory cell array CA. In an embodiment, after manufacturing a first wafer including the memory cell array CA and a second wafer including peripheral circuitry PC, the first and second wafers can be electrically connected via a bonding structure BS. After bonding, at least a portion of the support base SP_B of the first wafer can be removed. The support base SP_B can be completely removed or can be partially retained on the memory cell array CA.

[0168] The support substrate SP_B can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The support substrate SP_B can be a bulk wafer, an epitaxial layer grown using selective epitaxial growth (SEG), or a layer formed using metal-induced lateral crystallization (MILC). The support substrate SP_B can be in a single-crystal, polycrystalline, or amorphous state. The support substrate SP_B can include group II, III, IV, V, or VI impurities.

[0169] The bonding structure BS can be used to connect the memory cell array CA and the peripheral circuit PC. In embodiments, the memory cell array CA and the peripheral circuit PC can be bonded using wafer-to-wafer bonding, chip-to-wafer bonding, chip-to-chip bonding, etc. The bonding structure BS may include bonding pads, bonding interfaces, etc. The bonding pads may include metals and / or alloys such as copper and aluminum. The bonding interfaces may include non-metal-to-non-metal interfaces, metal-to-metal interfaces, etc. The memory cell array CA and the peripheral circuit PC can be electrically connected through the bonding structure BS.

[0170] For reference, interconnect structures included in the cell array CA and / or peripheral circuit PC can also be used as bonding structures BS. In an embodiment, interconnect structures included in the cell array CA and interconnect structures included in the peripheral circuit PC can be directly bonded. In this case, bit lines, source lines, etc., can be used as bonding structures without additional bonding pads.

[0171] Semiconductor devices may also have a combination of previous references Figure 15 The described embodiment has a structure or a partially modified structure. At least one memory cell array CA and / or at least one peripheral circuit PC may be additionally coupled to the reference. Figure 15 The described implementation is as follows. For example, a third wafer including a memory cell array CA can be additionally manufactured, and then the third wafer can be bonded to a first wafer including the memory cell array CA. Here, the bonding structure BS can be used to connect the memory cell array CA and the memory cell array CA.

[0172] Although embodiments according to the technical spirit of this disclosure have been described with reference to the accompanying drawings, this is merely for illustrating embodiments based on the concept of this disclosure, and this disclosure is not limited to the described embodiments. Within the scope of the technical spirit of this disclosure as described in the claims, various substitutions, modifications, and alterations to the embodiments are possible for those skilled in the art, and these also fall within the scope of this disclosure. Furthermore, embodiments can be combined to form other embodiments.

[0173] Cross-references to related applications

[0174] This application claims priority to Korean Patent Application No. 10-2024-0059930, filed on May 7, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: Peripheral circuits; A first gate structure, the first gate structure being located above the peripheral circuit and comprising alternating layers of a first insulating layer and a first conductive layer; A first stack, located at a level corresponding to the first gate structure and comprising alternating stacks of the first insulating layer and the first sacrificial layer; A source junction structure is located on the first gate structure; A first contact bonding structure is located on the first stack; A first channel structure extends partially through the first gate structure into the source junction structure; A first contact plug extends through the first stack into the first contact engagement structure; A second gate structure is located on the source junction structure and includes alternating layers of a second insulating layer and a second conductive layer. The second stack is located on the first contact bonding structure and includes alternating stacks of the second insulating layer and the second sacrificial layer; A second channel structure extends through the second gate structure into the source junction structure; as well as The second contact plug extends through the second stack into the first contact engagement structure.

2. The semiconductor device according to claim 1, wherein, The first channel structure and the second channel structure share the source junction structure.

3. The semiconductor device according to claim 1, wherein, The first contact plug and the second contact plug are electrically connected through the first contact engagement structure.

4. The semiconductor device according to claim 1, wherein, The source junction structure is located at the level corresponding to the first contact junction structure.

5. The semiconductor device according to claim 1, wherein, The source bonding structure includes a first source bonding pattern and a second source bonding pattern on the first source bonding pattern, and The first source bonding pattern and the second source bonding pattern are directly bonded.

6. The semiconductor device according to claim 1, wherein, The first contact bonding structure includes a first contact bonding pattern and a second contact bonding pattern on the first contact bonding pattern, and The first contact bonding pattern and the second contact bonding pattern are directly bonded.

7. The semiconductor device according to claim 1, further comprising: A dielectric bonding structure located at a level corresponding to the source bonding structure and the first contact bonding structure.

8. The semiconductor device according to claim 1, wherein, The first gate structure includes a first stepped structure exposing the upper surface of each of the first conductive layers, and the second gate structure includes a second stepped structure exposing the upper surface of each of the second conductive layers. The semiconductor device further includes: A first contact via extends through the first stepped structure and connects to the first conductive layer; A second contact via, the second contact via extending through the second stepped structure and connecting to the second conductive layer; and A second contact bonding structure is located on the first gate structure and at a level corresponding to the source bonding structure.

9. The semiconductor device according to claim 8, wherein, The second contact via is electrically connected to the peripheral circuit through the second contact engagement structure and the first contact via.

10. The semiconductor device according to claim 8, wherein, The second contact bonding structure includes a third contact bonding pattern and a fourth contact bonding pattern on the third contact bonding pattern, and The third contact bonding pattern and the fourth contact bonding pattern are directly bonded.

11. The semiconductor device according to claim 8, wherein, The second contact engagement structure is arranged along the first direction and the second direction that intersects the first direction.

12. The semiconductor device according to claim 1, wherein, The first gate structure includes a first stepped structure exposing the upper surface of each of the first conductive layers, and the second gate structure includes a second stepped structure exposing the upper surface of each of the second conductive layers. The semiconductor device further includes: First contact vias with different heights, directly connected to the upper surface of each of the first conductive layers; and The second contact vias are directly connected to the upper surface of each of the second conductive layers and have different heights.

13. The semiconductor device of claim 12, further comprising: The third stack located at the level corresponding to the first stack; The fourth stack located at the level corresponding to the second stack; A third contact bonding structure located on the third stack and at the layer corresponding to the source bonding structure; A third contact plug extending through the third stack into the third contact engagement structure; as well as The fourth contact plug extends through the fourth stack into the third contact engagement structure.

14. The semiconductor device according to claim 13, wherein, The second contact through hole is electrically connected to the peripheral circuit through the fourth contact plug, the third contact engagement structure, and the third contact plug.

15. The semiconductor device of claim 1, further comprising: A first contact via extending through the first gate structure and connecting to the first conductive layer; as well as A second contact via extends through the second gate structure and connects to the second conductive layer.

16. The semiconductor device of claim 15, further comprising: The third stack located at the level corresponding to the first stack; The fourth stack located at the level corresponding to the second stack; A third contact bonding structure located on the third stack and at the layer corresponding to the source bonding structure; A third contact plug extending through the third stack into the third contact engagement structure; as well as The fourth contact plug extends through the fourth stack into the third contact engagement structure.

17. The semiconductor device according to claim 16, wherein, The second contact through hole is electrically connected to the peripheral circuit through the fourth contact plug, the third contact engagement structure, and the third contact plug.

18. The semiconductor device of claim 1, further comprising: Dielectric bonding structures located between adjacent source bonding structures.

19. The semiconductor device according to claim 18, wherein, The first contact bonding structure is located within the dielectric bonding structure.

20. The semiconductor device of claim 19, wherein, The first contact bonding structures are insulated from each other by the dielectric bonding structure.

21. The semiconductor device according to claim 1, wherein, The first contact engagement structure is arranged along a first direction and a second direction that intersects the first direction.

22. The semiconductor device according to claim 1, wherein, The source junction structure and the first contact junction structure are made of the same or substantially the same material.

23. The semiconductor device according to claim 22, wherein, The source junction structure and the first contact junction structure comprise polycrystalline silicon.

24. A method for manufacturing a semiconductor device, the method comprising the following steps: A first layer is formed on a first substrate; A first channel structure is formed that extends through the first stack and into the first substrate; Forming a first contact plug that extends through the first stack; Remove the first substrate; A first dielectric bonding layer is formed on the first stack; A first opening is formed to expose the first channel structure by partially removing the first dielectric bonding layer; A second opening is formed to expose the first contact plug by partially removing the first dielectric bonding layer; A first source junction pattern is formed in the first opening; as well as A first contact engagement pattern is formed in the second opening.

25. The method according to claim 24, wherein, The second opening is formed when the first opening is formed.

26. The method according to claim 24, wherein, The first contact bonding pattern is formed when the first source bonding pattern is formed.

27. The method according to claim 24, wherein, The steps for forming the first source junction pattern include the following steps: A conductive bonding layer is formed on the first channel structure to fill the first opening; Annealing the conductive bonding layer; and The conductive bonding layer is planarized by using the first dielectric bonding layer as a planarization barrier, and the first source bonding pattern is formed in the first opening.

28. The method of claim 24, further comprising the step of: A first unit wafer is formed, the first unit wafer including the first source bonding pattern, the first contact bonding pattern, the first dielectric bonding layer, the first contact plug and the first channel structure; A second unit wafer is formed, the second unit wafer including a second stack, a second gate structure, a second channel structure extending through the second gate structure, a second contact plug extending through the second stack, a second dielectric bonding layer formed on the second stack, a second source bonding pattern formed on the second gate structure, and a second contact bonding pattern formed on the second stack. as well as The first unit wafer and the second unit wafer are joined such that the first source bonding pattern and the second source bonding pattern are connected, the first contact bonding pattern and the second contact bonding pattern are connected, and the first dielectric bonding layer and the second dielectric bonding layer are connected.

29. The method according to claim 28, wherein, The second contact plug is electrically connected to the second contact engagement pattern, the first contact engagement pattern, and the first contact plug.

30. The method according to claim 28, wherein, The first stack comprises alternating layers of first and second materials, the first stack including a first stepped structure exposing the upper surface of each of the second material layers, and The method further includes forming first contact vias extending through the first stepped structure and each connected to the second material layer before removing the first substrate.

31. The method according to claim 30, wherein, The second stack comprises alternating layers of a third material layer and a fourth material layer, and the second stack includes a second stepped structure exposing the upper surface of each of the fourth material layers. The second unit wafer also includes second contact vias extending through the second step structure and each connected to the fourth material layer.

32. The method according to claim 31, wherein, The first unit wafer also includes a third contact bonding pattern formed at a layer corresponding to the first source bonding pattern. The second unit wafer further includes a fourth contact bonding pattern formed at a layer corresponding to the second source bonding pattern, and The second contact via is electrically connected to the third contact bonding pattern, the fourth contact bonding pattern, and the first contact via.

33. The method according to claim 28, wherein, The first stack comprises alternating layers of first and second materials, the first stack including a first stepped structure exposing the upper surface of each of the second material layers, and The method further includes forming first contact vias with different heights on the upper surface directly connected to each of the second material layers before removing the first substrate.

34. The method according to claim 33, wherein, The second stack comprises alternating layers of a third and a fourth material layer, the second stack including a second stepped structure exposing the upper surface of each of the fourth material layers, and The second unit wafer also includes a second contact via that is directly connected to the upper surface of each of the fourth material layers and has a different height.

35. The method according to claim 34, wherein, The first unit wafer further includes: a third stack formed at a layer corresponding to the first stack, a fifth contact bonding pattern formed at a layer corresponding to the first source bonding pattern, and a third contact plug extending through the third stack into the fifth contact bonding pattern. The second unit wafer further includes: a fourth stack formed at a layer corresponding to the second stack, a sixth contact bonding pattern formed at a layer corresponding to the second source bonding pattern, and a fourth contact plug extending through the fourth stack into the sixth contact bonding pattern. The second contact through hole is electrically connected to the fourth contact plug, the sixth contact engagement pattern, and the fifth contact engagement pattern.

36. The method according to claim 28, wherein, The first stack comprises alternating layers of first and second materials, and The method further includes the step of forming a first contact via extending through the first stack and connecting to the second material layer.

37. The method of claim 36, wherein, The second stack includes alternating layers of a third material layer and a fourth material layer, and The second unit wafer also includes a second contact via extending through the second stack and connected to the fourth material layer.

38. The method according to claim 37, wherein, The first unit wafer further includes: a third stack formed at a layer corresponding to the first stack, a fifth contact bonding pattern formed at a layer corresponding to the first source bonding pattern, and a third contact plug extending through the third stack into the fifth contact bonding pattern. The second unit wafer further includes: a fourth stack formed at a layer corresponding to the second stack, a sixth contact bonding pattern formed at a layer corresponding to the second source bonding pattern, and a fourth contact plug extending through the fourth stack into the sixth contact bonding pattern. The second contact through hole is electrically connected to the fourth contact plug, the sixth contact engagement pattern, and the fifth contact engagement pattern.

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