Semiconductor device and forming method

Abstract

The invention provides a semiconductor device and a forming method. The forming method comprises the following steps: providing an SOI (Silicon On Insulator); forming an active region and a shallow trench isolation structure which are adjacent to each other in the top layer silicon; forming a grid electrode on the surface of a part of the active region and respectively forming a source end and a drain end in the active region on two sides of the grid electrode; the connecting structure and the charge release structure are located in the first dielectric layer, the first dielectric layer exposes the surface of one end of the connecting structure, the other end of the connecting structure is connected with the grid, one end of the charge release structure is connected with the connecting structure, and the other end of the charge release structure penetrates through the shallow trench isolation structure to be connected with the bottom layer silicon. The connection structure comprises at least one metal layer and a contact hole, the metal layer passes through the contact hole and the grid electrode, the charge release structure comprises at least one metal layer and a contact hole, and the metal layer is connected with the bottom layer silicon through the contact hole; forming a second dielectric layer and a passivation layer on the surface of the connection structure; and etching a part of the passivation layer and the second dielectric layer to expose a part of the surface of the connection structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming it. Background Technology

[0002] In radio frequency (RF) front-end circuits, RF switches are essential components among semiconductor devices. Typically, RF switches are configured using a stack of multiple MOSFETs. These MOSFETs can be externally connected to other circuit structures via metal layers and contact holes; this type of semiconductor device is widely used.

[0003] Please refer to Figure 1 The prior art semiconductor device includes SOI comprising a bottom silicon 101, a buried oxide layer 102, and a top silicon layer stacked sequentially. An active region 103 and a shallow trench isolation structure 104 are located within the top silicon. A gate oxide layer 105 and a gate 106 are located on the surface of a portion of the active region 103, along with sidewalls 107 on both sides of the oxide layer 105 and the gate 106. A source terminal 108 and a drain terminal 109 are located within the active regions on both sides of the gate 106. A first oxide layer 110 is located on the surface of the gate 106, and a first contact hole 111 is located within the first oxide layer 110, the first contact hole 111 connecting to the gate 106. A second oxide layer 112 and a first metal layer 113 are located on the surfaces of the first oxide layer 110 and the first contact hole 111, the first metal layer 113 connecting to the first contact hole 111. The second oxide layer 112 exposes a portion of the surface of the first metal layer 113, thereby allowing the device containing the gate 106 to be connected to other external circuits through the first contact hole 111 and the first metal layer 113. The method for exposing the second oxide layer 112 to the first metal layer 113 involves first depositing the second oxide layer 112 and a passivation layer 114 to cover the first metal layer 113, and then etching a portion of the passivation layer 114 and the second oxide layer 112 to expose a portion of the first metal layer 113.

[0004] However, in the methods of forming existing semiconductor devices, etching the passivation layer 114 generates ionization charge, which degrades the performance and reliability of the semiconductor device. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device and a method for forming it, which can reduce the ionization charge generated by etching the passivation layer, thereby improving the performance and reliability of the semiconductor device.

[0006] To achieve the above objectives, the present invention provides a method for forming a semiconductor device, comprising:

[0007] SOI is provided, which consists of a bottom silicon layer, a buried oxide layer and a top silicon layer stacked sequentially.

[0008] Adjacent active regions and shallow trench isolation structures are formed within the top silicon layer;

[0009] A gate is formed on the surface of a portion of the active region, and a source terminal and a drain terminal are formed in the active regions on both sides of the gate, respectively.

[0010] A first dielectric layer and a connection structure and a charge release structure are formed on the surface of the gate. The first dielectric layer exposes the surface of one end of the connection structure. The other end of the connection structure is connected to the gate. One end of the charge release structure is connected to the connection structure, and the other end of the charge release structure passes through the shallow trench isolation structure and is connected to the underlying silicon. The connection structure includes at least one metal layer and a contact hole. The metal layer is connected to the gate through the contact hole. The charge release structure includes at least one metal layer and a contact hole. The metal layer is connected to the underlying silicon through the contact hole.

[0011] A second dielectric layer and a passivation layer are formed on the surface of the connection structure;

[0012] The passivation layer and the second dielectric layer are etched to expose the surface of the connection structure.

[0013] Optionally, in the method for forming the semiconductor device, after etching a portion of the passivation layer and the second dielectric layer to expose a portion of the surface of the connection structure, the method further includes: laser cutting a portion of the second dielectric layer, the third oxide layer, and the second metal layer, thereby severing the connection between the connection structure and the charge release structure.

[0014] Optionally, in the method for forming the semiconductor device, the method for forming adjacent active regions and shallow trench isolation structures within the top silicon layer includes:

[0015] Ions are implanted into the top silicon layer to form an active region;

[0016] The active region is etched to form multiple spaced shallow trenches within the active region;

[0017] An oxide layer is filled into the shallow trench to form a shallow trench isolation structure.

[0018] Optionally, the method for forming the semiconductor device further includes: forming a gate oxide layer on the surface of the active region, the gate oxide layer being located between the active region and the gate.

[0019] Optionally, the method for forming the semiconductor device further includes forming sidewalls on both sides of the gate and the gate oxide layer.

[0020] Optionally, in the method for forming the semiconductor device, the first dielectric layer includes multiple oxide layers stacked together.

[0021] Optionally, in the method of forming the semiconductor device, forming a first dielectric layer and a connection structure and a charge release structure within the first dielectric layer on the surface of the gate, wherein the first dielectric layer exposes the surface of one end of the connection structure, the other end of the connection structure is connected to the gate, one end of the charge release structure is connected to the connection structure, and the other end of the charge release structure passes through the shallow trench isolation structure and is connected to the underlying silicon, the method comprising:

[0022] A first oxide layer is formed on the surface of the gate, the surface of the active region, and the surface of the shallow trench isolation structure;

[0023] Two types of first contact holes are formed in the first oxide layer at intervals. One type of first contact hole passes through the first oxide layer and is connected to the gate. The other type of first contact hole passes through the first oxide layer, the shallow trench isolation structure and the buried oxide layer and is connected to the underlying silicon.

[0024] Two types of first metal layers are formed at intervals on the surface of the first oxide layer, and are respectively connected to the two types of first contact holes;

[0025] A second oxide layer is formed on the surface of the first oxide layer and the surface of the first metal layer;

[0026] Two types of second contact holes are formed in the second oxide layer at intervals, and the two types of second contact holes pass through the second oxide layer and are respectively connected to the two types of first metal layers;

[0027] A second metal layer is formed on the surface of the second oxide layer, and the second metal layer connects the two types of second contact holes;

[0028] A third oxide layer is formed on the surface of the second oxide layer and the second metal layer;

[0029] A third contact hole is formed within the third oxide layer, and the third contact hole connects to the second metal layer;

[0030] A third metal layer is formed on the surface of the third oxide layer.

[0031] Optionally, in the method for forming the semiconductor device, the passivation layer includes a nitride layer.

[0032] Optionally, in the method for forming the semiconductor device, a portion of the passivation layer and the second dielectric layer is dry-etched to expose a portion of the surface of the interconnect structure.

[0033] The present invention also provides a semiconductor device, comprising:

[0034] SOI consists of a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially.

[0035] An active region and a shallow trench isolation structure located within and adjacent to the top silicon layer;

[0036] The gate located on the surface of a portion of the active region, and the source and drain terminals within the active regions on both sides of the gate;

[0037] A first dielectric layer is located on the surface of the gate, and a connection structure and a charge release structure are located within the first dielectric layer. The surface of the first dielectric layer exposes one end of the connection structure, and the other end of the connection structure is connected to the gate. One end of the charge release structure is connected to the connection structure, and the other end of the charge release structure passes through the shallow trench isolation structure and is connected to the underlying silicon. The connection structure includes at least one metal layer and a contact hole. The metal layer is connected to the gate through the contact hole. The charge release structure includes at least one metal layer and a contact hole. The metal layer is connected to the underlying silicon through the contact hole.

[0038] A second dielectric layer is located on the surface of the connection structure, and the second dielectric layer exposes a portion of the surface of the connection structure.

[0039] The semiconductor device and its formation method provided by the present invention include: providing an SOI, the SOI comprising a bottom silicon, a buried oxide layer and a top silicon stacked sequentially; forming adjacent active regions and shallow trench isolation structures within the top silicon; forming a gate on the surface of a portion of the active regions and forming a source terminal and a drain terminal in the active regions on both sides of the gate, respectively; forming a first dielectric layer and a connection structure and a charge release structure within the first dielectric layer on the surface of the gate, the first dielectric layer exposing the surface of one end of the connection structure, the other end of the connection structure being connected to the gate, one end of the charge release structure being connected to the connection structure, and the other end of the charge release structure passing through the shallow trench isolation structure and being connected to the bottom silicon, wherein the connection structure includes at least one metal layer and a contact hole, the metal layer being connected to the gate through the contact hole, and the charge release structure includes at least one metal layer and a contact hole, the metal layer being connected to the bottom silicon through the contact hole; forming a second dielectric layer and a passivation layer on the surface of the connection structure; etching a portion of the passivation layer and the second dielectric layer to expose a portion of the surface of the connection structure. This invention adds a charge release structure that can release ionized charge to the ground through the underlying silicon, thereby reducing the ionized charge generated by etching the passivation layer and improving the performance and reliability of semiconductor devices. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a semiconductor device in the prior art;

[0041] Figure 2 This is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0042] Figures 3 to 5 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0043] In the diagram: 101-bottom silicon, 102-buried oxide layer, 103-active region, 104-shallow trench isolation structure, 105-gate oxide layer, 106-gate, 107-sidewall, 108-source terminal, 109-drain terminal, 110-first oxide layer, 111-first contact hole, 112-second oxide layer, 113-first metal layer, 114-passivation layer, 201-bottom silicon, 202-buried oxide layer, 203-top silicon, 204-active region, 20 5-Shallow trench isolation structure, 206-Gate oxide layer, 207-Gate, 208-Sidewall, 209-Source terminal, 210-Drain terminal, 211-First oxide layer, 212-First contact hole, 213-First metal layer, 214-Second oxide layer, 215-Second contact hole, 216-Second metal layer, 217-Third oxide layer, 218-Third contact hole, 219-Third metal layer, 220-Second dielectric layer, 221-Passivation layer. Detailed Implementation

[0044] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0045] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.

[0046] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0047] Please refer to Figure 2 The present invention provides a method for forming a semiconductor device, comprising:

[0048] S11: Provides SOI, which consists of a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially.

[0049] S12: Form adjacent active regions and shallow trench isolation structures within the top silicon layer;

[0050] S13: A gate is formed on the surface of a portion of the active region, and a source terminal and a drain terminal are formed in the active regions on both sides of the gate, respectively.

[0051] S14: A first dielectric layer and a connection structure and a charge release structure located within the first dielectric layer are formed on the surface of the gate. The surface of one end of the first dielectric layer is exposed, and the other end of the connection structure is connected to the gate. One end of the charge release structure is connected to the connection structure, and the other end of the charge release structure passes through a shallow trench isolation structure and is connected to the underlying silicon. The connection structure includes at least one metal layer and a contact hole. The metal layer is connected to the gate through the contact hole. The charge release structure includes at least one metal layer and a contact hole. The metal layer is connected to the underlying silicon through the contact hole.

[0052] S15: A second dielectric layer and a passivation layer are formed on the surface of the connection structure;

[0053] S16: Etch part of the passivation layer and the second dielectric layer to expose the surface of part of the connection structure.

[0054] Please refer to Figure 3 First, SOI is provided, which consists of a bottom silicon 201, a buried oxide layer 202 and a top silicon 203 stacked in sequence.

[0055] Next, please refer to the following: Figure 4 Ions are implanted into the top silicon layer 203 to form an active region 204. The active region 204 is etched to form multiple spaced shallow trenches within it. An oxide layer is then filled into the shallow trenches to form a shallow trench isolation structure 205. This results in the formation of adjacent active regions 204 and shallow trench isolation structures 205 within the top silicon layer.

[0056] Next, a gate oxide layer 206 is formed on the surface of a portion of the active region 204, and a gate 207 is formed on the surface of the gate oxide layer 206. Sidewalls 208 are formed on both sides of the gate 207 and the gate oxide layer 206. Then, a source terminal 209 and a drain terminal 210 are formed in the active regions 204 on both sides of the gate 207, respectively.

[0057] Next, a first oxide layer 211 is formed on the surface of the gate 207, the surface of the active region 204, and the surface of the shallow trench isolation structure 205. Two types of first contact holes 212 are formed spaced apart within the first oxide layer 211. One type of first contact hole 212 passes through the first oxide layer 211 and connects to the gate 207, while the other type of first contact hole 212 passes through the first oxide layer 211, the shallow trench isolation structure 205, and the buried oxide layer 202 and connects to the underlying silicon 201. Two types of first metal layers 213 are formed spaced apart on the surface of the first oxide layer 211, respectively connecting the two types of first contact holes 212. The first oxide layer 211 and the first metal layer 213 are then connected. A second oxide layer 214 is formed on the surface of the first metal layer 213. Two types of second contact holes 215 are formed in the second oxide layer 214 at intervals, and the two types of second contact holes 215 pass through the second oxide layer 214 and are respectively connected to the two types of first metal layers 213. A second metal layer 216 is formed on the surface of the second oxide layer 214, and the second metal layer 216 connects the two types of second contact holes 215. A third oxide layer 217 is formed on the surface of the second oxide layer 214 and the second metal layer 216. A third contact hole 218 is formed in the third oxide layer 217, and the third contact hole 218 connects to the second metal layer 215. A third metal layer 219 is formed on the surface of the third oxide layer 217. The method of forming the contact hole includes first forming a through hole, and then filling the through hole with metal to form a contact hole. The specific method is not described in detail. The first oxide layer to the third oxide layer of the present invention constitute the first dielectric layer. The present invention has a connection structure in which one end is connected to the gate and the other end can be connected to an external circuit, and a connection structure in which one end is connected to the bottom silicon, and a charge release structure in which the contact hole and the metal layer are connected. The first dielectric layer exposes the surface of one end of the connection structure, and the other end of the connection structure is connected to the gate. One end of the charge release structure is connected to the connection structure, and the other end of the charge release structure passes through the shallow trench isolation structure and is connected to the underlying silicon, thereby grounding the ionized charge generated in the connection structure through the underlying silicon 201. In other embodiments of the invention, the connection structure may also be connected to the source 209 or the drain 210. In other embodiments of the invention, the connection structure and the charge release structure may not be connected by the second metal layer 216, but by the third metal layer or the first metal layer. That is, the connection structure and the charge release structure are connected by the first metal layer, the second metal layer, and / or the third metal layer. In other embodiments of the invention, other numbers of metal layers may also be used, such as two metal layers or four metal layers. In summary, the connection structure includes at least one metal layer and a contact hole, with the metal layer connected to the gate through the contact hole. The charge release structure includes at least one metal layer and a contact hole, with the metal layer connected to the underlying silicon through the contact hole.

[0058] Next, a second dielectric layer 220 and a passivation layer 221 are sequentially formed on the surface of the connection structure. The second dielectric layer 220 can be an oxide layer, and the passivation layer 221 can be a nitride layer. Then, a portion of the passivation layer 221 and the second dielectric layer 220 is etched to expose a portion of the surface of the connection structure; in this embodiment, this exposes the surface of the third metal layer 219. The exposed third metal layer 219 can serve as a pad for connecting to other external circuits. In semiconductor device fabrication, the underlying silicon 201 is generally grounded; therefore, in this embodiment, the ionized charge generated during the etching of the passivation layer 221 is released to ground through the charge release structure via the underlying silicon 201.

[0059] The present invention also provides a semiconductor device, comprising: SOI, the SOI comprising a bottom silicon, a buried oxide layer and a top silicon stacked sequentially; an active region and a shallow trench isolation structure disposed adjacent to each other within the top silicon; a gate located on the surface of a portion of the active region and a source terminal and a drain terminal in the active regions on both sides of the gate; a first dielectric layer located on the surface of the gate and a connection structure and a charge release structure located within the first dielectric layer, the first dielectric layer exposing the surface of one end of the connection structure, the other end of the connection structure being connected to the gate, one end of the charge release structure being connected to the connection structure, and the other end of the charge release structure passing through the shallow trench isolation structure and being connected to the bottom silicon, wherein the connection structure includes at least one metal layer and a contact hole, the metal layer being connected to the gate through the contact hole, and the charge release structure includes at least one metal layer and a contact hole, the metal layer being connected to the bottom silicon through the contact hole; a second dielectric layer located on the surface of the connection structure, the second dielectric layer exposing a portion of the surface of the connection structure.

[0060] Once a semiconductor product is manufactured and intended for use elsewhere, the connections between the interconnecting and charge-discharge structures can be directly severed to ensure the proper functioning of the semiconductor device. For details, please refer to... Figure 5 Laser cutting can be used to cut the second dielectric layer 220, the third oxide layer 217, and the second metal layer 216, thereby severing the connection between the connection structure and the charge release structure.

[0061] In summary, the semiconductor device and formation method provided in the embodiments of the present invention include: providing SOI, the SOI including a bottom silicon, a buried oxide layer and a top silicon stacked sequentially; forming adjacent active regions and shallow trench isolation structures in the top silicon; forming a gate on the surface of a portion of the active regions and forming a source terminal and a drain terminal in the active regions on both sides of the gate, respectively; forming a first dielectric layer and a connection structure and a charge release structure located in the first dielectric layer on the surface of the gate, the first dielectric layer exposing the surface of one end of the connection structure, the other end of the connection structure being connected to the gate, one end of the charge release structure being connected to the connection structure, and the other end of the charge release structure passing through the shallow trench isolation structure and being connected to the bottom silicon, wherein the connection structure includes at least one metal layer and a contact hole, the metal layer being connected to the gate through the contact hole, and the charge release structure including at least one metal layer and a contact hole, the metal layer being connected to the bottom silicon through the contact hole; forming a second dielectric layer and a passivation layer on the surface of the connection structure; etching a portion of the passivation layer and the second dielectric layer to expose a portion of the surface of the connection structure. This invention adds a charge release structure that can release ionized charge to the ground through the underlying silicon, thereby reducing the ionized charge generated by etching the passivation layer and improving the performance and reliability of semiconductor devices.

[0062] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that, include: SOI is provided, which consists of a bottom silicon layer, a buried oxide layer and a top silicon layer stacked sequentially. Adjacent active regions and shallow trench isolation structures are formed within the top silicon layer; A gate is formed on the surface of a portion of the active region, and a source terminal and a drain terminal are formed in the active regions on both sides of the gate, respectively. A first dielectric layer and a connection structure and a charge release structure are formed on the surface of the gate. The first dielectric layer exposes the surface of one end of the connection structure. The other end of the connection structure is connected to the gate. One end of the charge release structure is connected to the connection structure, and the other end of the charge release structure passes through the shallow trench isolation structure and is connected to the underlying silicon. The connection structure includes at least one metal layer and a contact hole. The metal layer is connected to the gate through the contact hole. The charge release structure includes at least one metal layer and a contact hole. The metal layer is connected to the underlying silicon through the contact hole. A second dielectric layer and a passivation layer are formed on the surface of the connection structure; The passivation layer and the second dielectric layer are etched to expose the surface of the connection structure.

2. The method for forming a semiconductor device as described in claim 1, characterized in that, After etching portions of the passivation layer and the second dielectric layer to expose the surface of a portion of the connection structure, the process further includes: laser cutting portions of the second dielectric layer, the third oxide layer, and the second metal layer to sever the connection between the connection structure and the charge release structure.

3. The method for forming a semiconductor device as described in claim 1, characterized in that, A method for forming adjacent active regions and shallow trench isolation structures within the top silicon layer includes: Ions are implanted into the top silicon layer to form an active region; The active region is etched to form multiple spaced shallow trenches within the active region; An oxide layer is filled into the shallow trench to form a shallow trench isolation structure.

4. The method for forming a semiconductor device as described in claim 1, characterized in that, Also includes: A gate oxide layer is formed on the surface of the active region, the gate oxide layer being located between the active region and the gate.

5. The method for forming a semiconductor device as described in claim 4, characterized in that, Also includes: Sidewalls are formed on both sides of the gate and the gate oxide layer.

6. The method for forming a semiconductor device as described in claim 1, characterized in that, The first dielectric layer includes multiple oxide layers stacked together.

7. The method for forming a semiconductor device as described in claim 1, characterized in that, A method for forming a first dielectric layer and a connection structure and a charge release structure within the first dielectric layer on the surface of the gate, wherein the first dielectric layer exposes the surface of one end of the connection structure, the other end of the connection structure is connected to the gate, one end of the charge release structure is connected to the connection structure, and the other end of the charge release structure passes through the shallow trench isolation structure and is connected to the underlying silicon includes: A first oxide layer is formed on the surface of the gate, the surface of the active region, and the surface of the shallow trench isolation structure; Two types of first contact holes are formed in the first oxide layer at intervals. One type of first contact hole passes through the first oxide layer and is connected to the gate. The other type of first contact hole passes through the first oxide layer, the shallow trench isolation structure and the buried oxide layer and is connected to the underlying silicon. Two types of first metal layers are formed at intervals on the surface of the first oxide layer, and are respectively connected to the two types of first contact holes; A second oxide layer is formed on the surface of the first oxide layer and the surface of the first metal layer; Two types of second contact holes are formed in the second oxide layer at intervals, and the two types of second contact holes pass through the second oxide layer and are respectively connected to the two types of first metal layers; A second metal layer is formed on the surface of the second oxide layer, and the second metal layer connects the two types of second contact holes; A third oxide layer is formed on the surface of the second oxide layer and the second metal layer; A third contact hole is formed within the third oxide layer, and the third contact hole connects to the second metal layer; A third metal layer is formed on the surface of the third oxide layer.

8. The method for forming a semiconductor device as described in claim 1, characterized in that, The passivation layer includes a nitrided layer.

9. The method for forming a semiconductor device as claimed in claim 1, characterized in that, Dry etching is used to partially etch the passivation layer and the second dielectric layer to expose the surface of a portion of the connection structure.

10. A semiconductor device formed using the method for forming a semiconductor device according to any one of claims 1 to 9, characterized in that, include: SOI consists of a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially. An active region and a shallow trench isolation structure located within and adjacent to the top silicon layer; The gate located on the surface of a portion of the active region, and the source and drain terminals within the active regions on both sides of the gate; A first dielectric layer is located on the surface of the gate, and a connection structure and a charge release structure are located within the first dielectric layer. The surface of the first dielectric layer exposes one end of the connection structure, and the other end of the connection structure is connected to the gate. One end of the charge release structure is connected to the connection structure, and the other end of the charge release structure passes through the shallow trench isolation structure and is connected to the underlying silicon. The connection structure includes at least one metal layer and a contact hole. The metal layer is connected to the gate through the contact hole. The charge release structure includes at least one metal layer and a contact hole. The metal layer is connected to the underlying silicon through the contact hole. A second dielectric layer is located on the surface of the connection structure, and the second dielectric layer exposes a portion of the surface of the connection structure.

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