High electron mobility transistor and method for manufacturing high electron mobility transistor

Abstract

The invention provides a high electron mobility transistor capable of reducing gate leakage and a manufacturing method of the high electron mobility transistor. The high electron mobility transistor includes: a substrate; a semiconductor laminate provided on the substrate; and a gate electrode in Schottky contact with the semiconductor laminate, the gate electrode having: a first metal layer in direct contact with the semiconductor laminate; and a second metal layer covering the first metal layer, the first metal layer containing at least one selected from the group consisting of cobalt and ruthenium in an amorphous state.

Description

Technical Field

[0001] This disclosure relates to high electron mobility transistors and methods for manufacturing high electron mobility transistors. Background Technology

[0002] As the gate electrode of a high electron mobility transistor (HEMT), a laminated film of nickel, platinum and gold layers has been proposed (Patent Document 1, Patent Document 2).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-145605

[0006] Patent Document 2: Japanese Patent Application Publication No. 2021-044357

[0007] Although the desired objectives have been achieved by the technologies described in Patent Documents 1 and 2, the demand for further reduction of gate leakage has increased in recent years. Summary of the Invention

[0008] The purpose of this disclosure is to provide a high electron mobility transistor that can reduce gate leakage and a method for manufacturing a high electron mobility transistor.

[0009] The high electron mobility transistor disclosed herein has: a substrate; a semiconductor stack disposed on the substrate; and a gate electrode in Schottky contact with the semiconductor stack, the gate electrode having: a first metal layer in direct contact with the semiconductor stack; and a second metal layer covering the first metal layer, the first metal layer comprising at least one selected from the group consisting of cobalt and ruthenium in an amorphous state.

[0010] Invention Effects

[0011] According to this disclosure, gate leakage can be reduced. Attached Figure Description

[0012] Figure 1 This is a cross-sectional view showing the high electron mobility transistor of the first embodiment.

[0013] Figure 2 This is a cross-sectional view (one of the first embodiments) showing a method for manufacturing a high electron mobility transistor.

[0014] Figure 3 This is a cross-sectional view (second one) showing a method for manufacturing a high electron mobility transistor according to the first embodiment.

[0015] Figure 4 This is a cross-sectional view (third one) showing a method for manufacturing a high electron mobility transistor according to the first embodiment.

[0016] Figure 5 This is a cross-sectional view (one of the methods for forming the gate electrode).

[0017] Figure 6 This is a cross-sectional view (second one) showing the method of forming the gate electrode.

[0018] Figure 7 This is a cross-sectional view (third one) showing the method of forming the gate electrode.

[0019] Figure 8 This is a diagram illustrating an example of temperature changes during the formation of the gate electrode.

[0020] Figure 9 This is a graph showing other examples of temperature changes during the formation of the gate electrode.

[0021] Figure 10 This is a cross-sectional view showing the high electron mobility transistor of the second embodiment.

[0022] Figure 11 This is a diagram (one of) showing an electron beam diffraction pattern.

[0023] Figure 12 This is a diagram (the second one) showing an electron beam diffraction pattern.

[0024] Figure 13 This is a diagram representing an electron beam diffraction pattern (Part Three).

[0025] Explanation of reference numerals in the attached figures

[0026] 44D: Drain electrode; 44S: Source electrode; 50: Gate electrode; 51: First metal layer; 52: Second metal layer; 53: Third metal layer; 100, 200: High electron mobility transistor; 110, 210: Substrate; 120, 220: Semiconductor stack; 120A: Surface; 122, 222: Buffer layer; 124, 224: Channel layer; 126, 226: Barrier layer; 128, 228: Cap layer; 130, 230: Insulating film; 130D, 130G, 130S, 230D, 230G, 230S: Opening; 140D, 140S, 240D, 240S: Recess; 142D, 142S, 242D, 242S: Regenerated layer; 155: Two-dimensional electron gas; t1: Dimension. Detailed Implementation

[0027] [Description of embodiments of this disclosure]

[0028] First, the implementation plan disclosed herein will be listed for explanation.

[0029] [1] A high electron mobility transistor of one aspect of the present disclosure has: a substrate; a semiconductor stack disposed on the substrate; and a gate electrode in Schottky contact with the semiconductor stack, the gate electrode having: a first metal layer in direct contact with the semiconductor stack; and a second metal layer covering the first metal layer, the first metal layer comprising at least one selected from the group consisting of cobalt and ruthenium in an amorphous state.

[0030] The gate electrode comprises at least one element selected from the group consisting of amorphous cobalt and ruthenium as the first metal layer. Such a first metal layer is less prone to gate leakage. Therefore, gate leakage can be reduced.

[0031] [2] In [1], the resistance of the second metal layer may also be lower than that of the first metal layer. In this case, it is easier to suppress the resistance of the gate electrode to be low.

[0032] [3] In [1] or [2], the first metal layer may also contain hydrogen atoms, carbon atoms, nitrogen atoms, and oxygen atoms. In this case, it is easier to make the first metal layer amorphous.

[0033] [4] In any of [1] to [3], the second metal layer may also comprise at least one material selected from the group consisting of gold, copper, and aluminum. In this case, it is easy to suppress the resistance of the second metal layer to a low level.

[0034] [5] In any of [1] to [4], the thickness of the first metal layer may be 3 nm or more and 50 nm or less. In this case, it is easy to reduce gate leakage while suppressing the resistance of the gate electrode.

[0035] [6] In any of [1] to [5], the gate electrode may also have a third metal layer located between the first metal layer and the second metal layer. In this case, good adhesion can be obtained between the first metal layer and the second metal layer.

[0036] [7] In [6], the third metal layer may also comprise titanium. In this case, good adhesion is easily achieved between the first metal layer and the second metal layer.

[0037] [8] In any of [1] to [7], the semiconductor stack may also have: a channel layer; and a barrier layer located between the channel layer and the gate electrode, the gate electrode being in direct contact with the barrier layer. In this case, excellent crystallinity is readily obtained in the channel layer and the barrier layer.

[0038] [9] In any of [1] to [7], the semiconductor stack may also have: a channel layer; a barrier layer located between the channel layer and the gate electrode; and a cap layer located between the barrier layer and the gate electrode, the gate electrode being in direct contact with the cap layer. In this case, excellent crystallinity is readily obtained in the channel layer, barrier layer, and cap layer, which facilitates the reduction of electron trapping.

[0039]

[10] In any of [1] to [7], the semiconductor stack may also have: a barrier layer; and a channel layer located between the barrier layer and the gate electrode, the gate electrode being in direct contact with the channel layer. In this case, it is easy to suppress the contact resistance between the source electrode and the drain electrode and the semiconductor stack to be low.

[0040]

[11] In any of [1] to [7], the semiconductor stack may also have: a barrier layer; a channel layer located between the barrier layer and the gate electrode; and a cap layer located between the channel layer and the gate electrode, the gate electrode being in direct contact with the cap layer. In this case, it is easy to suppress the contact resistance between the source electrode and the drain electrode and the semiconductor stack to be low, and it is easy to reduce electron trapping.

[0041]

[12] In any of [1] to

[11] , it may also include: an insulating film covering the semiconductor stack, with an opening formed in the insulating film, through which the gate electrode makes Schottky contact with the semiconductor stack. In this case, the semiconductor stack can be protected by the insulating film.

[0042]

[13] Another aspect of the present disclosure describes a method for manufacturing a high electron mobility transistor, comprising the steps of: forming a semiconductor stack on a substrate; and forming a gate electrode in Schottky contact with the semiconductor stack, wherein the step of forming the gate electrode comprises the steps of: forming a first metal layer in direct contact with the semiconductor stack by atomic layer deposition; and forming a second metal layer covering the first metal layer, wherein the first metal layer comprises at least one selected from the group consisting of cobalt and ruthenium in an amorphous state.

[0043] A first metal layer comprising at least one element selected from the group consisting of cobalt and ruthenium is formed by atomic layer deposition, thus facilitating the formation of an amorphous state in the first metal layer. Such a first metal layer is less prone to gate leakage. Therefore, gate leakage can be reduced.

[0044]

[14] In

[13] , the raw material for the first metal layer may also include at least one selected from the group consisting of bis(diisopropylbutanemidyl)cobalt and bis(diisopropylbutanemidyl)ruthenium. In this case, an amorphous first metal layer is readily formed.

[0045]

[15] In

[14] , it is also possible that, in the process of forming the first metal layer, the raw material and at least one selected from the group consisting of hydrogen and ammonia are supplied into the furnace. In this case, it is particularly easy to form an amorphous first metal layer.

[0046]

[16] In any of

[13] to

[15] , the process of forming the gate electrode may also include, prior to the process of forming the first metal layer, a reduction treatment at a first temperature that decomposes the native oxide film on the surface of the semiconductor stack, wherein the first metal layer is formed at a second temperature lower than the first temperature. In this case, good Schottky characteristics are readily obtained between the gate electrode and the semiconductor stack.

[0047]

[17] In

[16] , the reduction process and the formation of the first metal layer may also be carried out in the same furnace without being exposed to the atmosphere. In this case, a particularly high degree of cleanliness can be easily obtained on the surface of the semiconductor laminate.

[0048]

[18] In

[17] , the reduction process and the formation of the first metal layer may also be carried out in separate furnaces that are not open to the atmosphere. In this case, the temperatures in the furnaces for the reduction process and the formation of the first metal layer are controlled independently, making it easier to achieve high production capacity.

[0049]

[19] In any of

[16] to

[18] , hydrogen and ammonia may also be used in the reduction process. In this case, oxygen atoms are removed from the native oxide film by hydrogen, and nitrogen deficiency in the semiconductor stack is compensated by ammonia.

[0050] [Details of the embodiments of this disclosure]

[0051] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited to these embodiments. It should be noted that in this specification and drawings, sometimes repeated descriptions are omitted by referring to constituent elements that have substantially the same functional configuration with the same reference numerals.

[0052] (First Implementation)

[0053] The first embodiment will be described. The first embodiment relates to a high electron mobility transistor (HEMT). Figure 1 This is a cross-sectional view showing the high electron mobility transistor of the first embodiment.

[0054] like Figure 1As shown, the high electron mobility transistor 100 of the first embodiment has a substrate 110, a semiconductor stack 120, an insulating film 130, a gate electrode 50, a source electrode 44S, and a drain electrode 44D.

[0055] The substrate 110 is, for example, a substrate for growing a gallium nitride (GaN) semiconductor layer, such as a semi-insulating silicon carbide (SiC) substrate. When the substrate 110 is a SiC substrate, its upper surface is a silicon (Si) polar surface. When the surface of the substrate 110 is a Si polar surface, the semiconductor stack 120 grows crystals using the gallium (Ga) polar surface as the growth surface.

[0056] The semiconductor stack 120 has a buffer layer 122, a channel layer 124, a barrier layer 126, a cap layer 128, a regeneration layer 142S, and a regeneration layer 142D.

[0057] A buffer layer 122 is located above the substrate 110. The buffer layer 122 is, for example, an aluminum nitride (AlN) layer. The buffer layer 122 may also have an AlN layer and a GaN layer or an aluminum gallium nitride (AlGaN) layer above the AlN layer. A channel layer 124 is located above the buffer layer 122. The channel layer 124 is, for example, an undoped gallium nitride (GaN) layer. A barrier layer 126 is located above the channel layer 124. The barrier layer 126 is, for example, an n-type AlGaN layer. A two-dimensional electron gas (2DEG) 155 exists near the upper surface of the channel layer 124. A cap layer 128 is located above the barrier layer 126. The cap layer 128 is, for example, an n-type GaN layer.

[0058] A recess 140S for the active electrode and a recess 140D for the drain electrode are formed in a portion of the cap layer 128, the barrier layer 126, and the channel layer 124. Recesses 140S and 140D penetrate the cap layer 128 and the barrier layer 126 and enter the channel layer 124. The channel layer 124 is exposed from the recesses 140S and 140D.

[0059] An insulating film 130 is located above the cap layer 128. The insulating film 130 is, for example, a silicon nitride (SiN) film. The thickness of the insulating film 130 is, for example, 1 nm or more and 10 nm or less. An opening 130S for the active electrode and an opening 130D for the drain electrode are formed on the insulating film 130. The opening 130S is connected to the recess 140S, and the opening 130D is connected to the recess 140D.

[0060] The regenerated layer 142S lies above the channel layer 124 within the recess 140S and the opening 130S. The regenerated layer 142D lies above the channel layer 124 within the recess 140D and the opening 130D. The regenerated layers 142S and 142D are, for example, n-type GaN layers. The resistivity of the regenerated layers 142S and 142D is lower than that of the channel layer 124.

[0061] The source electrode 44S is located on the regenerated layer 142S, and the drain electrode 44D is located on the regenerated layer 142D. The source electrode 44S is in direct contact with the regenerated layer 142S, and the drain electrode 44D is in direct contact with the regenerated layer 142D. The source electrode 44S is in ohmic contact with the regenerated layer 142S, and the drain electrode 44D is in ohmic contact with the regenerated layer 142D.

[0062] An opening 130G for a gate is formed in the insulating film 130. The opening 130G is located between the openings 130S and 130D. The gate electrode 50 is disposed on the insulating film 130 and makes a Schottky contact with the semiconductor stack 120 via the opening 130G.

[0063] The gate electrode 50 has a first metal layer 51, a second metal layer 52, and a third metal layer 53. The first metal layer 51 is in direct contact with the semiconductor stack 120. The second metal layer 52 covers the first metal layer 51. The third metal layer 53 is located between the first metal layer 51 and the second metal layer 52. The first metal layer 51 is, for example, an amorphous cobalt (Co) layer. The thickness of the first metal layer 51 is, for example, 3 nm or more and 50 nm or less. The resistance of the second metal layer 52 is lower than that of the first metal layer 51. The second metal layer is, for example, a gold (Au) layer. The thickness of the second metal layer 52 is, for example, 300 nm or more and 1000 nm or less. The third metal layer 53 improves the adhesion between the first metal layer 51 and the second metal layer 52. The third metal layer 53 is, for example, a titanium (Ti) layer. The thickness of the third metal layer 53 is, for example, 2 nm or more and 20 nm or less.

[0064] Next, the manufacturing method of the high electron mobility transistor 100 of the first embodiment will be described. Figures 2 to 4 This is a cross-sectional view showing a method for manufacturing the high electron mobility transistor 100 according to the first embodiment.

[0065] First, such as Figure 2As shown, a buffer layer 122, a channel layer 124, a barrier layer 126, and a cap layer 128 are formed on the substrate 110. The buffer layer 122, channel layer 124, barrier layer 126, and cap layer 128 can be formed, for example, by metal-organic chemical vapor deposition (MOCVD). Next, an insulating film 130 is formed on the cap layer 128. The insulating film 130 can be formed, for example, by CVD.

[0066] Next, openings 130S and 130D are formed in the insulating film 130, and recesses 140S and 140D are formed in a portion of the cap layer 128, the barrier layer 126, and the channel layer 124. Openings 130S and 130D can be formed, for example, by reactive ion etching (RIE) using a reactive gas containing fluorine (F). Recesses 140S and 140D can be formed, for example, by RIE using a reactive gas containing chlorine (Cl). Next, a regenerated layer 142S is formed within the recesses 140S and openings 130S, and a regenerated layer 142D is formed within the recesses 140D and openings 130D. Regenerated layers 142S and 142D can be formed, for example, by MOCVD, molecular beam epitaxy (MBE), or sputtering. In this way, a semiconductor laminate 120 can be obtained.

[0067] Next, as Figure 3 As shown, a source electrode 44S is formed on the regenerated layer 142S, and a drain electrode 44D is formed on the regenerated layer 142D. The source electrode 44S and the drain electrode 44D can be formed, for example, by vapor deposition and stripping.

[0068] Next, as Figure 4 As shown, an opening 130G is formed in the insulating film 130. The opening 130G can be formed, for example, by using a reactive gas containing fluorine (F) in an RIE. Next, a gate electrode 50 is formed on the insulating film 130, which makes a Schottky contact with the semiconductor stack 120 via the opening 130G.

[0069] Here, the method for forming the gate electrode 50 will be described in detail. Figures 5 to 7 This is a cross-sectional view showing the method of forming the gate electrode 50.

[0070] First, such as Figure 5As shown, a first metal layer 51 is formed on the insulating film 130, the inner wall surface of the opening 130G, and the portion of the semiconductor stack 120 exposed from the opening 130G by atomic layer deposition (ALD). When forming a Co layer as the first metal layer 51, bis(diisopropylbutanemidinate)cobalt is supplied to the ALD furnace as a raw material for Co. Furthermore, for the decomposition of the Co raw material, at least one gas selected from the group consisting of hydrogen (H2) and ammonia (NH3) is supplied to the ALD furnace. Nitrogen (N2) or argon (Ar), as inert gases, can also be used as the carrier gas.

[0071] When forming the first metal layer 51, such as Figure 8 As shown, for example, the temperature inside the ALD furnace is raised from room temperature to 200°C, and the first metal layer 51 is formed at 200°C. Then, after the first metal layer 51 is formed, the temperature inside the ALD furnace is lowered to room temperature. Figure 8 This is a diagram showing an example of temperature change during the formation of the gate electrode 50.

[0072] Next, as Figure 6 As shown, a second metal layer 52 and a third metal layer 53 are formed on top of a first metal layer 51. The second metal layer 52 and the third metal layer 53 can be formed, for example, by vapor deposition and stripping.

[0073] Next, as Figure 7 As shown, the portion of the first metal layer 51 exposed from the second metal layer 52 and the third metal layer 53 is removed by etching. This etching is, for example, wet etching. The etching can also be RIE (Residual Etching). Next, annealing is performed in a nitrogen (N2) atmosphere at a temperature of 350°C or higher and 450°C or lower for 10 minutes to 50 minutes. As a result, a gate electrode 50 having the first metal layer 51, the second metal layer 52, and the third metal layer 53 is formed. Annealing can also be performed before etching the portion of the first metal layer 51 exposed from the second metal layer 52 and the third metal layer 53.

[0074] In this way, the high electron mobility transistor 100 of the first embodiment can be manufactured.

[0075] In the high electron mobility transistor 100 of the first embodiment, the gate electrode 50 includes an amorphous Co layer as the first metal layer 51. The amorphous Co layer is less prone to gate leakage. Therefore, according to the first embodiment, gate leakage can be reduced.

[0076] The first metal layer 51 may comprise an amorphous ruthenium (Ru) layer instead of an amorphous Co layer, or it may comprise both an amorphous Co layer and an amorphous Ru layer. When the amorphous Ru layer is formed by the ALD method, bis(diisopropylbutanemidinate)ruthenium may be used as the raw material for Ru, for example.

[0077] When the first metal layer 51 contains hydrogen, carbon, nitrogen, and oxygen, it is easy to make the first metal layer 51 amorphous. The proportions of hydrogen (H) atoms, carbon (C) atoms, nitrogen (N) atoms, and oxygen (O) atoms in the first metal layer 51 are, for example, 2 atomic percent or more and 25 atomic percent or less. The respective proportions of H atoms, C atoms, N atoms, and O atoms can be determined by secondary ion mass spectrometry (SIMS). H atoms and N atoms originate from the raw materials and carrier gas of the first metal layer 51. C atoms and O atoms originate from the raw materials of the first metal layer 51.

[0078] As described above, the thickness of the first metal layer 51 is, for example, 3 nm or more and 50 nm or less. If the thickness of the first metal layer 51 is less than 3 nm, it may be difficult to reduce gate leakage. If the thickness of the first metal layer 51 is greater than 50 nm, the resistance of the gate electrode 50 may become too high. The thickness of the first metal layer 51 may also be 5 nm or more and 30 nm or less, or it may be 7 nm or more and 20 nm or less.

[0079] The thickness of the first metal layer 51 can be measured using transmission electron microscopy (TEM) or scanning transmission electron microscopy (STEM). Furthermore, in this disclosure, the thickness of the first metal layer 51 refers to... Figure 7 The smallest dimension t1 is shown on the inside of the opening 130G along the axis perpendicular to the surface 120A of the semiconductor stack 120.

[0080] The gate electrode 50 includes a second metal layer 52, the resistance of which is lower than that of the first metal layer 51, thereby suppressing the resistance of the gate electrode 50 to a low level. The second metal layer 52 is not limited to an Au layer. The second metal layer 52 may also contain at least one material selected from the group consisting of gold, copper (Cu), and aluminum (Al).

[0081] The gate electrode 50 has a third metal layer 53 located between the first metal layer 51 and the second metal layer 52, thereby achieving good adhesion between the first metal layer 51 and the second metal layer 52. When the third metal layer 53 contains titanium, good adhesion is easily achieved.

[0082] The semiconductor stack 120 includes a channel layer 124 and a barrier layer 126 located between the channel layer 124 and the gate electrode 50. This facilitates the growth of the channel layer 124 and the barrier layer 126, and allows for the attainment of excellent crystallinity in both layers. The semiconductor stack 120 may or may not include a cap layer 128. For example, when the semiconductor stack 120 includes a cap layer 128, the gate electrode 50 is in direct contact with the cap layer 128; when the semiconductor stack 120 does not include a cap layer 128, the gate electrode 50 is in direct contact with the barrier layer 126. In either case, gate leakage is reduced. When the semiconductor stack 120 includes a cap layer 128, excellent crystallinity is also readily attained in the cap layer 128. Furthermore, electron trapping is easily reduced.

[0083] An insulating film 130 is formed therein, and the gate electrode 50 makes Schottky contact with the semiconductor stack 120 through the opening 130G. Therefore, the semiconductor stack 120 can be protected by the insulating film 130.

[0084] The first metal layer 51 is formed using the ALD method, resulting in a Co layer that is easily formed into an amorphous state. The raw material for the first metal layer 51 includes at least one selected from the group consisting of bis(diisopropylbutanemidyl)cobalt and bis(diisopropylbutanemidyl)ruthenium, thereby facilitating the formation of the amorphous first metal layer 51. Furthermore, during the formation of the first metal layer 51, the raw material and at least one selected from the group consisting of hydrogen (H2) and ammonia (NH3) are supplied to the ALD furnace, thereby facilitating the decomposition of the raw material and particularly facilitating the formation of the amorphous first metal layer. It should be noted that only one of hydrogen or ammonia needs to be supplied to the ALD furnace along with the raw material; the other may not be supplied. If at least one is supplied, the raw material can be decomposed.

[0085] In the formation of the gate electrode 50, such as Figure 9As shown, before forming the first metal layer 51, a reduction treatment is performed at a first temperature that decomposes the native oxide film on the surface of the semiconductor stack 120, thereby obtaining good Schottky characteristics between the gate electrode 50 and the semiconductor stack 120. For example, a high Schottky barrier is obtained, the threshold voltage of the high electron mobility transistor 100 becomes higher, and thus the voltage applied to the gate electrode 50 can be increased. For example, the native oxide film is a gallium oxide (Ga2O3) film, and the first temperature is 400°C or higher and 500°C or lower. The first metal layer 51 is formed at a second temperature lower than the first temperature, for example, 150°C or higher and 250°C or lower. Figure 9 This is a diagram showing other examples of temperature changes during the formation of gate electrode 50.

[0086] In the reduction process, hydrogen (H2) and ammonia (NH3) are used, for example. In this case, oxygen atoms are removed from the native oxide film by hydrogen, and nitrogen deficiency in the semiconductor stack 120 is compensated by ammonia. In the reduction process, for example, the flow rate of H2 is set to 1 standard cubic centimeter (sccm) or more and 500 sccm or less, and the flow rate of NH3 is set to 1 sccm or more and 500 sccm or less.

[0087] In the case of reduction processing, the reduction process and the formation of the first metal layer 51 are carried out in the same furnace without exposure to the atmosphere, i.e., the processing is carried out continuously in situ, thereby achieving particularly excellent cleanliness on the surface of the semiconductor stack 120. Therefore, superior Schottky characteristics are readily obtained. The supply of hydrogen and ammonia can continue continuously from the reduction process until the formation of the first metal layer 51.

[0088] Furthermore, in the case of reduction treatment, the reduction treatment and the formation of the first metal layer 51 are carried out in different furnaces without being open to the atmosphere, thereby independently controlling the temperature in the furnace where the reduction treatment is carried out and the temperature in the furnace where the first metal layer 51 is formed, making it easy to obtain high production capacity.

[0089] (Second Implementation)

[0090] The second embodiment will be described. The second embodiment differs from the first embodiment mainly in the composition of the substrate and the semiconductor laminate. Figure 10 This is a cross-sectional view showing the high electron mobility transistor of the second embodiment.

[0091] like Figure 10 As shown, the high electron mobility transistor 200 of the second embodiment has a substrate 210, a semiconductor stack 220, an insulating film 230, a gate electrode 50, a source electrode 44S, and a drain electrode 44D.

[0092] The substrate 210 is, for example, a substrate for growing a GaN-based semiconductor layer, or a semi-insulating SiC substrate. When the substrate 210 is a SiC substrate, the upper surface of the substrate 210 is a carbon (C) polar surface. When the surface of the substrate 210 is a C polar surface, the semiconductor stack 220 grows crystals using a nitrogen (N) polar surface as the growth surface.

[0093] The semiconductor stack 220 has a buffer layer 222, a barrier layer 226, a channel layer 224, a cap layer 228, a regeneration layer 242S, and a regeneration layer 242D.

[0094] A buffer layer 222 is located above the substrate 210. The buffer layer 222 is, for example, an AlN layer. The buffer layer 222 may also have an AlN layer and a GaN layer or an AlGaN layer above the AlN layer. A barrier layer 226 is located above the buffer layer 222. The barrier layer 226 is, for example, an n-type AlGaN layer. A channel layer 224 is located above the barrier layer 226. The channel layer 224 is, for example, an undoped GaN layer. A 2DEG255 is present near the lower surface of the channel layer 224. A cap layer 228 is located above the channel layer 224. The cap layer 228 is, for example, an AlN layer or an AlGaN layer.

[0095] A recess 240S for the active electrode and a recess 240D for the drain electrode are formed in a portion of the cap layer 228 and the channel layer 224. The recesses 240S and 240D penetrate the cap layer 228 and enter the channel layer 224. The channel layer 224 is exposed from the recesses 240S and 240D.

[0096] An insulating film 230 is located above the cap layer 228. The insulating film 230 is, for example, a SiN film. The thickness of the insulating film 230 is, for example, 1 nm or more and 10 nm or less. An opening 230S for the active electrode and an opening 230D for the drain electrode are formed on the insulating film 230. The opening 230S is connected to the recess 240S, and the opening 230D is connected to the recess 240D.

[0097] The regenerated layer 242S lies above the channel layer 224 within the recess 240S and the opening 230S. The regenerated layer 242D lies above the channel layer 224 within the recess 240D and the opening 230D. The regenerated layers 242S and 242D are, for example, n-type GaN layers. The resistivity of the regenerated layers 242S and 242D is lower than that of the channel layer 224.

[0098] The source electrode 44S is located on the regenerated layer 242S, and the drain electrode 44D is located on the regenerated layer 242D. The source electrode 44S is in direct contact with the regenerated layer 242S, and the drain electrode 44D is in direct contact with the regenerated layer 242D. The source electrode 44S is in ohmic contact with the regenerated layer 242S, and the drain electrode 44D is in ohmic contact with the regenerated layer 242D.

[0099] An opening 230G for a gate is formed in the insulating film 230. The opening 230G is located between the openings 230S and 230D. The gate electrode 50 is disposed on the insulating film 230 and makes a Schottky contact with the semiconductor stack 220 via the opening 230G.

[0100] Next, the manufacturing method of the high electron mobility transistor 200 according to the second embodiment will be described.

[0101] First, a buffer layer 222, a barrier layer 226, a channel layer 224, and a cap layer 228 are formed on a substrate 210. The buffer layer 222, barrier layer 226, channel layer 224, and cap layer 228 can be formed, for example, by MOCVD. Next, an insulating film 230 is formed on the cap layer 228. The insulating film 230 can be formed, for example, by CVD.

[0102] Next, openings 230S and 230D are formed in the insulating film 230, and recesses 240S and 240D are formed in a portion of the cap layer 228 and the channel layer 224. Openings 230S and 230D can be formed, for example, using a reactive gas containing fluorine (F). Recesses 240S and 240D can be formed, for example, using a reactive gas containing chlorine (Cl). Next, a regenerated layer 242S is formed within the recesses 240S and openings 230S, and a regenerated layer 242D is formed within the recesses 240D and openings 230D. The regenerated layers 242S and 242D are formed, for example, by MOCVD, MBE, or sputtering. In this way, a semiconductor laminate 220 can be obtained.

[0103] Next, a source electrode 44S is formed on the regenerated layer 242S, and a drain electrode 44D is formed on the regenerated layer 242D. The source electrode 44S and the drain electrode 44D can be formed by the same method as in the first embodiment.

[0104] Next, an opening 230G is formed in the insulating film 230. The opening 230G can be formed, for example, by using a reactive gas containing fluorine (F) in an RIE. Next, a gate electrode 50 is formed on the insulating film 230, which makes a Schottky contact with the semiconductor stack 220 via the opening 230G. The gate electrode 50 can be formed by the same method as in the first embodiment.

[0105] In this way, the high electron mobility transistor 200 of the second embodiment can be manufactured.

[0106] In the high electron mobility transistor 200 of the second embodiment, the gate electrode 50 comprises an amorphous Co layer as the first metal layer 51. Therefore, similar to the first embodiment, gate leakage can be reduced. In the second embodiment, the first metal layer 51 may also comprise an amorphous ruthenium (Ru) layer instead of an amorphous Co layer.

[0107] The semiconductor stack 220 includes a barrier layer 226 and a channel layer 224 located between the barrier layer 226 and the gate electrode 50, thereby easily suppressing the contact resistance between the source electrode 44S and the drain electrode 44D and the semiconductor stack 220 to a low level. The semiconductor stack 220 may or may not include a cap layer 228. For example, when the semiconductor stack 220 includes a cap layer 228, the gate electrode 50 is in direct contact with the cap layer 228; when the semiconductor stack 220 does not include a cap layer 228, the gate electrode 50 is in direct contact with the channel layer 224. In either case, gate leakage is reduced. When the semiconductor stack 220 includes a cap layer 228, excellent crystallinity is also easily obtained in the cap layer 228. Furthermore, electron trapping is easily reduced.

[0108] Next, the various experiments conducted by the inventors of this application will be described.

[0109] (First Experiment)

[0110] In the first experiment, three samples (samples No. 1, No. 2, and No. 3) were prepared, and the leakage current was measured when a reverse voltage of -5V was applied to the gate electrode. Furthermore, for each of the three samples, the drain current (I) was measured while the gate voltage (V) was varied to obtain I-V curves, and the Schottky barrier and ideality coefficient were calculated from the I-V curves.

[0111] In the formation of the semiconductor stack of samples No.1, No.2 and No.3, a barrier layer is formed on the channel layer, similar to the first embodiment.

[0112] In the fabrication of sample No. 1, during the formation of the gate electrode, nickel (Ni) layer, palladium (Pd) layer, and gold (Au) layer were deposited and stripped, followed by annealing. In this way, a gate electrode composed of Ni layer, Pd layer, and Au layer stacked sequentially was formed.

[0113] In the fabrication of sample No. 2, the gate electrode was formed in the same manner as in the first embodiment, including the formation of the Co layer using the ALD method, the deposition and stripping of the Ti and Au layers, followed by etching and annealing of the Co layer. This resulted in a gate electrode formed by sequentially stacking the Co, Ti, and Au layers.

[0114] In the fabrication of sample No. 3, a reduction treatment was performed during the formation of the gate electrode. Then, as in the first embodiment, the Co layer was formed using the ALD method, and the Ti and Au layers were vapor-deposited and stripped. Following this, the Co layer was etched and annealed. In this way, a gate electrode was formed by sequentially stacking the Co, Ti, and Au layers.

[0115] The other conditions for samples No.1, No.2 and No.3 are the same.

[0116] Leakage current, Schottky barrier, and ideality coefficient are shown in Table 1.

[0117] [Table 1]

[0118]

[0119] As shown in Table 1, the leakage current of samples No. 2 and No. 3 is lower than that of sample No. 1. Furthermore, the Schottky barrier of sample No. 3 is larger than that of sample No. 1, with an ideality factor close to 1.00. That is, sample No. 3 exhibits better Schottky characteristics than sample No. 1.

[0120] (Second Experiment)

[0121] In the second experiment, the structures of the Ni layer in sample No. 1, the Co layer in sample No. 2, and the Co layer in sample No. 3 were resolved using electron beam diffraction with a scanning transmission electron microscope (STEM). The electron beam diffraction images of the three samples are shown below. Figures 11 to 13 . Figure 11 This is a diagram showing the electron beam diffraction pattern of sample No. 1. Figure 12 This is a diagram showing the electron beam diffraction pattern of sample No. 2. Figure 13 This is a diagram showing the electron beam diffraction pattern of sample No. 3.

[0122] like Figure 11 As shown, the Ni layer in sample No. 1 becomes a single crystal. On the other hand, as... Figure 12 and Figure 13 As shown, the Co layer in sample No. 2 and the Co layer in sample No. 3 are in an amorphous state.

[0123] The embodiments have been described in detail above, but this disclosure is not limited to specific embodiments, and various modifications and alterations can be made within the scope of the claims.

Claims

1. A high electron mobility transistor, having: substrate; A semiconductor stack is disposed on the substrate; and The gate electrode is in contact with the Schottky layer of the semiconductor stack. The gate electrode has: A first metal layer is in direct contact with the semiconductor stack; and A second metal layer covers the first metal layer. The first metal layer comprises at least one selected from the group consisting of cobalt and ruthenium in an amorphous state.

2. The high electron mobility transistor according to claim 1, wherein, The resistance of the second metal layer is lower than that of the first metal layer.

3. The high electron mobility transistor according to claim 1 or 2, wherein, The first metal layer contains hydrogen atoms, carbon atoms, nitrogen atoms, and oxygen atoms.

4. The high electron mobility transistor according to claim 1 or 2, wherein, The second metal layer comprises at least one selected from the group consisting of gold, copper, and aluminum.

5. The high electron mobility transistor according to claim 1 or 2, wherein, The thickness of the first metal layer is more than 3 nm and less than 50 nm.

6. The high electron mobility transistor according to claim 1 or 2, wherein, The gate electrode has a third metal layer located between the first metal layer and the second metal layer.

7. The high electron mobility transistor according to claim 6, wherein, The third metal layer contains titanium.

8. The high electron mobility transistor according to claim 1 or 2, wherein, The semiconductor stack has: Channel layer; and A barrier layer is located between the channel layer and the gate electrode. The gate electrode is in direct contact with the barrier layer.

9. The high electron mobility transistor according to claim 1 or 2, wherein, The semiconductor stack has: Channel layer; A barrier layer is located between the channel layer and the gate electrode; and A cap layer, located between the barrier layer and the gate electrode. The gate electrode is in direct contact with the cap layer.

10. The high electron mobility transistor according to claim 1 or 2, wherein, The semiconductor stack has: Barrier layer; and The channel layer is located between the barrier layer and the gate electrode. The gate electrode is in direct contact with the channel layer.

11. The high electron mobility transistor according to claim 1 or 2, wherein, The semiconductor stack has: Barrier layer; A channel layer is located between the barrier layer and the gate electrode; and A cap layer, located between the channel layer and the gate electrode. The gate electrode is in direct contact with the cap layer.

12. The high electron mobility transistor according to claim 1 or 2, comprising: an insulating film covering the semiconductor stack, An opening is formed in the insulating film. The gate electrode is in contact with the semiconductor stack Schottky via the opening.

13. A method for manufacturing a high electron mobility transistor, comprising the following steps: Forming a semiconductor stack on a substrate; and A gate electrode is formed that contacts the Schottky junction of the semiconductor stack. The process of forming the gate electrode includes the following steps: A first metal layer in direct contact with the semiconductor stack is formed by atomic layer deposition; and A second metal layer is formed to cover the first metal layer. The first metal layer comprises at least one selected from the group consisting of cobalt and ruthenium in an amorphous state.

14. The method for manufacturing a high electron mobility transistor according to claim 13, wherein, The raw material of the first metal layer comprises at least one selected from the group consisting of bis(diisopropylbutanemidyl)cobalt and bis(diisopropylbutanemidyl)ruthenium.

15. The method for manufacturing a high electron mobility transistor according to claim 14, wherein, In the process of forming the first metal layer, the raw material and at least one selected from the group consisting of hydrogen and ammonia are supplied into the furnace.

16. The method for manufacturing a high electron mobility transistor according to any one of claims 13 to 15, wherein, The process of forming the gate electrode, prior to the process of forming the first metal layer, includes the following step: performing a reduction treatment at a first temperature that decomposes the native oxide film on the surface of the semiconductor laminate. The first metal layer is formed at a second temperature lower than the first temperature.

17. The method for manufacturing a high electron mobility transistor according to claim 16, wherein, The reduction process and the process of forming the first metal layer are carried out in the same furnace without being exposed to the atmosphere.

18. The method for manufacturing a high electron mobility transistor according to claim 16, wherein, The reduction process and the formation of the first metal layer are carried out in separate furnaces that are not open to the atmosphere.

19. The method for manufacturing a high electron mobility transistor according to claim 16, wherein, Hydrogen and ammonia are used in the reduction process.

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