HEMT (High Electron Mobility Transistor) power device based on single field plate and preparation method

Abstract

The invention relates to an HEMT (High Electron Mobility Transistor) power device based on a single field plate and a preparation method. The HEMT power device based on the single field plate comprises a substrate; an epitaxial layer; a source ohmic contact electrode; a drain ohmic contact electrode; an insulating layer or a first gate layer; a gate passivation layer; the grid opening penetrates through the grid passivation layer to reach the insulating layer or the first grid layer; the gate field plate is arranged on the gate passivation layer; wherein the gate passivation layer is formed by arranging SiN and / or SiO2 on the barrier layer through a low-pressure chemical vapor deposition method or an inductively coupled plasma-chemical vapor deposition method. According to the HEMT power device, the compactness of the gate passivation layer is better, and the surface passivation effect is better, so that more uniform electric field distribution can be obtained in a single field plate structure jointly formed by the gate opening and the gate field plate, the obtained HEMT power device based on the single field plate has a better voltage withstanding result, and meanwhile, the HEMT power device based on the single field plate is simple in process, low in manufacturing cost and easy to popularize. And the reliability is higher.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a HEMT power device based on a single field plate and its fabrication method. Background Technology

[0002] In recent years, GaN high electron mobility transistors (GaN HEMTs) have transformed power systems due to their high efficiency and miniaturization. Their wide bandgap and high electron drift velocity give them an excellent Baliga factor of quality, enabling GaN HEMT power devices to operate at high voltage, high frequency switching, and high temperature. They can also provide low on-resistance and switching losses, making them promising for applications in consumer electronics, industrial, and automotive fields.

[0003] High-voltage GaN HEMT power devices simplify power system topologies, reduce component count, and thus increase power density. Increased voltage withstand reduces the risk of device failure under high-voltage transients and effectively suppresses device degradation caused by overshoot voltage. To improve voltage withstand, multi-layer field plate technology is typically used in GaN HEMT power devices to optimize electric field distribution and reduce electric field spikes, thereby increasing the voltage withstand. In applications with voltage withstand of 650V and above, GaN HEMT power devices generally employ a three-field plate design, allowing the voltage withstand to significantly exceed the voltage across the device during application. This higher voltage margin allows for shorter gate-drain spacing in the design, reducing device area and lowering costs. The fabrication process for multi-field plate HEMT power devices still requires further simplification. Summary of the Invention

[0004] In view of this, the present invention provides a HEMT power device based on a single field plate and a method for fabricating it, aiming to simplify the process of HEMT power devices based on multi-field plate structures and reduce manufacturing costs.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a HEMT power device based on a single field plate, comprising: Substrate; The epitaxial layer includes a buffer layer, a channel layer, and a barrier layer sequentially disposed on the substrate in a direction away from the substrate; A source ohmic contact electrode is disposed on the channel layer and forms a source ohmic contact with the two-dimensional electron gas between the barrier layer and the channel layer. A drain ohmic contact electrode is disposed on the channel layer and forms a drain ohmic contact with the two-dimensional electron gas between the barrier layer and the channel layer. An insulating layer or a gate layer is disposed on the barrier layer, wherein the gate layer is disposed at a distance from the source ohmic contact electrode and the drain ohmic contact electrode; A gate passivation layer is disposed on the insulating layer or covers the gate layer; A gate opening extends through the gate passivation layer to the insulating layer or the gate-first layer; A gate field plate is disposed on the gate passivation layer and located between the source ohmic contact electrode and the drain ohmic contact electrode. The gate field plate covers and fills the gate opening and forms a Schottky contact with the gate passivation layer. The end of the gate field plate near the drain ohmic contact electrode extends beyond the end of the gate opening near the drain ohmic contact electrode. The gate passivation layer is formed by depositing SiN and / or SiO2 onto the barrier layer using low-pressure chemical vapor deposition or inductively coupled plasma-chemical vapor deposition.

[0006] In one embodiment, the contact resistance between the source ohmic contact electrode and the drain ohmic contact electrode is less than 1 ohm*mm; and / or The distance between the gate opening and the barrier layer is 10nm-60nm; and / or The length of the end of the gate field plate near the drain ohmic contact electrode that extends beyond the end of the gate opening near the drain ohmic contact electrode is 2μm-10μm.

[0007] In one embodiment, the HEMT power device based on a single field plate further includes a device isolation region disposed outside the active region. The formation of the device isolation region includes implanting F ions or N ions into the epitaxial layer by ion implantation or etching the epitaxial layer.

[0008] In one embodiment, the ion implantation depth or etching depth of the isolation region of the device reaches the buffer layer.

[0009] In one embodiment, the HEMT power device based on a single field plate further includes a passivation layer disposed on the gate passivation layer and covering the source ohmic contact electrode, the drain ohmic contact electrode, the gate field plate, and the device isolation region.

[0010] In one embodiment, the thickness of the passivation layer is 100nm-6000nm; and / or The HEMT power device based on a single field plate also includes: A source via, wherein the source via penetrates the passivation layer and the gate passivation layer to reach the surface of the source ohmic contact electrode; A drain via, wherein the drain via penetrates the passivation layer and the gate passivation layer to reach the surface of the drain ohmic contact electrode; A source interconnect metal electrode is disposed on the passivation layer and is electrically connected to the source ohmic contact electrode through the source via; A drain interconnect metal electrode is disposed on the passivation layer and is electrically connected to the drain ohmic contact electrode through the drain via.

[0011] In one embodiment, the insulating layer is made of the same material and formed in the same way as the gate passivation layer, or SiN is formed by in-situ growth; and / or The substrate material includes Si, SiC, or sapphire; and / or The material of the buffer layer includes one or more of AlN, GaN, and AlGaN; and / or The channel layer material includes one or more of AlN, GaN, InGaN, InAlN, InAlGaN, and AlGaN; and / or The material of the barrier layer includes one or more of AlGaN, AlN, InAlN, and InAlGaN; and / or The passivation layer is made of one or more of SiN, SiO2, and SiON, or one or more of AlN, Al2O3, and AlON; and / or The source interconnect metal electrode is made of one or more of the following materials: Ti, Al, Au, TiN, Ta, TaN, Cu, and AlCu; and / or The source ohmic contact electrode is made of one or more of Ti, Al, and TiN; or one or more of Ti, Al, Ni, Au, and Mo; or one or more of Ta, Al, and TaN; and / or The material of the gate field plate includes one or more of Ti, Al, AlCu, TiN, Ni, Pt, Au, Ir, Ru, Ta, TaN, W, Zr, Mo, Rh, Pd, Pb, Os, Cu, Ag, and ITO; and / or The material of the drain ohmic contact electrode includes one or more of Ti, Al, and TiN; or one or more of Ti, Al, Ni, Au, and Mo; or one or more of Ta, Al, and TaN; and / or The material of the drain interconnect metal electrode includes one or more of Ti, Al, Au, TiN, Ta, TaN, Cu, and AlCu.

[0012] Secondly, the present invention provides a method for fabricating a HEMT power device based on a single field plate, comprising: A substrate and buffer layer material, a channel layer material and a barrier layer material are provided, and the buffer layer material, the channel layer material and the barrier layer material are sequentially disposed on the substrate to form a buffer layer, a channel layer and a barrier layer; Source ohmic contact electrode material and drain ohmic contact electrode material are provided and respectively disposed on the barrier layer to form source ohmic contact electrode and drain ohmic contact electrode, and the source ohmic contact electrode and the drain ohmic contact electrode form ohmic contact with the two-dimensional electron gas between the barrier layer and the channel layer. An insulating layer material or p-type doped PGaN is provided and disposed on the barrier layer to form an insulating layer, wherein the gate layer is spaced apart from the source ohmic contact electrode and the drain ohmic contact electrode; SiN and / or SiO2 are provided, and the SiN and / or SiO2 are disposed on the insulating layer or covered by the gate layer by low-pressure chemical vapor deposition or inductively coupled plasma-chemical vapor deposition to form a gate passivation layer. The gate passivation layer is etched to form a gate opening, and the gate opening penetrates the gate passivation layer to reach the insulating layer or the gate layer. A gate field plate material is provided and disposed on the gate passivation layer to form a gate field plate between the source ohmic contact electrode and the drain ohmic contact electrode. The gate field plate covers and fills the gate opening and forms a Schottky contact with the gate passivation layer.

[0013] In one embodiment, providing an insulating layer material, disposed on the barrier layer (203) to form an insulating layer (401), includes: Provide SiN and / or SiO2, and deposit the SiN and / or SiO2 onto the barrier layer using low-pressure chemical vapor deposition (LPCVD), inductively coupled plasma-chemical vapor deposition (ICPCVD), or plasma-enhanced chemical vapor deposition (PECVD), or deposit the SiN onto the barrier layer by in-situ growth to form an insulating layer; and / or The preparation method further includes: F or N ions are provided to inject F or N ions into the buffer layer, the channel layer, and the barrier layer outside the active region to form a device isolation region; or The buffer layer, the channel layer, and the barrier layer are etched to form a device isolation region.

[0014] In one embodiment, it further includes: A passivation layer material is provided and disposed on the gate passivation layer to form a passivation layer, wherein the passivation layer covers the source ohmic contact electrode, the drain ohmic contact electrode, the gate field plate and the device isolation region; The passivation layer and the gate passivation layer are etched to form source vias and drain vias. The source vias and the drain vias penetrate the passivation layer and the gate passivation layer to reach the surfaces of the source ohmic contact electrode and the drain ohmic contact electrode, respectively. Source interconnect metal electrode material and drain interconnect metal electrode material are provided and respectively disposed on the passivation layer to form source interconnect metal electrode and drain interconnect metal electrode, respectively. The source interconnect metal electrode is electrically connected to the source ohmic contact electrode through the source via, and the drain interconnect metal electrode is electrically connected to the drain ohmic contact electrode through the drain via.

[0015] In this invention, the gate passivation layer is formed by SiN and / or SiO2 through low-pressure chemical vapor deposition (LPCVD), inductively coupled plasma-chemical vapor deposition (ICPCVD), or plasma-enhanced chemical vapor deposition (PECVD). This results in better density and surface passivation of the gate passivation layer, thereby enabling a more uniform electric field distribution in the single field plate structure (FP1) formed by the gate opening and the gate field plate. This leads to better breakdown voltage performance of the resulting HEMT power device based on the single field plate, while also offering simple processing, low manufacturing cost, and higher reliability. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the HEMT power device based on a single field plate provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the HEMT power device based on a single field plate provided in Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the HEMT power device based on a single field plate provided in Comparative Example 1 of the present invention; Figure 4 These are the turn-off withstand voltage test results of the HEMT devices of Embodiment 1 and Comparative Example 1 of the present invention, wherein... Figure 4 (a) shows the turn-off withstand voltage test results of the HEMT device in Example 1. Figure 4 (b) shows the turn-off withstand voltage test results of the HEMT device in Comparative Example 1.

[0018] Explanation of reference numerals in the attached figures: Substrate-1; Epitaxial layer-2; Buffer layer-201; Channel layer-202; Barrier layer-203; Gate passivation layer-301; Passivation layer-302; Source interconnect metal electrode-303; Source via-304; Source ohmic contact electrode-305; Gate opening-306; First gate layer-307; Gate field plate-308; Drain interconnect metal electrode-309; Drain via-310; Drain ohmic contact electrode-311; Device isolation region-312; Second gate field plate-313; Third gate field plate-314. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0021] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in its actual use or operating state, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device. Furthermore, in the description of this invention, the term "comprising" means "including but not limited to". The terms first, second, third, etc., are used merely as illustrative purposes and do not impose numerical requirements or establish an order.

[0022] In this invention, "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural.

[0023] In this invention, "at least one" means one or more, and "more than one" means two or more. "One or more", "at least one of the following", or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, "at least one of a, b, or c", or "at least one of a, b, and c", can both represent: a, b, c, ab (i.e., a and b), ac, bc, or abc, where a, b, and c can be single or multiple.

[0024] Various embodiments of the present invention may exist in the form of a range; it should be understood that the description in the form of a range is merely for convenience and brevity and should not be construed as a hard limitation on the scope of the invention; therefore, it should be considered that the range description has specifically disclosed all possible subranges and single numerical values ​​within that range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and single numbers within the range, such as 1, 2, 3, 4, 5, and 6, regardless of the range. Furthermore, whenever a numerical range is referred to herein, it means including any referenced number (fraction or integer) within the range referred to.

[0025] The technical solution of the present invention is as follows: Firstly, please refer to Figures 1-2 This invention provides a HEMT power device based on a single field plate, comprising: Substrate 1; Epitaxial layer 2 includes a buffer layer 201, a channel layer 202 and a barrier layer 203 sequentially disposed on the substrate along a direction away from the substrate 1; A source ohmic contact electrode 305 is disposed on the channel layer 202 and forms a source ohmic contact with the two-dimensional electron gas between the barrier layer 203 and the channel layer 202. The drain ohmic contact electrode 311 is disposed on the channel layer 202 and forms a drain ohmic contact with the two-dimensional electron gas between the barrier layer 203 and the channel layer 202. An insulating layer 401 or a gate layer 307 is disposed on the barrier layer 203, and the gate layer is disposed at intervals from the source ohmic contact electrode (305) and the drain ohmic contact electrode (311); A gate passivation layer 301 is disposed on the insulating layer 401 or covers the gate layer 307; The gate opening 306 penetrates the gate passivation layer 301 and reaches the insulating layer 401 or the gate layer 307; A gate field plate 308 is disposed on the gate passivation layer 301 and located between the source ohmic contact electrode 305 and the drain ohmic contact electrode 311. The gate field plate 308 covers and fills the gate opening 306 and forms a Schottky contact with the gate passivation layer 301. The end of the gate field plate 308 near the drain ohmic contact electrode 311 extends beyond the end of the gate opening 306 near the drain ohmic contact electrode 311. The gate passivation layer 301 is formed on the barrier layer 203 by depositing SiN and / or SiO2 on the barrier layer 203 using low-pressure chemical vapor deposition or inductively coupled plasma-chemical vapor deposition.

[0026] In this invention, the gate passivation layer 301 is formed by SiN and / or SiO2 through low-pressure chemical vapor deposition (LPCVD), inductively coupled plasma-chemical vapor deposition (ICPCVD), or plasma-enhanced chemical vapor deposition (PECVD). This results in better density and surface passivation of the gate passivation layer 301, thereby enabling a more uniform electric field distribution in the single field plate structure (FP1) formed by the gate opening 306 and the gate field plate 308. This leads to better breakdown voltage performance of the resulting HEMT power device based on the single field plate, while also offering simple processing, low manufacturing cost, and higher reliability.

[0027] In this invention, ICPCVD has low-temperature characteristics, which can prevent damage to the material surface.

[0028] In this invention, HEMT power devices with a single field plate structure (FP1) are compared to multi-field plate structures (such as... Figure 3 Compared to GaN HEMT power devices with FP1 / FP2 / FP3 structures, the single-field-plate HEMT power device of this invention has the same breakdown voltage but a simpler and easier-to-implement structure. Therefore, compared to GaN HEMT power devices with multi-field-plate structures, the single-field-plate HEMT power device of this invention simplifies the process and reduces manufacturing costs. At the same time, due to fewer film layers and a simpler structure, its reliability can also be improved, and it has the prospect of large-scale industrial mass production.

[0029] In one embodiment, the contact resistance of the source ohmic contact electrode 305 and the drain ohmic contact electrode 311 is less than 1 ohm*mm. This improves device performance and usability.

[0030] In one embodiment, the distance between the gate opening 306 and the barrier layer 203 is 10nm-60nm, for example, it can be 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, etc. The distance between the gate opening 306 and the barrier layer 203 refers to the distance between the side of the gate opening 306 closest to the insulating layer 401 and the side of the barrier layer 203 closest to the insulating layer 401, that is, the distance between surfaces.

[0031] In one embodiment, the length of the end of the gate field plate 308 near the drain ohmic contact electrode 311 extending beyond the end of the gate opening 306 near the drain ohmic contact electrode 311 is 2μm-10μm, for example, it can be 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc. This allows for uniform electric field distribution through the field plate structure.

[0032] In one embodiment, the HEMT power device based on a single field plate further includes a device isolation region 312, which is disposed outside the active region. The formation of the device isolation region 312 includes implanting F ions or N ions into the epitaxial layer 2 by ion implantation or etching the epitaxial layer 2.

[0033] In one embodiment, the ion implantation depth or etching depth of the device isolation region 312 reaches the buffer layer 201.

[0034] In one embodiment, the HEMT power device based on a single field plate further includes a passivation layer 302 disposed on the gate passivation layer 301 and covering the source ohmic contact electrode 305, the drain ohmic contact electrode 311, the gate field plate 308, and the device isolation region 312.

[0035] In one embodiment, the thickness of the passivation layer 302 is 100nm-6000nm, for example, it can be 100nm, 300nm, 500nm, 700nm, 1000nm, 2000nm, 3000nm, 4000nm, 5000nm, 6000nm, etc.

[0036] In one embodiment, the HEMT power device based on a single field plate further includes: Source via 304, which penetrates the passivation layer 302 and the gate passivation layer 301 to reach the surface of the source ohmic contact electrode 305; Drain via 310, the drain via 310 penetrates the passivation layer 302 and the gate passivation layer 301 to reach the surface of the drain ohmic contact electrode 311; A source interconnect metal electrode 303 is disposed on the passivation layer 302 and is electrically connected to the source ohmic contact electrode 305 through the source via 304. A drain interconnect metal electrode 309 is disposed on the passivation layer 302 and is electrically connected to the drain ohmic contact electrode 311 through the drain via 310.

[0037] In one embodiment, the insulating layer 401 is made of the same material and is formed in the same way as the gate passivation layer 301, or SiN is formed by in-situ growth.

[0038] In one embodiment, the substrate 1 is made of Si, SiC, or sapphire.

[0039] In one embodiment, the material of the buffer layer 201 includes one or more of AlN, GaN, and AlGaN.

[0040] In one embodiment, the material of the channel layer 202 includes one or more of AlN, GaN, InGaN, InAlN, InAlGaN, and AlGaN.

[0041] In one embodiment, the material of the barrier layer 203 includes one or more of AlGaN, AlN, InAlN, and InAlGaN.

[0042] In one embodiment, the material of the passivation layer 302 includes one or more of SiN, SiO2 and SiON, or one or more of AlN, Al2O3 and AlON.

[0043] The material of the source interconnect metal electrode 303 includes one or more of Ti, Al, Au, TiN, Ta, TaN, Cu, and AlCu.

[0044] In one embodiment, the material of the source ohmic contact electrode 305 includes one or more of Ti, Al and TiN, or one or more of Ti, Al, Ni, Au and Mo, or one or more of Ta, Al and TaN.

[0045] In one embodiment, the material of the gate field plate 308 includes one or more of Ti, Al, AlCu, TiN, Ni, Pt, Au, Ir, Ru, Ta, TaN, W, Zr, Mo, Rh, Pd, Pb, Os, Cu, Ag and ITO.

[0046] In one embodiment, the material of the drain ohmic contact electrode 311 includes one or more of Ti, Al and TiN, or one or more of Ti, Al, Ni, Au and Mo, or one or more of Ta, Al and TaN.

[0047] In one embodiment, the material of the drain interconnect metal electrode 309 includes one or more of Ti, Al, Au, TiN, Ta, TaN, Cu, and AlCu.

[0048] Secondly, the present invention provides a method for fabricating a HEMT power device based on a single field plate, comprising: A substrate 1 and a buffer layer material, a channel layer material and a barrier layer material are provided. The buffer layer material, the channel layer material and the barrier layer material are sequentially disposed on the substrate 1 to form a buffer layer 201, a channel layer 202 and a barrier layer 203. Source ohmic contact electrode material and drain ohmic contact electrode material are provided and respectively disposed on the barrier layer 203 to form source ohmic contact electrode 305 and drain ohmic contact electrode 311, and the source ohmic contact electrode 305 and the drain ohmic contact electrode 311 form ohmic contacts with the two-dimensional electron gas between the barrier layer 203 and the channel layer 202; An insulating layer material or a gate layer material is provided and disposed on the barrier layer 203 to form an insulating layer 401 or a gate layer 307. The gate layer is disposed at a distance from the source ohmic contact electrode (305) and the drain ohmic contact electrode (311). SiN and / or SiO2 are provided, and the SiN and / or SiO2 are disposed on the insulating layer 401 or covered on the gate layer 307 by low-pressure chemical vapor deposition (LPCVD), inductively coupled plasma-chemical vapor deposition (ICPCVD), or plasma-enhanced chemical vapor deposition (PECVD) to form a gate passivation layer 301. The gate passivation layer 301 is etched to form a gate opening 306, and the gate opening 306 penetrates the gate passivation layer 301 to reach the insulating layer 401 or the gate layer 307. A gate field plate material is provided and disposed on the gate passivation layer 301, forming a gate field plate 308 between the source ohmic contact electrode 305 and the drain ohmic contact electrode 311, and the gate field plate 308 covers and fills the gate opening 306 and forms a Schottky contact with the gate passivation layer 301.

[0049] In one embodiment, the provision of the insulating layer material, disposed on the barrier layer 203 to form an insulating layer 401, includes: SiN and / or SiO2 are provided, and the SiN and / or SiO2 are deposited on the barrier layer 203 by low-pressure chemical vapor deposition (LPCVD), inductively coupled plasma-chemical vapor deposition (ICPCVD), or plasma-enhanced chemical vapor deposition (PECVD), or the SiN is deposited on the barrier layer 203 by in-situ growth to form an insulating layer 401.

[0050] In one embodiment, the gate layer 307 is p-type doped PGaN or a metal.

[0051] In one embodiment, it further includes: F or N ions are provided to inject F or N ions into the buffer layer 201, the channel layer 202, and the barrier layer 203 outside the active region, forming a device isolation region 312; or The buffer layer 201, the channel layer 202 and the barrier layer 203 are etched to form the device isolation region 312.

[0052] In one embodiment, it further includes: A passivation layer material is provided and disposed on the gate passivation layer 301 to form a passivation layer 302, wherein the passivation layer 302 covers the source ohmic contact electrode 305, the drain ohmic contact electrode 311, the gate field plate 308 and the device isolation region 312; The passivation layer 302 and the gate passivation layer 301 are etched to form a source via 304 and a drain via 310. The source via 304 and the drain via 310 penetrate the passivation layer 302 and the gate passivation layer 301 to reach the surfaces of the source ohmic contact electrode 305 and the drain ohmic contact electrode 311, respectively. Source interconnect metal electrode material and drain interconnect metal electrode material are provided and disposed on the passivation layer 302, respectively forming source interconnect metal electrode 303 and drain interconnect metal electrode 309. The source interconnect metal electrode 303 is electrically connected to the source ohmic contact electrode 305 through the source via 304, and the drain interconnect metal electrode 309 is electrically connected to the drain ohmic contact electrode 311 through the drain via 310.

[0053] The materials used in the fabrication method of the HEMT power device based on a single field plate of the present invention are as described above.

[0054] Example 1 A single-field-plate-based HEMT power device (e.g.) Figure 1 The present invention (shown) and its preparation method include the following steps: (1) An epitaxial layer 2 is grown on the substrate 1. The epitaxial layer 2 includes a buffer layer 201, a channel layer 202 and a barrier layer 203 in sequence in the direction away from the substrate 1. (2) Deposit source ohmic contact electrode 305 and drain ohmic contact electrode 311 on epitaxial layer 2, and make ohmic contact between source ohmic contact electrode 305 and drain ohmic contact electrode 311 and the two-dimensional electron gas between barrier layer 203 and channel layer 202. (3) Provide SiN and form an insulating layer 401 on the barrier layer 203 by in situ growth; (4) Provide SiN and deposit SiN on the barrier layer 203 by inductively coupled plasma-chemical vapor deposition (ICP-CVD) to form a 150nm thick gate passivation layer 301; (5) Etch the gate passivation layer 301 to form a gate opening 306. The gate opening 306 penetrates the gate passivation layer 301 to reach the insulating layer 401. The distance between the gate opening 306 and the side of the barrier layer 203 near the insulating layer 401 is 30nm. (6) A gate field plate 308 is deposited on the gate passivation layer 301, and the metal material of the gate field plate 308 covers and fills the gate opening 306. The end of the gate field plate 308 near the drain ohmic contact electrode 311 (corresponding to) Figure 1 The right end of the gate opening 306 extends beyond the gate opening 306 and is close to the drain ohmic contact electrode 311 (corresponding to the right end of the gate opening 306). Figure 1 The length of the right end of the middle part is 5.5 μm; (7) F ions are implanted into the epitaxial layer 2 by ion implantation to form the device isolation region 312; (8) A passivation layer 302 is deposited on the gate passivation layer 301, and the passivation layer 302 covers the source ohmic contact electrode 305, the drain ohmic contact electrode 311, the gate field plate 308 and the device isolation region 312. (9) Etch passivation layer 302 and gate passivation layer 301 to form source via 304 and drain via 310 respectively. Source via 304 and drain via 310 reach the surfaces of source ohmic contact electrode 305 and drain ohmic contact electrode 311 respectively. (10) A source interconnect metal electrode 303 and a drain interconnect metal electrode 309 are deposited on the passivation layer 302. The source interconnect metal electrode 303 is electrically connected to the source ohmic contact electrode 305 through the source via 304, and the drain interconnect metal electrode 309 is electrically connected to the drain ohmic contact electrode 311 through the drain via 310.

[0055] Example 2 like Figure 2 As shown, this embodiment is basically the same as embodiment 1, except that the insulating layer 401 is removed in this embodiment, and a gate layer 307 (made of p-type doped PGaN or metal) is placed on the barrier layer 203. The gate layer is spaced apart from the source ohmic contact electrode and the drain ohmic contact electrode, and the gate field plate 308 is positioned at one end near the drain ohmic contact electrode 311 (corresponding to...). Figure 1 The right end of the gate layer 307 extends beyond the end of the gate layer 307 closest to the drain ohmic contact electrode 311 (corresponding to the right end of the gate layer 307). Figure 1 (The right end of the middle).

[0056] Comparative Example 1 like Figure 3 As shown, this comparative example is basically the same as Example 1, except that the passivation layer 302 in this comparative example also has a second gate field plate 313 (FP2) and a third gate field plate 314 (FP3).

[0057] Test case The HEMT devices of Example 1 and Comparative Example 1 were subjected to a turn-off withstand voltage test (gate-source voltage less than the threshold voltage, gate-drain voltage with a bias of 0-3000V). The test results are as follows. Figure 4 As shown, where Figure 4 (a) shows the turn-off withstand voltage test results of the HEMT device in Example 1, where Figure 4 (b) shows the turn-off withstand voltage test results of the HEMT device in Comparative Example 1.

[0058] from Figure 4 It can be seen that the HEMT device with a single field plate structure (FP1) of the present invention has the same level of withstand voltage as the HEMT device with a three field plate structure (FP1 / FP2 / FP3) in Comparative Example 1, but its structure is simple and easy to implement.

Claims

1. A HEMT power device based on a single field plate, characterized in that, include: Substrate (1); The epitaxial layer (2) includes a buffer layer (201), a channel layer (202) and a barrier layer (203) sequentially disposed on the substrate in a direction away from the substrate (1). A source ohmic contact electrode (305) is disposed on the channel layer (202) and forms a source ohmic contact with the two-dimensional electron gas between the barrier layer (203) and the channel layer (202); A drain ohmic contact electrode (311) is disposed on the channel layer (202) and forms a drain ohmic contact with the two-dimensional electron gas between the barrier layer (203) and the channel layer (202); An insulating layer (401) or a gate layer (307) is disposed on the barrier layer (203), and the gate layer is disposed at a distance from the source ohmic contact electrode (305) and the drain ohmic contact electrode (311); A gate passivation layer (301) is disposed on the insulating layer (401) or covers the gate layer (307). A gate opening (306) extends through the gate passivation layer (301) to the insulating layer (401) or the gate layer (307). A gate field plate (308) is disposed on the gate passivation layer (301) and located between the source ohmic contact electrode (305) and the drain ohmic contact electrode (311). The gate field plate (308) covers and fills the gate opening (306) and forms a Schottky contact with the gate passivation layer (301). The end of the gate field plate (308) near the drain ohmic contact electrode (311) extends beyond the end of the gate opening (306) near the drain ohmic contact electrode (311). The gate passivation layer (301) is formed on the barrier layer (203) by depositing SiN and / or SiO2 on the barrier layer (203) by low-pressure chemical vapor deposition (LPCVD), inductively coupled plasma-chemical vapor deposition (ICPCVD), or plasma-enhanced chemical vapor deposition (PECVD).

2. The HEMT power device based on a single field plate according to claim 1, characterized in that, The contact resistance of the source ohmic contact electrode (305) and the drain ohmic contact electrode (311) is less than 1 ohm*mm; and / or The distance between the gate opening (306) and the barrier layer (203) is 3nm-60nm; and / or The length of the end of the gate field plate (308) near the drain ohmic contact electrode (311) extending beyond the end of the gate opening (306) near the drain ohmic contact electrode (311) is 2μm-10μm. The thickness of the gate passivation layer (301) is 100-500 nm.

3. The HEMT power device based on a single field plate according to claim 1, characterized in that, The HEMT power device based on a single field plate also includes a device isolation region (312), which is located outside the active region. The formation of the device isolation region (312) includes implanting F or N ions into the epitaxial layer (2) by ion implantation or etching the epitaxial layer (2).

4. The HEMT power device based on a single field plate according to claim 3, characterized in that, The ion implantation depth or etching depth of the isolation region (312) of the device reaches the buffer layer (201).

5. The HEMT power device based on a single field plate according to claim 3, characterized in that, The HEMT power device based on a single field plate further includes a passivation layer (302), which is disposed on the gate passivation layer (301) and covers the source ohmic contact electrode (305), the drain ohmic contact electrode (311), the gate field plate (308), and the device isolation region (312).

6. The HEMT power device based on a single field plate according to claim 5, characterized in that, The passivation layer (302) has a thickness of 100nm-6000nm; and / or The HEMT power device based on a single field plate also includes: A source via (304) penetrates the passivation layer (302) and the gate passivation layer (301) to reach the surface of the source ohmic contact electrode (305); Drain via (310), the drain via (310) penetrates the passivation layer (302) and the gate passivation layer (301) to reach the surface of the drain ohmic contact electrode (311); A source interconnect metal electrode (303) is disposed on the passivation layer (302) and is electrically connected to the source ohmic contact electrode (305) through the source via (304); A drain interconnect metal electrode (309) is disposed on the passivation layer (302) and is electrically connected to the drain ohmic contact electrode (311) through the drain via (310).

7. The HEMT power device based on a single field plate according to claim 6, characterized in that, The insulating layer (401) is made of the same material and formed in the same way as the gate passivation layer (301), or SiN is formed by in-situ growth; and / or The substrate (1) is made of Si, SiC, or sapphire; and / or The material of the buffer layer (201) includes one or more of AlN, GaN, and AlGaN; and / or The channel layer (202) is made of one or more of AlN, GaN, InGaN, InAlN, InAlGaN, and AlGaN; and / or The material of the barrier layer (203) includes one or more of AlGaN, AlN, InAlN, and InAlGaN; and / or The passivation layer (302) is made of one or more of SiN, SiO2, and SiON, or one or more of AlN, Al2O3, and AlON; and / or The source interconnect metal electrode (303) is made of one or more of the following materials: Ti, Al, Au, TiN, Ta, TaN, Cu, and AlCu; and / or The source ohmic contact electrode (305) is made of one or more of Ti, Al, and TiN; or one or more of Ti, Al, Ni, Au, and Mo; or one or more of Ta, Al, and TaN; and / or The material of the gate field plate (308) includes one or more of Ti, Al, AlCu, TiN, Ni, Pt, Au, Ir, Ru, Ta, TaN, W, Zr, Mo, Rh, Pd, Pb, Os, Cu, Ag, and ITO; and / or The material of the drain ohmic contact electrode (311) includes one or more of Ti, Al and TiN, or one or more of Ti, Al, Ni, Au and Mo, or one or more of Ta, Al and TaN; and / or The material of the drain interconnect metal electrode (309) includes one or more of Ti, Al, Au, TiN, Ta, TaN, Cu and AlCu.

8. A method for fabricating a HEMT power device based on a single field plate, characterized in that, include: A substrate (1) and a buffer layer material, a channel layer material and a barrier layer material are provided. The buffer layer material, the channel layer material and the barrier layer material are sequentially disposed on the substrate (1) to form a buffer layer (201), a channel layer (202) and a barrier layer (203). Source ohmic contact electrode material and drain ohmic contact electrode material are provided and respectively disposed on the barrier layer (203) to form source ohmic contact electrode (305) and drain ohmic contact electrode (311), and the source ohmic contact electrode (305) and the drain ohmic contact electrode (311) form ohmic contacts with the two-dimensional electron gas between the barrier layer (203) and the channel layer (202); An insulating layer material or p-type doped PGaN is provided and disposed on the barrier layer (203) to form an insulating layer (401) or a gate layer (307), wherein the gate layer is disposed at a distance from the source ohmic contact electrode (305) and the drain ohmic contact electrode (311); SiN and / or SiO2 are provided, and the SiN and / or SiO2 are disposed on the insulating layer (401) or covered on the gate layer (307) by low-pressure chemical vapor deposition (LPCVD), inductively coupled plasma-chemical vapor deposition (ICPCVD), or plasma-enhanced chemical vapor deposition (PECVD) to form a gate passivation layer (301). The gate passivation layer (301) is etched to form a gate opening (306), and the gate opening (306) penetrates the gate passivation layer (301) to reach the insulating layer (401) or the gate layer (307). A gate field plate material is provided and disposed on the gate passivation layer (301) to form a gate field plate (308) between the source ohmic contact electrode (305) and the drain ohmic contact electrode (311), and the gate field plate (308) covers and fills the gate opening (306) and forms a Schottky contact with the gate passivation layer (301).

9. The method for fabricating a HEMT power device based on a single field plate according to claim 8, characterized in that, The insulating layer material is provided and disposed on the barrier layer (203) to form an insulating layer (401), comprising: Provide SiN and / or SiO2, and deposit the SiN and / or SiO2 on the barrier layer (203) by low-pressure chemical vapor deposition (LPCVD), inductively coupled plasma-chemical vapor deposition (ICPCVD), or plasma-enhanced chemical vapor deposition (PECVD), or deposit the SiN on the barrier layer (203) by in-situ growth to form an insulating layer (401); and / or The preparation method further includes: F or N ions are provided and injected into the buffer layer (201), the channel layer (202), and the barrier layer (203) outside the active region to form a device isolation region (312); or The buffer layer (201), the channel layer (202) and the barrier layer (203) are etched to form a device isolation region (312).

10. The method for fabricating a HEMT power device based on a single field plate according to claim 9, characterized in that, Also includes: A passivation layer material is provided and disposed on the gate passivation layer (301) to form a passivation layer (302), the passivation layer (302) covering the source ohmic contact electrode (305), the drain ohmic contact electrode (311), the gate field plate (308) and the device isolation region (312). The passivation layer (302) and the gate passivation layer (301) are etched to form a source via (304) and a drain via (310). The source via (304) and the drain via (310) penetrate the passivation layer (302) and the gate passivation layer (301) to reach the surfaces of the source ohmic contact electrode (305) and the drain ohmic contact electrode (311), respectively. Source interconnect metal electrode material and drain interconnect metal electrode material are provided and disposed on the passivation layer (302) respectively, and form source interconnect metal electrode (303) and drain interconnect metal electrode (309) respectively. The source interconnect metal electrode (303) is electrically connected to the source ohmic contact electrode (305) through the source via (304), and the drain interconnect metal electrode (309) is electrically connected to the drain ohmic contact electrode (311) through the drain via (310).

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