Semiconductor device

Abstract

The invention provides a semiconductor device which can more stably realize high withstand voltage. On the surface of the withstand voltage improvement region between the high-potential region and the low-potential region, there are provided: a plurality of field plates (31) which are formed so as to face the surface with an insulating layer therebetween, are formed so as to be arranged between the high-potential region and the low-potential region so as to be capacitively coupled with each other, and extend in a direction intersecting the arrangement direction; a p-type auxiliary semiconductor region (15) that is locally provided on the surface of an n-type first semiconductor region constituting the withstand voltage improvement region so as to correspond to the field plate (31); and a connection electrode (33) that connects the auxiliary semiconductor region (15) and the corresponding field plate (31).

Description

Technical Field

[0001] This disclosure relates to a semiconductor device having a structure that suppresses electric field concentration by using a field plate structure. Background Technology

[0002] In lateral power semiconductor devices, voltage-enhancing structures are used in the terminal regions formed between the drain and gate, and around the semiconductor substrate where power semiconductor elements (IGBTs, etc.) are formed. These structures are used to suppress local increases in electric field strength and homogenize the electric field strength as the depletion layer extends laterally, thereby improving the voltage withstand. Field plates are sometimes used as such structures.

[0003] Such a structure is described in Patent Documents 1 and 2. In Patent Documents 1 and 2, multiple field plates (first field plate: a conductive layer facing the surface of a semiconductor layer separated by an insulating layer) are arranged between the high-potential side and the low-potential side above the drift layer in a lateral MOSFET. Each first field plate is electrically insulated from the others. Furthermore, sometimes the first field plate on the highest potential (e.g., drain) side is connected to a high-potential electrode, and the first field plate on the lowest potential (e.g., gate) side is connected to a low-potential electrode. The other first field plates are, for example, all floating. Furthermore, on the upper side between these first field plates, second field plates are similarly arranged and formed with an insulating layer in between. The second field plates are also similarly all floating. In this structure, the first field plates or the second field plates are capacitively coupled to each other or between the first and second field plates, and the high-potential electrode is also capacitively coupled to the first or second field plate, and the low-potential electrode is also capacitively coupled to the first or second field plate. Therefore, the field plate as a whole, including the first and second field plates, is capacitively coupled to both the high-potential electrode and the low-potential electrode. In the structure described in Patent Document 2, each field plate surrounds the drain region in a concentric ring. Furthermore, a protective film (insulating layer) covers the top of the field plates to ensure the floating state of each field plate.

[0004] When using the aforementioned field plates, the surface potential of the semiconductor layer directly beneath the field plate is affected by the potential of the field plate above it. Therefore, by forcibly adjusting the surface potential to be identical under a common field plate, local increases in electric field strength are suppressed. In particular, when a double-layer field plate arrangement is used as described above, the exposed surface of the semiconductor layer is reduced by being covered by the field plate when viewed from above, and the capacitance between the field plates is easily adjusted. Therefore, the surface potential difference of the semiconductor layers is divided into appropriate intervals, resulting in a particularly significant improvement in breakdown voltage.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2010-157760

[0006] Patent Document 2: Japanese Patent No. 3275964

[0007] In the above structure, for example, when impurity ions are adsorbed onto the surface protective film from the outside, the potential of the field plate, which has a non-fixed potential, can sometimes be affected by this charge. As a result, the surface potential of the semiconductor layer is also affected by this charge, resulting in a situation where the surface potential of the semiconductor layer cannot be properly segmented as described above.

[0008] Therefore, there is a desire for more stable high-voltage-resistance semiconductor devices. Summary of the Invention

[0009] This disclosure was made in view of the aforementioned problems, and its purpose is to provide a semiconductor device that solves the aforementioned problems.

[0010] In order to solve the above-mentioned problems, this disclosure adopts the following structure.

[0011] The semiconductor device disclosed herein has, on the surface of a breakdown voltage improvement region between a high-potential region (a region connected to an electrode on a high-potential side) and a low-potential region (a region connected to an electrode on a low-potential side) in a semiconductor substrate, the following: a plurality of field plates, each formed opposite to the surface with an insulating layer in between, arranged in a manner capacitively coupled between the high-potential and low-potential regions, and extending along a direction intersecting the arrangement direction; an auxiliary semiconductor region of a second conductivity type, which is partially disposed on the surface of a first semiconductor region of a first conductivity type constituting the breakdown voltage improvement region, corresponding to the field plates, wherein the second conductivity type is opposite to the first conductivity type; and a connecting electrode connecting the auxiliary semiconductor region and the corresponding field plate.

[0012] Alternatively, the field plate disposed on the high-potential region side can be connected to the electrode on the high-potential side, or the field plate disposed on the low-potential region side can be connected to the electrode on the low-potential side.

[0013] Alternatively, when viewed from above, the ratio of the length of the auxiliary semiconductor region along the extension direction of the field plate to the length of the field plate is less than 1 / 10.

[0014] Alternatively, the auxiliary semiconductor regions corresponding to three or more different field plates may not be arranged in a straight line when viewed from above.

[0015] Alternatively, the auxiliary semiconductor region may be provided in the area where the field plate is partially cut out in the extending direction of the field plate.

[0016] Alternatively, the plurality of field plates may be configured to include: a first field plate group consisting of a plurality of first field plates arranged separately as field plates when viewed from above; and a second field plate group consisting of second field plates, each of which is formed between two adjacent first field plates to be capacitively coupled to the two first field plates respectively.

[0017] Alternatively, an insulating layer may be placed above the first field plate, and a metal plate may be placed between the first field plate and the insulating layer. The auxiliary semiconductor region may not be disposed on the surface of the first semiconductor region directly below the metal plate.

[0018] Alternatively, the metal plate can be connected to either the electrode on the high-potential side or the electrode on the low-potential side.

[0019] Because this disclosure is configured as described above, it is possible to obtain a semiconductor device that stably achieves high voltage resistance. Attached Figure Description

[0020] Figure 1 This is a plan view showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0021] Figure 2 This is a cross-sectional view of the first part of the semiconductor device according to an embodiment of the present disclosure.

[0022] Figure 3 This is a top view showing a partially enlarged portion of the semiconductor device according to an embodiment of the present disclosure.

[0023] Figure 4 This is a cross-sectional view of the second part of the semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 5 This is a cross-sectional view of the third part of the semiconductor device according to an embodiment of the present disclosure.

[0025] Figure 6 This is a plan view illustrating an example of the configuration of an auxiliary semiconductor region in a semiconductor device according to an embodiment of the present disclosure.

[0026] Figure 7 This is a partially enlarged top view of a portion of a first modified example of the semiconductor device according to the present disclosure.

[0027] Figure 8 This is a cross-sectional view of a first modified example of a semiconductor device according to an embodiment of the present disclosure.

[0028] Figure 9 This is a cross-sectional view of a second modified example of the semiconductor device according to an embodiment of the present disclosure.

[0029] Figure 10 This is a cross-sectional view of a third variation of the semiconductor device according to an embodiment of the present disclosure.

[0030] Figure 11 This is a cross-sectional view of a fourth variation of the semiconductor device according to an embodiment of the present disclosure.

[0031] Figure 12 This is a cross-sectional view of the fifth variation of the semiconductor device according to the present disclosure.

[0032] Figure 13 This is a plan view of the sixth modified example of the semiconductor device according to the present disclosure.

[0033] Figure 14 The results were obtained by simulating the current-voltage characteristics of an existing semiconductor device (a) and a sixth variation (b) of the semiconductor device according to the present disclosure.

[0034] Figure 15 This is a cross-sectional view of the seventh variation of the semiconductor device according to the present disclosure.

[0035] Label Explanation

[0036] 1-6: Semiconductor device; 11: p-layer (substrate); 12: n-layer (first semiconductor region); 13, 14, 63: n + Layer; 15:p + 16: p-layer (auxiliary semiconductor region); 17: n-layer (first semiconductor region); + 18: p-layer (body layer); 21, 72: source electrodes; 22, 71: gate electrodes; 23, 73: drain electrodes; 31: first field plate (field plate); 32: second field plate (field plate); 33, 82, 93: connection electrodes; 41: first insulating layer; 42: second insulating layer; 51, 51A, 51B: cover metal; 61: n-layer (first semiconductor region); 62: p-layer; 64: termination region; 65: p-layer (body layer); + Layer (auxiliary semiconductor region); 66:p + Layer; 74: Terminal electrode; 81, 91: Field plate; 211: Source electrode wiring section; 212: Source electrode connection section; 231: Drain electrode wiring section; 232, 233: Drain electrode connection section; 221: Gate electrode opposing section; 222: Gate electrode wiring section; 223: Gate electrode connection section; 331, 931: Connection electrode wiring section; 332, 333, 932, 933: Connection electrode connection section; CR: Connection area; D: Drain (high potential side area); DP, X2: Withstand voltage improvement area; G: Gate; S: Source (low potential side area); T: Trench; X1: Component area. Detailed Implementation

[0037] The semiconductor device according to embodiments of the present disclosure will now be described. Furthermore, in the following drawings, the same or similar parts are labeled with the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of lengths of various parts, etc., may differ from reality. Therefore, specific dimensions should be determined by referring to the following description. In addition, the drawings naturally include parts with different dimensional relationships and proportions. Furthermore, the embodiments shown below exemplify apparatuses used to embody the technical concept of the present disclosure, and the technical concept of the present disclosure does not limit the shape, structure, arrangement, etc., of structural components to the following content. Various modifications can be made to the embodiments of the present invention in the claims. In addition, in this disclosure, terms such as "upper" and "lower" are used for convenience of description, and even when disposed on a side surface, as long as they are substantially the same as the structural elements of the present disclosure, they are also within the scope of the present disclosure. Furthermore, "upper" includes not only the case formed in contact with the object but also the case formed with other layers in between. Furthermore, in this disclosure, "connection" is not limited to direct connection. Even if a component such as a resistor is inserted between the two components, as long as the structural elements are substantially the same as those in this disclosure, it is still within the scope of this disclosure.

[0038] The semiconductor device 1 is a lateral MOSFET (LDMOSFET). Figure 1 A general outline of its planar structure is shown. Here, the drain D is located at the center, and the gate G and source S surround the drain D to form a ring around it. Additionally, planar regions in the semiconductor substrate that function as the drain (D: high-potential side region), gate (G: low-potential side region), and source (S) are shown here; these regions do not necessarily correspond to the planar shapes of the drain electrode, gate electrode, and source electrode, respectively. Here, the surface side of the semiconductor substrate between the gate G and the drain D becomes the drift layer of the MOSFET. When turned off, this becomes the breakdown voltage improvement region DP, in which a depletion layer is formed laterally (between the gate G and the drain D) within the drift layer. It is necessary to suppress the generation of regions with localized increases in electric field intensity within the breakdown voltage improvement region DP to improve the breakdown voltage of the semiconductor device 1 when turned off.

[0039] Figure 2 This is the main part of the semiconductor device 1 that corresponds to the drift layer (damping improvement region DP). Figure 1 A cross-sectional view perpendicular to the plane of the paper along the AA direction. In this semiconductor device 1, an n-layer (first semiconductor region) 12, which serves as a drift region, and a p-layer 18, which serves as a body layer for generating channels, are formed in the p-layer 11, which serves as a p-layer that ... + Layer 13. In n +Layer 13 connects to the active electrode 21, and a gate electrode 22 is formed on the p-layer 18, separated by a thin gate oxide film. Furthermore, an n-layer is formed on the n-layer 12, separate from the gate electrode 22. + Layer 14, in n + Layer 14 is connected to drain electrode 23.

[0040] At gate electrode 22 and n + Between layers 14, a first field plate 31 of the first layer and a second field plate 32 of the second layer are formed, respectively surrounded by a first insulating layer 41. Similar to the structure described in Patent Document 2, when viewed from above, the end portions of the second field plate 32 overlap with the end portions of the first field plates 31 on both sides in an opposing manner. Therefore, in Figure 2 In this structure, at least one of the adjacent first field plates 31 or second field plates 32, or between the first field plate 31 and the second field plate 32, is capacitively coupled. Furthermore, the first field plate 31 and the second field plate 32 are in a floating state; however, it is also possible that the leftmost (drain-side) first field plate 31 or second field plate 32 in the figure is connected to the drain electrode 23, and the rightmost (gate-side) first field plate 31 or second field plate 32 in the figure is connected to the gate electrode 22. The first field plate 31 and the second field plate 32 are, for example, both made of conductive polysilicon with a high concentration of impurities. Thus, the multiple field plates used here are divided into a first field plate group composed of the first field plate 31 and a second field plate group composed of the second field plate 32. Regarding the above aspects, it is the same as the technology described in Patent Document 2. In addition, this includes the sectional views described later, in which, for ease of explanation, each field plate and its associated structural elements (described later) are depicted differently from the actual plates. + The number of layers (e.g., 15).

[0041] Furthermore, the source electrode 21 consists of an upper portion, namely the source electrode wiring portion 211, which functions as a source electrode wiring, and a lower portion that is connected to n. + The via wiring portion connected to layer 13 constitutes the source electrode connection portion 212. Similarly, the drain electrode 23 consists of a drain electrode wiring portion 231 and a drain electrode connection portion 232 (connected to n...). +The p-layer 14 is connected to the drain electrode 233 (the portion connected to the leftmost first field plate 31). The gate electrode 22 is composed of the portion opposite to the p-layer 18, namely the gate electrode opposing portion 221, the gate electrode wiring portion 222, and the gate electrode connection portion 223. The gate electrode 22 is connected to the rightmost first field plate 31 outside the area shown in the figure. The source electrode connection portion 212, the gate electrode opposing portion 221, the gate electrode connection portion 223, the drain electrode connection portion 232, the drain electrode connection portion 233, the first field plate 31, and the second field plate 32 are formed in the lower layer side of the first insulating layer 41. On the other hand, the upper source electrode wiring portion 211, the drain electrode wiring portion 231, and the gate electrode wiring portion 222 are formed in the upper side of the first insulating layer 41 of the second insulating layer 42. The second insulating layer 42 functions as a surface protective film.

[0042] Figure 3 It is Figure 1 A magnified plan view of region X, specifically showing only the first field plate 31, the second field plate 32, and p (described later). + The auxiliary semiconductor region 15, the connecting electrode connection portion 332, the connecting electrode connection portion 333, and related structures are included. Here, the first field plate 31 and the second field plate 32 are both connected to... Figure 1 The gate (G) and source (S) are similarly formed into a ring surrounding the drain (D). Figure 3 Within the range shown, they extend parallel to the vertical direction in the diagram. In this direction of extension, p + Layer 15 is shorter than the first plate 31 and the second plate 32. Figure 2 cross section and Figure 3 BB direction (without p set) + The cross-sections of layer 15 and the connecting electrode connection parts 332 and 333 correspond to each other.

[0043] For example, p + Width of layer 15 ( Figure 4 The length in the left-right direction is narrower than the width of the first plate 31, p + The depth of layer 15 can be related to n + Layer 13, n + Layer 14 is equal to or comparable to other semiconductor devices such as p-type MOSFETs. + The contact areas are formed simultaneously at the same depth. This can also increase the impurity concentration in layer n, making p... + The depth of layer 15 is greater than n + Layer 13, n + Layer 14 is deep.

[0044] exist Figure 3In the middle, there is a region (connecting region CR) where the first field plate 31 is partially removed and does not exist in the extension direction of the first field plate 31. The connecting region CR is in Figure 3 Arranged horizontally along the center. Figure 4 This is a cross-sectional view along the CC direction, including the connecting region CR. Within the connecting region CR, a p-shaped area is locally formed directly below the region where the first field plate 31 does not exist. + Layer (auxiliary semiconductor region) 15. In addition, a layer related to p is provided. + The connecting electrode 33 connected to layer 15 Figure 4 With p + The cross-section of the part where layer 15 is connected to connecting electrode 33 (connecting electrode connecting part 332) corresponds.

[0045] The connecting electrode 33 is at a distance p + The first plate 31 of layer 15 is connected. Figure 5 It is a sectional view of the part that connects them. Figure 3 A cross-sectional view along the EE direction. For example... Figure 3 As shown, the connecting area CR is sandwiched between the two sides in the circumferential direction. Figure 3 (The top and bottom of the paper), connecting electrode 33 and distance p + The first field plate 31 near layer 15 is connected. The connecting electrode 33 has a connecting electrode wiring portion 331, which is as follows: Figure 4 , Figure 5 As shown, it is disposed on the first insulating layer 41 (in the second insulating layer 42); and the connecting electrode connection portion 332, which is as follows Figure 4 As shown, it becomes a connection p + Through-hole wiring of layer 15 and connecting electrode wiring section 331.

[0046] like Figure 3 , Figure 5 As shown, the connecting electrode wiring portion 331 is not only within the connecting region CR, but also extends beyond the connecting region CR along the circumference of the first field plate 31. Figure 3 The connection area (extended vertically in the diagram) is connected to the first field plate 31 via a connection electrode connection portion 333, which serves as a via wiring. The connection area CR, partially removed from the first field plate 31, is configured such that the connection electrode 33 (connection electrode wiring portion 331) is positioned above the first field plate 31 and connected to it, thereby achieving the above structure. If the connection electrode connected to the auxiliary semiconductor region is formed on the lower side of the first field plate, and if the first field plate is formed to cover this connection electrode, then the partially removed area of ​​the first field plate is unnecessary. That is, the relationship between the auxiliary semiconductor region, the connection electrode, and the first field plate is as follows, except... Figure 3 It can also be implemented in structures other than the one described above.

[0047] exist Figure 4 , Figure 5 In this process, each connection portion (connection electrode connection portion 333, drain electrode connection portions 232, 233, gate electrode connection portion 223, source electrode connection portion 212) and each wiring portion (connection electrode wiring portion 331, drain electrode wiring portion 231, gate electrode wiring portion 222, source electrode wiring portion 211) can be formed as the same metal layer.

[0048] For the above p + The functions of layer 15 and connecting electrode 33 will be explained. When semiconductor device 1 is turned off, the depletion layer generated in n-layer 12 extends from the boundary between p-layer 11 and p-layer 18. When the depletion layer reaches p... + In the case of layer 15, the depleted layer is also in p. + The interface between layer 15 and layer n, 12, is extended; however, p + Layer 15 is set to a concentration that is not completely depleted. This non-depleted p + A portion of layer 15 is connected to the connecting electrode 33. Therefore, the potential of the first field plate 31 connected to the connecting electrode 33 is not determined by a potential distribution based on capacitive coupling, but is uniquely determined as a specified potential by the potential structure within the semiconductor. The depletion layer further extends, reaching a point where it connects to n... + adjacent p on layer 14 + When layer 15 is connected to p via connecting electrode 33 + The potential of the first field plate 31 connected to layer 15 is uniquely determined to be a different specified potential than previously defined. The depletion layer further extends, reaching a potential different from n... + adjacent p on layer 14 + When layer 15 is connected to p via connecting electrode 33 + The potential of the first field plate 31 connected to layer 15 is uniquely determined to be a different specified potential than previously defined. This process is repeated.

[0049] Furthermore, it is preferable that the connecting electrode 33 can be connected to p + The degree of connection of layer 15 forms p within a relatively narrow range compared to layer n, 12. + Layer 15 has a smaller impact on the depletion layer that extends in layer 12 (n layers). Furthermore, to prevent p... + Layer 15 is completely depleted, and its impurity concentration is significantly higher than that of layer n, 12, for example, set to 1 × 10⁻⁶. 19 cm -3 Above and 5×10 21 cm -3 the following.

[0050] p reached from the depletion layer extending within layer n, 12 +The potential of the first field plate 31, extracted from layer 15, is uniquely determined. Therefore, even if impurity ions (foreign ions) are adsorbed onto the second insulating layer 42 from the outside of the semiconductor device 1, the potential of the uniquely determined first field plate 31 is less affected, resulting in a potential distribution with less impact compared to the case where impurity ions (foreign ions) are not adsorbed from the outside. That is, the effect of increasing the withstand voltage of the semiconductor device 1 can be stably maintained. Here, p + Layer 15 preferred and distance p + The first field plate 31 on the high-voltage side of layer 15 is electrically connected. As a result, the potential of the first field plate 31 on the high-voltage side affects the surface potential of the semiconductor layer, which can cause the depletion layer on the surface side of the semiconductor layer to extend further towards the high-voltage side, thereby stably maintaining the effect of further improving the withstand voltage of the semiconductor device 1.

[0051] exist Figure 3 In the structure, p + Layer 15 (the area where the local potential is extracted) is located horizontally in the figure ( Figure 1 The drain (D) and gate (G) are aligned in a straight line. + The configuration of layer 15 can be set appropriately. Figure 6 Is Figure 1 p is shown in the structure + The diagram shows the location of layer 15, with the dashed lines schematically indicating that each of the first field plates 31 (or second field plates 32) surrounds the drain D. The shape of each of the first field plates 31 (or second field plates 32) is set to be approximately annular. Figure 6 p of (a) + Layer 15 is arranged in a straight line between the drain (D) and the gate (G).

[0052] exist Figure 6 In case (a), due to the adjacent p + Layer 15 is close, therefore it may affect the expansion of the depletion layer generated in layer n, layer 12. In contrast, as... Figure 6 As shown in (b), in order to make adjacent p + The way the spacing between layers 15 is increased is to make p + The dispersed configuration of layer 15 in the drain (D)-gate (G) direction will cause p + When layers 15 are arranged in an alternating pattern, this effect can be reduced. Furthermore, as... Figure 6 As shown in (c), when the overall shape is circular, each p can also be made + Layer 15 is distributed in a circumferential and / or radial manner and connected to each of the first field plates 31.

[0053] In addition, such as Figure 6 As shown in (d), each p can also be made along the first field plate 31 (or the second field plate 32).+ Layer 15 is a concentric ring surrounding the drain (D). Here, the connecting electrodes 33 can also be arranged in a ring shape, similar to each p+ layer 15, and can be arranged as one or evenly spaced at 4, 6, 8, or dozens of locations along the circumference of the first field plate 31. Each p+ layer is arranged in a ring shape surrounding the drain (D). + Layer 15, with the first field plate 31 (or the second field plate 32) and p + Layer 15 is electrically connected via connecting electrode 33, thereby preventing further impact on the potential of the first field plate 31, even if impurity ions (foreign ions) are adsorbed onto the second insulating layer 42 from the outside of the semiconductor device 1. That is, the effect of improving the withstand voltage of the semiconductor device 1 can be maintained more stably. Furthermore, in this case, p + Layer 15 can be formed unevenly on the entire circumference of a ring shape, or it can be truncated along the circumference.

[0054] In addition, Figure 6 of (a), Figure 6 In (b), each p + Layer 15 is only located in the right region of the drain (D) in the figure; however, each p can also be placed in the right region. + Layer 15 is disposed above, to the left, and below the drain (D) in the figure. Furthermore, in the extension direction of the first field plate 31 (or the second field plate 32), p... + Layer 15 is shorter than the first field plate 31 and the second field plate 32, so that the p-value occupied by the first field plate 31 and the second field plate 32 is... + Layer 15 is smaller, for example, less than 1 / 10, more preferably less than 1 / 100.

[0055] In addition, Figure 6 In (a) to (d), in the radial direction from the drain (D) towards the gate (G), p + Layer 15 can also be configured with unequal intervals. For example, p + The spacing of layer 15 can be progressively widened or progressively narrowed. Furthermore, the spacing can be wider near the midpoint between the drain (D) and gate (G), and progressively narrowed towards at least one side of the drain (D) side or the gate (G) side. Additionally, it is not necessary to provide a p-connected to each of all the first field plates 31. + Layer 15 can also be repeatedly applied to p in a radial direction from the drain (D) towards the gate (G). + Layer 15 connects to one or more groups of the first field plate 31 and is not related to p + Layer 15 connects to one or more groups of the first field plate 31.

[0056] A variation of the semiconductor device 1 described above will be described. In the semiconductor device 1 described above, such as... Figure 3 As shown, a first field plate 31 and a second field plate 32 are provided, and p corresponds to the first field plate 31. + Layer 15 connection. Here, a connection region CR is provided where the first field plate 31 is partially cut off, and here, p is provided. + Layer (auxiliary semiconductor region) 15, connecting electrode 33. In contrast, in... Figure 7 , Figure 8 In the semiconductor device 2 of the first modified example shown, only one type of field plate 91 corresponding to the first field plate 31 is used. That is, the second field plate 32 is not provided, and multiple types of field plates 91 are separately arranged in the radial direction from the drain (D) to the gate (G), and each field plate 91 is arranged to surround the drain (D) when viewed from above.

[0057] In this case, it is possible to p + Layer 15 is positioned adjacent to field plate 91 when viewed from above, and can be connected to a connecting electrode to p. + Layer 15 and field plate 91. Here, p + Layer 15 preferably uses a connecting electrode to connect with a distance p + The high-voltage side of layer 15 is connected to the field plate 91. Figure 7 This illustrates the planar structure in this case. Figure 3 The corresponding diagram. Furthermore, Figure 8 Is with Figure 7 The sectional view corresponding to the FF direction in the diagram. Here, p + Layer 15 is formed between adjacent field plates 91, and is connected to electrode 93. Figure 7 p in + The left side of layer 15 is connected to the adjacent field plate 91. At this time, it is connected to... Figure 4 , Figure 5 Similarly, the connecting electrode 93 has a connecting electrode wiring portion 931 formed on the upper side of the field plate 91, and a connection electrode wiring portion 931 with p + The connecting electrode connection part 932 connected to layer 15 and the connecting electrode connection part 933 connected to field plate 91.

[0058] Additionally, in this structure, such as Figure 6 As shown in (a), it is sometimes difficult to p + Layer 15 is formed as a column, however, by p + Layer 15 is set as follows Figure 6 The configurations of (b) and (c) can be easily implemented. Figure 7 The structure. Furthermore, making p + Layer 15 is as follows Figure 6The configuration of (d) ensures that, for example, even if impurity ions (foreign ions) are adsorbed from the outside of the semiconductor device 2 onto the second insulating layer 42, the potential of the field plate 91 is less likely to be further affected. That is, the effect of increasing the withstand voltage of the semiconductor device 2 can be maintained more stably. Furthermore, it is not necessary to cut off the field plate 91 as described above for the connection region CR, but... Figure 7 As shown, by p + On both sides of layer 15, the field plate 91 is partially cut off in the width direction, making the field plate 91 locally thinner, and portions that widen the spacing are locally provided in the extension direction, thereby easily realizing this structure. However, even if the width of the field plate 91 is made uniform, p can be formed without problems. + In the case of layer 15 and connecting electrode 93, it is not necessary to locally thin the field plate 91 in this way.

[0059] Next, the second variation will be described. The semiconductor device 1 described above is an LDMOSFET in which the n-layer 12 on the p-layer 11 is set as a drift layer, but it can also be used in a double RESURF structure in which a p-layer is formed on the surface of the drift layer (n-layer 12). Figure 9 This illustrates the structure of the semiconductor device 3, which is a first modified example of this. Figure 4 The corresponding cross-sectional view. Here, a concentration ratio of p is formed on the surface of layer n 12. + Layer 15 has a lower p-layer (voltage resistance improvement region) 16, on which multiple n-layers are locally formed. + Layer (auxiliary semiconductor region) 17, the first field plate 31 is connected to n via connecting electrode 33 + Layer 17 is connected in the same way as described above. In this case, at cutoff, the depletion layer also extends from the interface between layer n 12 and layer p 16. The depletion layer within layer p 16 extends further as the depletion layer reaches layer n. + At layer 17, the depletion layer is also at p layers 16 and n. + The interface of layer 17 is extended, but n + Layer 17 is set to a concentration that is not completely depleted. This is because the connecting electrode 33 is connected to this non-depleted n... + The partial connection of layer 17 ensures that the potential of the first field plate 31, connected to the connecting electrode 33, is uniquely determined as a predetermined potential. When the depletion layer reaches the adjacent n... + When layer 17 is connected to n via connecting electrode 33 + The potential of the first field plate 31 connected to layer 17 is uniquely determined to be a different specified potential than previously defined. + The concentration of layer 17 is, for example, 1×10⁻⁶. 19 cm -3 Above and 5×10 21 cm -3In semiconductor device 3, similarly to semiconductor device 1, even when impurity ions (foreign ions) are adsorbed onto the second insulating layer 42 from the outside, the potential of the uniquely determined first field plate 31 can mitigate this effect, and the potential distribution is performed with relatively small changes compared to the case where impurity ions (foreign ions) are not adsorbed from the outside. That is, the effect of improving the withstand voltage of semiconductor device 3 can be stably maintained.

[0060] Furthermore, in the aforementioned semiconductor devices 1 and 3, each connecting electrode 33 is connected to the first field plate 31 at its respective formation location. However, it is clear that the same effect is achieved when the connecting electrode 33 is connected to the second field plate 32 instead of the first field plate 31. However, if the first field plate 31 is closer to the semiconductor surface than the second field plate 32, then if each connecting electrode 33 is connected to the first field plate 31, the effect of improving the withstand voltage of the semiconductor devices 1 and 3 can be maintained more stably. Alternatively, both a connecting electrode 33 connected to the first field plate 31 and a connecting electrode 33 connected to the second field plate 32 may be provided.

[0061] Alternatively, the same effect can be obtained even if the second field plate 32 is not provided in the structure of the semiconductor devices 1 and 3, but only the field plates 91 are arranged as in semiconductor device 2.

[0062] In the aforementioned semiconductor devices 1 and 3, all the first field plates 31 (or second field plates 32) are connected to p through each connecting electrode 33. + Layer 15 or n + Layer 17 is connected. However, it is not necessary to set p corresponding to all first field plates 31 (or second field plates 32). + Layer 15 or n + Layer 17.

[0063] Figure 10 This illustrates the structure of the semiconductor device 4 in the third modified example. Figure 4 Corresponding cross-sectional view. In this structure, a metal plate (covering metal) 51, composed of a metal layer, is formed on the second insulating layer 42 on the high potential side (left side of the figure) and the low potential side (right side of the figure). + Layer 15 is positioned directly beneath the covering metal 51. Here, p + Layer 15 may not be positioned directly beneath the cover metal 51. Furthermore, the cover metal 51 may be disposed across multiple adjacent first field plates 31 (or second field plates 32). Moreover, the first field plates 31 (or second field plates 32) are not directly beneath the cover metal 51 and are not adjacent to p. + Layer 15 is connected. In this case, since the influence of impurity ions (foreign ions) in the region directly below is suppressed by covering metal 51, p can also be omitted in this region. + Layer 15. As described above, set p+ Layer 15, which may affect the extension of the depletion layer in layer n 12, can mitigate this effect by setting metal plate 51.

[0064] Figure 11 This illustrates the structure of the semiconductor device 5 in the fourth modified example. Figure 4 Corresponding cross-sectional view. In this structure, the same covering metal 51,p as described above, is also formed. + Layer 15 is not positioned directly beneath the covering metal 51. Furthermore, as... Figure 6 As in (a), this structure is similar to p + Layer 15, with connecting electrodes 33 arranged in a row, corresponds to the configuration where they are connected to each of the first field plates 31. Therefore, in Figure 6 In case (a), for all first-field plates 31, there is a corresponding p + Layer 15 (and connecting electrode 33), in contrast, here, p is formed only in three separate locations. + Layer 15, p + Layer 15 is connected to its corresponding first field plate 31 (due to...) Figure 11 It is the cross section of the connecting region CR, therefore in Figure 11 (Not illustrated in the diagram). Therefore, no corresponding p is formed for the other first field plates 31a. + Layer 15, similar to field plates in the prior art, has a first field plate 31a at a floating potential. However, the first field plate 31a is connected to p... + The first field plate 31 of layer 15 is capacitively coupled. Therefore, high voltage withstand capability can also be achieved through this structure. That is, it is not necessary to set p for all first field plates 31. + Layer 15 are interconnected. Here, the structure of semiconductor device 5 is not limited to... Figure 6 (a), even in cases such as Figure 6 As shown in (b), p is applied in the drain (D)-gate (G) direction. + Layer 15, connecting electrodes 33 are arranged in an alternating pattern, such as... Figure 6 p (c) + When layer 15 and connecting electrode 33 are circular in shape, such as... Figure 6 p as shown in (d) + When layer 15 is ring-shaped, it is not necessary to set a p connected to each of the first field plates 31. + Layer 15, and no p is set directly below the covering metal 51. + Layer 15.

[0065] In the aforementioned semiconductor devices 4 and 5, the covering metal 51 can be connected to either the source electrode 21 or the drain electrode 23, and can also be at a floating potential. Furthermore, in Figure 11 Alternatively, one or more covering metals 51 may be further provided between the covering metals 51 on the second insulating layer 42. For example, in p + If there are no field plates 31 and 32 directly above layer 15, it can also be set to be p between the covering metal 51. + The structure directly above layer 15 is covered by an additional covering metal. This suppresses the influence of impurity ions (external ions) on p. + The effect of the potential of layer 15.

[0066] Figure 12 This is a cross-sectional view showing the structure of the semiconductor device 6, which is a further modification (the fifth modification) of the fourth modification. Figure 11 In this structure, the cover metal 51 is formed on the second insulating layer 42. However, in this structure, the drain electrode wiring portion 231 in the first insulating layer 41 extends towards the gate (G) side on the first field plate 31a, and a portion of it is provided as cover metal 51A. Furthermore, the gate electrode wiring portion 222 extends towards the drain (D) side on the first field plate 31a, and a portion of it is provided as cover metal 51B. In particular, since the influence of positively charged foreign ions is relatively large, the gate electrode wiring portion 222 on the low potential side is extended on the first field plate 31a, thereby more effectively reducing the influence of foreign ions. Furthermore, in this semiconductor device 6, it is also... Figure 9 Similarly, the semiconductor device 3 is provided with a p-layer (voltage-adjustable region) 16, and a plurality of n-layers are locally disposed on the p-layer 16. + As described above, layer (auxiliary semiconductor region) 17 may not have a p-type layer directly below the cover metal 51. + Layer 15, n + Layer 17, therefore, does not require an auxiliary semiconductor region corresponding to all of the first field plates 31, and can thus be appropriately omitted. Figure 9 p in + Layer 15, n + Floor 17. Figure 12 Alternatively, one or more covering metals may be added between the covering metals 51A and 51B and the connecting electrode 33, or between adjacent connecting electrodes 33.

[0067] In the aforementioned semiconductor devices 3 to 6, such as Figure 6 As in (a), it shows that p + In the example where layer 15 is arranged in a straight line, and assuming that a p is set and connected for a first field plate 31 (selected in the semiconductor device 4, etc.) + Layer 15. However, p + Layer 15 can also be connected to a single field plate in multiple locations.

[0068] For example, Figure 13 This illustrates the structure of the semiconductor device 7 in such a sixth modified example. Figure 6 The corresponding plan view. The cross-sectional structure in this case is similar to... Figure 8 The same. Here, p is only set for a portion of the perimeter. + Part of the 15th layer, the first field plate 31 (3 pieces) is connected to p + Layer 15, other field plates 31a are not related to p + Layer 15 is connected and set to a floating state. But if Figure 13 As shown, p + Layer 15 (and connecting electrodes 33, etc.) is disposed at 8 locations along the circumferential direction for each first field plate 31. That is, based on making the surface potential of these 8 locations the same, this potential becomes the potential of the first field plate 31.

[0069] Figure 14 This is for p that is not connected to the first field plate 31 at all. + In the case of layer 15 (a), a portion of the first field plate 31 is provided with and connected to p connected to the first field plate 31. + Case (b) of layer 15, through simulation Figure 13 The results were obtained by simulating the current-voltage characteristics between the source electrode 21 and the drain electrode 23 in the semiconductor device 7 at cutoff time. Here, in the calculation, it is assumed that p... + Layer 15 lies around the corresponding first field plate 31.

[0070] Here, we show the case where (1) the fixed charge of the foreign ions is not present on the second insulating layer 42, and (2) 1×10 12 cm -2 (3) 1.3×10 12 cm -2 This is the result of the presence of a unit charge. Here, the voltage (horizontal axis) that rises sharply with the current (vertical axis) corresponds to the withstand voltage.

[0071] Based on this result, in the case where the fixed charge is absent (1), the p connected to the first field plate 31 + The case where layer 15 does not exist ( Figure 14 (a) and p which is connected to the first field plate 31 + Case of layer 15 ( Figure 14 There is no significant difference between (b) and (3). However, in the case of a fixed charge (2) and (3), a p connected to the first field plate 31 is provided. + Case of layer 15 ( Figure 14 (b) compared to p connected to the first field plate 31 + The case where layer 15 does not exist ( Figure 14(a) shows that the breakdown voltage is improved. That is, it has been confirmed that the above structure mitigates the breakdown voltage reduction caused by the adsorption of foreign ions onto the semiconductor device, and the above structure is effective in improving the breakdown voltage.

[0072] The examples described above all demonstrate the use of the aforementioned structure in the drift layer of an LDMOSFET. However, this structure can also be used in other semiconductor devices or other parts of a semiconductor device other than the drift layer. For example, such a part may have a termination region, which is formed outside the element region in the case where the power semiconductor element is formed from the element region in the center of the semiconductor substrate. In the termination region, a structure to improve breakdown voltage to suppress electric field concentration during cutoff can also be used, and the aforementioned structure can also be employed. Furthermore, the semiconductor element can be a vertically oriented semiconductor element where the operating current flows longitudinally (in the thickness direction of the semiconductor layer), or a horizontally oriented semiconductor element where the operating current flows laterally (in the width direction of the semiconductor layer).

[0073] Figure 15 (a) and (b) show the structure of semiconductor device 8 (7th variation), which is an example of a vertical semiconductor element such as a MOSFET. Figure 2 , Figure 4 The corresponding cross-sectional view. In semiconductor device 6, in element region X1, a p-layer 62 is formed in the n-layer (first semiconductor region) 61, which serves as the drain side. Furthermore, a trench T is formed penetrating the p-layer 62 from the front side, and a gate electrode 71 is formed in the trench T, separated by a thin gate oxide film. An n-layer, which serves as the source region, is formed on the surface of the p-layer 62 adjacent to the trench T. + Layer 63 and p for contacting layer 62 + Layer 66, in n + Layer 63 and p layer 62 (p + An active electrode 72 is formed on layer 66. A drain electrode 73 is formed on the back side of layer n 61.

[0074] exist Figure 15 In (a), a layer 61 of the withstand voltage improvement region X2 on the outer side of the component region X1 (right side of the figure) is formed as n. + The layer has a terminal region 64 and a terminal electrode 74 connected thereto. Multiple field plates 81 are arranged separately on the n-layer 61 between the source electrode (low-potential side electrode) 72 and the terminal electrode (high-potential side electrode) 74, in a capacitively coupled manner. Each field plate 81 extends perpendicularly to the plane of the paper, and when viewed from above, each field plate 81 and the breakdown voltage improvement region X2 form a region surrounding the element X1.

[0075] The field plate 81, which should be uniquely fixed in potential, is connected to the p electrode disposed on the surface of the n layer 61 via the connecting electrode 82.+ Layer (auxiliary semiconductor region) 65 is connected. Connection electrode 82 functions similarly to connection electrode 33 described above, p + Layer 65 and the above p + Layer 15 functions similarly. Clearly, the same effect as described in semiconductor device 1 can be achieved in semiconductor device 6. At this time, due to the p in the breakdown voltage improvement region X2... + Layer 65 with p in component region X1 + Layer 66, with the same impurity concentration, is also formed at a shallower depth, thus enabling them to be formed simultaneously during the manufacturing process.

[0076] In existing semiconductor devices without a field plate 81, p is used as a guard ring. + The layer is formed in a circumferential, continuous, and relatively deep ring shape surrounding the element region X1 to control the expansion of the depletion layer within the semiconductor layer. In contrast, as described above, p becomes the auxiliary semiconductor region. + Layer 65 is relatively shallow and forms locally.

[0077] However, p can also be formed in a manner that surrounds the element region X1, similar to the protective ring structure. + Layer 65. At this time, p, which is connected to the field plate 81 via connecting electrode 82, can also be used. + One or more p-type electrodes that are not connected to the field plate 81 via the connecting electrode 82 are provided between layers 65. + Floor 65.

[0078] exist Figure 15 In the example, only one layer of the field plate 81 is provided, but the field plate can also be a double-layer structure in the same way as described above. Furthermore, in Figure 9 In the middle, it can also be that p layers 16 and n + The auxiliary semiconductor region 17 is disposed on the surface of the n-layer 12 in such a way that the p-layer (RESURF layer), which is equivalent to the p-layer 16, is formed on the breakdown voltage improvement region X2 of the n-layer 61, which is equivalent to multiple n + n of the auxiliary semiconductor region of layer 17 + The layer is locally formed on the p layer and connected to the n layer via a connecting electrode corresponding to the connecting electrode 33. + Layers and field plates 81.

[0079] Thus, the structure combining the field plates and auxiliary semiconductor regions as described above can be appropriately used in semiconductor devices that have a structure that improves breakdown voltage (suppresses the formation of regions with locally high electric field strength) by forming a depletion layer at cutoff. Furthermore, other layers can be appropriately added or removed in conjunction with this. Moreover, in the above example, it is clear that the same structure can also be applied when all p-type and n-type in the semiconductor are reversed. Furthermore, in the above example, it is clear that the first field plate 31, the second field plate 32, and field plates 81 and 91 may not have the same width, and the adjacent spacing may also be different; the width and spacing can also be appropriately changed in stages.

Claims

1. A semiconductor device, characterized in that, In a semiconductor substrate, the surface of a voltage-enhancing region between a high-potential region (connected to an electrode on the high-potential side) and a low-potential region (connected to an electrode on the low-potential side) has the following characteristics: Multiple field plates, each formed opposite to the surface with an insulating layer between them, are arranged in a manner that allows for mutual capacitive coupling between the high-potential region and the low-potential region, and extend along a direction that intersects the arrangement direction. An auxiliary semiconductor region of a second conductivity type is partially disposed on the surface of the first semiconductor region of the first conductivity type constituting the voltage withstand improvement region, corresponding to the field plate; the second conductivity type is opposite to the first conductivity type; and A connecting electrode is provided, which connects the auxiliary semiconductor region and the corresponding field plate.

2. The semiconductor device according to claim 1, characterized in that, The field plate disposed on the high-potential region side is connected to the electrode on the high-potential side, or the field plate disposed on the low-potential region side is connected to the electrode on the low-potential side.

3. The semiconductor device according to claim 1 or 2, characterized in that, When viewed from above, the length of the auxiliary semiconductor region along the extension direction of the field plate is less than 1 / 10 of the length of the field plate.

4. The semiconductor device according to claim 1 or 2, characterized in that, The auxiliary semiconductor regions corresponding to three or more different field plates are not arranged in a straight line when viewed from above.

5. The semiconductor device according to claim 1 or 2, characterized in that, The auxiliary semiconductor region is provided in the area where the field plate is partially cut out in the extending direction of the field plate.

6. The semiconductor device according to claim 1 or 2, characterized in that, The plurality of field plates are configured to include: The first field plate group consists of a plurality of first field plates arranged separately as field plates when viewed from above; and The second field plate group is composed of second field plates, each of which is formed between two adjacent first field plates to be capacitively coupled to the two first field plates respectively.

7. The semiconductor device according to claim 1 or 2, characterized in that, Above the field plate, separated by an insulating layer, there is a metal plate, and the surface of the first semiconductor region directly below the metal plate does not have the auxiliary semiconductor region.

8. The semiconductor device according to claim 7, characterized in that, The metal plate is connected to either the electrode on the high potential side or the electrode on the low potential side.

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