Gate structure in three-dimensional semiconductor device

Abstract

Devices and systems for gate structures in three-dimensional semiconductor devices are provided. In one aspect, a semiconductor device includes a first transistor, where the first transistor includes a source, a drain, and a gate structure. The gate structure includes a first region and a second region protruding from a first corner of the first region toward the source or drain in a first direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and manufacturing processes for semiconductor devices. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive because they can increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuitry for facilitating the operation of the memory array. Memory cells may include vertical structures. Summary of the Invention

[0003] This disclosure describes methods, apparatus, systems, and techniques for managing vertical structures in three-dimensional (3D) semiconductor devices.

[0004] One aspect of this disclosure is a semiconductor device comprising: a first transistor, wherein the first transistor includes a source, a drain, and a gate structure, and wherein the gate structure includes a first region; and a second region protruding from a first corner of the first region toward the source or the drain in a first direction.

[0005] In some implementations, the first direction is on the line connecting the source and the drain.

[0006] In some embodiments, the first transistor includes a channel structure, the gate structure is between the source and the drain, and the channel structure is on the gate structure in a vertical direction perpendicular to the first direction.

[0007] In some embodiments, the first transistor includes a channel structure, and the gate structure is wider than the channel structure in a second direction perpendicular to the first direction.

[0008] In some implementations, the first distance is in the second direction and extends from the edge of the channel structure to the boundary of the second region, the second distance is in the second direction and extends from the edge of the channel structure to the boundary of the first region, and the first distance is greater than the second distance.

[0009] In some implementations, the first distance is between two points in the first direction and on the boundary of the first region, the second distance is between a point in the first direction and on the boundary of the first region and a point on the boundary of the second region, and the first distance is less than the second distance.

[0010] In some embodiments, the second region protrudes from the first corner of the first region along a second direction perpendicular to the first direction.

[0011] In some embodiments, the gate structure includes a third region protruding from a second corner of the first region.

[0012] In some implementations, the second corner is positioned diagonally relative to the first corner.

[0013] In some embodiments, the semiconductor device includes an additional gate structure adjacent to the gate structure along a second direction perpendicular to the first direction, wherein the additional gate structure includes an additional first region and an additional second region protruding from a first corner of the additional first region, and wherein the first corner of the first region and the first corner of the additional first region are positioned along the second direction.

[0014] In some implementations, the first corner and the second corner are on the same edge of the first region.

[0015] In some embodiments, the semiconductor device includes an additional gate structure adjacent to the gate structure along a second direction perpendicular to the first direction, wherein the additional gate structure includes an additional first region and an additional second region protruding from a first corner of the additional first region, and wherein the first corner of the first region and the first corner of the additional first region are diagonally positioned relative to the first direction and the second direction.

[0016] In some embodiments, the semiconductor device includes an additional gate structure adjacent to the gate structure along the first direction, wherein the additional gate structure includes an additional first region and an additional second region protruding from a first corner of the additional first region, wherein the second corner of the first region lies between the first corner of the first region and the first corner of the additional first region along the first direction, and wherein there is no region protruding from the second corner of the first region.

[0017] In some embodiments, the semiconductor device includes a complementary metal-oxide-semiconductor (CMOS) device, and the first transistor is included in the CMOS device.

[0018] In some implementations, the CMOS device is included in the page buffer.

[0019] Another aspect of this disclosure is a mask for forming a gate structure, wherein the mask includes: a first region; and a second region protruding from a first corner of the first region toward a source or drain associated with the gate structure along a first direction.

[0020] In some embodiments, the second region protrudes from the first corner of the first region along a second direction perpendicular to the first direction.

[0021] In some embodiments, the mask includes a third region protruding from a second corner of the first region.

[0022] In some implementations, the second corner is positioned diagonally relative to the first corner.

[0023] In some embodiments, the mask is included in a layout, wherein the layout includes an additional mask adjacent to the mask along a second direction perpendicular to the first direction, wherein the additional mask includes an additional first region and an additional second region protruding from a first corner of the additional first region, and wherein the first corner of the first region and the first corner of the additional first region are positioned along the second direction.

[0024] In some implementations, the first corner and the second corner are on the same edge of the first region.

[0025] In some embodiments, the mask is included in a layout, wherein the layout includes an additional mask adjacent to the mask along a second direction perpendicular to the first direction, wherein the additional mask includes an additional first region and an additional second region protruding from a first corner of the additional first region, and wherein the first corner of the first region and the first corner of the additional first region are positioned diagonally relative to the first direction and the second direction.

[0026] In some embodiments, the mask is included in a layout, wherein the layout includes an additional mask adjacent to the mask along a second direction perpendicular to the first direction, wherein the additional mask includes an additional first region and an additional second region protruding from a first corner of the additional first region, wherein the second corner of the first region lies between the first corner of the first region and the first corner of the additional first region along the first direction, and wherein there is no region protruding from the second corner of the first region.

[0027] Another aspect of this disclosure is a system comprising: a semiconductor device including a first transistor, wherein the first transistor includes a source, a drain, and a gate structure, and wherein the gate structure includes a first region; and a second region protruding from a first corner of the first region toward the source or the drain in a first direction; and a memory controller electrically connected to the semiconductor device, wherein the memory controller is configured to control the semiconductor device.

[0028] Embodiments of this disclosure may provide one or more of the following technical advantages and / or benefits. For example, in some cases, a gate structure with one or more protruding regions at one or more corners of the gate structure can be formed. The one or more protruding regions allow the size of the gate structure to remain larger than the channel length of the transistor having the gate structure, thereby avoiding transistor leakage. Furthermore, in some cases, the fabrication of the gate structure does not involve removing one or more circular regions at the edges(one or more) of the gate structure. Therefore, the manufacturing cost of the gate structure can be reduced. Additionally, in some cases, by positioning two adjacent gate structures such that their inward corners are adjacent to the protruding regions of another gate structure, the two gate structures can be positioned close to each other while maintaining a safe distance between them. As a result, the density of the active region can be increased, thereby increasing the density of transistors on the semiconductor device.

[0029] This technology can be applied to various types of semiconductor devices, volatile memory devices (such as DRAM memory devices), or non-volatile memory (NVM) devices (such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) (such as phase-change random access memory (PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM)), and so on. It can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices, and floating-gate based memory devices. This technology can be applied to three-dimensional (3D) memory devices. It can be applied to various memory types, such as SLC (single-cell) devices, MLC (multi-cell) devices such as 2-cell devices, TLC (triple-cell) devices, QLC (quadruple-cell) devices, or PLC (five-cell) devices. Alternatively or concurrently, this technology can be applied to various types of devices and systems, such as secure digital cards (SD cards), embedded multimedia cards (eMMC), or solid-state drives (SSDs), embedded systems, etc.

[0030] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0031] The accompanying drawings, which are incorporated herein and form part of this disclosure, illustrate various aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0032] Figure 1A A cross-sectional view of an example memory device is shown.

[0033] Figure 1B A cross-sectional view of another example memory device is shown.

[0034] Figure 2 A plan view showing an example layout of transistors in the peripheral circuitry of a memory device is shown.

[0035] Figure 3 It shows along Figure 2 The diagram shows a cross-sectional view of the transistor with cut line AA'.

[0036] Figure 4 It shows Figure 2 A 3D view of an example layout of transistors shown.

[0037] Figure 5 A plan view of an example layout of transistors in the peripheral circuitry of a memory device is shown after the circular region of the gate structure has been removed.

[0038] Figure 6 A plan view of an example transistor with an example gate structure is shown, which has one or more protruding regions.

[0039] Figure 7 A plan view of an example layout of a transistor including a gate structure with one or more protruding regions is shown.

[0040] Figure 8 A plan view of another example gate structure with one or more protruding regions is shown.

[0041] Figure 9 A plan view of an example layout of a transistor including a gate structure with one or more protruding regions is shown.

[0042] Figure 10 A plan view of the layout of two example masks used to form the gate structure is shown.

[0043] Figure 11 An example mask and an example gate structure formed by using the mask based on simulation results are shown.

[0044] Figure 12 A block diagram of a system having one or more semiconductor devices according to one or more embodiments of the present disclosure is shown.

[0045] The same reference numerals and names in the various figures indicate the same elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0046] Figure 1A-Figure 1B Cross-sectional views of example memory devices 100A and 100B are shown. Memory device 100A or memory device 100B may represent an example of a memory device including the gate structure disclosed herein.

[0047] Figure 1A A cross-sectional view of an example memory device 100A is shown. As shown, the memory device 100A includes a first wafer 102A, a second wafer 104A, a pad output interconnect layer 103A, and a bonding interface 106A. In some embodiments, at least some of the memory cell array and peripheral circuitry of the memory device 100A are formed in parallel on different wafers (e.g., the first wafer 102A and the second wafer 104A), and then bonded to form a bonding structure.

[0048] The first wafer 102A may include an array of memory cells (also referred to herein as a "memory cell array"). In some embodiments, each cell includes a capacitor for storing one bit of data and one or more transistors for controlling (e.g., switching and selecting) access to the cell. In some embodiments, each memory cell is a transistor-capacitor (1T1C) cell.

[0049] like Figure 1A As shown, the first wafer 102A may include at least some of the peripheral circuitry of the memory device 100A. The second wafer 104A may include the remaining peripheral circuitry of the memory device 100A. That is, the peripheral circuitry of the memory device 100A may be divided into at least two wafers 102A and 104A, with some of the peripheral circuitry and memory cell arrays integrated into the first wafer 102A.

[0050] Peripheral circuitry (also referred to herein as “control and sensing circuitry”) may include any suitable digital, analog, and / or mixed-signal circuitry used to facilitate the operation of the memory cell array. For example, peripheral circuitry may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), data input / output buffers, charge pumps, voltage sources or generators, current or voltage references, any portion of the functional circuitry mentioned above (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry in the first wafer 102A and the second wafer 104A may be implemented using, for example, complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented using logic processes at any suitable technology node (e.g., 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0051] In some cases, the first wafer 102A and the second wafer 104B are stacked in different planes. Therefore, the memory cell array and peripheral circuits in the first wafer 102A and the peripheral circuits in the second wafer 104A can be stacked in different planes, thereby reducing the planar size of the memory device 100A compared to a memory device in which all peripheral circuits are arranged in the same plane.

[0052] like Figure 1A As shown, bonding interface 106A is located between first wafer 102A and second wafer 104A. Bonding interface 106A can be an interface between two semiconductor wafers formed using any suitable bonding technique (such as hybrid bonding). In some embodiments, bonding interface 106A is the location where bonding layers meet and bond. In some cases, bonding interface 106A can be a layer of a certain thickness, comprising the bottom surface of the bonding layer of first wafer 102A and the top surface of the bonding layer of second wafer 104A.

[0053] First wafer 102A and second wafer 104A can be manufactured separately (and in some embodiments in parallel), such that the thermal budget for manufacturing one of the first wafer 102A and second wafer 104A does not limit the process for manufacturing the other of the first wafer 102A and second wafer 104A. Furthermore, a large number of interconnects (e.g., bonding contacts) can be formed across bonding interface 106 to form direct, short-distance (e.g., micrometer-scale) electrical connections between wafers 102A and 104A, rather than long-distance (e.g., millimeter- or centimeter-scale) chip-to-chip data buses on a circuit board (e.g., printed circuit board (PCB)), thereby eliminating chip interface latency and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the memory cell array and different peripheral circuits in the first wafer 102A and second wafer 104A can be performed via interconnects (e.g., bonding contacts) across bonding interface 106A. By vertically integrating the first wafer 102A and second wafer 104A, chip size can be reduced and memory cell density can be increased. In some implementations, the pad output interconnect layer 103A can be used for pad output purposes, such as interconnecting with external devices using contact pads on which bonding wires can be soldered.

[0054] Figure 1B A cross-sectional view of an example memory device 100B is shown. Similar to example memory device 100A, example memory device 100B includes a first wafer 102B, a second wafer 104B, a pad output interconnect layer 103B, and a bonding interface 106B. Unlike example memory device 100A, the pad output interconnect layer 103B is included in the second wafer 104B, which does not include the memory cell array. In other words, the pad output interconnect layer can be disposed on either side of the memory device. The first wafer 102B, the second wafer 104B, the pad output interconnect layer 103B, and the bonding interface 106B may be structurally and / or functionally similar to the first wafer 102A, the second wafer 104A, the pad output interconnect layer 103A, and the bonding interface 106A, respectively, and details are omitted here for simplicity.

[0055] Figure 2 A plan view of an example layout 200 of transistors in the peripheral circuitry of a memory device is shown. Figure 3 It shows along Figure 2 The cross-sectional view of transistor 300 with cut line AA' shown. Figure 4 It shows Figure 2 The image shows a three-dimensional view of an example transistor layout 200. In some cases, example layout 200 is in a CMOS device (such as a page buffer), on a wafer of peripheral circuitry (such as...). Figure 1A The second wafer 104A or Figure 1B In the second wafer 104B).

[0056] like Figure 2 As shown, the example layout 200 includes active regions 202, gate structures 206, and contact structures 204. Each active region extends along a first direction (also referred to herein as the "Y direction"). The active regions 202 may be positioned adjacent to each other along a second direction perpendicular to the first direction (also referred to herein as the "X direction"). The active regions 202 include a plurality of transistors ( Figure 2 (Not shown in the image). For example... Figure 3 As shown, transistor 300 typically includes a substrate 214, a well 216, a source 208, a drain 210, and a gate structure 206 arranged as shown. The source 208 and drain 210 are formed in the well 216. The gate structure 206 may also be referred to as the gate. In some cases, the gate structure 206 is formed by a metal gate electrode 211 and a gate dielectric 212 arranged as shown. A channel structure (not shown) is a portion of the well 216 between the source 208 and the drain 210. The channel structure may be formed below the gate structure 206 along a third direction perpendicular to the Y and X directions (also referred to herein as the "vertical direction" or "Z direction"). For example, the channel structure may be formed on the side of the gate dielectric 212 opposite to the side of the metal gate electrode 211. In some cases, the channel structure and the source 208 may form a gate-controlled PN diode. When a negative gate-to-source voltage (V0) is applied... GS When the gate-controlled PN diode is reverse-biased, tunneling current occurs. For example... Figure 4 As shown, the contact structure 204 can extend along the Z direction and couple the transistor (e.g., the source and / or drain of the transistor) to other components of the memory device.

[0057] like Figure 2 As shown, the two active regions 202 can be separated by a distance A along the X direction. Generally, reducing the distance A allows for an increase in the number of active regions that can be formed in the memory device. An increase in the number of active regions leads to an increase in the number of transistors that can be formed in the memory device, and thus an increase in transistor density. The distance A can be influenced by factors such as... Figure 2 The constraints of length B and distance C are shown. Length B is the width of a circular region along the X direction at the edge of gate structure 206. The circular region can be formed during the manufacturing process of gate structure 206. Distance C is the distance between two adjacent gate structures 206 along the X direction. For example, distance C could be the distance along the X direction between the rightmost point of one gate structure 206 and the leftmost point of another gate structure 206.

[0058] In some cases, distance A needs to satisfy or exceed the sum of length B and distance C. As shown in the figure, distance A can be shortened by reducing length B and / or shortening distance C. Shortening length B can be achieved, for example, by reducing or even eliminating the circular region. In some cases, shortening distance C may not be feasible because distance C needs to satisfy (e.g., satisfy or exceed) a distance threshold to maintain a safe distance between two adjacent gate structures. Some example gate structures where distance A can be shortened and thus transistor density increased are discussed below.

[0059] Figure 5 A plan view of an example layout 500 of transistors in the peripheral circuitry of a memory device after the circular region of the gate structure has been removed is shown. The example layout 500 of transistors before the circular region of the gate structure has been removed may be structurally and / or functionally similar to... Figure 2 The example layout 200 of the transistors shown is shown.

[0060] Similar to Figure 2 The example transistor layout 200 shown includes an active region 502, a gate structure 506, and a contact structure 504. However, as... Figure 5 As shown, with Figure 2 Compared to gate structure 206, the circular region of gate structure 506 has been removed. As a result, as... Figure 2 The length B shown is no longer in Figure 5 As shown in the diagram. Therefore, with Figure 2 In contrast, distance A is constrained by distance C; for example, distance A needs to satisfy or exceed distance C, rather than... Figure 2 The diagram shows limitations imposed by both length B and distance C. Without the limitation of length B, distance A can be shortened, and transistor density can be increased.

[0061] In some implementations, a gate structure 506 with a circular region may be formed first, and then the circular region of the gate structure 506 may be removed, for example, by using one or more masks. However, the additional step of removing the circular region of the gate structure 506 can increase the cost of manufacturing the memory device.

[0062] Figure 6 A plan view of an example transistor 600 with an example gate structure 601 having one or more protruding regions is shown. The example transistor 600 includes a source 608 (label indicates the location of the source), a drain 610 (label indicates the location of the drain), and a gate structure 601. The example transistor 600 may be structurally and / or functionally similar to... Figure 3 The transistor 300 shown is different from the gate structure 206 except that the gate structure 601 is different.

[0063] Gate structure 601 includes a first region 602, a second region 604 protruding from a first corner of the first region 602, and a third region 606 protruding from a second corner of the first region 602. The Y direction is along the line connecting the source and drain. As shown, the second region 604 (or correspondingly, the first corner) is positioned diagonally relative to the third region 606 (or correspondingly, the second corner). Although Figure 6 Both second region 604 and third region 606 are shown, but in some cases, gate structure 601 includes only one of the second region 604 or the third region 606.

[0064] As shown in the figure, the second region 604 protrudes towards the source 608 along the Y direction. The second region 604 also protrudes along the X direction. In some cases, the second region 604 protrudes only along one of the Y or X directions.

[0065] Similarly, the third region 606 protrudes towards the drain 610 along the Y direction. The third region 606 also protrudes along the X direction. In some cases, the third region 606 protrudes only along one of the Y or X directions.

[0066] As shown in the figure, distance D is between two points in the Y direction and on the boundary of the first region 602. Distance E is between a point in the Y direction on the boundary of the first region 602 and a point on the boundary of the second region 604. In some cases, distance D is less than or equal to distance E. This method can prevent leakage of transistor 600 that could lead to defects in transistor 600. Protruding from the corner of the first region 602 along the Y direction can extend distance E and avoid leakage problems.

[0067] Distance F is the distance between points in the Y direction on the boundary of the first region 602 and points on the boundary of the third region 606. In some cases, distance D is less than or equal to distance F.

[0068] Figure 7 A plan view of an example layout 700 of a transistor including a gate structure with one or more protruding regions is shown. Figure 7 As shown, the array of gate structures is positioned along both the X and Y directions, such as in parallel. In some cases, Figure 7 Each gate structure in the structure is structurally and / or functionally similar to Figure 6 The gate structure is 601.

[0069] Two gate structures 701 and 711 are adjacent to each other (e.g., parallel) along the X-direction. Gate structure 701 includes a first region 702, a second region 704 protruding from a first corner of the first region 702, and a third region 706 protruding from a second corner of the first region 702. Similarly, gate structure 711 includes a first region 712, a second region 714 protruding from a first corner of the first region 712, and a third region 716 protruding from a second corner of the first region 712. As shown, the second region 704 of gate structure 701 (or correspondingly, the first corner of the first region 702) and the second region 714 of gate structure 711 (or correspondingly, the first corner of the first region 712) are positioned along the X-direction. Similarly, the third region 706 of gate structure 701 (or correspondingly, the second corner of the first region 702) and the third region 716 of gate structure 711 (or correspondingly, the second corner of the first region 712) are positioned along the X-direction.

[0070] As shown in the figure, gate structure 701 has an inward corner portion 708, and the inward corner portion 708 is adjacent to the second region 714 of gate structure 711. Distance G represents the distance along the X-direction between a point in the inward corner portion 708 of gate structure 701 and a point in the second region 714. Similarly, gate structure 711 has an inward corner portion 718, and the inward corner portion 718 is adjacent to the third region 706 of gate structure 701. Distance H represents the distance along the X-direction between a point in the inward corner portion 718 of gate structure 711 and a point in the third region 706 of gate structure 701. Distance I represents the distance along the X-direction between a point in the first region 702 of gate structure 701 and a point in the first region 712 of gate structure 711. In some cases, distances G, I, and H are approximately the same.

[0071] By positioning two adjacent gate structures such that their inner corners are adjacent to the protruding regions of another gate structure, the two gate structures can be positioned close to each other while maintaining a safe distance between them. As a result, the density of the active region can be increased, thereby increasing the density of transistors on the semiconductor device.

[0072] Similar positioning can be applied in the Y direction. For example, gate structure 721 is adjacent to (e.g., parallel to) gate structure 701 along the Y direction. Gate structure 721 includes a first region 722, a second region 724 protruding from a first corner of the first region 722, and a third region 726 protruding from the second corner of the first region 722. As shown, along the Y direction, the inward corner 710 of gate structure 701 lies between the second region 704 of gate structure 701 (or correspondingly, the first corner of the first region 702) and the second region 724 of gate structure 721 (or correspondingly, the first corner of the first region 722). There is no region protruding from the inward corner 710 of gate structure 701. Therefore, similar to the X direction, the inward corner of a gate structure can be adjacent to the protruding region of another gate structure along the Y direction.

[0073] Figure 8 A plan view of another example gate structure 801 with one or more protruding regions is shown. As shown, the gate structure 801 includes a first region 802, a second region 804 protruding from a first corner of the first region 802, and a third region 806 protruding from a second corner of the first region 802. Although Figure 8 Both second region 804 and third region 806 are shown, but in some cases, gate structure 801 includes only one of the second region 804 or the third region 806.

[0074] and Figure 6 In the gate structure 601, where the second region 604 is diagonally positioned relative to the third region 606, the second region 804 and the third region 806 are... Figure 8 On the same edge of the first region 802 in the gate structure 801. Apart from this difference, the gate structure 801 may be structurally and / or functionally similar to Figure 6 The gate structure 601 shown is illustrated, and details are omitted here for the sake of brevity.

[0075] Figure 9 A plan view of an example layout 900 of a transistor including a gate structure with one or more protruding regions is shown. Figure 9 As shown, the array of gate structures is positioned along both the X and Y directions, such as in parallel. In some cases, Figure 9 Each gate structure in the structure is structurally and / or functionally similar to Figure 8 The gate structure is 801.

[0076] Two gate structures 901 and 911 are adjacent to each other (e.g., parallel) along the X direction. Gate structure 901 includes a first region 902, a second region 904 protruding from a first corner of the first region 902, and a third region 906 protruding from a second corner of the first region 902. Similarly, gate structure 911 includes a first region 912, a second region 914 protruding from a first corner of the first region 912, and a third region 916 protruding from a second corner of the first region 912. As shown, the second region 904 (or correspondingly, the first corner of the first region 902) and the second region 914 (or correspondingly, the first corner of the first region 912) are positioned diagonally relative to the X and Y directions.

[0077] As shown in the figure, gate structure 901 has an inward corner portion 908, and the inward corner portion 908 is adjacent to the second region 914 of gate structure 911 along the X direction. Distance K represents the distance along the X direction between a point in the inward corner portion 908 of gate structure 901 and a point in the second region 914. Similarly, gate structure 911 has an inward corner portion 918, and the inward corner portion 918 is adjacent to the second region 904 of gate structure 901 along the X direction. Distance J represents the distance along the X direction between a point in the inward corner portion 918 of gate structure 911 and a point in the second region 904 of gate structure 901. Distance L represents the distance along the X direction between a point in the first region 902 of gate structure 901 and a point in the first region 912 of gate structure 911. In some cases, distances J, L, and K are approximately the same.

[0078] As indicated and similar Figure 7 The example layout 700 shown illustrates that by positioning two adjacent gate structures with their inner corners adjacent to the protruding regions of another gate structure, the two gate structures can be positioned close to each other while maintaining a safe distance between them. As a result, the density of the active region can be increased, thereby increasing the density of transistors on the semiconductor device.

[0079] Figure 10 A plan view of the layout of two example masks for forming a gate structure is shown. As shown, the layout includes mask 1001 and mask 1010 adjacent to mask 1001 along the X direction.

[0080] Mask 1001 includes a first region 1002 and a second region 1004 protruding from a first corner of the first region 1002. In some cases, the first region 1002 of mask 1001 can be used to form, for example... Figure 6 The first region 602 of the gate structure 601 shown is or Figure 8The first region 802 of the gate structure 801 is shown. In some cases, the second region 1004 of the mask 1001 can be used to form, for example... Figure 6 The second region 604 and the third region 606 of the gate structure 601 shown are illustrated. Figure 8 The second region 804 or the third region 806 of the gate structure 801 shown.

[0081] As shown in the figure, the second region 1004 protrudes along the Y direction (e.g., toward the source or drain of a transistor having a gate structure formed using a mask 1001). The second region 1004 also protrudes along the X direction. However, in some cases, the second region 1004 protrudes only along one of the X or Y directions. Although not shown in Figure 10 As shown in the figure, however, in some embodiments, mask 1001 may include a third region protruding from the second corner of the first region 1002.

[0082] Mask 1010 includes a first region 1012 and a second region 1014 protruding from a first corner of the first region 1012. When the two protruding regions of the gate structure are diagonally positioned, the layout including masks 1001 and 1010 can be used to form, for example, [the following is a description of a gate structure]. Figure 7 The gate structure shown in layout 700. Alternatively, when the two protruding regions of the gate structure are on the same edge, the layout including masks 1001 and 1010 can be used to form, for example, as shown in the diagram. Figure 9 The gate structure shown in layout 900.

[0083] More specifically, consider the case where the two protruding regions of the gate structure are located diagonally (e.g. Figure 6 (Gate structure 601 in the middle). Although not in Figure 10 As shown, however, in some embodiments, mask 1010 may include a third region projecting from a second corner of first region 1012, wherein the third region (or correspondingly, the second corner of first region 1012) is diagonally positioned relative to second region 1014 (or correspondingly, the first corner of first region 1012). The second region 1004 of mask 1001 (or correspondingly, the first corner of first region 1002) and the third region of mask 1010 (or correspondingly, the second corner of first region 1012) may be positioned along the X-direction. This arrangement can be used to form, for example, […]. Figure 7 The gate structure shown in layout 700.

[0084] Alternatively, consider the case where the two protruding regions of the gate structure are located at the same edge. In this case, in the layout including mask 1001 and mask 1010, the second region 1004 (or correspondingly, the first corner of the first region 1002) and the second region 1014 (or correspondingly, the first corner of the first region 1012) are positioned diagonally with respect to the X and Y directions. This layout can be used to form, for example, Figure 9 The gate structure shown in layout 900.

[0085] In some cases, although not shown, the layout may include an additional mask adjacent to mask 1001 along the Y direction. The additional mask may include an additional first region and an additional second region protruding from a first corner of the additional first region. A second corner 1006 of the first region 1002 of mask 1001 lies along the Y direction between the second region 1004 of mask 1001 (or correspondingly, the first corner of the first region 1002) and the additional second region of the additional mask (or correspondingly, the first corner of the additional first region). There is no region protruding from the second corner 1006 of the first region 1002 of mask 1001.

[0086] Table I below shows Figure 10 The example value ranges for lengths A, B, C, D, and E shown are as follows:

[0087] A B C D E Range (nm) 40-90 8-24 10-40 20-50 20-50

[0088] Table 1

[0089] Figure 11 An example mask 1101 and an example gate structure 1102 formed using the mask 1101 based on simulation results are shown. A transistor having the gate structure 1102 may include a channel structure (not shown) that is narrower than or equal to the width of the active region 1103 along the X direction. In some cases, the gate structure 1102 is wider than the channel structure in the X direction.

[0090] As shown in the figure, distance M is in the X direction and extends from the edge of the active region 1103 (or, if the width of the channel structure is equal to the width of the active region 1103 along the X direction, the edge of the channel structure) to the boundary of the protruding region of the gate structure 1102. Distance N is in the X direction and extends from the edge of the active region 1103 (or, if the width of the channel structure is equal to the width of the active region 1103 along the X direction, the edge of the channel structure) to the boundary of the gate structure 1102. In some cases, distance M is greater than distance N.

[0091] As can be seen from the above description, regarding Figure 6-11 The fabrication of the example gate structure described does not involve, as with, the fabrication of the example gate structure described. Figure 5The description refers to the circular region at the edge of the removed gate structure. Therefore, the fabrication of... Figure 6-11 The described example gate structure costs less than manufacturing costs related to Figure 5 The cost of the example gate structure described, and regarding Figure 6-11 The described example gate structure is still similar to that of... Figure 5 The example gate structure described can increase transistor density.

[0092] Figure 12 A block diagram of a system 1200 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of this disclosure is shown. System 1200 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 12 As shown, system 1200 may include a host device 1208 and a memory system 1202 having one or more 3D memory devices 1204 and a memory controller 1206. The host device 1208 may include a processor (such as a central processing unit (CPU)) or a system-on-a-chip (SoC) (such as an application processor (AP)). The host device 1208 may be configured to send data to or receive data from one or more 3D memory devices 1204.

[0093] 3D memory device 1204 can be any 3D memory device disclosed herein, such as Figure 1A-Figure 1B The 3D memory device 1204 is shown in the diagram. In some embodiments, the 3D memory device 1204 includes NAND flash memory. A memory controller 1206 (also referred to as controller circuitry) is coupled to the 3D memory device 1204 and the host device 1208. Consistent with embodiments of this disclosure, the 3D memory device 1204 may include a plurality of conductive interconnects through a cover layer, the plurality of conductive interconnects contacting conductive pads in a conductive pad layer, and the memory controller 1206 may be coupled to the 3D memory device 1204 through at least one of the plurality of conductive interconnects. The memory controller 1206 is configured to control the 3D memory device 1204. For example, the memory controller 1206 may be configured to operate a plurality of channel structures via word lines. The memory controller 1206 may manage data stored in the 3D memory device 1204 and communicate with the host device 1208.

[0094] In some embodiments, the memory controller 1206 is designed / configured to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1206 is designed / configured to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage for mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. The memory controller 1206 can be configured to control the operation of the 3D memory device 1204, such as read, erase, and program (or write) operations. The memory controller 1206 can also be configured to manage various functions regarding data stored or to be stored in the 3D memory device 1204, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 1206 is also configured to process error correction codes (ECCs) relating to data read from or written to the 3D memory device 1204. Any other suitable function, such as formatting the 3D memory device 1204, may also be performed by the memory controller 1206.

[0095] The memory controller 1206 can communicate with external devices (e.g., host device 1208) according to a specific communication protocol. For example, the memory controller 1206 can communicate with external devices through at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0096] The memory controller 1206 and one or more 3D memory devices 1204 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 1202 can be implemented and packaged into different types of end electronic products. Figure 12In one example shown, the memory controller 1206 and a single 3D memory device 1204 can be integrated into the memory system 1202. The memory system 1202 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0097] The subjects and embodiments of action and operation described in this disclosure can be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, or in computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or combinations thereof. Embodiments of the subjects described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium can be one or more of the following: a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or combinations thereof. The computer storage medium is not a propagation signal.

[0098] It should be noted that references to "an embodiment," "an embodiment," "an example embodiment," "some embodiments," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other implementations is within the knowledge of those skilled in the art.

[0099] Generally, terms can be understood at least partly from their usage in context. For example, the term "one or more," as used herein, depends at least partly on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can also be understood, at least partly on the context, to express either a singular or a plural usage. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of other factors that are not necessarily explicitly described, which also depends at least partly on the context.

[0100] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with an intermediate feature or layer in between. Furthermore, “above” or “on top of” means not only “above” or “on top of” something, but also includes “above” or “on top of” something without an intermediate feature or layer in between (i.e., directly on) something.

[0101] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship between one element or feature as shown in the figures and another element(s) or feature(s). In addition to the orientations shown in the figures, the spatially relative terms are intended to cover different orientations of the apparatus during use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially related descriptive terms used herein may be interpreted accordingly.

[0102] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where a semiconductor device is formed, and therefore, unless otherwise stated, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0103] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, while the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0104] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process step, set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates the value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate the value of a given quantity that varies, for example, within 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0105] In this disclosure, the terms “horizontal / horizontally / laterally” refer to a lateral surface nominally parallel to the substrate, and the terms “vertical” or “perpendicularly” refer to a lateral surface nominally perpendicular to the substrate.

[0106] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in the vertical direction relative to the substrate.

[0107] This disclosure provides numerous different implementations or examples for achieving various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include implementations in which the first and second features can directly contact each other, and may also include implementations in which an additional feature can be formed between the first and second features such that the first and second features do not directly contact each other. Additionally, reference numerals and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various implementations and / or configurations discussed.

[0108] The foregoing description of specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0109] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features that may be specific to particular embodiments of the invention. Certain features described in this disclosure within the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claims may be directed to sub-combinations or variations thereof.

[0110] Similarly, although operations are illustrated in the accompanying drawings and recited in a specific order in the claims, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order, or to perform all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0111] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions recited in the claims can be performed in different orders and still achieve the desired result. As an example, the processes shown in the figures do not necessarily require the specific order or sequential order shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0112] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: A first transistor, wherein the first transistor includes a source, a drain, and a gate structure, and wherein the gate structure includes: First region; and The second region protrudes from the first corner of the first region toward the source or the drain along a first direction.

2. The semiconductor device according to claim 1, wherein, The first direction is on the line connecting the source and the drain.

3. The semiconductor device according to claim 1 or 2, wherein, The first transistor includes a channel structure, the gate structure is between the source and the drain, and the channel structure is on the gate structure in a vertical direction perpendicular to the first direction.

4. The semiconductor device according to any one of claims 1-3, wherein, The first transistor includes a channel structure, and the gate structure is wider than the channel structure in a second direction perpendicular to the first direction.

5. The semiconductor device according to claim 4, wherein, The first distance is a point in the second direction from the edge of the channel structure to the boundary of the second region, the second distance is a point in the second direction from the edge of the channel structure to the boundary of the first region, and the first distance is greater than the second distance.

6. The semiconductor device according to any one of claims 1-5, wherein, The first distance is between two points in the first direction and on the boundary of the first region, the second distance is between a point in the first direction and on the boundary of the first region and a point on the boundary of the second region, and the first distance is less than the second distance.

7. The semiconductor device according to any one of claims 1-6, wherein, The second region protrudes from the first corner of the first region along a second direction perpendicular to the first direction.

8. The semiconductor device according to any one of claims 1-7, wherein, The gate structure includes a third region protruding from the second corner of the first region.

9. The semiconductor device according to claim 8, wherein, The second corner is positioned diagonally relative to the first corner.

10. The semiconductor device of claim 8 or 9, further comprising an additional gate structure adjacent to the gate structure along a second direction perpendicular to the first direction, wherein, The additional gate structure includes an additional first region and an additional second region protruding from a first corner of the additional first region, wherein the first corner of the first region and the first corner of the additional first region are positioned along the second direction.

11. The semiconductor device according to claim 8, wherein, The first corner and the second corner are on the same edge of the first region.

12. The semiconductor device of claim 8 or 11, further comprising an additional gate structure adjacent to the gate structure along a second direction perpendicular to the first direction, wherein, The additional gate structure includes an additional first region and an additional second region protruding from a first corner of the additional first region, wherein the first corner of the first region and the first corner of the additional first region are diagonally positioned relative to the first direction and the second direction, respectively.

13. The semiconductor device according to any one of claims 1-12, comprising an additional gate structure adjacent to the gate structure along the first direction, wherein, The additional gate structure includes an additional first region and an additional second region protruding from a first corner of the additional first region, wherein the second corner of the first region lies between the first corner of the first region and the first corner of the additional first region along the first direction, and wherein there is no region protruding from the second corner of the first region.

14. A mask for forming a gate structure, wherein, The mask includes: First region; and The second region protrudes from the first corner of the first region along a first direction toward the source or drain associated with the gate structure.

15. The mask according to claim 14, wherein, The second region protrudes from the first corner of the first region along a second direction perpendicular to the first direction.

16. The mask according to any one of claims 14-15, wherein, The mask includes a third region protruding from the second corner of the first region.

17. The mask according to claim 16, wherein, The second corner is positioned diagonally relative to the first corner.

18. The mask according to any one of claims 16-17, wherein, The mask is included in a layout, wherein the layout includes an additional mask adjacent to the mask along a second direction perpendicular to the first direction, wherein the additional mask includes an additional first region and an additional second region protruding from a first corner of the additional first region, and wherein the first corner of the first region and the first corner of the additional first region are positioned along the second direction.

19. The mask according to claim 16, wherein, The first corner and the second corner are on the same edge of the first region.

20. A system comprising: A semiconductor device includes a first transistor, wherein the first transistor includes a source, a drain, and a gate structure, and wherein the gate structure includes: First region; and A second region, the second region protruding from a first corner of the first region along a first direction toward the source or the drain; and A memory controller electrically connected to the semiconductor device, wherein the memory controller is configured to control the semiconductor device.

Images