Method of forming semiconductor device

Abstract

In an embodiment, a method may include forming a multilayer stack over a substrate. The multilayer stack has alternating layers of first semiconductor layers and second semiconductor layers. The method may also include removing the first semiconductor layer. Further, the method may include forming a disposable material between the second semiconductor layers. In addition, the method may include performing a first implant process on the disposable material and the second semiconductor layer. Further, the method may include forming a source / drain region adjacent the second semiconductor layer and the disposable material. The method may also include replacing the disposable material with a metal gate structure. The embodiment of the invention also relates to a method for forming the semiconductor device.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming semiconductor devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a multilayer stack over a substrate, the multilayer stack including alternating layers of a first semiconductor layer and a second semiconductor layer; removing the first semiconductor layer; forming a disposable material between the second semiconductor layers; performing a first implantation process on the disposable material and the second semiconductor layer; forming a source / drain region adjacent to the second semiconductor layer and the disposable material; and replacing the disposable material with a metal gate structure.

[0005] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a multilayer stack over a substrate, the multilayer stack including alternating layers of a first semiconductor layer and a second semiconductor layer; patterning the multilayer stack to define fins; forming a groove adjacent to the fins; selectively removing the first semiconductor layer; forming a sacrificial material between the second semiconductor layers; performing a doping process on the sacrificial material and the second semiconductor layer to change etch selectivity; growing an epitaxial source / drain region adjacent to the second semiconductor layer in the groove; and replacing the sacrificial material with a metal gate structure.

[0006] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a fin of a multilayer stack above a substrate, the multilayer stack including alternating layers of a first semiconductor layer and a second semiconductor layer; forming a first gate structure above the fin; etching a first groove in the fin; removing the first semiconductor layer from the fin; forming a dielectric material between the second semiconductor layers and in the first groove; recessing the sidewalls of the dielectric material in the first groove to form a second groove between adjacent second semiconductor layers; performing a doping process in the first groove and the second groove on the dielectric material and the second semiconductor layer; forming an internal spacer on the recessed sidewalls of the dielectric material; forming a source / drain region adjacent to the internal spacer and the second semiconductor layer in the first groove; performing an ion implantation process to introduce a dopant into the source / drain region; and replacing the first gate structure and the dielectric material with a metal gate structure. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 Examples of nanostructured field-effect transistors (nanoFETs) are shown in three-dimensional views according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 12F , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B and Figure 19C A variation view of intermediate steps in the fabrication of nanoFET transistors according to some embodiments is shown.

[0010] Figure 20 A cross-sectional view is shown of an intermediate step in the fabrication of a nanoFET transistor according to some embodiments.

[0011] Figure 21 , Figure 22A , Figure 22B and Figure 22C A cross-sectional view is shown of an intermediate step in the fabrication of a nanoFET transistor according to some embodiments.

[0012] Figure 23 A cross-sectional view is shown of an intermediate step in the fabrication of a nanoFET transistor according to some embodiments. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0015] This disclosure relates to a method for forming nanoFETs using a one-time oxide interposer (DOI) scheme. The method may involve tilt implantation or plasma doping methods to increase the DOI oxide etch rate. By enhancing the etch rate, the method can reduce the likelihood of residual oxide remaining after the DOI removal step, a challenge often encountered in conventional wafer fabrication processes.

[0016] In some embodiments, the method can also mitigate the risk of over-etching the wafer during the DOI oxide etching process. Over-etching can potentially lead to source / drain epitaxial damage, as well as changes in channel strain and wafer height, results that are generally undesirable in wafer fabrication processes.

[0017] Furthermore, the method allows for more doping in the extended regions. This increased doping can potentially address junction under-scrambling issues and enhance silicon etch rates. Dopant concentration, energy, dose, tilt angle, and temperature can all be adjusted to achieve the desired results, providing a level of flexibility and control uncommon in conventional methods.

[0018] This disclosure also provides several embodiments of the method, each with a different doping strategy and potential results. For example, in some embodiments, the corners of the wafer may be doped to prevent DOI residue, while in other embodiments, the center may be doped to prevent over-etching. Other embodiments may involve different doping sequences and the use of hard masks for shallow trench isolation (STI) to prevent doped STI.

[0019] Overall, the methods described in the embodiments of this disclosure offer a potential solution to the problem of residual materials from DOI processes, providing a more efficient and precise method for forming nanoFETs using DOI schemes.

[0020] The embodiments described below are given in a specific context, with the die comprising a nanoFET. However, various embodiments may be adapted to include other types of transistors (e.g., stacked transistors, etc.) instead of the nanoFET or the die combined with the nanoFET.

[0021] Figure 1Examples of nanoFETs (e.g., nanowire FETs, nanosheet FETs (nanoFETs), etc.) are shown in three-dimensional views according to some embodiments. For ease of illustration, in Figure 1 Certain components have been simplified and / or omitted. The nanoFET includes a nanostructure 54 (e.g., nanosheet, nanowire, etc.) located above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 54 serves as a channel region for the nanoFET. The nanostructure 54 may include p-type nanostructures, n-type nanostructures, or combinations thereof. STI regions 68 (also referred to as STI structures or STI regions) are disposed between adjacent fins 66, and the fins 66 may protrude above and from between adjacent STI regions 68. Although the STI regions 68 are described / shown as separated from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the fin 66 is shown as being a single, continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent STI regions 68.

[0022] A gate dielectric layer 100 is located above the top surface of fin 66 and extends along the top, sidewalls, and bottom surface of nanostructure 54. A gate electrode 102 is located above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102. The source / drain regions 92 may refer to either a source or a drain, individually or collectively, depending on the context.

[0023] Figure 1 Reference cross sections used in later figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the direction of current between the epitaxial source / drain regions 92 of the nanoFET. Cross section B-B' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the nanoFET fin 66 and in a direction, for example, the direction of current between the epitaxial source / drain regions 92 of the nanoFET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions of the nanoFET. For clarity, the following figures refer to these reference cross sections.

[0024] Some of the embodiments discussed herein are presented in the context of nanoFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments contemplate aspects of use in planar devices, such as planar FETs, or in FinFETs.

[0025] Figures 2 to 19CThis is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A and Figure 19A It shows Figure 1 The reference section A-A' shown in the figure. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 9C , Figure 10B , Figure 10C , Figure 10D , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B and Figure 19B It shows Figure 1 The reference section B-B' is shown in the figure. Figure 7C , Figure 12E , Figure 12F , Figure 17C , Figure 18C and Figure 19C It shows Figure 1 The reference section C-C' shown in the figure. Figure 10E , Figure 12C and Figure 12D A plan view of an intermediate stage in the fabrication of a nanoFET according to some embodiments is shown.

[0026] exist Figure 2A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., having p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0027] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nanoFET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nanoFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided. The following figures describe processing steps that can be implemented in either the n-type region 50N or the p-type region 50P, unless otherwise stated.

[0028] In addition, Figure 2 In this process, a multilayer stack 64 is formed over a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layer 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layer 53). For illustrative purposes, and as discussed in more detail below, the first semiconductor layer 51 will be removed, and the second semiconductor layer 53 will be patterned to form the channel regions of the nanoFET in the n-type region 50N and the p-type region 50P. However, in some embodiments, the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form the channel regions of the nanoFET in the n-type region 50N and the p-type region 50P. For example, the channel regions in the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and be formed simultaneously.

[0029] In other embodiments, the first semiconductor layer 51 may be removed, and the second semiconductor layer 53 may be patterned to form the channel region of the nanoFET in the p-type region 50P. The second semiconductor layer 53 may also be removed, and the first semiconductor layer 51 may be patterned to form the channel region of the nanoFET in the n-type region 50N. Again, in other embodiments, the first semiconductor layer 51 may be removed, and the second semiconductor layer 53 may be patterned to form the channel region of the nanoFET in the n-type region 50N. The second semiconductor layer 53 may also be removed, and the first semiconductor layer 51 may be patterned to form the channel region of the nanoFET in the p-type region 50P. In such embodiments, the channel region of the n-type region 50N may have a different material composition than the channel region of the p-type region 50P. The first semiconductor layer 51 and the second semiconductor layer 53 may be selectively removed from each of the n-type region 50N and the p-type region 50P by additional masking and etching steps. For example, the channel region of the n-type region 50N can be a silicon channel region, while the channel region of the p-type region 50P can be a silicon-germanium channel region.

[0030] For illustrative purposes, the multilayer stack 64 is shown as three layers comprising each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0031] In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material such as silicon germanium, and the second semiconductor layer 53 may be formed of a second semiconductor material such as silicon or silicon carbon. The first and second semiconductor materials may be materials with high etch selectivity towards each other. Therefore, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nanoFET.

[0032] Now for reference Figure 3According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 may be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches 58 in multilayer stack 64 and substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching may be anisotropic. During the etching process, a hard mask 56 may be used to define the patterning of fins 66 and nanostructures 55. Hard mask 56 may include any suitable insulating material, such as oxides, nitrides, oxynitrides, and carbonitrides. In some embodiments (not shown separately), hard mask 56 may be a multilayer structure. Hard mask 56 may be formed over nanostructures 55 using acceptable processes such as thermal oxidation, physical vapor deposition (PVD), CVD, ALD, or combinations thereof.

[0033] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a smaller spacing than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66 and nanostructures 55.

[0034] The nanostructure 55 formed by etching the multilayer stack 64 can also be defined by a first semiconductor layer 51 defining first nanostructures 52A-52C (collectively referred to as first nanostructure 52), and by a second semiconductor layer 53 defining second nanostructures 54A-54C (collectively referred to as second nanostructure 54). The first nanostructure 52 and the second nanostructure 54 can also be collectively referred to as nanostructure 55.

[0035] For the purpose of explanation, Figure 3 Fins 66 with substantially equal widths are shown. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or thinner than the width of the fins 66 in the p-type region 50P. Furthermore, although... Figure 3 It is shown that each of the fins 66 and nanostructures 55 always has a consistent width, but in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each of the fins 66 and / or nanostructures 55 increases continuously in the direction toward the substrate 50. In such embodiments, each of the nanostructures 55 may have a different width and be trapezoidal in shape.

[0036] exist Figure 4 Shallow trench isolation (STI) regions 68 are formed adjacent to fin 66. STI regions 68 can be formed by depositing an insulating material over the substrate 50, fin 66, and nanostructure 55, and between adjacent fins 66, to fill the trench 58. The insulating material can be an oxide, such as silicon oxide, nitrides, or combinations thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or combinations thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In the embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a pad (not shown separately) can be formed first along the surfaces of the substrate 50, fin 66, and nanostructure 55. A filler material, such as those discussed above, can then be formed over the pad.

[0037] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof, can be utilized. The planarization process exposes the nanostructure 55 so that, after the planarization process is completed, the nanostructure 55 is flush with the top surface of the insulating material.

[0038] The insulating material is then recessed to form the STI region 68. The insulating material is recessed such that the upper portion of the fin 66 protrudes from between adjacent STI regions 68. Furthermore, the top surface of the STI region 68 can have a flat surface, a convex surface, a concave surface (such as a recess), or a combination thereof, as shown. The top surface of the STI region 68 can be formed as flat, convex, and / or concave by appropriate etching. The STI region 68 can be recessed using acceptable etching processes, such as etching processes selective for the material of the insulating material (e.g., etching the material of the insulating material at a rate faster than that of the materials of the fin 66 and the nanostructure 55). For example, oxide removal can be used, or dilute hydrofluoric acid (dHF) can be used.

[0039] In addition, Figure 4In this process, suitable wells (not shown separately) can be formed in the fins 66 and / or nanostructures 55. In embodiments with different well types, different implantation steps for the n-type region 50N and p-type region 50P can be implemented using photoresist or other masks (not shown separately). For example, photoresist can be formed over the fins 66 and nanostructures 55 in the n-type region 50N and p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurity implantation into the n-type region 50N. The n-type impurity can be implanted in the region to form an impurity in the p-type region 50N. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Phosphorus, arsenic, antimony, etc., within a certain concentration range. After implantation, the photoresist is removed, such as through an acceptable ashing process.

[0040] After or before implantation of the p-type region 50P, photoresist or other masks (not shown separately) are formed over the fins 66 and nanostructures 55 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin-coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurity implantation into the p-type region 50P. The p-type impurity can be implanted in the region to form a fin 66 and nanostructure 55 from approximately 10 13 atoms / cm 3 To about 10 14 atoms / cm 3 The concentrations of boron, boron fluoride, indium, etc., are within a certain range. After implantation, the photoresist can be removed, such as through an acceptable ashing process.

[0041] After implanting the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and to reactivate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation, but in-situ doping and implantation doping can be used together.

[0042] exist Figure 5A and Figure 5BIn this process, a dummy gate is formed above and along the sidewalls of nanostructure 55 and fin 66. To form the dummy gate, firstly, a dummy dielectric layer is formed on fin 66 and / or nanostructure 55. The dummy dielectric layer can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed above the dummy dielectric layer, and a mask layer is formed above the dummy gate layer. The dummy gate layer can be deposited above the dummy dielectric layer and then planarized, for example, by CMP. The mask layer can be deposited above the dummy gate layer. The dummy gate layer can be a conductive or non-conductive material and can be selected from the group including amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer can be made of other materials that have high etch selectivity relative to the etching of the isolation region. The mask layer may include, for example, silicon nitride, silicon oxynitride, etc.

[0043] Subsequently, the mask layer can be patterned using acceptable photolithography and etching techniques to form mask 78. The pattern of mask 78 can then be transferred to a dummy gate layer and then to a dummy dielectric layer to form dummy gate 76 and dummy gate dielectric 70, respectively. The dummy gate 76 covers the corresponding channel region of fin 66. The pattern of mask 78 can be used to physically separate each of the dummy gate 76 from its adjacent counterpart. The dummy gate 76 may also have a longitudinal orientation substantially perpendicular to the longitudinal direction of the corresponding fin 66. It should be noted that, for illustrative purposes only, the dummy gate dielectric 70 is shown as covering only fin 66 and nanostructure 55. In some embodiments, the dummy gate dielectric 70 may be deposited such that the dummy gate dielectric 70 covers STI region 68, thereby extending between the dummy gate 76 and STI region 68.

[0044] exist Figure 6A and Figure 6BIn this context, above nanostructure 55 and STI region 68, a gate spacer 81 is formed on the exposed sidewalls of mask 78 (if present), dummy gate 76, and dummy gate dielectric 70. The gate spacer 81 can be formed by conformally forming one or more dielectric materials and subsequently etching the dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Other insulating materials formed by any acceptable process can be used. Any acceptable etching process, such as dry etching, wet etching, etc., or combinations thereof, can be performed to pattern the dielectric material. The etching can be anisotropic. The dielectric material (when etched) has portions remaining on the sidewalls of dummy gate 76 (thus forming the gate spacer 81). As described in more detail later, the dielectric material (when etched) may also have portions remaining on the sidewalls of fin 66 and / or nanostructure 55 (thus forming fin spacer 83, see...). Figure 7C After etching, the fin spacer 83 and / or the gate spacer 81 may have straight sidewalls (as shown) or may have curved sidewalls (not shown separately).

[0045] Furthermore, implantation can be performed for lightly doped source / drain (LDD) regions (not shown separately). LDD implantation can be performed before forming the gate spacer 81. In embodiments with different device types, similar to implantation for the previously described well, a mask, such as photoresist, can be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the fins 66 and nanostructures 55 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask, such as photoresist, can be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the fins 66 and nanostructures 55 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have a range from 10 15 atoms / cm 3 Up to 10 19 atoms / cm 3 The impurity concentration is within a certain range. Annealing can be used to repair implantation damage and reactivate implanted impurities.

[0046] It should be noted that previous disclosures generally describe the processes for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be employed, additional spacers can be formed and removed, etc. Furthermore, n-type and p-type devices can be formed using different structures and steps.

[0047] exist Figures 7A to 7C In some embodiments, a first groove 86 is formed in the fin 66, nanostructure 55, and substrate 50. An epitaxial source / drain region is then formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54, and extend into the substrate 50. Figure 7C As shown, the top surface of the STI region 68 may be flush with the bottom surface of the first recess 86. In other embodiments, the fin 66 may be etched such that the bottom surface of the first recess 86 is positioned above or below the top surface of the STI region 68. The first recess 86 may be formed by etching the fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process (such as RIE, NBE, etc.). During the etching process used to form the first recess 86, the gate spacer 81, fin spacer 83, and mask 78 mask portions of the fin 66, nanostructure 55, and substrate 50. Each layer of the nanostructure 55 and / or fin 66 may be etched using a single etching process or multiple etching processes. After the first recess 86 reaches the desired depth, a timed etching process may be used to stop the etching of the first recess 86.

[0048] exist Figures 8A to 9C In this process, the first nanostructure 52 is replaced with a sacrificial material 72 (also known as a disposable interposer (DOI) 72). Replacing the first nanostructure 52 may include etching away the first nanostructure 52 using a suitable etching process (such as an isotropic etching process) implemented through the first groove 86. Figures 8A to 8B As shown. The etching process can be selective for the material of the first nanostructure 52 and remove the first nanostructure 52 without significantly removing the second nanostructure 54 or the fin 66. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to remove the first nanostructure 52.

[0049] Subsequently, a sacrificial material layer 71 is deposited in the gap between the first groove 86 and the removal of the first nanostructure 52. The sacrificial material layer 71 can be deposited by a conformal deposition process, such as CVD, ALD, etc. The sacrificial material layer 71 may include an insulating material that can be selectively etched relative to the second nanostructure 54, such as silicon oxide (e.g., SiO2), silicon oxynitride, aluminum oxide, etc.

[0050] exist Figures 9A to 9C Then, the sacrificial material layer 71 can be etched to form the sacrificial material 72. Etching can be isotropic or anisotropic. For example, the sacrificial material layer can be etched using a wet etching process employing diluted HF or the like as an etchant. In some embodiments, etching is performed until the sidewalls of the sacrificial material 72 are recessed beyond the sidewalls of the nanostructure 54. While the sidewalls of the sacrificial material 72 are in... Figure 9B and Figure 9C The figure is shown as straight, but the sidewalls can be concave or convex (see example). Figure 11C ).

[0051] Figure 9B and Figure 9C Similar cross-sectional views according to different embodiments are shown. Figure 9B A configuration similar to the previous figures is shown, illustrating a nanostructure 54 with a flat surface and square corners, gate structures 76 / 78, spacers 81, and sacrificial material 72. On the other hand, Figure 9C The configuration of the structure is shown, illustrating a nanostructure 54 with non-planar surfaces and rounded corners, gate structures 76 / 78, spacers 81, and sacrificial material 72. For example, Figure 9C The second nanostructure 54 is shown in the cross-sectional view; it is thicker in the middle and thinner towards the edges with rounded corners. Furthermore, Figure 9C The fin 66 / substrate 50 exposed at the bottom of the groove 86 is shown to have a recess in the middle region of the groove 86. Furthermore, Figure 9C The gate spacer 81 is shown as comprising multiple spacer layers. While most of the figures in the embodiments of this disclosure show structures with flat surfaces and square corners, the scope of the embodiments of this disclosure is not limited thereto, as structures with non-flat surfaces and rounded corners and contours are also contemplated.

[0052] Replacing the first nanostructure 52 with a sacrificial material 72 can offer advantages. For example, one or more high-temperature processes can be performed in subsequent source / drain formation steps to, for example, activate dopants in the source / drain regions. When the material of the first nanostructure 52 (e.g., SiGe) is exposed to high temperatures, germanium mixing and increased roughness may occur at the interface between nanostructures 52 and 54. Such manufacturing defects can degrade the performance of the resulting transistor device. For example, when germanium diffuses into the second nanostructure 54, germanium residues may remain in the channel region of the resulting transistor device, adversely affecting the performance of the channel region. By replacing the first nanostructure 52 with an insulating material prior to high-temperature processes (e.g., source / drain annealing), manufacturing defects can be reduced, and device performance can be improved (e.g., increased current drive, reduced capacitance, and improved short-channel effect).

[0053] Figures 10A to 10D An implantation process 88 is shown, in which a doped region 89 is formed in the second nanostructure 54 and a sacrificial material 72 is formed in the first groove 86 to alter the etch rate of the structure. Similar to the above. Figure 9C , Figure 10C and Figure 10D An embodiment with a structure having a non-planar surface and rounded corners is shown. The implantation process 88 is designed to selectively modify the etch rate or etch selectivity of the second nanostructure 54 relative to the sacrificial material 72. This process may involve introducing implant material into both the second nanostructure 54 and the sacrificial material 72 to create differential etch characteristics that promote the subsequent removal of the sacrificial material 72 without adversely affecting the second nanostructure 54. The implantation process 88 can be implemented using a tilted implantation technique, where the implantation angle is controlled to optimize the distribution of the implant material within the target region. In some embodiments, a mask 91 is formed (see, for example...). Figure 10D To cover one of the regions (either 50P or 50N), while simultaneously performing an injection process 88 on another region. For example... Figure 10C As shown, due to the non-planar surface of the fin 66 / substrate 50 at the bottom of the groove 86 and the tilt angle of the implantation process 88, the doped region 89 may be discontinuous across the bottom of the groove 86. In some embodiments, the doped region 89 is not formed in the recess at the bottom of the groove 86.

[0054] In some embodiments, implantation process 88 may utilize n-type dopants, such as phosphorus, arsenic, or antimony, or other substances such as germanium, xenon, argon, silicon, or nitrogen, to enhance the etching rate of sacrificial material 72. Alternatively, p-type dopants, such as boron, boron fluoride, indium, or other substances such as carbon, may be used to slow the etching rate, thereby preventing over-etching of sacrificial material 72. The choice of implantation material may depend on the desired outcome of the etching process and the materials involved.

[0055] The implantation process 88 is characterized by a range of parameters that can be adjusted to achieve desired modifications in etch rate or etch selectivity. The implantation tilt angle can range from 0 degrees to 60 degrees, allowing for precise control of the implantation distribution. The implantation energy can be set between 1 keV and 50 keV, which is comparable to that of 5E... 13 To 1E 16 atoms / cm 2 The dosage, together with the injection material, determines the depth and concentration of the injected material. The temperature during the injection process can be maintained within the range of -100°C to 500°C to accommodate various material properties and injection results.

[0056] In some embodiments, implantation process 88 can create an implantation-induced damage layer on the sacrificial material 72, which can improve the efficiency of cleaning and etching during these processes. This enhancement can result in increased etch selectivity, allowing complete removal of the sacrificial material 72 without leaving any residue and without damaging the source / drain regions 92. Consequently, the interface of the second nanostructure 54 can be smoother, which is beneficial for improved channel mobility in semiconductor devices.

[0057] By carefully selecting and controlling these parameters, the implantation process 88 can be customized to modify the etch rate or etch selectivity of the second nanostructure 54 and the sacrificial material 72 in a controllable manner. This makes the etching process more efficient and precise, reduces the possibility of residual material, and improves the overall quality of the semiconductor device.

[0058] The doped region 89 in the second nanostructure 54 can be doped to a depth from approximately 1E. 18 To 1E 19 atoms / cm 3 The concentration range is [range missing]. This doping concentration helps control the shape of the second nanostructure during the subsequent etching process to remove the sacrificial material 72. Furthermore, the dopant distribution slope within this concentration range can be controlled within approximately 1 to 5 nm / decimal, representing a sharp transition between doped and undoped regions.

[0059] Compared to the second nanostructure 54, the doped regions 89 in the sacrificial material 72 can be doped to a lower concentration, exhibiting a lower doping density from approximately 5E. 17 Up to 5E 18 atoms / cm 3 The concentration range is selected to optimize etch selectivity during the removal of sacrificial material 72, ensuring that the second nanostructure 54 remains intact and undamaged. The dopant distribution slope in sacrificial material 72 is also controlled to facilitate a controllable etching process, contributing to overall device fabrication efficiency.

[0060] In some embodiments, the top second nanostructure 54C has a higher dopant concentration than the middle second nanostructure 54B and the lower second nanostructure 54A because the gate spacer 81 and the above structure block some of the dopant during the implantation process 88. Figure 10B and Figure 10C As seen, the top second nanostructure 54C has doped regions 89 formed on two surfaces (e.g., side surface and bottom surface), while the middle second nanostructure 54B and the lower second nanostructure 54A have doped regions 89 formed on three surfaces (e.g., top surface, side surface and bottom surface).

[0061] Adjusting the dopant concentration and distribution slope in the second nanostructure 54 and the sacrificial material 72 enhances the etching process and ensures the formation of semiconductor devices with improved channel mobility and reduced resistance. This approach allows for precise customization of semiconductor device characteristics to meet specific performance requirements.

[0062] Figure 10E A plan view of a second nanostructure 54 having a doped region 89 within a second nanostructure 54 according to some embodiments is shown. The doped region 89 is configured to modify the etch rate of the second nanostructure 54, a critical step in the fabrication process. An implantation process 88 introduces a dopant into the second nanostructure 54 in a manner that creates differential etch characteristics between the second nanostructure 54 and the sacrificial material 72. This differential etch characteristic is advantageous for the subsequent removal of the sacrificial material 72 because it allows for selective etching of the sacrificial material 72 without adversely affecting the second nanostructure 54.

[0063] The configuration of the doped region 89 allows it to be customized to meet the specific requirements of the semiconductor device being manufactured. By adjusting the parameters of the implantation process 88, such as tilt angle, energy, dose, and temperature, the etching rate or etching selectivity of the second nanostructure 54 can be controlled.

[0064] Although the doped region 89 is shown in the following figures as having a defined boundary, in some embodiments the boundary of the doped region 89 is more gentle and can be moved or changed from the dispersion of the dopant due to further processing such as thermal processes, etching processes, etc.

[0065] exist Figure 11A and Figure 11B In this process, an internal spacer 90 is formed in a first recess 86 on the sidewall of the sacrificial material 72 and / or the doped region 89. The internal spacer 90 serves as an isolation component between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86, and the sacrificial material 72 will be replaced with the corresponding gate structure. The internal spacer 90 can also be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as those used to form the gate structure.

[0066] The internal spacer 90 can be used in Figure 10A and Figure 10BThe structure shown is formed by depositing an internal spacer layer (not shown separately) over it. The internal spacer layer can be deposited using conformal deposition processes such as CVD, ALD, etc. The internal spacer layer can comprise materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k material with a k value less than about 3.5. The internal spacer layer can then be anisotropically etched to form the internal spacer 90. The internal spacer layer can be etched using anisotropic etching processes such as RIE, NBE, etc.

[0067] Although the outer wall of the inner spacer 90 is shown flush with the sidewall of the second nanostructure 54, the outer wall of the inner spacer 90 may extend beyond or be recessed from the sidewall of the second nanostructure 54 (see example). Figure 11C Furthermore, although the outer wall of the internal spacer 90 is in Figure 11B The diagram shows it as straight, but the outer wall of the inner spacer 90 can be concave or convex. As an example, Figure 11C An embodiment is shown in which the sidewalls of the sacrificial material 72 are concave, the outer sidewalls of the internal spacer 90 are concave, and the internal spacer 90 is recessed from the sidewalls of the second nanostructure 54. Other configurations are also possible. For example, Figure 11D An embodiment is shown in which the sidewalls of the sacrificial material 72 are concave, the outer sidewalls of the inner spacer 90 are straight, and the inner spacer 90 is flush with the sidewalls of the second nanostructure 54.

[0068] exist Figures 12A to 12F In this process, an epitaxial source / drain region 92 is formed in the first groove 86. In some embodiments, the source / drain region 92 may apply stress to the second nanostructure 54 in the n-type region 50N and / or the first nanostructure 52 in the p-type region 50P, thereby improving performance. Figure 12B As shown, epitaxial source / drain regions 92 are formed in the first recess 86, such that each dummy gate 76 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, gate spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and internal spacers 90 are used to separate the epitaxial source / drain regions 92 from the sacrificial material 72 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit with the subsequently formed gate of the resulting nanoFET.

[0069] The epitaxial source / drain region 92 in the n-type region 50N (e.g., an NMOS region) can be formed by masking the p-type region 50P (e.g., a PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 in the n-type region 50N can comprise a material on which tensile strain is applied, such as Si, SiP, SiAs, SiP+SiAs / SiSb, SiSb, SiP+SiAs+SiSb, etc.

[0070] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first groove 86 in the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 in the p-type region 50P can comprise a material on which compressive strain is applied, such as SiGe, Ge, GeSn, SiB, SiGe:B, SiGe:Ga, etc.

[0071] The epitaxial source / drain region 92, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the process discussed earlier for forming lightly doped source / drain regions, followed by annealing. The source / drain region can have a dopant density of approximately 1 × 10⁻⁶. 19 atoms / cm 3 1×10 21 atoms / cm 3 The impurity concentrations between these values. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0072] Figure 12C A plan view of the second nanostructure 54 and the epitaxial source / drain region 92 according to some embodiments is shown. In some embodiments, the wafer is tilted during the implantation process 88, which allows selective doping of the corners of the second nanostructure 54, which can be beneficial in preventing residual sacrificial material 72 during subsequent removal of the sacrificial material 72. In some embodiments, not only the corners of the second nanostructure 54 (see, for example) Figure 10EFurthermore, the entire side of the second nanostructure 54 (including the middle region besides the corners) can be doped, which helps prevent over-etching. This selective doping produces a customized dopant distribution that can be used to modify the etch rate of the second nanostructure 54, thereby enhancing the etching process and improving overall device performance. For example, using this control of the etch rate, the rounding of the sides of the second nanostructure 54 can be configured. Figure 12C In this diagram, the rounding of the sides of the second nanostructure 54 is indicated by a distance D1, which is the difference between the innermost and outermost points of the sides of the second nanostructure 54 in this planar view. In some embodiments, the distance D1 in this configuration is less than 1 nm. This configuration facilitates a smooth interface between the second nanostructure 54 and the epitaxial source / drain region 92, which is desirable for better junction uniformity and device performance.

[0073] Figure 12D A plan view of a second nanostructure 54 and an epitaxial source / drain region 92 according to some embodiments is shown. In this embodiment, the wafer is not tilted during implantation process 88, resulting in a uniform dopant distribution across the entire side of the second nanostructure 54 (e.g., from the top corner to the bottom corner on both sides). This uniform dopant distribution leads to a curved profile between the second nanostructure 54 and the epitaxial source / drain region 92 due to the faster etching rate at the center than at the edges. Figure 12D In this diagram, the rounding of the sides of the second nanostructure 54 is indicated by a distance D2, which is the difference between the innermost and outermost points of the sides of the second nanostructure 54 in this planar view. In some embodiments, the distance D2 in this configuration is 3 nm or greater.

[0074] Using various implantation materials not only enhances the etching rate for the sacrificial material 72 and the second nanostructure 54, but also deepens the junction. The dopant concentration within the sacrificial material 72 is lower than that within the source / drain region 92. During the formation of the source / drain region 92, the implantation process may introduce defects into these regions, which could promote dopant diffusion from the source / drain region 92 into adjacent channel regions. This dopant diffusion may reduce the channel resistance of the subsequently formed transistor structure.

[0075] In the tilted implantation embodiment, the distribution of the doped regions 89 can be selectively controlled. For example, the STI region 68, fin 66, the lower portion of the second nanostructure 54, and the sacrificial material 72 can remain undoped, while the upper portion of the structure is doped. Therefore, varying dopant concentrations can be achieved across different layers of the second nanostructure 54. For example, in a three-layer configuration with the second nanostructure 54, the initial implantation process 88 can introduce dopant into all three layers, while subsequent implantation processes 88 can target only the top two layers. Various other doping sequences are also possible. Furthermore, the gate spacer 81 adjacent to the dummy gate 76 can be doped. This doping can potentially reduce the dielectric constant (k-value) of the gate spacer 81, which can also lead to a reduction in leakage current.

[0076] In the plasma-doped embodiment, the STI region 68, fin 66, gate spacer 81 adjacent to the dummy gate 76, second nanostructure 54, and sacrificial material 72 are all doped during implantation process 88. When the dopant reaches the bottom portion of fin 66, it may affect the bottom-up growth of the source / drain region 92. For example, the introduction of dopant may potentially damage the lattice, which could reduce the quality of the epitaxial source / drain region 92.

[0077] Furthermore, when STI region 68 is doped, the etching rate of STI region 68 during subsequent etching processes can be modulated (see example). Figure 20 Therefore, this allows for adjustment of the height of the top surface of STI region 68, as per [the context of the previous sentence]. Figure 20 Further discussion is needed. To prevent doping in the STI region 68, an optional hard mask structure can be used, such as... Figures 21 to 22C As depicted in the text.

[0078] The doped regions 89 formed by implantation process 88, particularly the source / drain extension regions adjacent to the second nanostructure 54, can enhance the etch rate of these structures. This enhancement facilitates the modulation of the convexity of the source / drain regions 92 into the channel regions (e.g., the second nanostructure 54), a technique used to control short-channel effects in semiconductor devices. By adjusting the dopant distribution, the shape of the interface between the second nanostructure 54 and the source / drain regions 92 can be finely tuned, contributing to improved device performance.

[0079] Due to the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has small planes that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these small planes cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge, such as... Figure 12EAs shown. In other embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated, as shown. Figure 12F As shown. In Figure 12E and Figure 12F In the illustrated embodiment, fin spacers 83 may be formed on the top surface of the STI region 68 to block epitaxial growth. In some other embodiments, fin spacers 83 may cover portions of the sidewalls of the nanostructure 55 to further block epitaxial growth. In some other embodiments, the spacer etching used to form the fin spacers 83 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 68.

[0080] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers can be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration less than that of the second semiconductor material layer 92B and greater than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0081] exist Figure 13A and Figure 13B In Figure 18A and Figure 19B A first interlayer dielectric (ILD) 96 is deposited over the structure shown. The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, mask 78, and gate spacer 81. CESL 94 may include a dielectric material having a different etch rate than the material of the first ILD 96 above, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0082] After depositing the first ILD 96, a planarization process, such as CMP, can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and portions of the gate spacer 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the gate spacer 81, and the first ILD 96 are flush within a process variation. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the gate spacer 81.

[0083] exist Figure 14A and Figure 14B In one or more etching steps, the dummy gate 76 and mask 78 (if present) are removed to form a second recess 98. A portion of the dummy gate dielectric 70 and a portion of the dummy gate 76 in the second recess 98 may also be removed. In some embodiments, the dummy gate 76 and dummy gate dielectric 70 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 76 at a rate faster than the first ILD 96 or the gate spacer 81. Each second recess 98 exposes a portion of the nanostructure 55 and / or is located on top of a portion of the nanostructure 55 that serves as a channel region in the subsequently completed nanoFET. The portions of the nanostructure 55 that serve as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 70 may serve as an etch stop layer when the dummy gate 76 is etched. The dummy gate dielectric 70 may then be removed after the dummy gate 76 has been removed.

[0084] exist Figure 15A and Figure 15B In this process, sacrificial material 72 is removed, which extends the second groove 98. In some embodiments, the removal of sacrificial material 72 removes a portion of the doped region 89 located in or adjacent to the sacrificial material. The removal of sacrificial material 72 may involve isotropic etching processes, such as wet etching using diluted hydrofluoric acid (HF) or dry etching using chemical oxide removal (COR). These etchants are selective for the material of sacrificial material 72, ensuring that the second nanostructure 54 remains relatively unetched compared to sacrificial material 72. Sacrificial material 72 may be completely removed, or a residue of sacrificial material 72 may remain on the sidewalls of the internal spacers in the second groove 98 (see, for example...). Figure 16C ).

[0085] In some embodiments, the STI region 68 may be etched during the removal of the sacrificial material 72, but the total loss in the STI region 68 can be reduced by controlling the etching parameters (e.g., timing) during the removal of the sacrificial material 72. In other embodiments, the STI region 68 may include a hard mask at the top surface (see, for example...). Figures 21 to 22C This is done to protect the underlying STI region 68 from etching during patterning and removal of the sacrificial material 72. In such embodiments, the hard mask may include, for example, a nitride.

[0086] After the etching process (e.g., in) Figures 15A to 15B The residual dopant from the implantation process 88 retained in the second nanostructure 54 after etching can be used to reduce the channel resistance. This reduction in resistance is beneficial to the overall electrical performance of the device because it can lead to increased transistor current and improved switching characteristics. Therefore, precise control over dopant concentration and distribution is a valuable tool in optimizing semiconductor device fabrication.

[0087] exist Figures 16A to 16C In the second recess 98, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. The gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50 and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 can also be deposited on the top surface of the first ILD 96, CESL 94, gate spacer 81, and STI region 68.

[0088] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. Methods for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0089] Gate electrodes 102 are deposited over gate dielectric layer 100 and fill the remaining portion of second trench 98. Gate electrodes 102 may comprise metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although in Figures 16A to 16CA single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of pad layers, any number of work function adjustment layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited in the n-type region 50N between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent first nanostructures 52.

[0090] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When different processes are used, individual masking steps can be used to mask and expose appropriate regions.

[0091] After filling the second recess 98, a planarization process, such as CMP, can be performed to remove excess material from the gate dielectric layer 100 and the gate electrode 102, which lies above the top surface of the first ILD 96. The remaining material of the gate electrode 102 and the gate dielectric layer 100 thus forms the replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the “gate structure”.

[0092] Figure 16C It shows Figure 16B Detailed views of the various components, including the epitaxial source / drain region 92, the gate dielectric layer 100, the gate electrode 102, the second nanostructure 54, and the internal spacer 90. In some embodiments, such as Figure 16C As shown, residues of sacrificial material 72 may remain on the internal spacer 90, such as between the internal spacer 90 and the gate dielectric layer 100 / gate electrode 102. For example, sacrificial material 72 may not be completely removed, and the gate dielectric layer 100 may be formed on the remaining sacrificial material 72. Because sacrificial material 72 is an insulating material (e.g., silicon oxide), the remaining residue may not significantly affect the electrical performance of the resulting device.

[0093] exist Figures 17A to 17CIn this process, the gate structure (including the gate dielectric layer 100 and the corresponding gate electrode 102) is recessed, thereby forming a groove between the gate structure directly above and the opposite portion of the gate spacer 81. A gate mask 104 comprising one or more dielectric material layers (such as silicon nitride, silicon oxynitride, etc.) is filled into the groove, followed by a planarization process to remove excess dielectric material extending over the first ILD 96. The gate contacts (such as those described below) are then formed. Figures 19A to 19C The gate contact 114 discussed penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102.

[0094] like Figures 17A to 17C As further shown, a second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PECVD, etc.

[0095] exist Figures 18A to 18C In the process, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a third recess 108 that exposes the surfaces of the epitaxial source / drain regions 92 and / or the gate structure. The third recess 108 can be formed by etching using anisotropic etching processes (such as RIE, NBE, etc.). In some embodiments, the third recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; it can be etched through the gate mask 104 using a second etching process; and then it can be etched through the CESL 94 using a third etching process. A mask such as photoresist can be formed and patterned over the second ILD 106 to mask portions of the second ILD 106 from the first and second etching processes. In some embodiments, the etching process may over-etch, and therefore, the third groove 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third groove 108 may be flush with the epitaxial source / drain region 92 and / or gate structure (e.g., at the same level, or at the same distance relative to the substrate), or lower than the epitaxial source / drain region 92 and / or gate structure (e.g., closer to the substrate). Although Figure 18B The third groove 108 is shown to expose the epitaxial source / drain region 92 and the gate structure in the same cross section, but in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross sections, thereby reducing the risk of short circuits in the subsequently formed contacts.

[0096] After the third groove 108 is formed, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by: firstly depositing a metal (such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium) of the epitaxial source / drain region 92 to form a silicide or germanide region over the exposed portion of the epitaxial source / drain region 92; then performing a thermal annealing process to form the silicide region 110. Unreacted portions of the deposited metal are then removed, for example, by an etching process. While the silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicides and germanides). In an embodiment, the silicide region 110 comprises TiSi and has a thickness in the range of about 2 nm to about 10 nm.

[0097] Next step, in Figures 19A to 19C In the third recess 108, contacts 112 and 114 (also referred to as contact plugs) are formed. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to underlying conductive components (e.g., the gate electrode 102 and / or the silicide region 110 in the illustrated embodiment). Contact 114 is electrically coupled to the gate electrode 102 and may be referred to as gate contact 114, and contact 112 is electrically coupled to the silicide region 110 and may be referred to as source / drain contact 112. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, may be implemented to remove excess material from the surface of the second ILD 106.

[0098] Figure 20 A cross-sectional view is shown of an intermediate step in the fabrication of a nanoFET transistor according to some embodiments. Figure 20 It shows Figure 1 The reference section C-C' is shown in the diagram. Figure 20 In the text, the same reference numerals indicate that they are used in conjunction with those above. Figures 2 to 19C The same components are formed using the same process described herein, unless otherwise stated. Figure 20 The process is shown with Figures 10A to 10C Similar steps will not be repeated in this article.

[0099] In this embodiment, the implantation process 88 also forms a doped region 89 within the upper surface of the STI region 68. This allows modification of the etch rate of the STI during subsequent etching and patterning steps (e.g., etching the internal spacers or removing the sacrificial material 72). By adjusting the etch rate, the height of the top surface of the STI can be controlled.

[0100] The doped region 89 in the STI region 68 can be formed simultaneously with the doped regions in the second nanostructure 54 and the sacrificial material 72. The type and concentration of the dopant, as well as the implantation conditions, can be controlled to achieve desired modifications to the etching rate.

[0101] The ability to adjust the height of the STI top surface can offer several benefits. For example, it can help achieve a more uniform device structure, which may lead to improved device performance. It can also help reduce manufacturing defects and improve the overall yield of the manufacturing process. Furthermore, the ability to control the STI height provides flexibility in the design and manufacture of semiconductor devices, allowing for the customization of device characteristics to meet specific performance requirements.

[0102] Figure 20 A cross-sectional view is shown of an intermediate step in the fabrication of a nanoFET transistor according to some embodiments. Figure 21 It shows Figure 1 The reference section C-C' shown in the figure. Figure 22A It shows Figure 1 The reference section A-A' shown in the figure. Figure 22B It shows Figure 1 The reference section B-B' is shown in the figure. Figure 22C It shows Figure 1 The reference section C-C' is shown in the diagram. Figures 20 to 22C In the text, the same reference numerals indicate that they are used in conjunction with those above. Figures 2 to 19C The same components are formed using the same process described herein, unless otherwise stated.

[0103] In this embodiment, a hard mask layer can be formed on the top surface of the STI region 68 to reduce the loss of isolation area during subsequent cleaning and / or etching processes implemented to manufacture transistors. Figure 21 It shows the process with Figure 4 Similar steps will not be repeated in this article. Figures 22A to 22C It shows the process with Figures 7A to 7C Similar steps will not be repeated in this article.

[0104] like Figure 21As shown, a hard mask structure 120 is formed on the top surface of the STI region 68. In some embodiments, the hard mask structure 120 is a multilayer structure including, for example, a nitride hard mask and a silicon hard mask above the nitride hard mask. In some embodiments, prior to forming the hard mask structure 120, an optional protective liner 118 is deposited above and along the sidewalls of the nanostructure 55 and on the exposed upper sidewalls of the fin 66.

[0105] For example, the optional protective pad 118 may be formed after the STI region 68 and before the formation of the dummy gate. In some embodiments, the protective pad 118 is fabricated by growing a silicon layer using an epitaxial process such as CVD, ALD, VPE, MBE, etc. In some embodiments, the protective pad 118 is selectively deposited on the semiconductor material of the nanostructures 55 and fins 66 without being deposited on the exposed surface of the STI region 68. The deposition process used to form the protective pad 118 can allow for the formation of a relatively high-quality material. For example, when the protective pad 118 is a silicon layer deposited via an ALD process, the protective pad 118 can have improved coverage and be more crystalline than the second nanostructure 54. The higher quality material of the protective pad 118 can be more etch-resistant and reduce undesirable thinning of the second nanostructure 54 during subsequent processing steps. Therefore, the protective pad 118 can allow for the formation of a higher quality channel region in the resulting device. In some embodiments, the protective pad 118 may be omitted.

[0106] After the optional protective pad 118 is formed and before the dummy gate is formed, a first hard mask 120A is deposited above and along the sidewalls of the nanostructure 55, on the upper sidewall of the fin 66, and on the upper surface of the STI region 68. The first hard mask 120A may be a nitride layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon carbonitride layer, etc. The nitrogen concentration of the first hard mask 120A may be greater than the nitrogen concentration of the STI region 68. In some embodiments, the first hard mask 120A is deposited using a non-conformal deposition process, such as a plasma-enhanced CVD (PECVD) process. The non-conformal deposition process can form sidewall portions of the first hard mask 120A with a thickness smaller than that of the lateral portions of the first hard mask 120A. The non-conformal deposition process can facilitate patterning and selective removal of the sidewall portions of the first hard mask 120A.

[0107] Before forming the second hard mask 120B, the upper portion and sidewall portions of the first hard mask 120A can be removed. The upper portion of the first hard mask 120A may include a lateral portion of the first hard mask 120A disposed on the nanostructure 55. Removing the upper portion of the first hard mask 120A may include depositing a mask layer (not shown) over the first hard mask 120A, followed by one or more etching processes that can remove the upper portion of the first hard mask 120A. Removing the sidewall portions of the first hard mask 120A may include etching processes, such as isotropic etching processes.

[0108] Furthermore, a second hard mask 120B is deposited over the first hard mask 120A. The second hard mask 120B may be deposited over the top surface of the nanostructure 55, along the sidewalls of the nanostructure 55, and above the upper surface of the first hard mask 120A. The second hard mask 120B may be formed of a material that has higher etch selectivity for the STI region 68 than the first hard mask 120A, relative to the same etching process. In some embodiments, the second hard mask 120B is a semiconductor material. For example, when the first hard mask 120A is made of a nitride material and the STI region 68 is made of an oxide material, the second hard mask 120B may be made of silicon or the like.

[0109] The second hard mask 120B can be formed by a non-conformal deposition process, such as FCVD. Once the second hard mask 120B is formed, an annealing process can be performed. Furthermore, non-conformal deposition processes may deposit a material of lower quality than the material of the protective liner 118. For example, the second hard mask 120B may have poorer coverage than the protective liner 118, particularly on the sidewalls and top surface of the nanostructure 55, and less crystallinity. Therefore, the second hard mask 120B is more easily etched away than the protective liner 118 in subsequent processes. In other embodiments, other non-conformal deposition processes, such as PECVD, can be used to deposit the second hard mask 120B.

[0110] Subsequently, the sidewall and upper portions of the second hard mask 120B are removed, while the bottom portion of the second hard mask 120B is retained (see...). Figures 20 to 22C Removing the sidewall and top portions of the second hard mask 120B may include etching processes, such as isotropic etching. Optional protective pads 118 may be removed during the gate replacement process.

[0111] The hard mask structure 120 has a multilayer structure including a first hard mask 120A (e.g., a nitride) and a second hard mask 120B (e.g., a silicon hard mask). The hard mask structure 120 protects the underlying STI region 68 during subsequent processing steps (e.g., subsequent etching and / or cleaning processes). Furthermore, by including a combination of materials in the first hard mask 120A and the second hard mask 120B, parasitic capacitance in the resulting device can be reduced.

[0112] Figure 23 A cross-sectional view is shown of an intermediate step in the fabrication of a nanoFET transistor according to some embodiments. Figure 23 It shows Figure 1 The reference section C-C' is shown in the diagram. Figure 23 In the text, the same reference numerals indicate that they are used in conjunction with those above. Figures 2 to 19C The same components are formed using the same process described herein, unless otherwise stated. Figure 23 It shows the process with Figures 19A to 19C Similar steps will not be repeated in this article.

[0113] In this embodiment, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated (similar to...). Figure 12F Furthermore, the source / drain contact 112 may extend between adjacent epitaxial source / drain regions 92 to have a bottom surface lower than the top surface of the epitaxial source / drain region 92. Although the contact 112 is shown extending into the STI region 68 between adjacent epitaxial source / drain regions 92, using embodiments of this disclosure, the contact 112 may not extend as far as in conventional devices because the removal and loss of the STI region 68 is reduced in the case of embodiments of this disclosure. This can improve yield and reduce parasitic capacitance in the resulting device.

[0114] The disclosed method provides a way to form nanoFETs in semiconductor fabrication, addressing challenges such as the presence of residual oxides after removal of the primary oxide interposer (DOI) and over-etching issues during the DOI oxide etching process. By using tilted implantation or plasma doping techniques, the method increases the DOI etching rate, which helps minimize the presence of residual oxides and reduces the likelihood of source / drain epitaxial damage, channel strain, and wafer height variations.

[0115] The method also allows for increased doping in the extended regions, which can address junction under-lap and improve silicon etch rates. This control over doping enhances the interface between the wafer and the source / drain regions, potentially leading to better channel mobility and device performance. Dopant distribution can be selectively tuned in specific regions (such as the corners or centers of nanostructures) to modulate etch rates and dopant distribution.

[0116] This approach is applicable to a variety of doping strategies and results, and can be tailored to manufacturing requirements. It allows for control of dopant concentrations across different layers of the nanostructure, which can be tuned through multi-tilt implantation condition design. Furthermore, the method can reduce the dielectric constant of adjacent gate spacers, which can reduce leakage current and improve device reliability.

[0117] In summary, this method provides a way to enhance the efficiency and accuracy of semiconductor nanoFET formation, thus offering a solution to some of the limitations found in previous methods. It allows for tuning of the etch rate and dopant distribution, which can reduce the risks associated with residual material and over-etching, making it a useful technique in the fabrication of semiconductor devices.

[0118] In an embodiment, the method may include forming a multilayer stack over a substrate. The multilayer stack has alternating layers of a first semiconductor layer and a second semiconductor layer. The method may also include removing the first semiconductor layer. Furthermore, the method may include forming a disposable material between the second semiconductor layers. Additionally, the method may include performing a first implantation process on the disposable material and the second semiconductor layer. Moreover, the method may include forming a source / drain region adjacent to the second semiconductor layer and the disposable material. The method may also include replacing the disposable material with a metal gate structure.

[0119] The described embodiments may also include one or more of the following features. The method may use a disposable material selected from the group consisting of silicon oxide, silicon oxynitride, and aluminum oxide. Furthermore, the method may include performing a second implantation process to introduce an n-type dopant into the source / drain region after forming the disposable material between the second semiconductor layers. The first implantation process for the disposable material and the second semiconductor layer may include a tilted implantation process. The first implantation process may include plasma. The method may use phosphorus, arsenic or antimony, germanium, xenon, argon, silicon, nitrogen, boron, boron fluoride, indium, and carbon for the first implantation process of the disposable material and the second semiconductor layer. The first implantation process for the disposable material and the second semiconductor layer may alter the etch selectivity between the second semiconductor layer and the disposable material. The method of replacing the disposable material with a metal gate structure may also include removing the disposable material using an etch process selectively targeting the disposable material above the second semiconductor layer. The method may include forming internal spacers on the sidewalls of the disposable material after performing the first implantation process. The internal spacers may include silicon nitride, silicon oxynitride, or combinations thereof. The internal spacers may have a convex shape facing the disposable material.

[0120] In embodiments, the method may include forming a multilayer stack over a substrate. The multilayer stack has alternating layers of a first semiconductor layer and a second semiconductor layer. The method may also include patterning the multilayer stack to define fins. Furthermore, the method may include forming a trench adjacent to the fins. Additionally, the method may include selectively removing the first semiconductor layer. Moreover, the method may include forming a sacrificial material between the second semiconductor layers. The method may also include performing a doping process on the sacrificial material and the second semiconductor layer to modify etch selectivity. Furthermore, the method may include growing an epitaxial source / drain region adjacent to the second semiconductor layer in the trench. The method may also include replacing the sacrificial material with a metal gate structure.

[0121] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a multilayer stack over a substrate, the multilayer stack including alternating layers of a first semiconductor layer and a second semiconductor layer; removing the first semiconductor layer; forming a disposable material between the second semiconductor layers; performing a first implantation process on the disposable material and the second semiconductor layer; forming a source / drain region adjacent to the second semiconductor layer and the disposable material; and replacing the disposable material with a metal gate structure.

[0122] In some embodiments, the disposable material is selected from the group consisting of silicon oxide, silicon oxynitride, and aluminum oxide. In some embodiments, the method further includes: after forming the disposable material between the second semiconductor layers, performing a second implantation process to introduce an n-type dopant into the source / drain region. In some embodiments, performing the first implantation process on the disposable material and the second semiconductor layer includes a tilted implantation process. In some embodiments, the first implantation process includes plasma. In some embodiments, performing the first implantation process on the disposable material and the second semiconductor layer includes implanting phosphorus, arsenic or antimony, germanium, xenon, argon, silicon, nitrogen, boron, boron fluoride, indium, and carbon. In some embodiments, performing the first implantation process on the disposable material and the second semiconductor layer alters the etch selectivity between the second semiconductor layer and the disposable material. In some embodiments, replacing the disposable material with the metal gate structure further includes: removing the disposable material using an etching process selectively targeting the disposable material above the second semiconductor layer. In some embodiments, the method further includes: after performing the first implantation process on the disposable material and the second semiconductor layer, forming internal spacers on the sidewalls of the disposable material. In some embodiments, the internal spacers include silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, the internal spacer has a convex shape facing the disposable material.

[0123] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a multilayer stack over a substrate, the multilayer stack including alternating layers of a first semiconductor layer and a second semiconductor layer; patterning the multilayer stack to define fins; forming a groove adjacent to the fins; selectively removing the first semiconductor layer; forming a sacrificial material between the second semiconductor layers; performing a doping process on the sacrificial material and the second semiconductor layer to change etch selectivity; growing an epitaxial source / drain region adjacent to the second semiconductor layer in the groove; and replacing the sacrificial material with a metal gate structure.

[0124] In some embodiments, the doping process includes introducing a dopant comprising phosphorus, arsenic or antimony, germanium, xenon, argon, silicon, nitrogen, boron, boron fluoride, indium, and carbon. In some embodiments, the sacrificial material comprises a material selected from the group consisting of silicon oxide, silicon oxynitride, and aluminum oxide. In some embodiments, the doping process is a plasma doping process. In some embodiments, the method further includes forming internal spacers on the sidewalls of the sacrificial material after performing the doping process. In some embodiments, the method further includes performing an implantation process to introduce a dopant into the epitaxial source / drain regions after growing the epitaxial source / drain regions.

[0125] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a fin of a multilayer stack above a substrate, the multilayer stack including alternating layers of a first semiconductor layer and a second semiconductor layer; forming a first gate structure above the fin; etching a first groove in the fin; removing the first semiconductor layer from the fin; forming a dielectric material between the second semiconductor layers and in the first groove; recessing the sidewalls of the dielectric material in the first groove to form a second groove between adjacent second semiconductor layers; performing a doping process in the first groove and the second groove on the dielectric material and the second semiconductor layer; forming an internal spacer on the recessed sidewalls of the dielectric material; forming a source / drain region adjacent to the internal spacer and the second semiconductor layer in the first groove; performing an ion implantation process to introduce a dopant into the source / drain region; and replacing the first gate structure and the dielectric material with a metal gate structure.

[0126] In some embodiments, the doping process includes plasma doping. In some embodiments, the doping process includes tilted ion implantation.

[0127] The described embodiments may also include one or more of the following features: The doping process may include introducing dopants such as phosphorus, arsenic or antimony, germanium, xenon, argon, silicon, nitrogen, boron, boron fluoride, indium, and carbon. The sacrificial material may include a material selected from the group consisting of silicon oxide, silicon oxynitride, and aluminum oxide. The doping process may be a plasma doping process. The method may include forming internal spacers on the sidewalls of the sacrificial material after performing the doping process. The method may include performing an implantation process to introduce dopants into the epitaxial source / drain regions after growing the epitaxial source / drain regions.

[0128] In embodiments, the method may include forming fins of a multilayer stack over a substrate. The multilayer stack includes alternating layers of first and second semiconductor layers. The method may also include forming a first gate structure over the fin. Furthermore, the method may include etching a first groove in the fin. Additionally, the method may include removing the first semiconductor layer from the fin. Moreover, the method may include forming a dielectric material between the second semiconductor layers and in the first groove. The method may also include recessing the sidewalls of the dielectric material in the first groove to form a second groove between adjacent second semiconductor layers. Furthermore, the method may include performing a doping process in the first and second grooves on the dielectric material and the second semiconductor layer. Additionally, the method may include forming internal spacers on the recessed sidewalls of the dielectric material. Moreover, the method may include forming source / drain regions adjacent to the internal spacers and the second semiconductor layer in the first groove. The method may also include performing an ion implantation process to introduce dopant into the source / drain regions. Furthermore, the method may include replacing the first gate structure and the dielectric material with a metal gate structure.

[0129] The described embodiments may also include one or more of the following features: The doping process may include plasma doping or tilted ion implantation.

[0130] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A multilayer stack is formed over a substrate, the multilayer stack comprising alternating layers of a first semiconductor layer and a second semiconductor layer; Remove the first semiconductor layer; A one-time material is formed between the second semiconductor layers; A first implantation process is performed on the disposable material and the second semiconductor layer; Forming a source / drain region adjacent to the second semiconductor layer and the disposable material; as well as Replace the disposable material with a metal gate structure.

2. The method according to claim 1, wherein, The disposable material is selected from the group consisting of silicon dioxide, silicon oxynitride, and aluminum oxide.

3. The method according to claim 1, further comprising: After the primary material is formed between the second semiconductor layers, a second implantation process is performed to introduce an n-type dopant into the source / drain region.

4. The method according to claim 1, wherein, The first implantation process is performed on the disposable material and the second semiconductor layer, including a tilting implantation process.

5. The method according to claim 1, wherein, The first injection process includes plasma.

6. The method according to claim 1, wherein, Performing the first implantation process on the disposable material and the second semiconductor layer includes implanting phosphorus, arsenic or antimony, germanium, xenon, argon, silicon, nitrogen, boron, boron fluoride, indium, and carbon.

7. The method according to claim 1, wherein, Applying the first implantation process to the disposable material and the second semiconductor layer alters the etch selectivity between the second semiconductor layer and the disposable material.

8. The method according to claim 1, wherein, Replacing the disposable material with the metal gate structure also includes: The disposable material is removed using an etching process that selectively etches the disposable material above the second semiconductor layer.

9. A method for forming a semiconductor device, comprising: A multilayer stack is formed over a substrate, the multilayer stack comprising alternating layers of a first semiconductor layer and a second semiconductor layer; Pattern the multilayer stack to define the fins; A groove is formed adjacent to the fin; Selectively remove the first semiconductor layer; A sacrificial material is formed between the second semiconductor layers; The sacrificial material and the second semiconductor layer are subjected to a doping process to change the etch selectivity; An epitaxial source / drain region adjacent to the second semiconductor layer is grown in the groove; as well as The sacrificial material is replaced with a metal gate structure.

10. A method of forming a semiconductor device, comprising: A fin of a multilayer stack is formed above a substrate, the multilayer stack comprising alternating layers of a first semiconductor layer and a second semiconductor layer; A first gate structure is formed above the fin; A first groove is etched in the fin; Remove the first semiconductor layer from the fin; Dielectric material is formed between the second semiconductor layers and in the first groove; The sidewalls of the dielectric material in the first groove are recessed to form a second groove between adjacent second semiconductor layers; A doping process is performed in the first and second grooves on the dielectric material and the second semiconductor layer; An internal spacer is formed on the recessed sidewall of the dielectric material; A source / drain region adjacent to the internal spacer and the second semiconductor layer is formed in the first groove; An ion implantation process is performed to introduce dopant into the source / drain regions; as well as Replace the first gate structure and the dielectric material with a metal gate structure.

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