Semiconductor structure and forming method thereof

Abstract

Some embodiments of the present disclosure provide a semiconductor structure and a method of forming the same. A method of forming a semiconductor structure includes the following steps. The method includes forming a first conductive feature over a substrate, forming a first dielectric layer over the first conductive feature, forming a second dielectric layer over the first dielectric layer, forming a patterned mask over the second dielectric layer, performing a first etch process to form a trench extending through the first dielectric layer and the second dielectric layer to expose a top surface of the first conductive feature, and forming a second dielectric layer over the patterned mask. Wherein the etchant of the first etching process modifies a portion of the first dielectric layer exposed by the trench, performing a second etching process to remove the patterned mask and the modified portion of the first dielectric layer, and wherein the etchant of the second etching process further reacts with a portion of the remaining portion of the first dielectric layer, and forming a second conductive feature in the trench to cause a volume expansion of the remaining portion of the first dielectric layer.

Description

Technical Field

[0001] Some embodiments disclosed herein relate to a semiconductor structure and a method for forming a semiconductor structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded generations of ICs, each with circuits that are smaller and more complex than the previous generation. In IC development, functional density (i.e., the number of interconnects per wafer area) typically increases, while geometry (i.e., the smallest components or lines that can be produced using manufacturing processes) decreases. This scaling down process usually yields benefits through increased production efficiency and reduced associated costs.

[0003] As integrated circuit (IC) technology advances to smaller technology nodes, the risk of unwanted coupling between two adjacent conductive elements (e.g., a gate via and its adjacent source / drain contact) increases. While existing methods for forming gate vias are generally sufficient for intended use, these methods are not satisfactory in all cases. Summary of the Invention

[0004] Some embodiments disclosed herein relate to a method of forming a semiconductor structure, comprising the following steps: Receiving a semiconductor structure, the semiconductor structure including a gate structure located above a channel region, source / drain features coupled to the channel region, and source / drain contacts coupled to the source / drain features. Forming a low-k etch-stop layer above the source / drain contacts. Forming a dielectric layer above the low-k etch-stop layer. Performing an etching process to form a via opening extending through the dielectric layer and the low-k etch-stop layer to expose the gate structure. Performing a process on the structure to oxidize a portion of the low-k etch-stop layer adjacent to the via opening. Forming a gate via in the via opening.

[0005] Some embodiments disclosed herein relate to a method of forming a semiconductor structure, comprising the following steps: forming a first dielectric layer over a first conductive feature; forming a second dielectric layer over the first dielectric layer, the first and second dielectric layers having different compositions; forming a patterned mask over the second dielectric layer, the patterned mask having an opening directly above the first conductive feature; performing a first etching process to form a trench extending through the first and second dielectric layers to expose the top surface of the first conductive feature, wherein the etchant of the first etching process modifies a portion of the first dielectric layer exposed by the trench; performing a second etching process to remove the patterned mask and the modified portion of the first dielectric layer, wherein the etchant of the second etching process further reacts with a portion of the remaining portion of the first dielectric layer to cause volume expansion of the remaining portion of the first dielectric layer; and forming a second conductive feature in the trench.

[0006] Some embodiments disclosed herein relate to a semiconductor structure. The semiconductor structure includes a gate structure located above a channel region, source / drain features coupled to the channel region, a first dielectric layer located above the gate structure, a second dielectric layer located on the first dielectric layer, and a gate via extending along the first and second dielectric layers to couple to the gate structure. The first dielectric layer includes a first portion surrounding a portion of the gate via and a second portion surrounding the first portion, and the composition of the first portion of the first dielectric layer differs from the composition of the second portion of the first dielectric layer. Attached Figure Description

[0007] Some embodiments of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A flowchart illustrating a method for forming a semiconductor structure according to one or more embodiments of the present disclosure;

[0009] Figure 2 The description of various states according to some embodiments of this disclosure is as follows. Figure 1 A top view of a fragment of an exemplary structure that undergoes each operational stage in the method;

[0010] Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A and Figure 14A ( Figures 3A to 14A This describes one or more aspects of the embodiments disclosed herein. Figure 1 During each manufacturing stage of the method Figure 2 A cross-sectional view of the structure segment cut by line A-A' shown in the figure;

[0011] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B and Figure 14B ( Figures 3B to 14B This describes one or more aspects of the embodiments disclosed herein. Figure 1 During each manufacturing stage of the method Figure 2 A cross-sectional view of the structure segment cut by line B-B' shown in the figure;

[0012] Figure 15A , Figure 16A , Figure 17A and Figure 18A ( Figures 15A to 18A This describes one or more aspects of the embodiments disclosed herein. Figure 1 During each manufacturing stage of the method Figure 2 A cross-sectional view of the alternative structure segment cut by line A-A' shown in the figure;

[0013] Figure 15B , Figure 16B , Figure 17B and Figure 18B ( Figures 15B to 18B This describes one or more aspects of the embodiments disclosed herein. Figure 1 During each manufacturing stage of the method Figure 2 The cross-sectional view of the alternative structure segment cut by line B-B' shown.

[0014] [Symbol Explanation]

[0015] 10: First Area

[0016] 20: Second Zone

[0017] 100: Method

[0018] Blocks 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126

[0019] 200: Semiconductor Structure

[0020] 202:Substrate

[0021] 204: Fin-shaped active region

[0022] 204C: Channel Area

[0023] 204SD: Source / Drain Region

[0024] 208: Channel Layer

[0025] 210: Dummy gate stack

[0026] 210a: Dummy gate dielectric layer

[0027] 210b: Dummy gate electrode layer

[0028] 210c: Gate top hard masking layer

[0029] 212: Gate spacer

[0030] 214: Source / Drain Opening

[0031] 216: Internal Spacing Characteristics

[0032] 222: Source / Drain Characteristics

[0033] 226: Contact Etching Termination Layer

[0034] 228: First ILD layer

[0035] 230: Gate structure

[0036] 230a: Interface Layer

[0037] 230b: Dielectric layer

[0038] 230c: Work Function Layer

[0039] 230d: Metal filler layer

[0040] 236: Etching stop layer

[0041] 238: Second ILD layer

[0042] 240: Dielectric barrier layer

[0043] 241: Silicide layer

[0044] 242: Source / Drain Contact

[0045] 246, 246': Etching stop layer

[0046] 246a~246h: Correction area

[0047] 248: Third ILD layer

[0048] 250: Mask

[0049] 250a: Bottom layer

[0050] 250b: Intermediate layer

[0051] 250c: Top Floor

[0052] 252, 252', 254, 254': Opening

[0053] 256: First Etching Process

[0054] 258a~258d: Through-hole opening

[0055] 260, 260': Process

[0056] 262a~262h: Dielectric characteristics

[0057] 264a~264d: Gate vias

[0058] 266, 266': Metal oxide layer

[0059] 268: Third Etching Process

[0060] A-A', B-B': line

[0061] X, Y, Z: Direction Detailed Implementation

[0062] The following disclosure provides several different embodiments or instances for implementing the various features of the provided target. Specific examples of components and arrangements described below are used to simplify some embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, some embodiments of this disclosure may repeat element symbols or letters in various instances. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0063] Furthermore, for ease of description, some embodiments of this disclosure may use spatially relative terms such as “below,” “under,” “below,” “above,” or “above” to describe the relationship between one element or feature and another as shown in the figures. In addition to the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0064] Furthermore, when using terms such as "about," "approximately," etc., to describe a number or range of numbers, the term is intended to encompass a reasonable range of numbers that take into account variations inherent in manufacturing, as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing features having characteristics related to that number, a number or range of numbers encompasses a reasonable range including said number, such as within + / - 10% of said number. For example, a material layer with a thickness of "about 5 nm" may encompass a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%.

[0065] IC manufacturing processes are generally categorized into three types: front-end-of-line (FEOL) processes, middle-end-of-line (MEOL) processes, and back-end-of-line (BEOL) processes. FEOL processes typically encompass those related to manufacturing IC devices (such as transistors). For example, FEOL processes may include forming isolation features, gate structures, and source / drain features. A source / drain feature can refer to either the source or the drain, individually or collectively, depending on the context. MEOL processes typically encompass those related to the contact aspects of conductive features in IC devices, such as gate vias in gate structures and / or source / drain contacts in source / drain features. BEOL processes typically encompass those related to manufacturing multilayer interconnect structures that interconnect IC features manufactured through FEOL and MEOL processes, enabling the IC device to function. Features manufactured using FEOL processes are referred to as FEOL features. Features manufactured using MEOL processes are referred to as MEOL features. Features manufactured using BEOL processes are referred to as BEOL features.

[0066] When the distance between two adjacent conductive features is reduced to meet the design requirements of smaller technology nodes, high parasitic capacitance can lead to low device speeds (e.g., RC delay). Low-k dielectric (low-k) materials can be incorporated to reduce parasitic capacitance, thereby lowering RC delay. For example, etch-stop layers may include low-k materials. However, some low-k materials are porous and more susceptible to damage during etching processes, leading to device performance degradation or reliability issues. For instance, during middle-end-of-line (MEOL) processes, to form gate vias, an etching process may be performed to etch multiple dielectric layers to form gate via trenches exposing the gate structure, and an ashing process may be performed to remove the mask used during the etching process. The execution of the etching and ashing processes can result in lateral over-etching of the low-k etch-stop layer. Furthermore, misalignment and overlap issues in the gate via trench formation process can further exacerbate over-etching, resulting in a reduced process window for forming gate vias and even degraded chip integration performance. For example, due to overlap issues, the distance between the source / drain contact and the gate via trench may be reduced, and in a cross-sectional view, the side of the gate via trench closer to the source / drain contact may be etched laterally more than the other side. This could result in one side of the gate via having a curved sidewall profile protruding towards the source / drain contact. That is, the gate via formed in the gate via trench may have an asymmetrical profile, including a vertically extending main portion and an auxiliary portion protruding laterally from the main portion, located between the main portion and the source / drain contact. Therefore, due to the presence of the auxiliary portion, the distance between the resulting gate via and the source / drain contact is undesirably reduced. The close proximity between the source / drain contact and the gate via can lead to undesirable leakage between the gate via and the source / drain contact.

[0067] Some embodiments disclosed herein provide a method for preventing undesirable leakage between the gate via and the source / drain contact by reducing or even eliminating the formation of unwanted auxiliary portions of the gate via. In an exemplary method, after performing an etching process to form the gate via trench, an ashing process is performed to not only remove the mask but also react with a low-k etch-stop layer to cause localized volume expansion of the low-k etch-stop layer. In embodiments, the ashing process employs a combination of oxygen and hydrogen. The gate structure exposed by the gate via trench may undergo oxidation and reduction reactions during the ashing process. By using a low-k etch-stop layer, parasitic capacitance of the structure can be advantageously reduced, and the choice of etchant used during the ashing process will facilitate localized volume expansion of the low-k etch-stop layer to eliminate undesirable leakage between the gate via and the source / drain contact.

[0068] Various aspects of some embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. Figure 1A flowchart illustrating a method 100 for forming a semiconductor structure 200 according to some embodiments of this disclosure is provided below. Figure 2 , Figures 3A to 18A and Figures 3B to 18B Description method 100, Figure 2 , Figures 3A to 18A and Figures 3B to 18B These are top-view / cross-sectional views of a semiconductor structure 200 at different manufacturing stages according to an embodiment of method 100. Method 100 is merely an example and is not intended to limit some embodiments of this disclosure to what is explicitly described therein. Additional steps may be provided before, during, and after method 100, and some described steps may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, some embodiments of this disclosure do not describe all steps in detail. To avoid doubt, Figure 2 and Figures 3A to 18B The directions X, Y, and Z are perpendicular to each other and are used consistently throughout some embodiments of this disclosure. Throughout some embodiments of this disclosure, unless otherwise stated, the same element symbols denote the same features.

[0069] See Figure 1 , Figure 2 , Figure 3A and Figure 3B Method 100 includes block 102, wherein a semiconductor structure 200 including a first region 10 and a second region 20 is received. In some embodiments disclosed herein, the first region 10 represents a region where misalignment and overlap problems do not occur during the formation of a gate via, while the second region 20 represents a region where misalignment and overlap problems do occur during the formation of a gate via. Figure 2 Describing various states of experience according to some embodiments of this disclosure Figure 1 A top view of a fragment of the semiconductor structure 200 at each operational stage of the method. Figure 3A Explanation along Figure 2 The diagram shows a cross-sectional view of a segment of semiconductor structure 200 taken along line A-A', while... Figure 3B Explanation along Figure 2 The image shows a cross-sectional view of a segment of semiconductor structure 200 taken along line B-B'. Figure 3A and Figure 3BAs shown, the semiconductor structure 200 includes a substrate 202. The substrate 202 can be an elemental (single-element) semiconductor, such as crystalline silicon (Si) or germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); or an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP). In one embodiment, the substrate 202 is a silicon (Si) substrate. The composition of the substrate 202 can be homogeneous, or it can include various layers, some of which can be selectively etched to form finned active regions (e.g., finned active regions 204). These layers may have similar or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to cause device strain and thereby adjust device performance. Examples of layered substrates include silicon-on-insulator (SOI) substrates 202. In some such examples, the layers of substrate 202 may include insulators, such as semiconductor oxides, semiconductor nitrides, semiconductor oxide nitrides, semiconductor carbides, and / or other suitable insulating materials. Doped regions, such as wells, may be formed in substrate 202.

[0070] See also Figure 2 , Figure 3A and Figure 3B The semiconductor structure 200 includes multiple fin-shaped active regions 204 protruding from the substrate 202. Figure 2 , Figure 3A and Figure 3B The number of finned active regions 204 depicted is merely an example; the semiconductor structure 200 may include any suitable number of finned active regions. Each finned active region 204 extends longitudinally along direction X and is divided into a channel region 204C overlapping with the dummy gate stack 210 (described below) and a source / drain region 204SD adjacent to the channel region 204C. The source / drain region 204SD may refer individually or collectively to the source region or the drain region, depending on the context. Each channel region 204C is disposed along direction X between the two source / drain regions 204SD.

[0071] In an embodiment where the semiconductor structure 200 is fabricated to include a FinFET, each finned active region 204 may be formed from the top portion of the substrate 202. In an embodiment where the semiconductor structure 200 is fabricated to include a gate-all-around (GAA) transistor, each finned active region 204 may include a vertically stacked (not shown) alternating semiconductor layers and a portion of the substrate 202. The vertically stacked layer includes multiple channel layers 208 (e.g., ...) interleaved with multiple sacrificial layers (not shown). Figure 14A and Figure 14B (As shown). Each channel layer 208 may include a semiconductor material such as silicon, germanium, silicon carbide, silicon germanium, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof, while the composition of each sacrificial layer differs from that of the channel layer 208. In an embodiment, each channel layer 208 includes silicon (Si), and each sacrificial layer includes silicon germanium (SiGe).

[0072] Semiconductor structure 200 also includes isolation features (not shown) formed around fin active regions 204 to isolate two adjacent fin active regions 204. The isolation features may include shallow trench isolation (STI) features. In an exemplary process, a dielectric material for the isolation features is first deposited over semiconductor structure 200 to fill the trench between the fin active regions 204. In some embodiments, the dielectric material may include silicon oxide, silicon oxynitride, fluorosilicate glass (FSG), low-k dielectric materials and combinations thereof, and / or other suitable materials. In various instances, the dielectric material may be deposited via CVD processes, flowable CVD (FCVD) processes, spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process, until the top surface of the fin active regions 204 is exposed. The planarized dielectric material is further etched or etched back using dry etching processes, wet etching processes, and / or combinations thereof to form the STI features. The upper portion of the fin-shaped active region 204 protrudes from the STI feature, while the lower portion of the fin-shaped active region 204 remains covered or embedded in the STI feature. The deposited dielectric material can be a single-layer or multi-layer structure.

[0073] Semiconductor structure 200 also includes dummy gate stacks 210. Each dummy gate stack 210 includes a dummy gate dielectric layer 210a, a dummy gate electrode layer 210b above the dummy gate dielectric layer 210a, and a gate top hard mask layer 210c above the dummy gate electrode layer 210b. The dummy gate dielectric layer 210a may include silicon oxide. The dummy gate electrode layer 210b may include polysilicon. The gate top hard mask layer 210c may include silicon oxide, silicon nitride, and / or other suitable materials. The dummy gate stacks 210 can be formed using appropriate deposition processes, photolithography, and etching processes. In this embodiment, a gate replacement process (or post-gate process) is used, wherein the dummy gate stacks 210 serve as functional gate structures (e.g., Figure 7A and Figure 7B The placeholder for the gate structure 230 shown. Other processes and configurations are also possible. Figure 2 , Figure 3A and Figure 3B The number of dummy gate stacks 210 depicted is merely an example, and the semiconductor structure 200 may include any appropriate number of dummy gate stacks 210.

[0074] See Figure 1 , Figure 4A and Figure 4BMethod 100 includes block 104 in which source / drain openings 214 are formed. Prior to forming the source / drain openings, gate spacers 212 are formed to extend along the sidewall surfaces of the dummy gate stack 210. Each gate spacer 212 may be a single-layer or multi-layer structure. In exemplary processes, spacer layers are conformally deposited over the semiconductor structure 200 by atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable deposition process. Some embodiments of this disclosure may use the term "conformally" to describe layers having a substantially uniform thickness over various regions of the semiconductor structure 200. The spacer layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, metal nitride, other suitable dielectric materials, or combinations thereof. An etching process is performed to remove a portion of the spacer layer above the top surface of the semiconductor structure 200 to form gate spacers 212 extending along the sidewalls of the dummy gate stack 210. The source / drain regions 204SD of the finned active region 204 are then recessed to form source / drain openings 214. In some embodiments, the source / drain regions 204SD of the finned active region 204 are anisotropically etched by plasma etching with a suitable etchant. In embodiments where the semiconductor structure 200 is fabricated to include a GAA transistor, after forming the source / drain openings 214, vertically stacked sacrificial layers are selectively etched laterally to form inner spacer recesses. Internal spacer features 216 (such as...) are then formed in the inner spacer recesses. Figure 14A and Figure 14B (As shown). The internal spacer feature 216 may include any suitable dielectric material SiN, SiO and / or SiO2, SiCN, SiOC, SiON, SiOCN, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The internal spacer feature 216 may be used as a single-layer structure or a multilayer structure including the dielectric material combinations provided in some embodiments of this disclosure. In some embodiments, the internal spacer feature 216 has a different composition than the gate spacer 212.

[0075] See now Figure 1 and Figure 5A and Figure 5BMethod 100 includes block 106, in which source / drain features 222 are formed in source / drain openings 214. Source / drain features 222 may individually or collectively refer to a source or drain, depending on the context. Source / drain features 222 are coupled to channel region 204C. Each source / drain feature 222 can be selectively formed by epitaxy of a self-exposed semiconductor surface using epitaxial processes such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular-beam epitaxy (MBE), and / or other suitable processes. Exemplary N-type source / drain features may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and can be in-situ doped during the epitaxial process by introducing N-type dopants (such as phosphorus, arsenic, or antimony), or non-prestigious doped using a bonding implantation process. Exemplary P-type source / drain features may include germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, and may be performed in situ doping during the epitaxial process by introducing a P-type dopant (such as boron or gallium), or out-of-field doping using a bonding implantation process. In some embodiments, each of the N-type and P-type source / drain features may include multiple semiconductor layers with different doping concentrations. The N-type and P-type source / drain features may be formed in any suitable order.

[0076] See now Figure 1 , Figure 6A and Figure 6BMethod 100 includes block 108, wherein a first interlayer dielectric (ILD) layer 228 is formed over substrate 202. A contact etch stop layer (CESL) 226 and the first interlayer dielectric (ILD) layer 228 are deposited over semiconductor structure 200. The contact etch stop layer 226 may include silicon nitride, silicon oxynitride, and / or other suitable materials, and may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD), and / or other suitable deposition or oxidation processes. After depositing the contact etch stop layer 226, the first ILD layer 228 is deposited on semiconductor structure 200 by PECVD or other suitable deposition techniques. The first ILD layer 228 may include materials such as tetraethoxysilane (TEOS) oxide, undoped silicon glass, or doped silicon oxide such as borosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. A planarization process (such as chemical mechanical polishing (CMP)) may be performed on the semiconductor structure 200 to remove excess material and expose the top surface of the dummy gate electrode layer 210b in the dummy gate stack 210.

[0077] See now Figure 1 , Figure 7A and Figure 7BMethod 100 includes block 110, wherein the dummy gate stack 210 is replaced by a metal gate structure 230. After exposing the top surface of the dummy gate electrode layer 210b in the dummy gate stack 210, an etching process is performed to selectively remove the dummy gate electrode layer 210b and the dummy gate dielectric layer 210a of the dummy gate stack 210, without substantially removing the gate spacer 212, to form a gate trench. The metal gate structure 230 is then formed in the gate trenches in the first region 10 and the second region 20. The formation of the metal gate structure 230 includes forming an interface layer 230a over the substrate 202. The interface layer 230a may comprise silicon oxide or other suitable materials and may be formed using suitable methods, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), thermal oxidation, or other suitable methods. In an embodiment, the interface layer 230a is formed by thermal oxidation. After forming the interface layer 230a, a dielectric layer 230b is formed over the semiconductor structure 200 and in the gate trench. In embodiments, the dielectric layer 230b is conformally deposited over the semiconductor structure 200. Some embodiments of this disclosure may use the term "conformal" to conveniently describe layers having substantially uniform thickness over various regions. In some embodiments, the dielectric layer 230b is a high-k dielectric layer because the dielectric constant of the dielectric layer 230b is greater than that of silicon dioxide (~3.9). In some implementations, dielectric layer 230b may comprise titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), and combinations thereof, or other suitable materials. Dielectric layer 230b and interface layer 230a may be collectively referred to as the gate dielectric layer.

[0078] The formation of the metal gate structure 230 also includes forming a gate electrode over the gate dielectric layer. The gate electrode may be a multilayer structure, including at least one work function layer 230c and a metal filler layer 230d. For example, the at least one work function layer may include titanium nitride (TiN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum nitride (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal filler layer 230d may include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. In various embodiments, the gate electrode may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electron beam evaporation, or other suitable processes. In various embodiments, planarization processes, such as chemical mechanical polishing (CMP), may be performed to remove excess material above the first ILD layer 228, thereby providing a substantially flat top surface and facilitating further processing.

[0079] For an embodiment of fabricating semiconductor structure 200 to form a GAA transistor, prior to forming metal gate structure 230, method 100 further removes a sacrificial layer from the vertical stack during the wafer (or wire) fabrication process, thereby forming openings (not shown) between channel layers 208 (e.g., Figure 14A and Figure 14B (As shown). In this embodiment, the wafer fabrication process selectively removes the sacrificial layer without removing or substantially removing the channel layer 208. The metal gate structure 230 is further used to surround the channel layer 208.

[0080] See now Figure 1 , Figure 8A and Figure 8BMethod 100 includes block 112, wherein a second interlayer dielectric (ILD) layer 238 is formed over substrate 202. After forming metal gate structure 230, an etch stop layer 236 is formed over first interlayer dielectric (ILD) layer 228. Etch stop layer 236 may include silicon nitride, silicon oxynitride, and / or other suitable materials, and may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. In an embodiment, etch stop layer 236 includes silicon nitride. The composition of etch stop layer 236 may be the same as or different from that of contact etch stop layer 226. Formation of etch stop layer 236 may facilitate the formation of gate vias over metal gate structure 230 during subsequent manufacturing processes. Second ILD layer 238 is deposited on etch stop layer 236 on semiconductor structure 200 by PECVD process or other suitable deposition techniques. The second ILD layer 238 may include materials such as tetraethoxysilane (TEOS) oxide, undoped silicon glass or doped silicon oxide, such as borosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG) and / or other suitable dielectric materials.

[0081] See also Figure 1 , Figure 8A and Figure 8B Method 100 includes block 114 in which source / drain contacts 242 are formed extending through a first ILD layer 228 and a second ILD layer 238 to couple to source / drain features 222. In an embodiment, a patterned mask (not shown) is formed over the second ILD layer 238. While using the patterned mask as an etch mask, an etch process is performed to form source / drain contact trenches that extend through multiple dielectric layers (e.g., the first ILD layer 228, the second ILD layer 238, contact etch stop layer 226, and etch stop layer 236) and expose the source / drain features 222. After forming the source / drain contact trenches, a dielectric barrier layer 240 is formed to extend along the sidewall surface of each source / drain contact trench. In some embodiments, the dielectric barrier layer 240 is formed to enhance isolation between the source / drain contacts 242 and their adjacent gate structures 230. In an exemplary process, to form the dielectric barrier layer 240, a dielectric material layer is deposited over the semiconductor structure 200 (including in the source / drain contact trench), and then etched back to cover only the sidewalls of the source / drain contact trench and expose the source / drain features 222. The dielectric barrier layer 240 may include silicon nitride or other suitable materials.

[0082] After forming the dielectric barrier layer 240, a silicide layer 241 and source / drain contacts 242 are formed in the source / drain contact trench. To form the silicide layer 241, a metal precursor (e.g., titanium, tantalum, nickel, cobalt, or tungsten) is deposited over the semiconductor structure 200 (including the exposed surface of the source / drain feature 222). An annealing process is then performed to create silicide and / or germanization between the metal precursor and the exposed semiconductor surface. In some embodiments, unreacted metal precursors are selectively removed after forming the silicide layer 241. A conductive layer is then deposited over the semiconductor structure 200 (including in the source / drain contact trench and on the silicide layer 261). The conductive layer may include aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo) or other suitable materials and may be formed by any suitable deposition process (e.g., CVD). A planarization process (such as chemical mechanical polishing (CMP)) can then be performed to remove excess portions of the conductive layer to form source / drain contacts 242. Although not shown, in some embodiments, the source / drain contacts 242 may further include a conductive barrier layer (e.g., TiN, TaN, W) extending along the sidewalls and bottom surface of the conductive layer. In one embodiment, each source / drain contact 242 includes a barrier layer formed of titanium or titanium nitride extending along the sidewall and bottom surface of the conductive layer formed of cobalt. In another embodiment, each source / drain contact 242 includes a barrier layer formed of tungsten extending along the sidewall and bottom surface of the conductive layer deposited by physical vapor deposition (PVD).

[0083] See now Figure 1 , Figure 9A and Figure 9BMethod 100 includes block 116, wherein an etch stop layer 246 and a third ILD layer 248 are formed over a second ILD layer 238. After forming the source / drain contact 242, the etch stop layer 246 is formed on the source / drain contact 242 and the second ILD layer 238. The etch stop layer 246 can be formed by any suitable deposition process (such as CVD, PVD, ALD, high-density plasma chemical vapor deposition (HDPCVD), plasma-enhanced chemical vapor deposition (PECVD), other suitable methods, or combinations thereof). In this embodiment, to reduce parasitic capacitance, the etch stop layer 246 is a porous low-k material layer, and the dielectric constant of the etch stop layer 246 is less than the dielectric constant of the contact etch stop layer 226. For example, the etch stop layer 246 is formed of silicon carbonitride (SiCN). In this embodiment, the contact etch stop layer 226 is formed of SiN, and the nitrogen concentration of the etch stop layer 246 is lower than that of the contact etch stop layer 226. After forming the etch stop layer 246, a third ILD layer 248 is formed on the etch stop layer 246. The third ILD layer 248 may comprise materials such as tetraethoxysilane (TEOS) oxide, undoped silicon glass or doped silicon oxide, such as borosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG) and / or other suitable dielectric materials, and may be formed by any suitable deposition process (such as CVD, PVD, ALD, HDPCVD, PECVD, other suitable methods or combinations thereof).

[0084] See now Figure 1 , Figure 10A and Figure 10BMethod 100 includes block 118, wherein a patterned mask 250 is formed over a third ILD layer 248. In the illustrated embodiment, the patterned mask 250 is a three-layer structure having a bottom layer 250a, an intermediate layer 250b above the bottom layer 250a, and a top layer 250c above the intermediate layer 250b. The top layer 250c may be an exposure-sensitive photoresist (PR) layer. The intermediate layer 250b may be an anti-reflective layer to aid exposure and focusing when patterning the top layer 250c. The intermediate layer 250b may be a silicon-containing intermediate layer (e.g., spin-coated glass). In an embodiment, the intermediate layer 250b includes silicon and oxygen. The bottom layer 250a may be an organic film underlayer to provide further anti-reflective and etch-resistant properties when using the later-formed patterned bottom layer 250a as an etching mask. The bottom layer 250a may include carbon, nitrogen, hydrogen, and / or oxygen, but does not contain silicon. In some embodiments, the bottom layer 250a includes a bottom anti-reflection coating (BARC) layer.

[0085] In the exemplary process, see Figure 10A and Figure 10B After forming a mask 250 above the substrate 202, the top layer 250c of the mask 250 is patterned to form one or more openings 252 and 252' above the gate structure 230. The opening 252 is formed in the first region 10, and the opening 252' is formed in the second region 20. In this embodiment, the opening 252 in the first region 10 does not substantially experience misalignment or overlap, while the opening 252' in the second region 20 does experience misalignment and overlap. For example, the center line of the opening 252 may overlap with the center line of the gate structure 230 below it. Figure 10A The distance between the center line of the opening 252' and the center line of the gate structure 230 below it (represented by dashed lines) can be less than that between the center line of the opening 252' and the center line of the gate structure 230 below it. Figure 10B The distance between (represented by dashed lines). Using a patterned top layer 250c as an etching mask, an etching process is performed to pattern the intermediate layer 250b and the bottom layer 250a by transferring the pattern of the top layer 250c to the intermediate layer 250b and the bottom layer 250a. The patterned bottom layer 250a includes an opening 254 in the first region 10 (e.g., ...). Figure 11A (as shown) and the opening 254' in the second region 20 (as shown) Figure 11B (As shown). After patterning the bottom layer 250a, the top layer 250c and the middle layer 250b can be selectively removed, and the patterned bottom layer 250a remains above the third ILD layer 248.

[0086] See now Figure 1 , Figure 11A and Figure 11BMethod 100 includes block 120, in which a first etching process 256 is performed to form via openings (e.g., via openings 258a-258d) extending through a first ILD layer 228, a second ILD layer 238, a third ILD layer 248, a contact etch stop layer 236, and an etch stop layer 246 to expose a gate structure 230. While using a patterned underlayer 250a as an etch mask, the first etching process 256 is performed to form via openings 258a and 258b in a first region 10 and via openings 258c and 258d in a second region 20. In embodiments, the first etching process 256 may be a dry etching process performed using a fluorinated gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), other suitable gases, and / or plasma and / or combinations thereof. Free radicals and ions in the plasma of the first etching process 256 can alter a portion of the etching termination layer 246 adjacent to the via openings 258a-258d. More specifically, in Figure 11A and Figure 11B In the cross-sectional view shown, the etch termination layer 246 includes modified regions 246a and 246b adjacent to the via opening 258a in the first region 10, modified regions 246c and 246d adjacent to the via opening 258b in the first region 10, modified regions 246e and 246f adjacent to the via opening 258c in the second region 20, and modified regions 246g and 246h adjacent to the via opening 258d in the second region 20. Modified regions 246a to 246h may be referred to as etchant-modified dielectric features 246a to 246h, respectively. For embodiments where the etchant includes a fluorine-containing gas, modified regions 246a to 246h may also be referred to as fluorine-doped dielectric features 246a to 246h (e.g., SiCN:F). As described above, the etch termination layer 246 is a porous low-k dielectric layer and may be slightly etched during the etching process (e.g., the first etching process 256). Byproducts (e.g., polymers) from the first etching process 256 can refill the grooves formed due to the slight etching of the etch termination layer 246. Therefore, in some embodiments, the correction regions 246a–246h may also include byproducts (e.g., polymers) from the first etching process 256.

[0087] In some embodiments disclosed herein, the formation of via openings 258a and 258b in the first region 10 does not experience significant misalignment or overlap issues, while the formation of via openings 258c and 258d in the second region 20 does experience misalignment and / or overlap issues. Therefore, the distance between via opening 258c and its adjacent source / drain contact 242 is smaller than the distance between via openings 258a / 258b / 258d and their respective adjacent source / drain contacts 242. Due to the reduced distance, the source / drain contact 242 adjacent to via opening 258c can pull more free radicals and / or ions from the plasma of the first etching process 256 than other source / drain contacts 242, resulting in the width of the modified region 246e being greater than the widths of any other modified regions 246a-246d and 246f-246h. In the example, each of the correction regions 246a-246d and 246f-246h spans a width W1 along the direction X, and the correction region 246e spans a width W2 along the direction X and is greater than the width W1. In some embodiments disclosed herein, each of the via openings 258a-258d has a tapered profile and substantially linear sidewalls. For ease of description, the uncorrected region of the etch stop layer 246 will be referred to as the etch stop layer 246'.

[0088] See now Figure 1 , Figure 12A and Figure 12B Method 100 includes block 122, in which a second etching process 260 is performed to selectively remove the patterned underlayer 250a. In addition to the patterned underlayer 250a, the second etching process 260 also removes byproducts in the correction regions 246a–2466h, without substantially etching the uncorrected regions of the second ILD layer 238, the third ILD layer 248, the etch stop layer 246 (i.e., the etch stop layer 246'), and the contact etch stop layer 236. Since the second etching process 260 removes the patterned underlayer 250a of the patterned mask 250, the second etching process 260 can also be referred to as an ashing process 260.

[0089] Regions 246a to 246h include etchant-modified regions (e.g., SiCN:F) and have lower etch resistance than the unmodified regions (e.g., SiCN) of the etch stop layer 246 (i.e., etch stop layer 246'), and the execution of the second etching process 260 also removes the modified regions 246a to 246h. That is, the sidewalls of the etch stop layer 246' (e.g., SiCN:F) Figure 11AThe sidewalls 246s shown will be exposed through the gate via openings 258a to 258d. In other words, removing the correction regions 246a to 246h will cause the via openings 258a to 258d to expand laterally. Therefore, without intervention, the leakage risk between the source / drain contact 242 and the gate via that will be formed in the expanded via openings 258a to 258d will increase, especially the leakage risk between the source / drain contact 242 and the gate via that will be formed in the via opening 258c.

[0090] In some embodiments disclosed herein, to reduce the leakage risk between the source / drain contact 242 and adjacent gate vias, the etchant of the second etching process 260 is further selected to react with the exposed sidewalls of the etch stop layer 246', thereby causing local volume expansion to fill the grooves previously occupied by the modified regions 246a-246g. The reaction between the exposed sidewalls of the etch stop layer 246' and the etchant of the second etching process 260 forms dielectric features 262a, 262b, 262c, 262d, 262e, 262f, 262g, and 262h adjacent to the via openings 258a-258d. More specifically, dielectric features 262a and 262b are formed near via opening 258a, dielectric features 262c and 262d are formed near via opening 258b, dielectric features 262e and 262f are formed near via opening 258c, and dielectric features 262g and 262h are formed near via opening 258d. In an embodiment, the second etching process 260 is a plasma etching process implemented using an oxygen-based gas (e.g., O2), other suitable gases, and / or combinations thereof. For embodiments where the etch stop layer 246' comprises silicon carbonitride (SiCN), dielectric features 262a, 262b, 262c, 262d, 262e, 262f, 262g, and 262h each comprise silicon carbonitride oxide (SiOCN). The silicon carbonitride etch-stop layer 246' can be oxidized from the outside in, resulting in volume expansion of the silicon carbonitride dielectric features 262a, 262b, 262c, 262d, 262e, 262f, 262g, and 262h, as well as the etch-stop layer 246'. The formation and volume expansion of the dielectric features 262a, 262b, 262c, 262d, 262e, 262f, 262g, and 262h can substantially fill the grooves previously filled by the correction regions 246a to 246g. In other words, after performing the second etch process 260, the unreacted portion of the etch-stop layer 246' is separated from the via openings 258a to 258d by the dielectric features 262a to 262h, and the via openings 258a to 258d after performing the second etch process 260 have generally linear sidewalls. Since the etch stop layer 246' is vertically disposed between the second ILD layer 238 and the third ILD layer 248, which do not react with oxygen, each dielectric feature 262a, 262b, 262c, 262d, 262e, 262f, 262g, and 262h is limited to a height having a thickness approximately equal to that of the etch stop layer 246'. That is, the top and bottom surfaces of each dielectric feature 262a, 262b, 262c, 262d, 262e, 262f, 262g, and 262h are coplanar with the top and bottom surfaces of the etch stop layer 246', respectively.Each of dielectric features 262a, 262b, 262c, 262d, 262f, and 262g spans a width W1' along direction X, and dielectric feature 262e may span a width W2' greater than the width W1' along direction X. In an embodiment, dielectric feature 262e is in direct contact with the underlying dielectric barrier layer 240. In an embodiment, dielectric feature 262h vertically overlaps with the gate structure 230 exposed by the via opening 258d. In an embodiment, viewed from top, the gate via 264c is surrounded by annular dielectric features (e.g., dielectric features 262e and 262f) with non-uniform widths.

[0091] In embodiments where the etchant in the second etching process 260 includes oxygen, the top surface of the gate structure 230 exposed in the via openings 258a-258d will be oxidized. For example, the top portion of the work function layer 230c will be oxidized to form a first metal oxide layer, and the top portion of the metal filler layer 230d will be oxidized to form a second metal oxide layer. In embodiments where the work function layer 230c includes titanium nitride (TiN), the first metal oxide layer may include titanium oxynitride (TiON). In embodiments where the metal filler layer 230d includes tungsten, the second metal oxide layer may include tungsten oxide. In embodiments where the first and second metal oxide layers are removed without significantly reducing the volume of the gate structure 230 and adversely affecting the contact resistance Rc, the etchant in the second etching process 260 further includes hydrogen. The hydrogen will react with the first and second metal oxide layers to form a metal compound or metal. For example, the reduction reaction includes: H2 + TiON → TiN + H2O and / or H2 + WO x →W + H₂O. The reduction reaction between the metal oxide and hydrogen will form a conductive metal compound or metal (e.g., TiN or W). That is, the contact resistance Rc and volume of the gate structure 230 will not be substantially affected by performing the second etching process 260. In embodiments where the etchant of the second etching process 260 includes oxygen and hydrogen, performing the second etching process 260 achieves at least two functions: selectively removing the patterned underlayer 250a and byproducts of the first etching process; and obtaining a local volume expansion of the etch stop layer 246', reducing the risk of leakage, without substantially affecting the volume of the gate structure 230 exposed by the via openings 258a to 258d. In embodiments, the ratio of the hydrogen flow rate to the total flow rate of hydrogen and oxygen in the second etching process 260 is about 10% to about 40%. If the ratio is less than 10%, the reduction reaction between the metal oxide layer and hydrogen may be incomplete, which may adversely affect the contact resistance between the gate structure 230 and the gate via formed thereon; if the ratio is greater than about 40%, the oxidation reaction between the etch barrier layer 246' and oxygen may be incomplete, and the leakage window between the gate via and the source / drain contact may not be effectively changed.

[0092] See now Figure 1 , Figure 13A and Figure 13B Method 100 includes block 124, in which gate vias 264a-264d are formed in via openings 258a-258d. After performing a second etching process 260 and after forming dielectric features 262a-262h, gate vias 264a-264d are formed over gate structure 230 and in via openings 258a-258d, respectively. In an exemplary process, a barrier layer (not explicitly shown) is conformally deposited over semiconductor structure 200. The barrier layer may include a metal or metal nitride, such as titanium, titanium nitride, tantalum, tantalum nitride, cobalt nitride, nickel, tungsten, or tungsten nitride. Subsequently, a metal filler layer (not explicitly shown) may be deposited over the barrier layer. The metal filler layer may include tungsten, ruthenium, cobalt, nickel, or copper. A CMP process may then be performed to remove excess material, defining the final shape of the gate vias 264a-264d and providing a flat surface. Gate vias 264a to 264d respectively follow the shapes of via openings 258a to 258d. In this embodiment, the center line of gate via 264a is substantially aligned with the center line of the gate structure 230 below it, the center line of gate via 264b is substantially aligned with the center line of the gate structure 230 below it, the center line of gate via 264c is offset from the center line of the gate structure 230 below it, and the center line of gate via 264a is offset from the center line of the gate structure 230 below it. Each of the gate vias 264a to 264d is in direct contact with the etch stop layer 236, the second ILD layer 238, the corresponding dielectric features 262a, 262b, 262c, 262d, 262e, 262f, 262g or 262h, and the third ILD layer 248. Each of the gate vias 264a–264d is spaced from the etch stop layer 246' by a corresponding dielectric feature 262a, 262b, 262c, 262d, 262e, 262f, 262g, or 262h. By converting the modified regions 246a–246h and a portion of the etch stop layer 246' into dielectric features 262a–262d, the gate vias 264a–264d have substantially linear sidewall profiles that do not protrude into adjacent source / drain contacts 242. Therefore, the leakage risk between the gate vias and adjacent source / drain contacts can be advantageously reduced.

[0093] See Figure 1Method 100 includes block 126, in which further processes are performed. After forming gate vias 264a-264d, further processes are performed to complete the fabrication of semiconductor structure 200. For example, additional features, such as additional MEOL features and BEOL features (interconnect structures), may be formed above and / or below semiconductor structure 200. In some embodiments, the interconnect structure may include multiple intermetallic dielectric (IMD) layers and multiple metal lines or contact vias in each IMD layer. In some instances, the IMD layers and the first IMD layer 228 may share similar compositions. The metal lines and contact vias in each IMD layer may be formed of metals such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be lined with a barrier layer to prevent or reduce electromigration.

[0094] In the above embodiments, the semiconductor structure 200 is implemented using a fin-type field-effect transistor (FinFET). In some other embodiments, the semiconductor structure 200 may be implemented using a GAA transistor. For example, Figure 14A and Figure 14B An alternative embodiment is described, wherein the finned active region 204 includes a channel layer 208, wherein the gate structure 230 is bonded to the channel layer 208 to form a GAA transistor.

[0095] In reference Figures 12A to 14B In the embodiments described above, the etchant of the second etching process 260 includes a combination of oxygen and hydrogen, and during the execution of the second etching process 260, the first and second metal oxide layers formed on the gate structure 230 are converted into conductive materials. In embodiments where no reduction reaction occurs during the execution of the second etching process 260, an additional etching process is performed to selectively remove the first and second metal oxide layers. Figures 15A to 17B Alternative embodiments are described. See also Figure 15A and Figure 15B In the implementation of reference Figure 11A and Figure 11BFollowing the first etching process 256, a second etching process 260' is performed. The etchant in the second etching process 260' includes oxygen but not hydrogen. For example, the etchant in the second etching process 260' may include a combination of oxygen and nitrogen. Therefore, after performing the second etching process 260', the bottom layer 250a is removed to form dielectric features 262a to 262h, while the top portion of the conductive layer (e.g., the work function layer 230c and the metal fill layer 230d) of the gate structure 230 is oxidized to form a metal oxide layer 266 in the first region 10 and a metal oxide layer 266' in the second region 20. The metal oxide layers 266 and 266' may include titanium oxynitride, tungsten oxide, combinations thereof, or other possible materials. In some embodiments, due to overlapping and / or misalignment issues, via openings 258a to 258b expose a larger portion of the gate structure 230 beneath them than via openings 258c and 258d. Therefore, the width of the metal oxide layer 266 in the first region 10 may be greater than the width of the metal oxide layer 266' in the second region 20.

[0096] In this alternative embodiment, see Figure 16A and Figure 16B After performing the second etching process 260', a third etching process 268 is performed to selectively remove the metal oxide layers 266 and 266' to expose the unoxidized portions of the conductive layers (e.g., the work function layer 230c and the metal fill layer 230d) of the gate structure 230. In this embodiment, due to the selective removal of the metal oxide layers 266 and 266', the top surface of the unoxidized portion of the conductive layer of the gate structure 230 is lower than the top surface of the high-k dielectric layer 230b of the gate structure 230. That is, the via openings 258a to 258d extend vertically. See also Figure 17A and Figure 17B Gate vias 264a to 264d are formed in vertically extending via openings 258a to 258d, as described above. Figure 13A and Figure 13B As described above. In this embodiment, the bottom surface of each of the gate vias 264a to 264d may be lower than the top surface of the high-k dielectric layer 230b of the gate structure 230.

[0097] In the above reference Figures 15A to 17A and Figures 15B to 17B In the described alternative embodiments, semiconductor structure 200 is implemented using a FinFET. In some other embodiments, semiconductor structure 200 may be implemented using a GAA transistor. For example, Figures 18A to 18B An embodiment is described, in which the fin-shaped active region 204 includes a channel layer 208, wherein the gate structure 230 is bonded to the channel layer 208 to form a GAA transistor.

[0098] While not intended to be limiting, one or more embodiments disclosed herein offer numerous benefits for semiconductor structures and their formation. For example, parasitic capacitance of the semiconductor structure can be reduced by implementing a low-k etch-stop layer. The volume of the low-k dielectric layer can be increased, thereby reducing the risk of leakage between the source / drain contacts and adjacent gate vias. Thus, device performance and reliability of the semiconductor structure can be advantageously improved.

[0099] This disclosure provides many different embodiments. Some embodiments of this disclosure disclose a semiconductor structure and a method of manufacturing the same. In one exemplary embodiment, some embodiments of this disclosure relate to a method of forming a semiconductor structure, comprising the following steps: receiving a semiconductor structure including a gate structure located above a channel region, source / drain features coupled to the channel region, and source / drain contacts coupled to the source / drain features; forming a low-k etch-stop layer above the source / drain contacts; forming a dielectric layer above the low-k etch-stop layer; performing an etching process to form a via opening extending through the dielectric layer and the low-k etch-stop layer to expose the gate structure; performing a process on the structure to oxidize a portion of the low-k etch-stop layer adjacent to the via opening; forming a gate via in the via opening.

[0100] In some embodiments, the method of forming a semiconductor structure further includes the following steps: Before performing an etching process, a patterned mask is formed over a dielectric layer, the patterned mask including an opening directly above the gate structure, wherein a process further removes the patterned mask. In some embodiments, the process includes performing a plasma ashing process using an oxygen-containing process gas. In some embodiments, the oxygen-containing process gas includes a combination of oxygen and hydrogen. In some embodiments, the oxygen-containing process gas includes a combination of oxygen and nitrogen. In some embodiments, a process is performed on the structure to convert the top portion of the gate structure into a dielectric layer, and the method of forming a semiconductor structure further includes performing an additional etching process to remove the dielectric layer. In some embodiments, a portion of the low-k etch-stop layer is a first portion of the low-k etch-stop layer, the low-k etch-stop layer further including a second portion disposed between the first portion and the via opening, wherein the etching process further converts at least a portion of the second portion into an etchant-correcting feature, and wherein the process further removes the etchant-correcting feature before oxidizing the first portion. In some embodiments, before the process, the first portion of the low-k etch-stop layer includes silicon carbonitride, and after the process, the first portion of the low-k etch-stop layer includes silicon carbonitride oxide. In some embodiments, in a cross-sectional view, the oxidized portion of the low-k etch stop layer includes a first portion spanning a first width and a second portion opposite the first portion spanning a second width, wherein the distance between the first portion and the gate structure is less than the distance between the second portion and the gate structure, and the first width is greater than the second width. In some embodiments, in a cross-sectional view, the gate via has a substantially symmetrical profile, and the plurality of sidewalls of the gate via are substantially linear.

[0101] In another exemplary embodiment, some embodiments of this disclosure relate to a method of forming a semiconductor structure, comprising the following steps: forming a first dielectric layer over a first conductive feature; forming a second dielectric layer over the first dielectric layer, the first and second dielectric layers having different compositions; forming a patterned mask over the second dielectric layer, the patterned mask having an opening directly above the first conductive feature; performing a first etching process to form a trench extending through the first and second dielectric layers to expose the top surface of the first conductive feature, wherein the etchant of the first etching process modifies a portion of the first dielectric layer exposed by the trench; performing a second etching process to remove the patterned mask and the modified portion of the first dielectric layer, wherein the etchant of the second etching process further reacts with a portion of the remaining portion of the first dielectric layer to cause volume expansion of the remaining portion of the first dielectric layer; forming a second conductive feature in the trench.

[0102] In some embodiments, the etchant in the second etching process comprises oxygen (O2). In some embodiments, the etchant in the second etching process further comprises hydrogen (H2). In some embodiments, the flow rate of hydrogen (H2) in the second etching process is a ratio of 10% to 40% of the total flow rate of hydrogen (H2) and oxygen (O2). In some embodiments, prior to performing the second etching process, the first dielectric layer comprises silicon carbonitride, and after performing the second etching process, the first dielectric layer comprises a first region formed of silicon carbonitride and a second region formed of silicon carbonitride. In some embodiments, viewed from top to bottom, the second region of the first dielectric layer resembles a ring with a non-uniform width.

[0103] In yet another exemplary embodiment, some embodiments of this disclosure relate to a semiconductor structure. The semiconductor structure includes a gate structure located above a channel region, source / drain features coupled to the channel region, a first dielectric layer located above the gate structure, a second dielectric layer located on the first dielectric layer, and a gate via extending along the first and second dielectric layers to couple to the gate structure. The first dielectric layer includes a first portion surrounding a portion of the gate via and a second portion surrounding the first portion, and the composition of the first portion of the first dielectric layer differs from the composition of the second portion of the first dielectric layer.

[0104] In some embodiments, the semiconductor structure further includes a silicide layer on the source / drain features and source / drain contacts on the silicide layer and disposed below the first dielectric layer. In some embodiments, the width of a first portion of the first dielectric layer is non-uniform. In some embodiments, the first portion of the first dielectric layer comprises silicon carbonitride, and the second portion of the first dielectric layer comprises silicon carbonitride.

[0105] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various embodiments disclosed herein. Those skilled in the art should understand that they can readily use some of the embodiments disclosed herein as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of some of the embodiments disclosed herein, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of some of the embodiments disclosed herein.

Claims

1. A method for forming a semiconductor structure, characterized in that, Include: Receive a semiconductor structure, the semiconductor structure comprising: A gate structure is located above a channel region; A source / drain characteristic is coupled to this channel region, and A source / drain contact is coupled to the characteristics of that source / drain. A low-k etch stop layer is formed above the source / drain contact; A dielectric layer is formed above the low-k etch stop layer; An etching process is performed to form a via opening that extends through the dielectric layer and the low-k etch stop layer to expose the gate structure; A process is performed on the semiconductor structure to oxidize a portion of the low-k etch stop layer adjacent to the via opening; as well as A gate via is formed in the opening of the via.

2. The method as described in claim 1, characterized in that, in: This portion of the low-k etch-stop layer is a first portion of the low-k etch-stop layer, and the low-k etch-stop layer further includes a second portion disposed between the first portion and the via opening. The etching process further converts at least a portion of the second part into an etchant-modified feature, and The process further removes the etchant-modified feature before oxidizing the first part.

3. The method as described in claim 2, characterized in that, in: Before the process is performed, the first portion of the low-k etch-stop layer contains silicon carbonitride, and after the process is performed, the first portion of the low-k etch-stop layer contains silicon carbonitride oxide.

4. The method as described in claim 1, characterized in that, In one cross-sectional view, the oxidized portion of the low-k etch stop layer includes a first portion spanning a first width and a second portion opposite to the first portion spanning a second width. The distance between the first portion and the gate structure is less than the distance between the second portion and the gate structure, and the first width is greater than the second width.

5. A method for forming a semiconductor structure, characterized in that, Include: A first dielectric layer is formed over a first conductive feature; A second dielectric layer is formed above the first dielectric layer, and the first dielectric layer and the second dielectric layer have different compositions; A patterned mask is formed above the second dielectric layer, the patterned mask having an opening located directly above the first conductive feature; A first etching process is performed to form a trench extending through the first dielectric layer and the second dielectric layer to expose a top surface of the first conductive feature, wherein an etchant in the first etching process modifies a portion of the first dielectric layer exposed by the trench. A second etching process is performed to remove the patterned mask and the modified portion of the first dielectric layer, wherein an etchant in the second etching process further reacts with a portion of a remaining portion of the first dielectric layer, causing a volume expansion of the remaining portion of the first dielectric layer; and A second conductive feature is formed in the trench.

6. The method as described in claim 5, characterized in that, The etchant used in the second etching process contains oxygen.

7. The method as described in claim 6, characterized in that, The etchant in the second etching process further contains hydrogen.

8. The method as described in claim 7, characterized in that, In this second etching process, the ratio of the hydrogen flow rate to the total flow rate of hydrogen and oxygen is 10% to 40%.

9. A semiconductor structure, characterized in that, Include: A gate structure is located above a channel region; A source / drain characteristic is coupled to this channel region; A first dielectric layer is located above the gate structure; A second dielectric layer, located on the first dielectric layer; and A gate via extends along the first dielectric layer and the second dielectric layer to couple to the gate structure. The first dielectric layer includes a first portion surrounding a portion of the gate via and a second portion surrounding the first portion, and a component of the first portion of the first dielectric layer is different from a component of the second portion of the first dielectric layer.

10. The semiconductor structure as described in claim 9, characterized in that, The first portion of the first dielectric layer comprises silicon carbonitride, and the second portion of the first dielectric layer comprises silicon carbonitride.

Images