Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. In an embodiment, a method may include forming a multilayer stack over a substrate, the multilayer stack having alternating layers of first and second semiconductor layers. The method may further include forming a first source / drain region in the first region adjacent to the first semiconductor layer and the second semiconductor layer, the first source / drain region having a cap layer; forming a protective layer over the first source / drain region; forming a second source / drain region adjacent to the first semiconductor layer and the second semiconductor layer in the second region; removing the protective layer from over the first source / drain region; replacing the first semiconductor layer in the first region with a first metal gate structure; and replacing the first semiconductor layer in the second region with a second metal gate structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a multilayer stack on a substrate, the multilayer stack including alternating layers of a first semiconductor layer and a second semiconductor layer; forming a first source / drain region adjacent to the first semiconductor layer and the second semiconductor layer in a first region, the first source / drain region including a capping layer; forming a protective layer over the first source / drain region; forming a second source / drain region adjacent to the first semiconductor layer and the second semiconductor layer in a second region; removing the protective layer from the first source / drain region; replacing the first semiconductor layer in the first region with a first metal gate structure; and replacing the first semiconductor layer in the second region with a second metal gate structure.

[0005] According to one aspect of this disclosure, a method of manufacturing a semiconductor device is provided, the method comprising: forming a multilayer stack on a substrate, the multilayer stack including alternating layers of a first semiconductor layer and a second semiconductor layer; forming a first source / drain region adjacent to the first semiconductor layer and the second semiconductor layer in a first region, the first source / drain region including a capping layer; forming a protective layer over the first source / drain region; forming a second source / drain region adjacent to the first semiconductor layer and the second semiconductor layer in a second region; etching the second source / drain region with a chlorine-containing etchant, wherein the protective layer and the capping layer of the first source / drain region are exposed to the chlorine-containing etchant; removing the protective layer from the first source / drain region; replacing the first semiconductor layer in the first region with a first metal gate structure; and replacing the first semiconductor layer in the second region with a second metal gate structure.

[0006] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a stack of channel regions on a substrate; first source / drain regions adjacent to the stack of channel regions in a first region of the substrate, each of the first source / drain regions comprising: a first layer comprising silicon; a second layer above the first layer, the second layer comprising boron-doped silicon germanium; and a capping layer above the second layer, the capping layer comprising boron-doped silicon; a first metal gate structure surrounding the channel regions in the first region; and a conductive contact above and electrically coupled to the first source / drain regions, the conductive contact extending through the capping layer of the first source / drain regions. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nanoFET) according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 22C , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B and Figure 24C This is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments.

[0010] Figure 25 and Figure 26 This is a cross-sectional view of a nanoFET according to some embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially related terms (e.g., "below," "under," "lower," "above," "upper," etc.) may be used herein to readily describe the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). In addition to the orientations depicted in the figures, spatially related terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted similarly accordingly.

[0013] This disclosure relates (particularly in the context of nanostructured field-effect transistors (nanoFETs)) to semiconductor devices and methods for enhancing performance and reducing defects. This disclosure addresses challenges associated with protecting source / drain regions during manufacturing processes. As semiconductor technology advances to increasingly smaller nodes, the need for more precise and reliable manufacturing techniques becomes increasingly important. This disclosure introduces a silicon-based capping layer designed to enhance protection of the p-type source / drain regions in nanoFETs.

[0014] In some configurations of nanoFET fabrication, the source / drain epitaxial process sequence involves forming an n-type epitaxial region after the p-type epitaxial region. During the n-type epitaxial process, the p-type epitaxial region is protected by a protective layer (which may be an alumina layer). However, the protective layer may not always provide uniform or sufficient coverage. Therefore, the epitaxial layer beneath the p-type epitaxial structure may be susceptible to damage from etching chemicals (especially chlorine-containing etchants used in subsequent n-type source / drain formation steps).

[0015] This disclosure addresses this problem by introducing a silicon capping layer as part of a p-type source / drain epitaxial structure. The capping layer can be a highly boron-doped silicon layer. This capping layer (with a controlled thickness of 2 to 6 nanometers) completely covers the underlying layer(s) and acts as a protective barrier. The capping layer is particularly effective against HCl and Cl2 etchants, providing a layer of protection when the protective layer proves insufficient.

[0016] This method offers several advantages. First, it significantly enhances the protection of the p-type source / drain regions, ensuring their integrity throughout the fabrication process. This improved protection translates into increased reliability and potentially higher performance for the resulting nanoFETs. The versatility of the capping layer (which can be composed of various materials such as Si, SiB, SiGe, or SiGeB) allows for flexibility in the fabrication process and enables optimization of transistor characteristics.

[0017] Furthermore, precise control over the thickness and shape of the cap layer allows for fine-tuning of its protective properties, enabling manufacturers to tailor manufacturing processes to specific requirements. This approach integrates with existing nanoFET manufacturing workflows, minimizing the need for extensive modifications to established processes. By providing enhanced etch resistance and maintaining the integrity of the P-type source / drain regions, this method enables the fabrication of more reliable and higher-performance nanoFETs as components in a wide range of electronic devices, from smartphones and computers to advanced AI systems and IoT devices.

[0018] The embodiments are described below in a specific context (i.e., nanoFET transistors). However, various embodiments can be applied to dies that include other types of transistors combined with nanoFETs (e.g., FinFETs, planar transistors, etc.).

[0019] Figure 1 An example of a nanoFET (e.g., nanowire FET, nanosheet FET, etc.) according to some embodiments is shown in a three-dimensional view. The nanoFET includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) on fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region for the nanoFET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 68 are disposed between adjacent fins 66, and the fins 66 may protrude above these adjacent isolation regions 68. Although the isolation regions 68 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may refer only to the semiconductor substrate or to a combination of the semiconductor substrate and the isolation regions. Furthermore, although the bottom portion of the fin 66 is shown as being a single continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent isolation regions 68.

[0020] A gate dielectric layer 100 is located above the top surface of fin 66 and extends along the top, sidewalls, and bottom surface of nanostructure 55. A gate electrode 102 is located above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102. One or more source / drain regions 92 may individually refer to a source or drain, or collectively to both, depending on the context.

[0021] Figure 1Reference cross sections used in the following figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nanoFET. Cross section B-B' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the nanoFET fin 66 and in a direction, for example, between the epitaxial source / drain regions 92 of the nanoFET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions of the nanoFET. For clarity, the following figures refer to these reference cross sections.

[0022] Some embodiments discussed herein are discussed in the context of nanoFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments contemplate aspects used in planar devices such as planar FETs or fin field-effect transistors (FinFETs).

[0023] Figures 2 to 24C According to some embodiments Figure 1 A cross-sectional view of an intermediate stage in the fabrication of a nanoFET. Figures 2 to 5 , Figure 6A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A and Figure 24A It shows Figure 1 The reference cross section A-A' is shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 11C , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B and Figure 24B It shows Figure 1 The reference cross section B-B' is shown. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 16C , Figure 17C , Figure 22C , Figure 23C and Figure 24C It shows Figure 1 The reference cross section C-C' is shown.

[0024] exist Figure 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and can be doped (e.g., doped with p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate (typically a silicon substrate or a glass substrate). Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof.

[0025] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device (e.g., an NMOS transistor, such as an n-type nanoFET), and the p-type region 50P can be used to form a p-type device (e.g., a PMOS transistor, such as a p-type nanoFET). The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0026] In addition, Figure 2In this embodiment, a multilayer stack 64 is formed on a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layers 53). For illustrative purposes, the multilayer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 can be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), or molecular beam epitaxy (MBE). In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for p-type nanoFETs, such as silicon germanium, and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for n-type nanoFETs, such as silicon or silicon carbon. For illustrative purposes, the multilayer stack 64 is shown as having a bottom semiconductor layer suitable for p-type nanoFETs. In some embodiments, the multilayer stack 64 can be formed such that the bottommost layer is a semiconductor layer suitable for an n-type nanoFET.

[0027] Now for reference Figure 3 According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 can further define first nanostructures 52A to 52C (collectively referred to as first nanostructure 52) from first semiconductor layer 51, and second nanostructures 54A to 54C (collectively referred to as second nanostructure 54) from second semiconductor layer 53. First nanostructure 52 and second nanostructure 54 can also be collectively referred to as nanostructure 55.

[0028] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, one or more photolithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the fins 66 and nanostructures 55. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the patterns to be created to have smaller spacing, for example, than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0029] For illustrative purposes, Figure 3 Fins 66 with substantially equal widths are shown in n-type region 50N and p-type region 50P. In some embodiments, the width of the fin 66 in n-type region 50N may be larger or thinner than the width of the fin 66 in p-type region 50P. Furthermore, while each fin 66 and each nanostructure 55 is shown to have a consistent width across its respective portions, in other embodiments, the fin 66 and / or nanostructure 55 may have tapered sidewalls such that the width of each fin 66 and / or each nanostructure 55 continuously increases toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0030] exist Figure 4 In this embodiment, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, fin 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitrides, or combinations thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or combinations thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fin 66, and nanostructure 55. A filler material, such as that discussed above, can then be formed over the liner.

[0031] Then, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etching rollback, or a combination thereof may be employed. The planarization process exposes the nanostructure 55 such that, after the planarization process is completed, the top surface of the nanostructure 55 and the top surface of the insulating material are horizontal.

[0032] The insulating material is then recessed to form STI regions 68. The insulating material is recessed such that the upper portions of the fins 66 in the n-type region 50N and p-type region 50P protrude between adjacent STI regions 68. Furthermore, the top surface of the STI regions 68 can have a flat surface (as shown), a convex surface, a concave surface (such as a dish shape), or a combination thereof. The top surface of the STI regions 68 can be formed as flat, convex, and / or concave by appropriate etching. Acceptable etching processes can be used to recess the STI regions 68, for example, etching processes selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than etching the material of the fins 66 and nanostructures 55). For example, it can be removed using oxides, such as those using hydrogen fluoride, diluted hydrogen fluoride, or other fluorine-based etchants.

[0033] The above reference Figures 2 to 4 The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes relative to the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure can include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structure, the material to be epitaxially grown can be in-situ doped during growth, which avoids prior and / or subsequent implantation, but in-situ doping and implantation doping can be used together.

[0034] Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials in the p-type region 50P and the n-type region 50N or may be formed in different orders in the p-type region 50P and the n-type region 50N.

[0035] In addition, Figure 4In this process, suitable wells (not shown separately) can be formed in fins 66, nanostructures 55, and / or STI regions 68. In embodiments with different well types, different implantation steps for n-type regions 50N and p-type regions 50P can be achieved using photoresist or other masks (not shown separately). For example, photoresist can be formed over fins 66 and STI regions 68 in n-type regions 50N and p-type regions 50P. The photoresist is patterned to expose p-type regions 50P. The photoresist can be formed using spin coating techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type regions 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into n-type regions 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of 10. 13 atoms / cm 3 Up to 10 14 atoms / cm 3 Within the specified range. After injection, the photoresist is removed, for example, through an acceptable ashing process.

[0036] After or before implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted into the region at a concentration of 10. 13 atoms / cm 3 Up to 10 14 atoms / cm 3 Within the specified range. After injection, the photoresist is removed, for example, through an acceptable ashing process.

[0037] After implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation, but in-situ doping and implantation doping can be used together.

[0038] exist Figure 5In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 can be deposited on the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 can be deposited on the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity relative to the etching of the isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that, for illustrative purposes only, the dummy dielectric layer 70 is shown as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 can be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0039] Figures 6A to 24C Various additional steps in the manufacture of the embodiment device are shown. Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A and Figure 24B Features in region 50N or region 50P are shown. Figure 6A and Figure 6B In this process, acceptable photolithography and etching techniques can be used to pattern the mask layer 74 (see [link]). Figure 5 A mask 78 is formed. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from adjacent dummy gates 76. The dummy gate 76 may also have a length direction substantially perpendicular to the length direction of the corresponding fin 66.

[0040] exist Figure 7A and Figure 7B In, respectively in Figure 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed on top of the structure shown. The first spacer layer 80 and the second spacer layer 82 are then patterned to serve as spacers for forming self-aligned source / drain regions. Figure 7A and Figure 7B In this configuration, a first spacer layer 80 is formed on: the top surface of the STI region 68; the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78; and the sidewalls of the dummy gate 76 and dummy gate dielectric 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited using techniques such as thermal oxidation or by CVD, ALD, etc. The second spacer layer 82 can be formed of a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and the second spacer layer 82 can be deposited by CVD, ALD, etc.

[0041] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, implantation can be performed for the lightly doped source / drain (LDD) regions (not shown separately). In embodiments with different device types, similar to the above... Figure 4The implantation discussed earlier can involve forming a mask (e.g., photoresist) over the n-type region 50N while exposing the p-type region 50P, and implanting an impurity of an appropriate type (e.g., p-type) into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The lightly doped source / drain regions can have a doping density of 10... 15 atoms / cm 3 Up to 10 19 atoms / cm 3 The impurity concentration is within a certain range. Annealing can be used to repair implantation damage and reactivate the implanted impurities.

[0042] exist Figure 8A and Figure 8B In this process, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used for self-alignment of the subsequently formed source / drain regions, and for protecting the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process) or an anisotropic etching process (e.g., dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 can be used as an etch stop layer when the second spacer layer 82 is patterned, and that the second spacer layer 82 can be used as a mask when the first spacer layer 80 is patterned. For example, an anisotropic etching process can be used to etch the second spacer layer 82, wherein the first spacer layer 80 serves as an etching stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83, such as... Figure 8A As shown. Subsequently, when the exposed portion of the first spacer layer 80 is etched, the second spacer 83 acts as a mask, thereby forming the first spacer 81, as... Figure 8A As shown.

[0043] like Figure 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the sidewalls of the nanostructure 55. Figure 8BAs shown, in some embodiments, the second spacer layer 82 can be removed from the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain on the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0044] It should be noted that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or more spacers can be used, different step sequences can be used (e.g., the first spacer 81 can be patterned before depositing the second spacer layer 82), and / or additional spacers can be formed and removed, etc. Furthermore, different structures and steps can be used to form n-type devices and p-type devices.

[0045] exist Figure 9A and Figure 9B In this design, a first recess 84 is formed in the fin 66, nanostructure 55, and substrate 50 within both the p-type region 50P and the n-type region 50N. Subsequently, an epitaxial source / drain region is formed within the first recess 84. The first recess 84 can extend through the first nanostructure 52 and the second nanostructure 54, and into the substrate 50. Figure 9A As shown, the top surface of the STI region 68 can be flush with the bottom surface of the first recess 84. In various embodiments, the fin 66 can be etched such that the bottom surface of the first recess 84 is set below the top surface of the STI region 68; and so on. The fin 66, nanostructure 55, and substrate 50 can be etched to form the first recess 84 using anisotropic etching processes such as RIE, NBE, etc. During the etching process for forming the first recess 84, the first spacer 81, the second spacer 83, and the mask 78 mask portions of the fin 66, nanostructure 55, and substrate 50. Each layer of the nanostructure 55 and / or the fin 66 can be etched using a single-pass etching process or a multi-pass etching process. After the first recess 84 reaches the desired depth, a timed etching process can be used to stop the etching of the first recess 84.

[0046] exist Figure 10A and Figure 10B In the process, portions of the sidewalls of the layer (e.g., the first nanostructure 52) formed by the first semiconductor material exposed by the first recess 84 in the multilayer stack 64 are etched to form sidewall recesses 88 in both the p-type region 50P and the n-type region 50N. While the sidewalls of the first nanostructure 52 in the sidewall recess 88 are... Figure 10B The middle is shown as straight, but these sidewalls can be concave or convex (see example). Figure 11C Etching can be isotropic or anisotropic.

[0047] As an example of this process, the first nanostructure 52 is etched using an etchant selective for the first semiconductor material, such that the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52 (although some etching may occur). In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, the sidewalls of the first nanostructure 52 can be etched using a wet or dry etching process employing tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH), etc.

[0048] In some embodiments, due to the etch selectivity between the materials of the first nanostructure 52 and the second nanostructure 54, the recess 88 may extend upward and / or downward to give the recess 88 a more trapezoidal shape. In some embodiments, these recesses will have a flat upper surface and a flat bottom surface.

[0049] exist Figures 11A to 11C In the middle, a first internal spacer 90 is formed in the sidewall recess 88 of both the p-type region 50P and the n-type region 50N. This can be achieved by... Figure 10A and Figure 10B An internal spacer layer (not shown separately) is deposited on the structure shown to form the first internal spacer 90. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure (discussed further below).

[0050] The internal spacer layer can be deposited using conformal deposition processes (e.g., CVD, ALD, etc.) to form the shape of the recess 88. The internal spacer layer can comprise materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k material with a k value less than 3.5. The internal spacer layer can then be anisotropically etched to form the first internal spacer 90. Although the outer walls of the first internal spacer 90 are shown flush with the sidewalls of the second nanostructure 54, the outer walls of the first internal spacer 90 can extend beyond or be recessed relative to the sidewalls of the second nanostructure 54. Once formed, the first internal spacer 90 takes on the shape of the sidewalls of the recess 88, such that the first internal spacer 90 can have a flat upper / lower surface or an extended surface with a trapezoidal shape.

[0051] Furthermore, despite Figure 11B In the diagram, the outer wall of the first inner spacer 90 is shown as straight, but the outer wall of the first inner spacer 90 may be recessed or convex. As an example, Figure 11CAn embodiment is shown in which the sidewalls of the first nanostructure 52 are recessed, the outer sidewalls of the first internal spacer 90 are recessed, and the first internal spacer 90 is recessed relative to the sidewalls of the second nanostructure 54.

[0052] exist Figures 12A to 16C In this embodiment, an epitaxial source / drain region 92 is formed in a first recess 84 in both the p-type region 50P and the n-type region 50N. The source / drain region 92 can apply stress to the second nanostructure 54 in the n-type region 50N and / or the first nanostructure 52 in the p-type region 50P, thereby improving performance. In some embodiments, the epitaxial source / drain region 92 may include one or more semiconductor material layers, and in some embodiments, the epitaxial source / drain region 92 may be formed in the p-type region 50P before being formed in the n-type region 50N.

[0053] An epitaxial source / drain region 92 can be formed in a p-type region 50P (e.g., a PMOS region) by masking the n-type region 50N (e.g., an NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 84 in the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material on which compressive strain is applied, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 92 can also have a surface protruding from a corresponding surface of the multilayer stack 64 and can have a facet.

[0054] An epitaxial source / drain region 92 can be formed in an n-type region 50N (e.g., an NMOS region) by masking the p-type region 50P (e.g., a PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 84 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material on which tensile strain is applied, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 can have a surface protruding from the corresponding upper surface of the nanostructure 55 and can have a facet.

[0055] Figures 12A to 16C An exemplary process is shown for forming an epitaxial source / drain region 92 in a p-type region 50P prior to forming an epitaxial source / drain region 92 in an n-type region 50N. Figures 12A to 12BIn the epitaxial source / drain region 92, a first semiconductor material layer 92A and a second semiconductor material layer 92B are formed in the first recess 84 of both the p-type region 50P and the n-type region 50N. As described in the following figures, the epitaxial source / drain region may also include a third semiconductor material layer 92C and a fourth semiconductor material layer 92D. Although four layers are shown and described, any number of semiconductor material layers can be used for the epitaxial source / drain region 92. In some embodiments, the second semiconductor material layer 92B is omitted.

[0056] The first semiconductor material layer 92A (also referred to as L0) may be an undoped or lightly doped layer that prevents or reduces the diffusion of dopants from the upper epitaxial layers (e.g., particularly the third semiconductor material layer 92C and the fourth semiconductor material layer 92D) into the underlying substrate 50. In a specific example, the first semiconductor material layer 92A may be a substantially germanium-free silicon layer. In some embodiments, the first semiconductor material layer 92A may be formed by a bottom-up epitaxial growth process.

[0057] In embodiments including a second semiconductor material layer 92B (also referred to as L1), the second semiconductor material layer 92B may also be a substantially germanium-free silicon layer. In some embodiments, when the first nanostructures 52A to 52C are removed, the second semiconductor material layer 92B may prevent etchant leakage from the first nanostructures 52A to 52C (see, for example...). Figures 20A to 20B In some embodiments, the second semiconductor material layer 92B may include silicon, boron-doped silicon (SiB), or a combination thereof. The second semiconductor material layer 92B may be formed by an epitaxial process including silane (SiH4) or dichlorosilane (DCS) as a silicon precursor, and may include B2H6 or BCl3 as a boron precursor. The second semiconductor material layer 92B may include a lateral portion 92B', which is formed by applying a doping process to an undoped or lightly doped first semiconductor material layer 92A. In the subsequent... Figure 12B In the cross-sectional drawing, multiple layers 92A to 92D of the epitaxial source / drain region 92 are shown only in the central recess 84, but the outer recesses 84 of each region have a configuration similar to that of the epitaxial source / drain region 92.

[0058] exist Figures 13A to 13BIn this process, the remaining layer of the epitaxial source / drain region 92 is formed in the p-type region 50P. This process can be initiated by forming a mask layer 93 (also referred to as a protective layer 93) over the n-type region 50N and the p-type region 50P. In some embodiments, the mask layer 93 comprises an oxide layer (e.g., aluminum oxide), but other suitable materials are also within the scope of this disclosure. The mask layer 93 can be a conformal layer having a substantially uniform thickness (within the range of process variations) on both vertical and horizontal surfaces. The mask layer 93 can be removed from the p-type region 50P. In some embodiments, the removal of the mask layer 93 is performed by forming a photoresist and / or a mask (not shown separately) and patterning the photoresist and / or mask to expose the p-type region 50P, followed by an etching process to remove the exposed mask layer 93 in the p-type region 50P. Once the mask layer 93 is patterned, a third semiconductor material layer 92C (which may be referred to as L2) can be formed on the second semiconductor material layer 92B, and a fourth semiconductor material layer 92D (which may be referred to as L3) can be formed on the third semiconductor material layer 92C.

[0059] The epitaxial growth process of the source / drain region 92 in the p-type region 50P involves sequentially forming layers of a third semiconductor material layer 92C and a fourth semiconductor material layer 92D. The third semiconductor material layer 92C is epitaxially grown from an underlying layer (either a first semiconductor material layer 92A or a second semiconductor material layer 92B and / or a second semiconductor nanostructure 54, depending on the presence of the second semiconductor material layer 92B). The third semiconductor material layer 92C may be a boron-doped silicon-germanium layer. In some embodiments, the boron concentration of the third semiconductor material layer 92C is 7 × 10⁻⁶. 20 atoms / cm 3 Up to 1×10 21 atoms / cm 3 The concentration of germanium is within the range of 50% to 60%.

[0060] After forming the third semiconductor material layer 92C, a fourth semiconductor material layer 92D (also referred to as a cap layer 92D) is epitaxially grown from the third semiconductor material layer 92C. The fourth semiconductor material layer 92D can serve as a protective layer and can have various compositions. In one configuration, the fourth semiconductor material layer 92D is a boron-doped silicon-germanium layer. In some embodiments, the fourth semiconductor material layer 92D can have a composition ranging from 0 to 1 × 10⁻⁶. 22 atoms / cm 3The boron concentration is within the range specified, and the germanium concentration is less than 20%. In some embodiments, the fourth semiconductor material layer 92D may be composed of germanium-free silicon, or it may be a boron-free pure silicon layer. In some embodiments, the fourth semiconductor material layer 92D may be made of Si, SiB, SiGe, or SiGeB. Regardless of its specific composition, the germanium concentration in the third semiconductor material layer 92C is greater than the germanium concentration in the fourth semiconductor material layer 92D.

[0061] When the fourth semiconductor material layer 92D is a highly boron-doped silicon layer, it provides protection against HCl etching during p-type epitaxy followed by wet cleaning or n-type epitaxy. This is followed by the formation of a protective layer 95 (see, for example...). Figures 14A to 14B This protection is particularly useful when the source / drain region 92 in the p-type region 50P is not fully covered. The fourth semiconductor material layer 92D serves as a protective layer against etch damage during the formation of the n-type epitaxial source / drain region 92. Specifically, in some embodiments, the fourth semiconductor material layer 92D provides protection against HCl and Cl2 etchants, as well as other chlorine-containing etchants.

[0062] The fourth semiconductor material layer 92D is designed to completely cover the third semiconductor material layer 92C. In some embodiments, the fourth semiconductor material layer 92D has a thickness in the range of 2 nm to 6 nm, and the fourth semiconductor material layer 92D maintains this thickness along the (001), (110), and (111) crystal directions. This uniform coverage ensures complete protection of the underlying layers during subsequent processing steps.

[0063] In some embodiments, each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, the third semiconductor material layer 92C, and the fourth semiconductor material layer 92D may be formed of different semiconductor materials and may be doped to different dopant concentrations.

[0064] exist Figures 14A to 14B In this process, mask layer 93 is removed from n-type region 50N, and protective layer 95 is formed in both regions 50P and 50N. In some embodiments, protective layer 95 comprises an oxide layer (e.g., aluminum oxide), but other suitable materials are also within the scope of this disclosure. Protective layer 95 may be a conformal layer having a substantially uniform thickness (within the range of process variations) on both vertical and horizontal surfaces.

[0065] exist Figures 15A to 15BIn this process, the protective layer 95 is removed from the n-type region 50N, and the remaining portion of the epitaxial source / drain 92 is formed in the n-type region 50N. In some embodiments, the removal of the protective layer 95 is performed by forming a mask (not shown separately) and patterning the mask to expose the n-type region 50N, and then performing an etching process to remove the exposed protective layer 95 in the n-type region 50N.

[0066] The formation of the epitaxial source / drain region 92 in the n-type region 50N can include any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can include a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. In some embodiments, a third semiconductor material layer 92C is grown in the n-type region 50N with a suitable material composition. The capping layer 92D can be omitted from the n-type region 50N. The formation of the third semiconductor material layer 92C in the n-type region 50N can include an etching step, for example, using a chlorine-containing etchant in a deposition and etching cycle. As discussed above, a fourth semiconductor material layer 92D in the p-type region 50P serves as a protective layer to shield against etching damage during the formation of the n-type epitaxial source / drain region 92. Specifically, in some embodiments, the fourth semiconductor material layer 92D provides protection against HCl and Cl2 etchants, as well as other chlorine-containing etchants.

[0067] like Figure 15B As shown, epitaxial source / drain regions 92 of both regions 50P and 50N are formed in the first recess 84, such that each dummy gate 76 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit with the gate of the subsequently formed nanoFET.

[0068] During the respective formation processes of regions 50N and 50P, epitaxial source / drain regions 92, first nanostructure 52, second nanostructure 54, and / or substrate 50 may be implanted with dopants to form source / drain regions (this is similar to the previously discussed process for forming lightly doped source / drain regions), followed by annealing. In some embodiments, epitaxial source / drain regions 92 may be doped in situ during growth.

[0069] Several advantages can be achieved by utilizing a fourth semiconductor material layer 92D (which may be referred to as a cap layer or L3 layer) in the source / drain regions 92 of the p-type region 50P. First, this method significantly enhances the protection of the p-type source / drain regions, ensuring their integrity throughout the manufacturing process. This improved protection translates into increased reliability and higher performance of the resulting nanoFET. The versatility of the fourth semiconductor material layer 92D (which can be composed of various materials such as Si, SiB, SiGe, or SiGeB) allows for flexibility in the manufacturing process and optimization of transistor characteristics. Furthermore, precise control over the thickness and shape of the fourth semiconductor material layer 92D enables fine-tuning of its protective properties. The disclosed process also integrates with existing nanoFET manufacturing workflows, minimizing the need for extensive modifications to established manufacturing processes.

[0070] exist Figures 16A to 16C In the process, the protective layer 95 is removed after the formation of the epitaxial source / drain region 92 is completed. As a result of the epitaxial process used to form the epitaxial source / drain region 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain region 92 has small planes that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these small planes cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge, such as... Figure 16C As shown. In other embodiments, after the epitaxial process is completed, adjacent source / drain regions 92 remain separated, as shown. Figure 16A As shown. In Figure 16A and Figure 16C In the illustrated embodiment, a first spacer 81 may be formed onto the top surface of the STI region 68 to block epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewalls of the nanostructure 55 to further block epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 68.

[0071] exist Figures 17A to 17C In, respectively in Figure 6A , Figure 6B and Figure 16A ( Figures 7A to 16C The process remains unchanged. Figure 6AA first interlayer dielectric (ILD) 96 is deposited on the structure shown in the cross-section. The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, the mask 78, and the first spacer 81. The CESL 94 may include a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.) having an etch rate different from that of the overlying first ILD 96.

[0072] exist Figures 18A to 18B In this process, a planarization process (e.g., CMP) can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, and a portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within the process variation. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0073] exist Figure 19A and Figure 19B In one or more etching steps, the dummy gate 76 and mask 78 (if present) are removed, forming a second recess 98. A portion of the dummy dielectric layer 70 in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and dummy dielectric layer 70 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 76 at a faster rate than etching the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or overlays portions of the nanostructure 55, which serve as channel regions in the subsequently completed nanoFET. The portions of the nanostructure 55 serving as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 70 can serve as an etch stop layer as the dummy gate 76 is etched. The dummy dielectric layer 70 can then be removed after the removal of the dummy gate 76.

[0074] exist Figure 20A and Figure 20B In this process, the first nanostructure 52 in the n-type region 50N and the p-type region 50P is removed. The first nanostructure 52 can be removed by performing an isotropic etching process such as wet etching using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si, the first nanostructure 52 can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0075] exist Figure 21A and Figure 21B In the second recess 98, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. In the n-type region 50N and the p-type region 50P, the gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50, as well as on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 can also be deposited on the top surface of the first ILD 96, the top surface of the CESL 94, the top surface of the first spacer 81, and the top surface of the STI region 68.

[0076] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, or combinations thereof. For example, in some embodiments, the gate dielectric layer 100 may include an interface, a silicon oxide layer, and a metal oxide layer on top of the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. Methods for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, and PECVD, etc.

[0077] Gate electrode 102 is deposited on gate dielectric layer 100 and fills the remaining portion of second recess 98. Gate electrode 102 includes a protective layer (e.g., silicon), a barrier layer (e.g., titanium nitride), a work function material (e.g., a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, titanium aluminum, tungsten), combinations thereof, or multiple layers thereof. For example, although in Figure 19A and Figure 19BA single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of liner layers, any number of work function tuning layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50 in the n-type region 50N and the p-type region 50P.

[0078] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0079] After filling the second recess 98, a planarization process such as CMP can be performed to remove excess material from the gate dielectric layer 100 and gate electrode 102 above the top surface of the first ILD 96. The remaining material from the gate dielectric layer 100 and gate electrode 102 thus forms the replacement gate structure of the resulting nanoFET. The gate electrode 102 and gate dielectric layer 100 can be collectively referred to as the “gate structure”.

[0080] exist Figures 22A to 22C In this process, the gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed, such that a recess is formed directly over the gate structure and between opposing portions of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled into the recess, followed by a planarization process to remove excess dielectric material extending over the first ILD 96. The gate mask 104 is optional and is omitted in some embodiments. The subsequently formed gate contacts (e.g., referred to below) Figures 24A to 24C The contact 114 discussed penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102.

[0081] like Figures 22A to 22CAs further shown, the second ILD 106 is deposited over the first ILD 96 and the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, and can be deposited by any suitable method such as CVD, PECVD, etc.

[0082] exist Figures 23A to 23C In the etching process, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a third recess 108 that exposes the surface of the epitaxial source / drain region 92 and / or the surface of the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the third recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; the third recess 108 can be etched through the gate mask 104 using a second etching process; and then the third recess 108 can be etched through the CESL 94 using a third etching process. A mask (e.g., photoresist) can be formed over the second ILD 106 and the mask can be patterned to mask portions of the second ILD 106 in the first and second etching processes. In some embodiments, the etching process can be over-etched, and therefore, the third recess 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third recess 108 can be flush with the epitaxial source / drain region 92 and / or gate structure (e.g., at the same height, or at the same distance from the substrate), or lower than the epitaxial source / drain region 92 and / or gate structure (e.g., closer to the substrate). Although Figure 23BThe third recess 108 is shown as exposing the epitaxial source / drain region 92 and the gate structure in the same cross-section. However, in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross-sections, thereby reducing the risk of short circuits in subsequently formed contacts. After forming the third recess 108, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a metal (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium) of the epitaxial source / drain region 92 to form a silicide or germanide region, and then performing a thermal annealing process to form the silicide region 110. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicide and germanide). In an embodiment, the silicide region 110 comprises TiSi and has a thickness in the range of 2 nm to 10 nm.

[0083] Next, in Figures 24A to 24C In the third recess 108, contacts 112 and 114 (also referred to as contact plugs) are formed. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 both include a barrier layer and a conductive material, and are electrically coupled to underlying conductive features (e.g., the gate electrode 102 and / or the silicide region 110 in the illustrated embodiment). Contact 114 is electrically coupled to the gate electrode 102 and may be referred to as a gate contact, and contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0084] In some embodiments, the contact 112 in the p-type region 50P extends through the fourth semiconductor layer 92D to the third semiconductor layer 92C. In some embodiments, the contact 112 in the p-type region 50P does not extend through the fourth semiconductor layer 92D to the third semiconductor layer 92C. In some other embodiments, only the silicide region 110 in the p-type region 50P extends through the fourth semiconductor layer 92D to the third semiconductor layer 92C.

[0085] Figure 25 and Figure 26 A cross-sectional view of a device according to some embodiments is shown. Figure 25 and Figure 26 It shows Figure 1 The reference cross section C-C' is shown. Figure 25 and Figure 26 In the figures, the same reference numerals indicate that they are connected by the same reference numerals. Figures 2 to 24C The same components are formed using the same process as in the embodiments. Figure 25 and Figure 26 Each showed in relation to Figure 15A A similar p-type region 50P is located at a processing point.

[0086] Figure 25 and Figure 26 A fourth semiconductor material layer 92D with different shapes is shown in a cross-sectional view. These differences in shape can be controlled by the shape of the underlying layer (e.g., 92C), the parameters of the fabrication process of layer 92D, and / or by the crystal orientation of the layer. For example, in Figure 25 In the cross-sectional view, the fourth semiconductor material layer 92D has a more rounded or more circular shape. Figure 26 The fourth semiconductor material layer 92D in the cross-sectional view has a more square shape, or can be described as having a flat top. Figure 25 In one embodiment, the shape of the fourth semiconductor material layer 92D is a small plane defined at the 111 plane, which may be caused by the epitaxial growth temperature in the range of 600°C to 700°C. Figure 26 In one embodiment, the shape of the fourth semiconductor material layer 92D is more conformal, which may be due to the lower epitaxial growth temperature in the range of 500°C to 580°C.

[0087] The embodiments of this disclosure offer advantages. By utilizing a highly boron-doped silicon layer to protect the p-type source / drain regions in the nanoFET, nanoFETs fabricated using the disclosed process exhibit increased reliability and higher performance. In some configurations of nanoFET fabrication, the source / drain epitaxial process sequence includes forming an n-type epitaxial region after the p-type epitaxial region. During the n-type epitaxial process, the p-type epitaxial region is protected by a protective layer (e.g., an aluminum oxide layer). However, the protective layer may not always provide uniform or sufficient coverage. Therefore, the epitaxial layer beneath the p-type epitaxial structure may be damaged by etching chemicals (especially chlorine-containing etchants used in subsequent n-type source / drain formation steps).

[0088] This disclosure addresses this problem by introducing a highly boron-doped silicon layer as part of the p-type source / drain epitaxial structure. This layer completely covers the underlying layer(s) and acts as a protective barrier. The highly boron-doped silicon layer is particularly effective against HCl and Cl2 etchants, providing a layer of protection when the protective layer proves insufficient. This significantly enhances the protection of the p-type source / drain regions, ensuring their integrity throughout the fabrication process. This improved protection translates into increased reliability and higher performance in the resulting nanoFETs.

[0089] In one embodiment, a method may include: forming a multilayer stack on a substrate, the multilayer stack having alternating layers of a first semiconductor layer and a second semiconductor layer. The method may further include: forming a first source / drain region adjacent to the first and second semiconductor layers in a first region, the first source / drain region having a capping layer; forming a protective layer over the first source / drain region; forming a second source / drain region adjacent to the first and second semiconductor layers in a second region; removing the protective layer from the first source / drain region; replacing the first semiconductor layer in the first region with a first metal gate structure; and replacing the first semiconductor layer in the second region with a second metal gate structure.

[0090] The described embodiments may further include one or more of the following features: In this method, the protective layer may include aluminum oxide. In this method, the first source / drain region is part of a PMOS transistor. In this method, the second source / drain region is part of an NMOS transistor. In this method, forming a protective layer over the first source / drain region may include: forming a protective layer over the first source / drain region and the second source / drain region, and removing the protective layer from the second source / drain region. In this method, forming a second source / drain region adjacent to the first semiconductor layer and the second semiconductor layer in the second region may include: etching the second source / drain region with a chlorine-containing etchant, exposing the protective layer to the chlorine-containing etchant. In this method, a capping layer of the first source / drain region is exposed to a chlorine-containing etchant. In this method, each first source / drain region may include a first layer, a second layer above the first layer, and a capping layer above the second layer, wherein the first layer is a silicon layer, the second layer is a boron-doped silicon-germanium layer, and the capping layer is a boron-doped silicon layer. In this method, the capping layer has a higher boron doping concentration than the second layer. In this method, the capping layer may include germanium and has a lower germanium concentration than the second layer. The method may include: forming an interlayer dielectric over the first source / drain region and the second source / drain region; and forming a conductive contact electrically coupled to the first source / drain region in the interlayer dielectric, the conductive contact extending through the capping layer of the first source / drain region.

[0091] In one embodiment, a method may include: forming a multilayer stack on a substrate, the multilayer stack having alternating layers of a first semiconductor layer and a second semiconductor layer. The method may further include: forming a first source / drain region adjacent to the first and second semiconductor layers in a first region, the first source / drain region having a capping layer; forming a protective layer over the first source / drain region; forming a second source / drain region adjacent to the first and second semiconductor layers in a second region; etching the second source / drain region with a chlorine-containing etchant, wherein the protective layer and the capping layer of the first source / drain region are exposed to the chlorine-containing etchant; removing the protective layer from the first source / drain region; replacing the first semiconductor layer in the first region with a first metal gate structure; and replacing the first semiconductor layer in the second region with a second metal gate structure.

[0092] The described embodiments may also include one or more of the following features. In this method, the protective layer may include aluminum oxide. In this method, forming the first source / drain region may include: growing a first layer having silicon; growing a second layer on the first layer, the second layer having boron-doped silicon-germanium; and growing a capping layer on the second layer, the capping layer having boron-doped silicon. In this method, the capping layer has a higher boron doping concentration than the second layer, the capping layer may include germanium and has a lower germanium concentration than the second layer, and the capping layer has a thickness in the range of 2 nm to 6 nm. In this method, the capping layer may include Si, SiB, SiGe, or SiGeB.

[0093] In one embodiment, the semiconductor device may include a stack of channel regions on a substrate. The semiconductor device may further include: first source / drain regions adjacent to the stack of channel regions in the first region of the substrate, each first source / drain region having a first layer including silicon, a second layer above the first layer (the second layer including boron-doped silicon-germanium), and a capping layer above the second layer (the capping layer having boron-doped silicon); a first metal gate structure surrounding the channel regions in the first region; and conductive contacts above and electrically coupled to the first source / drain regions, the conductive contacts extending through the capping layer of the first source / drain regions.

[0094] The described embodiments may also include one or more of the following features. In this semiconductor device, the capping layer has a higher boron doping concentration than the second layer, and the capping layer may include germanium and have a lower germanium concentration than the second layer. In this semiconductor device, the capping layer may include Si, SiB, SiGe, or SiGeB. The semiconductor device may include: a second source / drain region adjacent to a channel region in a second region of the substrate; and a second metal gate structure surrounding the channel region in the second region, wherein the first source / drain region is part of a PMOS transistor, and the second source / drain region is part of an NMOS transistor.

[0095] Example 1. A method for manufacturing a semiconductor device, the method comprising:

[0096] A multilayer stack is formed on a substrate, the multilayer stack comprising alternating layers of a first semiconductor layer and a second semiconductor layer;

[0097] A first source / drain region adjacent to the first semiconductor layer and the second semiconductor layer is formed in the first region, the first source / drain region including a capping layer; and

[0098] A protective layer is formed above the first source / drain region;

[0099] A second source / drain region adjacent to the first semiconductor layer and the second semiconductor layer is formed in the second region;

[0100] Remove the protective layer from the first source / drain region;

[0101] Replace the first semiconductor layer in the first region with a first metal gate structure; and

[0102] The first semiconductor layer in the second region is replaced with a second metal gate structure.

[0103] Example 2. The method according to Example 1, wherein the protective layer comprises aluminum oxide.

[0104] Example 3. The method according to Example 1, wherein the first source / drain region is part of a PMOS transistor.

[0105] Example 4. The method according to Example 3, wherein the second source / drain region is part of an NMOS transistor.

[0106] Example 5. The method according to Example 1, wherein forming the protective layer over the first source / drain region comprises:

[0107] The protective layer is formed over the first source / drain region and the second source / drain region; and

[0108] Remove the protective layer from the second source / drain region.

[0109] Example 6. The method according to Example 1, wherein forming a second source / drain region adjacent to the first semiconductor layer and the second semiconductor layer in the second region includes:

[0110] The second source / drain region is etched with a chlorine-containing etchant, and the protective layer is exposed to the chlorine-containing etchant.

[0111] Example 7. The method according to Example 6, wherein the capping layer of the first source / drain region is exposed to the chlorine-containing etchant.

[0112] Example 8. The method according to Example 1, wherein each first source / drain region in the first source / drain region includes a first layer, a second layer above the first layer, and a capping layer above the second layer, the first layer being a silicon layer, the second layer being a boron-doped silicon-germanium layer, and the capping layer being a boron-doped silicon layer.

[0113] Example 9. The method according to Example 8, wherein the cap layer has a higher boron doping concentration than the second layer.

[0114] Example 10. The method according to Example 9, wherein the capping layer comprises germanium and has a lower germanium concentration than the second layer.

[0115] Example 11. The method described in Example 8 further includes:

[0116] An interlayer dielectric is formed over the first source / drain region and the second source / drain region; and

[0117] A conductive contact is formed in the interlayer dielectric to be electrically coupled to the first source / drain region, the conductive contact extending through the cap layer of the first source / drain region.

[0118] Example 12. A method of manufacturing a semiconductor device, the method comprising:

[0119] A multilayer stack is formed on a substrate, the multilayer stack comprising alternating layers of a first semiconductor layer and a second semiconductor layer;

[0120] A first source / drain region adjacent to the first semiconductor layer and the second semiconductor layer is formed in the first region, the first source / drain region including a capping layer; and

[0121] A protective layer is formed above the first source / drain region;

[0122] A second source / drain region adjacent to the first semiconductor layer and the second semiconductor layer is formed in the second region;

[0123] The second source / drain region is etched with a chlorine-containing etchant, wherein the protective layer and the capping layer of the first source / drain region are exposed to the chlorine-containing etchant;

[0124] Remove the protective layer from the first source / drain region;

[0125] Replace the first semiconductor layer in the first region with a first metal gate structure; and

[0126] The first semiconductor layer in the second region is replaced with a second metal gate structure.

[0127] Example 13. The method according to Example 12, wherein the protective layer comprises aluminum oxide.

[0128] Example 14. The method according to Example 12, wherein forming the first source / drain region includes:

[0129] The growth includes the first layer of silicon;

[0130] A second layer is grown on top of the first layer, the second layer comprising boron-doped silicon germanium; and

[0131] The capping layer is grown on top of the second layer, the capping layer comprising boron-doped silicon.

[0132] Example 15. According to the method described in Example 14, wherein:

[0133] The cap layer has a higher boron doping concentration than the second layer;

[0134] The capping layer comprises germanium and has a lower germanium concentration than the second layer; and

[0135] The cap layer has a thickness in the range of 2 nm to 6 nm.

[0136] Example 16. The method according to Example 12, wherein the capping layer comprises Si, SiB, SiGe, or SiGeB.

[0137] Example 17. A semiconductor device comprising:

[0138] Stacking in the channel region above the substrate;

[0139] First source / drain regions are stacked adjacent to the channel regions in the first region of the substrate, and each first source / drain region includes:

[0140] Including the first layer of silicon;

[0141] A second layer above the first layer, the second layer comprising boron-doped silicon germanium; and

[0142] A capping layer above the second layer, the capping layer comprising boron-doped silicon;

[0143] A first metal gate structure surrounds the channel region in the first region; and

[0144] A conductive contact is located above and electrically coupled to the first source / drain region, the conductive contact extending through the capping layer of the first source / drain region.

[0145] Example 18. The semiconductor device according to Example 17, wherein:

[0146] The cap layer has a higher boron doping concentration than the second layer; and

[0147] The capping layer comprises germanium and has a lower germanium concentration than the second layer.

[0148] Example 19. The semiconductor device according to Example 17, wherein the capping layer comprises Si, SiB, SiGe, or SiGeB.

[0149] Example 20. The semiconductor device according to Example 17 further includes:

[0150] The second source / drain region is adjacent to the channel region in the second region of the substrate; and

[0151] A second metal gate structure surrounds the channel region in the second region, wherein the first source / drain region is part of a PMOS transistor and the second source / drain region is part of an NMOS transistor.

[0152] The foregoing disclosure outlines features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A multilayer stack is formed on a substrate, the multilayer stack comprising alternating layers of a first semiconductor layer and a second semiconductor layer; A first source / drain region is formed in the first region adjacent to the first semiconductor layer and the second semiconductor layer, and the first source / drain region includes a capping layer; as well as A protective layer is formed above the first source / drain region; A second source / drain region adjacent to the first semiconductor layer and the second semiconductor layer is formed in the second region; Remove the protective layer from the first source / drain region; Replace the first semiconductor layer in the first region with a first metal gate structure; as well as The first semiconductor layer in the second region is replaced with a second metal gate structure.

2. The method according to claim 1, wherein, The protective layer comprises aluminum oxide.

3. The method according to claim 1, wherein, The first source / drain region is part of a PMOS transistor.

4. The method according to claim 3, wherein, The second source / drain region is part of an NMOS transistor.

5. The method according to claim 1, wherein, Forming the protective layer above the first source / drain region includes: The protective layer is formed over the first source / drain region and the second source / drain region; and Remove the protective layer from the second source / drain region.

6. The method according to claim 1, wherein, Forming a second source / drain region adjacent to the first semiconductor layer and the second semiconductor layer in the second region includes: The second source / drain region is etched with a chlorine-containing etchant, and the protective layer is exposed to the chlorine-containing etchant.

7. The method according to claim 6, wherein, The capping layer of the first source / drain region is exposed to the chlorine-containing etchant.

8. The method according to claim 1, wherein, Each first source / drain region in the first source / drain region includes a first layer, a second layer above the first layer, and a capping layer above the second layer, wherein the first layer is a silicon layer, the second layer is a boron-doped silicon-germanium layer, and the capping layer is a boron-doped silicon layer.

9. A method for manufacturing a semiconductor device, the method comprising: A multilayer stack is formed on a substrate, the multilayer stack comprising alternating layers of a first semiconductor layer and a second semiconductor layer; A first source / drain region is formed in the first region adjacent to the first semiconductor layer and the second semiconductor layer, and the first source / drain region includes a capping layer; as well as A protective layer is formed above the first source / drain region; A second source / drain region adjacent to the first semiconductor layer and the second semiconductor layer is formed in the second region; The second source / drain region is etched with a chlorine-containing etchant, wherein the protective layer and the capping layer of the first source / drain region are exposed to the chlorine-containing etchant; Remove the protective layer from the first source / drain region; Replace the first semiconductor layer in the first region with a first metal gate structure; and The first semiconductor layer in the second region is replaced with a second metal gate structure.

10. A semiconductor device, comprising: Stacking in the channel region above the substrate; First source / drain regions are stacked adjacent to the channel regions in the first region of the substrate, and each first source / drain region includes: Including the first layer of silicon; A second layer above the first layer, the second layer comprising boron-doped silicon germanium; and A capping layer above the second layer, the capping layer comprising boron-doped silicon; A first metal gate structure surrounds the channel region in the first region; and A conductive contact is located above and electrically coupled to the first source / drain region, the conductive contact extending through the capping layer of the first source / drain region.

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