Formation method of semiconductor device
By forming a protective layer and etching a pseudo-gate structure in the substrate edge region, the problem of wafer edge damage during the crystal edge etching process is solved, improving the yield and quality of semiconductor devices, and is applicable to a variety of substrate materials.
Patent Information
- Application Number
- CN202410551969.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-06
- Publication Date
- 2025-11-11
AI Technical Summary
Existing technologies suffer from wafer edge damage during the wafer edge etching process, leading to a decrease in semiconductor device yield and failing to effectively improve issues such as defects, breakdown, and excessive stress.
A protective layer is formed at the edge of the substrate. Multiple discrete pseudo-gate structures are formed by etching to protect the edge of the substrate and avoid direct exposure. A dry etching process is used to control the etching rate and time. Combined with chemical mechanical polishing for planarization, a high-quality pseudo-gate structure is formed.
It effectively protects the edge region of the substrate, improves the quality and yield of the edge region, and ensures the overall quality and yield of semiconductor devices. It is suitable for a variety of substrate materials.
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Figure CN120936095A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and more particularly to a method for forming a semiconductor device. Background Technology
[0002] With the development of semiconductor technology, the size of semiconductor devices continues to shrink, and the corresponding technology nodes continue to improve. The wafer bevel has an increasingly significant impact on the manufacturing process. For example, in the double exposure (SaDP) and quadruple exposure (SaQP) processes of CMOS devices at 10nm and higher technology nodes, the wafer bevel is one of the important factors affecting the photolithography pattern transfer effect.
[0003] Bevel etch technology is gaining increasing attention in the semiconductor manufacturing industry because it can improve the yield of manufactured semiconductor devices by addressing issues such as defects, arcing, and excessive stress. However, exposing the die edge during the manufacturing process can cause edge damage, thus failing to achieve the desired improvement in defects, arcing, and excessive stress. Consequently, the resulting increase in semiconductor device yield is often less than ideal.
[0004] Therefore, a new wafer edge etching method and semiconductor device manufacturing method are needed to reduce wafer edge damage and improve the yield of manufactured semiconductor devices. Summary of the Invention
[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor device to avoid substrate damage in the edge region, improve the substrate edge quality, and thereby improve the yield of the formed semiconductor device.
[0006] To address the aforementioned problems, the present invention provides a method for forming a semiconductor device, comprising: a substrate, the substrate including a central region and an edge region surrounding the central region; forming an initial dummy gate structure on the surface of the substrate in the central region, and forming a protective layer on the surface of the substrate in the edge region; etching the initial dummy gate structure, and forming a plurality of discrete dummy gate structures on the surface of the substrate in the central region.
[0007] Optionally, the material of the protective layer includes one or more combinations of silicon oxide, silicon nitride, and silicon carbide.
[0008] Optionally, the pseudo-gate structure includes a pseudo-gate dielectric layer formed on the surface of the substrate and a pseudo-gate layer formed on the surface of the pseudo-gate dielectric layer, wherein the material of the pseudo-gate layer includes polysilicon.
[0009] Optionally, the method of forming the initial pseudo-gate structure on the surface of the central region and the protective layer on the surface of the edge region includes: forming an initial pseudo-gate structure layer on the surface of the substrate, the initial pseudo-gate structure layer extending to the sidewall of the substrate; removing the initial pseudo-gate structure layer on the edge region and the sidewall of the substrate using an etching process to expose the surface of the substrate in the edge region; forming an initial protective layer on the surface of the initial pseudo-gate structure layer in the central region and the surface of the substrate in the edge region; etching away the initial protective layer in the central region to expose the surface of the initial pseudo-gate structure layer, forming the initial pseudo-gate structure on the surface of the central region, and forming the protective layer on the surface of the edge region.
[0010] Optionally, the thickness of the initial protective layer ranges from 1,500 angstroms to 3,000 angstroms.
[0011] Optionally, the method of removing the initial pseudo-gate structure layer on the edge region and the sidewall of the substrate using an etching process includes: removing a portion of the thickness of the initial pseudo-gate structure layer on the edge region and the sidewall of the substrate using a first etching process; and removing the initial pseudo-gate structure layer on the edge region and the sidewall of the substrate using a second etching process until the surface of the substrate of the edge region is exposed.
[0012] Optionally, the first etching process is a dry etching process, and the process parameters of the dry etching include an etching rate of less than 1000 angstroms / second and an etching time of less than 20 seconds.
[0013] Optionally, the initial dummy gate structure layer includes an initial dummy gate dielectric layer located on the substrate surface and an initial dummy gate layer located on the surface of the initial dummy gate dielectric layer. The second etching process is a dry etching process, and the process parameters of the dry etching include an etching rate of less than 1000 angstroms / second, an etching time of less than 20 seconds, and the ratio of the etching rate of the initial dummy gate layer to the etching rate of the initial dummy gate dielectric layer by the dry etching process is in the range of 1:1 to 1:1.5.
[0014] Optionally, before etching away the initial protective layer in the central region, the initial protective layer may be planarized using a chemical mechanical polishing method.
[0015] Optionally, during the planarization of the initial protective layer, the ratio of the etching rate of the initial protective layer to the etching rate of the initial pseudo-gate structure layer ranges from 1:1 to 1:5.
[0016] Optionally, during the etching of the initial pseudo-gate structure, the ratio of the etching rate of the protective layer to the etching rate of the initial pseudo-gate structure ranges from 1:1000 to 1:1.
[0017] Optionally, after forming the initial pseudo-gate structure and the protective layer, and before etching the initial pseudo-gate structure, the method further includes planarizing the surface of the initial pseudo-gate structure.
[0018] Optionally, the etching process for the initial pseudo-gate structure is a dry etching process, wherein the process parameters for the dry etching include an etching rate of less than 1000 angstroms / second and an etching time of less than 5 minutes.
[0019] Optionally, before forming the initial pseudo-gate structure on the surface of the central region and the protective layer on the surface of the edge region, the method further includes forming a plurality of discretely arranged fins on the surface of the substrate in the central region, the pseudo-gate structure spanning the fins.
[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0021] In the technical solution of this invention, the substrate includes a central region and an edge region surrounding the central region. An initial dummy gate structure is formed on the substrate surface of the central region, and a protective layer is formed on the substrate of the edge region. The initial dummy gate structure is etched, and multiple discrete dummy gate structures are formed on the surface of the substrate of the central region. By utilizing the protective layer formed on the surface of the substrate of the edge region, the substrate of the edge region is protected, preventing the substrate surface of the edge region from being directly exposed. Thus, during the etching process of the initial dummy gate structure to form the dummy gate structure, the substrate of the edge region is not damaged, improving the yield and quality of the substrate edge region, thereby ensuring the quality of the final semiconductor device. This invention has a wide range of applications. Attached Figure Description
[0022] Figures 1 to 4 This is a schematic diagram of the structure of each step in a method for forming a semiconductor device in one embodiment;
[0023] Figures 5 to 13 A schematic diagram of the steps in a method for forming a semiconductor device according to an embodiment of the present invention. Detailed Implementation
[0024] As described in the background section, the quality of existing substrate edges is poor. This will be explained in detail below with reference to the accompanying drawings.
[0025] Please refer to Figure 1 The substrate 100 includes a central region I and an edge region II surrounding the central region I. A plurality of discrete fins 101 are formed on the central region I, and an initial shallow trench isolation layer 102 is formed on the substrate 100. The top surface of the initial shallow trench isolation layer 102 is flush with the top surface of the fins 101.
[0026] Please refer to Figure 2The initial shallow trench isolation layer 102 is etched to form a shallow trench isolation structure 103.
[0027] Please refer to Figure 3 An initial dummy gate layer is formed across the fin 101 on the substrate 100, and the initial dummy gate layer is etched to form a dummy gate structure 104.
[0028] Please refer to Figure 4 Remove the pseudo-gate structure 104.
[0029] The inventor discovered that, Figure 2 During the formation of the shallow trench isolation structure 103, the edge region II of the substrate 100 is exposed; during the formation of the dummy gate structure 104 and the removal of the dummy gate structure 104, the substrate 100 of the edge region II is damaged (dashed part in the figure), thereby reducing the quality of the edge region II of the substrate 100, affecting the quality of the entire substrate, and thus affecting the yield of the final semiconductor device.
[0030] Based on this, the present invention provides a method for forming a semiconductor device, wherein a protective layer is formed in the edge region of the substrate. During the formation of the dummy gate structure, the protective layer can effectively protect the edge region of the substrate, eliminate damage to the edge region, improve the yield of the edge region, and thus improve the yield of the final semiconductor device.
[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0032] Figures 5 to 13 This is a schematic diagram of the structure of each step in the method for forming a semiconductor device according to an embodiment of the present invention.
[0033] Please refer to Figure 5 and Figure 6 Substrate 200 is provided.
[0034] In this embodiment, the substrate 200 is made of silicon.
[0035] In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium; in other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
[0036] In this embodiment, the substrate 200 includes a central region I and an edge region II surrounding the central region I, the central region I being used to form a device.
[0037] In this embodiment, a plurality of discretely arranged fins 201 are formed on the surface of the substrate 200 in the central region I.
[0038] in Figure 6 for Figure 5 The left view.
[0039] In this embodiment, the process for forming the fin 201 includes: providing an initial substrate (not shown) having a mask layer (not shown) on the initial substrate, the mask layer exposing a portion of the top surface of the initial substrate; etching the initial substrate using the mask layer as a mask to form the substrate 200 and the fin 201 located on the substrate 200.
[0040] In other embodiments, fins may not be formed on the surface of the substrate 200.
[0041] For the process of forming an initial dummy gate structure on the substrate surface in the central region I and forming a protective layer on the substrate surface in the edge region II, please refer to [reference needed]. Figures 7 to 12 .
[0042] Please refer to Figure 7 An initial pseudo-gate structure layer 202 is formed on the surface of the substrate 200, and the initial pseudo-gate structure layer 202 extends to the sidewall of the substrate 200.
[0043] Figure 7 View direction and Figure 6 The view orientation is consistent.
[0044] In this embodiment, the initial dummy gate structure layer 202 includes an initial dummy gate dielectric layer formed on the surface of the substrate 200 and an initial dummy gate layer formed on the surface of the initial dummy gate dielectric layer.
[0045] In this embodiment, the material of the initial pseudo-gate dielectric layer includes silicon oxide.
[0046] In this embodiment, the material of the initial dummy gate layer includes polycrystalline silicon.
[0047] In this embodiment, the initial pseudo-gate structure layer 202 extends to the sidewall of the substrate 200, thereby protecting the entire edge region II and improving the yield and quality of the entire edge region II.
[0048] For the process of removing the initial dummy gate structure layer 202 on the edge region II and the sidewall of the substrate 200 using an etching process until the surface of the substrate 200 of the edge region II is exposed, please refer to [reference needed]. Figure 8 and Figure 9 .
[0049] Please refer to Figure 8The initial pseudo-gate structure layer 202 is removed from the edge region II and the sidewall of the substrate 200 using a first etching process.
[0050] In this embodiment, the first etching process is a dry etching process, and the process parameters of the dry etching include an etching rate of less than 1000 angstroms / second and an etching time of less than 20 seconds.
[0051] Please refer to Figure 9 The initial pseudo-gate structure layer 202 on the edge region II and the sidewall of the substrate 200 is removed by a second etching process until the surface of the substrate 200 is exposed.
[0052] In this embodiment, the second etching process is a dry etching process. The process parameters of the dry etching process include an etching rate of less than 1000 angstroms / second, an etching time of less than 20 seconds, and a ratio of the etching rate of the dry etching process on the initial dummy gate layer to the etching rate of the dry etching process on the initial dummy gate dielectric layer ranging from 1:1 to 1:1.5.
[0053] In this embodiment, the purpose of using a two-stage etching process to remove the initial pseudo-gate structure layer 202 on the edge region II and the sidewall of the substrate 200 is to ensure that the initial pseudo-gate structure layer 202 on the edge region II is completely removed, and to ensure that each etching does not need to be too deep, thereby reducing damage to the substrate of the edge region II.
[0054] Please refer to Figure 10 An initial protective layer 203 is formed on the surface of the initial pseudo-gate structure layer 202 in the central region I and the substrate 200 in the edge region II.
[0055] In this embodiment, the thickness of the initial protective layer 203 ranges from 1500 angstroms to 3000 angstroms.
[0056] In this embodiment, the thickness of the initial protective layer 203 is greater than the thickness of the initial pseudo-gate structure layer 202. This is done to simplify subsequent processes. After forming the initial pseudo-gate structure layer 202, it is not directly planarized; instead, the initial protective layer 203 is formed directly. Subsequently, the initial protective layer 203 and the initial pseudo-gate structure layer 202 can be planarized together, thus simplifying the process. On the other hand, if the thickness of the initial protective layer 203 is less than the thickness of the initial pseudo-gate structure layer 202, the top height of the initial protective layer 203 in the edge region II will be lower than the thickness of the initial pseudo-gate structure layer 202, thereby increasing the complexity of the process.
[0057] In this embodiment, if the thickness of the initial protective layer 203 is greater than 3000 angstroms, the initial protective layer 203 will be too thick, resulting in a waste of material.
[0058] In this embodiment, the material of the initial protective layer 203 is silicon oxide.
[0059] In other embodiments, the material of the initial protective layer 203 may also be silicon nitride, silicon carbide, etc.
[0060] In this embodiment, the process for forming the initial protective layer 203 is chemical vapor deposition.
[0061] In other embodiments, the process for forming the initial protective layer 203 may also be a physical vapor deposition process, an atomic layer deposition process, etc.
[0062] The process of etching away the initial protective layer 203 in the central region I to expose the surface of the initial pseudo-gate structure layer 202, forming the initial pseudo-gate structure on the surface of the central region I, and forming the protective layer on the surface of the edge region II is described in [reference needed]. Figures 10 to 11 .
[0063] Please refer to Figure 11 The initial protective layer 203 is planarized by chemical mechanical polishing.
[0064] In this embodiment, during the planarization of the initial protective layer 203, the ratio of the etching rate of the initial protective layer 203 to the etching rate of the initial pseudo-gate structure layer 202 ranges from 1:1 to 1:5.
[0065] In this embodiment, the purpose of planarizing the initial protective layer 203 is to make the surface of the initial protective layer 203 flat.
[0066] Please refer to Figure 12 The initial protective layer 203 of the central region I is etched back until the surface of the initial pseudo-gate structure layer 202 is exposed, the initial pseudo-gate structure 204 is formed on the surface of the central region I, and the protective layer 205 is formed on the surface of the edge region II.
[0067] In this embodiment, the etching process is a dry etching process.
[0068] Please refer to Figure 13 The initial pseudo-gate structure 204 is etched to form a plurality of discrete pseudo-gate structures 206 on the surface of the substrate 200 in the central region I.
[0069] In this embodiment, before etching the initial pseudo-gate structure 204, the surface of the initial pseudo-gate structure 204 is planarized to make the surface of the initial pseudo-gate structure 204 smoother, thereby laying a foundation for the subsequent formation of a high-quality pseudo-gate structure 206. This is because the surface of the initial pseudo-gate structure 204 will also be damaged during the etching process to form the protective layer 205, resulting in an uneven surface of the initial pseudo-gate structure 204.
[0070] In this embodiment, the pseudo-gate structure 206 spans the fin 201.
[0071] In this embodiment, the pseudo-gate structure 206 includes a pseudo-gate dielectric layer formed on the surface of the substrate 200 and a pseudo-gate layer formed on the surface of the pseudo-gate dielectric layer. The material of the pseudo-gate layer includes polysilicon, and the material of the pseudo-gate dielectric layer includes silicon oxide.
[0072] In this embodiment, the etching process for the initial pseudo-gate structure 204 is a dry etching process. The process parameters for the dry etching include an etching rate of less than 1000 angstroms / second and an etching time of less than 5 minutes. The ratio of the etching rate of the initial pseudo-gate layer to the etching rate of the initial pseudo-gate dielectric layer by the dry etching process ranges from 1:1 to 1:1000.
[0073] In this embodiment, during the etching of the initial pseudo-gate structure 204, the ratio of the etching rate of the protective layer 205 to the etching rate of the initial pseudo-gate structure 204 ranges from 1:1000 to 1:1.
[0074] In this embodiment, by reasonably setting the ratio of the etching rate of the protective layer 205 to the etching rate of the initial pseudo-gate structure 204, a protective layer is always present on the surface of the substrate 200 in the edge region II, thereby providing good protection for the surface of the substrate 200 in the edge region II and avoiding damage to the surface of the substrate 200 in the edge region II.
[0075] In this embodiment, a protective layer 205 is formed on the surface of the substrate 200 in the edge region II to protect the substrate 200 in the edge region II, preventing the surface of the substrate 200 in the edge region II from being directly exposed. As a result, the substrate 200 in the edge region II will not be damaged during the etching of the initial dummy gate structure 204 to form the dummy gate structure 206, thus improving the yield and quality of the edge region II of the substrate 200 and ensuring the quality of the final semiconductor device. This method has a wide range of applications.
[0076] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor device, characterized in that, include: A substrate, the substrate comprising a central region and an edge region surrounding the central region; An initial pseudo-gate structure is formed on the substrate surface in the central region, and a protective layer is formed on the substrate surface in the edge region; The initial pseudo-gate structure is etched to form a plurality of discrete pseudo-gate structures on the surface of the substrate in the central region.
2. The method for forming a semiconductor device as described in claim 1, characterized in that, The material of the protective layer includes one or more combinations of silicon oxide, silicon nitride, and silicon carbide.
3. The method for forming a semiconductor device as described in claim 1, characterized in that, The pseudo-gate structure includes a pseudo-gate dielectric layer formed on the surface of the substrate and a pseudo-gate layer formed on the surface of the pseudo-gate dielectric layer, wherein the material of the pseudo-gate layer includes polysilicon.
4. The method for forming a semiconductor device as described in claim 1, characterized in that, The method of forming the initial pseudo-gate structure on the surface of the central region and forming the protective layer on the surface of the edge region includes: An initial pseudo-gate structure layer is formed on the surface of the substrate, and the initial pseudo-gate structure layer extends to the sidewall of the substrate; The initial pseudo-gate structure layer on the edge region and the sidewall of the substrate is removed by an etching process until the surface of the substrate in the edge region is exposed; An initial protective layer is formed on the surface of the initial pseudo-gate structure layer in the central region and the substrate in the edge region; The initial protective layer in the central region is etched away to expose the surface of the initial pseudo-gate structure layer, the initial pseudo-gate structure is formed on the surface of the central region, and the protective layer is formed on the surface of the edge region.
5. The method for forming a semiconductor device as described in claim 4, characterized in that, The thickness of the initial protective layer ranges from 1,500 angstroms to 3,000 angstroms.
6. The method for forming a semiconductor device as described in claim 4, characterized in that, A method for removing the initial pseudo-gate structure layer on the edge region and the sidewall of the substrate using an etching process includes: removing a portion of the initial pseudo-gate structure layer on the edge region and the sidewall of the substrate using a first etching process; The initial pseudo-gate structure layer on the edge region and the sidewall of the substrate is removed using a second etching process until the surface of the substrate in the edge region is exposed.
7. The method for forming a semiconductor device as described in claim 6, characterized in that, The first etching process is a dry etching process, and the process parameters of the dry etching process include an etching rate of less than 1000 angstroms / second and an etching time of less than 20 seconds.
8. The method for forming a semiconductor device as described in claim 6, characterized in that, The initial dummy gate structure layer includes an initial dummy gate dielectric layer located on the substrate surface and an initial dummy gate layer located on the surface of the initial dummy gate dielectric layer. The second etching process is a dry etching process. The process parameters of the dry etching include an etching rate of less than 1000 angstroms / second, an etching time of less than 20 seconds, and a ratio of the etching rate of the initial dummy gate layer to the etching rate of the initial dummy gate dielectric layer by the dry etching process ranging from 1:1 to 1:1.
5.
9. The method for forming a semiconductor device as described in claim 4, characterized in that, Before etching away the initial protective layer in the central region, the initial protective layer is planarized using a chemical mechanical polishing method.
10. The method for forming a semiconductor device as described in claim 9, characterized in that, During the planarization of the initial protective layer, the ratio of the etching rate of the initial protective layer to the etching rate of the initial pseudo-gate structure layer ranges from 1:1 to 1:
5.
11. The method for forming a semiconductor device as claimed in claim 1, characterized in that, During the etching of the initial pseudo-gate structure, the ratio of the etching rate of the protective layer to the etching rate of the initial pseudo-gate structure ranges from 1:1000 to 1:
1.
12. The method for forming a semiconductor device as claimed in claim 1, characterized in that, After forming the initial pseudo-gate structure and the protective layer, and before etching the initial pseudo-gate structure, the method further includes planarizing the surface of the initial pseudo-gate structure.
13. The method for forming a semiconductor device as claimed in claim 1, characterized in that, The etching process for the initial pseudo-gate structure is a dry etching process, and the process parameters for the dry etching include an etching rate of less than 1000 angstroms / second and an etching time of less than 5 minutes.
14. The method for forming a semiconductor device as claimed in claim 1, characterized in that, Before forming the initial pseudo-gate structure on the surface of the central region and the protective layer on the surface of the edge region, the method further includes forming a plurality of discretely arranged fins on the surface of the substrate in the central region, with the pseudo-gate structure spanning the fins.