Preparation method of solar cell and photovoltaic module

Abstract

The invention provides a preparation method of a solar cell and a photovoltaic module, and relates to the field of photovoltaic technology. The preparation method comprises the steps that the doped polycrystalline silicon layer and part of the silicon wafer in the non-grid line area are removed through etching, and the etching depth of the middle part of the silicon wafer is larger than that of the edge part of the silicon wafer. Compared with the non-grid line area of the middle part, the non-grid line area of the edge part is thicker, so that the structural strength of the non-grid line area of the edge part is better than that of the middle part. Therefore, the silicon wafer and the solar cell are not easy to warp, crack or fragment, and are not easy to damage due to collision. In the processing of a solar cell, the assembling process of a photovoltaic module and the subsequent use process of the photovoltaic module, the silicon wafer with better reliability can enable the solar cell to have higher product yield, better performance and longer service life.

Description

[0001] This application is a divisional application of the invention patent application filed on May 30, 2025, entitled "Solar Cell and its Preparation Method and Photovoltaic Module", with application number 202510713801.0. Technical Field

[0002] This application relates to the field of photovoltaic technology, and more specifically, to a method for preparing a solar cell and a photovoltaic module. Background Technology

[0003] Solar cells are affected by various factors during operation, with stress being a key one. Stress primarily arises from mismatched thermal expansion coefficients of materials during cell manufacturing, inadequate cell structure design, and temperature variations in the actual operating environment. For example, the fabrication of solar cells typically involves multiple different materials, such as silicon wafers, metal electrodes, and encapsulation materials. These materials have different thermal expansion coefficients. When subjected to high-temperature processes (such as annealing) or outdoor temperature changes, the varying degrees of expansion and contraction of these materials generate stress within the cell. This stress can lead to defects such as cracks and delamination, affecting product yield.

[0004] Currently, one technique in solar cell fabrication involves etching away the polycrystalline silicon layer in non-grid areas to improve cell performance. However, this etching process typically etches 2-3 μm of the non-grid areas across the entire silicon wafer. Given the already thin thickness of solar cells, this technique can disrupt the stress distribution within the solar cell, negatively impacting the long-term stability of the cell and module. For example, during high-temperature processes (such as coating and sintering), the cell may warp, develop microcracks, or even fragment; it is also more prone to cracking or breaking when subjected to impacts. Summary of the Invention

[0005] The purpose of this application includes providing a method for preparing a solar cell and a photovoltaic module, which can optimize the stress of the silicon wafer and improve the reliability of the solar cell.

[0006] The embodiments of this application can be implemented as follows: In a first aspect, this application provides a method for preparing a solar cell, comprising: A silicon wafer is obtained, the silicon wafer having a central portion and an edge portion, the edge portion forming the edge of the silicon wafer and surrounding the central portion, and at least one side of the silicon wafer having a gate line region and a non-gate line region; Deposit a doped polycrystalline silicon layer on a silicon wafer; The doped polysilicon layer and part of the silicon wafer in the non-gate area are etched away, wherein the etching depth of the silicon wafer in the middle part is greater than the etching depth of the silicon wafer in the edge part. Fabricate gate lines connected to the doped polysilicon layer.

[0007] In an optional implementation, the step of etching away the doped polysilicon layer and part of the silicon wafer in the non-gate region includes: The doped polysilicon layer in the non-gateline region is irradiated with a laser. Wet etching process is used to remove the doped polysilicon layer and part of the silicon wafer in the non-gate area.

[0008] In an optional implementation, in the step of irradiating the doped polysilicon layer in the non-gate region with a laser, the laser energy per unit area of ​​the non-gate region in the middle portion is greater than the laser energy per unit area of ​​the non-gate region in the edge portion.

[0009] In an optional implementation, the laser energy per unit area of ​​the non-gateline region in the middle portion is 210 mJ / cm². 2 ~380 mJ / cm 2 The laser energy per unit area in the non-grid region at the edge is 180 mJ / cm². 2 ~350 mJ / cm 2 .

[0010] In an optional embodiment, in the step of irradiating the doped polysilicon layer in the non-gate region with a laser, the irradiation duration of the non-gate region in the middle portion is greater than the irradiation duration of the non-gate region in the edge portion, and / or, the irradiation power of the non-gate region in the middle portion is greater than the irradiation power of the non-gate region in the edge portion.

[0011] In an optional implementation, the step of removing the doped polysilicon layer and part of the silicon wafer in the non-gate region using a wet etching process includes: The non-gateline area in the middle part is etched using a first etching solution, and the non-gateline area at the edge part is etched using a second etching solution. Wherein, the corrosiveness of the first etching solution is stronger than that of the second etching solution, and / or, the concentration of the first etching solution is greater than that of the second etching solution.

[0012] In an optional implementation, in the step of removing the doped polysilicon layer and part of the silicon wafer in the non-gate area using a wet etching process, the etching time of the middle part is longer than that of the edge part, and / or the etching temperature of the middle part is higher than that of the edge part.

[0013] In an optional implementation, the laser is a green laser.

[0014] In an optional embodiment, the etching solution used in the wet etching process includes at least one of sodium hydroxide and potassium hydroxide.

[0015] In an optional embodiment, the solar cell is a tunneling oxide passivated contact cell or a back contact cell, with the grid line region and the non-grid line region located on the back side of the silicon wafer.

[0016] Secondly, this application provides a photovoltaic module, including a solar cell prepared by any of the methods described in the foregoing embodiments.

[0017] The beneficial effects of the solar cell fabrication method and photovoltaic module provided in this application include: This application provides a method for fabricating a solar cell, comprising: obtaining a silicon wafer having a central portion and an edge portion, the edge portion forming the edge of the silicon wafer and surrounding the central portion, and at least one side of the silicon wafer having a grid line region and a non-grid line region; depositing a doped polycrystalline silicon layer on the silicon wafer; etching away the doped polycrystalline silicon layer and a portion of the silicon wafer from the non-grid line region, wherein the etching depth of the silicon wafer in the central portion is greater than the etching depth of the silicon wafer in the edge portion; and fabricating grid lines connected to the doped polycrystalline silicon layer. The fabrication method provided in this application allows the non-grid line region of the silicon wafer's edge portion to have a thicker thickness than the non-grid line region of the central portion, thus resulting in better structural strength. The edge portion is precisely where warping and microcracks are prone to occur, and it is also susceptible to impact damage. Therefore, strengthening the edge portion of the silicon wafer can improve the reliability of the entire silicon wafer and even the entire solar cell, making the silicon wafer and solar cell less prone to warping, microcracks, or fragmentation, and less susceptible to damage from impacts. In the processing of solar cells, the assembly of photovoltaic modules, and the subsequent use of photovoltaic modules, reliable silicon wafers enable solar cells to have higher product yield, better performance, and longer service life.

[0018] The photovoltaic modules provided in this application include solar cells prepared by the above-described method, and therefore also have the characteristics of high product yield, high reliability, and long service life. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1This is a schematic diagram of the back side of a solar cell in one embodiment of this application; Figure 2 This is a partial cross-sectional view of a solar cell (TOPCon cell) in one embodiment of this application; Figure 3 This is a schematic diagram of a silicon wafer in one embodiment of this application; Figure 4 This is a partial cross-sectional view of a solar cell (BC cell) in another embodiment of this application; Figure 5 This is a flowchart of a method for preparing a solar cell in one embodiment of this application; Figure 6 This is a schematic diagram showing the doped polycrystalline silicon layer after fabrication in one embodiment of this application; Figure 7 This is a schematic diagram showing the p-type doped polycrystalline silicon layer after fabrication in one embodiment of this application; Figure 8 This is a schematic diagram showing the n-type doped polycrystalline silicon layer after fabrication in one embodiment of this application; Figure 9 This is a flowchart illustrating the etching process to remove the doped polysilicon layer and a portion of the silicon wafer from the non-gateline region in one embodiment of this application. Figure 10 This is a schematic diagram of the doped polysilicon layer after etching away the non-gateline region in one embodiment of this application; Figure 11 This is a schematic diagram of the doped polysilicon layer after etching away the non-gateline regions in another embodiment of this application.

[0021] Icons: 010 - Solar cell; 100 - Silicon wafer; 101 - Middle section; 102 - Edge section; 110 - Grid line area; 120 - Non-grid line area; 200 - Grid line; 201 - First grid line; 202 - Second grid line; 300 - p-type doped polycrystalline silicon layer; 310 - First dielectric layer; 400 - n-type doped polycrystalline silicon layer; 410 - Second dielectric layer; 500 - Tunneling oxide layer; 610 - First passivation layer; 620 - Second passivation layer. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0024] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0025] In the description of this application, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, they are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0026] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0027] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0028] Parasitic absorption occurs in the polycrystalline silicon layer on the back of solar cells, affecting the photoelectric conversion efficiency (PCO) of the solar cell. Parasitic absorption refers to the phenomenon where photons are absorbed by inactive layers or non-ideal locations, rather than by the active layers (such as perovskite layers, monocrystalline or polycrystalline silicon layers) designed to generate electricity. Polycrystalline silicon is composed of many small silicon crystals with numerous grain boundaries and defects, which may cause additional absorption of specific wavelengths of light. Furthermore, impurities and structural defects in polycrystalline silicon can cause scattering and absorption of photon energy. This unwanted absorption leads to the loss of photogenerated carriers, thereby reducing the overall conversion efficiency of the solar cell. In related technologies, to improve the parasitic absorption problem on the back of solar cells, the doped polycrystalline silicon layer in the non-grid area on the back of the solar cell is removed. For example, by irradiating all non-grid areas on the back of a solar cell with a laser, the laser acts on the doped polycrystalline silicon layer and its surface phosphosilicate glass (PSG) film in the non-grid areas. The PSG film is removed or peeled off from the doped polycrystalline silicon layer under the laser's action (i.e., laser-induced film removal). Subsequent etching processes completely remove the doped polycrystalline silicon layer in the non-grid areas, leaving only the doped polycrystalline silicon layer in the grid areas. While back-side etching in related technologies can improve the parasitic absorption problem of the back polycrystalline silicon layer, the etching depth cannot be precisely controlled. To ensure complete removal of the polycrystalline silicon layer in the non-grid areas, a certain degree of etching occurs on the silicon wafer beneath the polycrystalline silicon layer. Typically, the non-grid areas on the back of the wafer are uniformly etched to a depth of 2-3 μm. Since the overall thickness of solar cells is already relatively thin (usually below 150 μm), this etching process results in poor wafer reliability, especially at the edges. Because subsequent processes involve high temperatures (such as coating and sintering), solar cells are prone to warping, increasing the risk of microcracks and fragmentation. Furthermore, silicon wafers / solar cells are susceptible to edge damage and even fragmentation during manufacturing and assembly due to impacts. Therefore, the fabrication methods used in related technologies can significantly negatively impact the structural strength of silicon wafers / solar cells, leading to reduced product yield, decreased product reliability, and shortened lifespan.

[0029] To address at least one deficiency in the aforementioned related technologies, this application provides a solar cell and its fabrication method. By increasing the thickness of the non-grid line region at the edge of the silicon wafer to be greater than that in the middle portion, the strength of the edge portion relative to the middle portion is improved. This optimizes the stress distribution of the silicon wafer, reducing warping, minimizing the risk of microcracks and fragmentation, and also reducing the risk of damage from edge impacts. Ultimately, this improves the product yield, reliability, and lifespan of the solar cell.

[0030] Figure 1 This is a schematic diagram of the back side of a solar cell 010 in one embodiment of this application. Figure 1 As shown, the solar cell 010 provided in this embodiment has a plurality of grid lines 200 on its back side. These grid lines 200 are made of metal and serve as metal electrodes to collect current. The photocurrent generated by the solar cell 010 can be transmitted to an external energy storage device or the power grid through the grid lines 200. The type of solar cell 010 provided in this embodiment can be a tunnel oxide passivated contact (TOPCon) cell or a back contact (BC) cell, or it can be other solar cells with a doped polycrystalline silicon layer that require the removal of the non-grid line region 120 (or non-metallized region) on the back side.

[0031] Figure 2 This is a partial cross-sectional view of a solar cell 010 (TOPCon cell) in one embodiment of this application. Figure 2 As shown, Figure 2 The solar cell 010 shown is a tunneling oxide passivated contact cell, also known as a TOPCon cell, which includes a silicon wafer 100 and a doped polycrystalline silicon layer and grid lines 200 disposed on the silicon wafer 100. The silicon wafer 100 has a front side and a back side opposite each other in its thickness direction; the front side corresponds to the light-facing side of the solar cell 010, and the back side corresponds to the light-reflecting side of the solar cell 010. Figure 2 In the diagram, the upper surface of silicon wafer 100 is the front side, and the lower surface of silicon wafer 100 is the back side.

[0032] In this embodiment, the doped polycrystalline silicon layer includes a p-type doped polycrystalline silicon layer 300 and an n-type doped polycrystalline silicon layer 400. Furthermore, the solar cell 010 also includes a tunneling oxide layer 500, a first passivation layer 610, and a second passivation layer 620. In this embodiment, the p-type doped polycrystalline silicon layer 300 is disposed on the light-facing side of the silicon wafer 100, and the first passivation layer 610 is disposed on the side of the p-type doped polycrystalline silicon layer 300 away from the silicon wafer 100. The back side of the silicon wafer 100 has a gate line region 110 and a non-gate line region 120. The tunneling oxide layer 500 and the n-type doped polycrystalline silicon layer 400 are sequentially stacked on the gate line region 110 on the back side, and the second passivation layer 620 is disposed on the non-gate line region 120 and the side of the n-type doped polycrystalline silicon layer 400 away from the silicon wafer 100. It should be understood that in this embodiment, the gate line region 110 on the back side of the silicon wafer 100 is the region covered by the n-type doped polysilicon layer 400, and the non-gate line region 120 is the region on the back side of the silicon wafer 100 not covered by the n-type doped polysilicon layer 400. The gate line 200 includes a first gate line 201 and a second gate line 202, wherein the first gate line 201 is connected to the p-type doped polysilicon layer 300, and the second gate line 202 is connected to the n-type doped polysilicon layer 400.

[0033] In this embodiment, the silicon wafer 100 is n-type doped, specifically n-type monocrystalline silicon. The materials of the first passivation layer 610 and the second passivation layer 620 are selected from at least one of alumina, silicon oxide, silicon nitride, and silicon oxynitride. The first passivation layer 610 and the second passivation layer 620 can cover the front and back sides of the solar cell 010, effectively reducing the surface state density and carrier recombination at the surface, thereby improving the open-circuit voltage (Voc) and conversion efficiency of the cell. The first passivation layer 610 (e.g., using SiN) x It can also have an anti-reflection effect, reducing the reflection loss of incident light and increasing light absorption, thereby improving the short-circuit current (Isc). The second passivation layer 620, together with the tunneling oxide layer 500 and the n-type doped polycrystalline silicon layer 400, constitutes a passivation contact structure, which can optimize the transport and collection efficiency of charge carriers. In addition, the first passivation layer 610 and the second passivation layer 620 can protect the silicon wafer 100 and the doped polycrystalline silicon layer from the effects of the external environment (such as moisture and pollutants), improving the long-term stability of the solar cell 010.

[0034] The tunneling oxide layer 500 effectively reduces the recombination rate on the back side and increases the open-circuit voltage (Voc) of the cell. As an interface layer between the silicon wafer 100 and the n-type doped polycrystalline silicon layer 400, the tunneling oxide layer 500 optimizes interface characteristics, reduces interface defects, and improves carrier transport efficiency. The material of the tunneling oxide layer 500 can be SiO2. The tunneling oxide layer 500 allows electrons to pass through via quantum tunneling while blocking holes, thereby achieving selective carrier transport. The tunneling oxide layer 500 is typically thin, for example, 1 nm to 2 nm thick.

[0035] Figure 3 This is a schematic diagram of a silicon wafer 100 in one embodiment of this application. (In conjunction with...) Figure 2 and Figure 3 In this embodiment, the silicon wafer 100 has a middle portion 101 and an edge portion 102. The edge portion 102 forms the edge of the silicon wafer 100 and surrounds the middle portion 101. The thickness of the silicon wafer 100 in the non-gate region 120 of the edge portion 102 is greater than the thickness of the silicon wafer 100 in the non-gate region 120 of the middle portion 101. It is understood that the area occupied by the non-gate region 120 is generally larger than the area occupied by the gate region 110, and the thickness of the silicon wafer 100 in the non-gate region 120 has a significant impact on the structural strength of the silicon wafer 100. Typically, the edge portion 102 of the silicon wafer 100 is more prone to warping and impacts than the middle portion 101. Therefore, the edge portion 102 is a weak point of the silicon wafer 100, prone to warping and microcracks. In this embodiment, because the thickness of the non-grid region 120 of the edge portion 102 of the silicon wafer 100 is greater than the thickness of the non-grid region 120 in the middle portion 101, the edge portion 102 of the silicon wafer 100 has higher structural strength than the middle portion 101. This type of silicon wafer 100 is less prone to warping and reduces the risk of silicon wafer 100 fragmentation due to impacts. Since the solar cell 010 is less prone to warping and has good strength, it facilitates subsequent processing and assembly of the cell and is less susceptible to damage, thus improving product yield. After being assembled into a photovoltaic module and put into use, the solar cell 010 has better reliability and a longer service life.

[0036] like Figure 3As shown, the portion enclosed by the dashed line is the middle portion 101 of the silicon wafer 100, and the portion between the dashed line and the edge of the silicon wafer 100 is the edge portion 102 of the silicon wafer 100. Optionally, the middle portion 101 of the silicon wafer 100 and the silicon wafer 100 are both rectangular; alternatively, the middle portion 101 of the silicon wafer 100 and the silicon wafer 100 have similar shapes (i.e., have the same aspect ratio). In other optional embodiments, the middle portion 101 of the silicon wafer 100 can also be selected as other shapes as needed, such as circular, elliptical, triangular, trapezoidal, or other irregular shapes, as long as the edge of the middle portion 101 of the silicon wafer 100 is spaced from the edge of the silicon wafer 100.

[0037] Optionally, the dimension of the edge portion 102 in its width direction (W1 and W2 in the figure) is 1% to 30% of the dimension of the silicon wafer 100 in the same direction, for example, any one of the following percentages or a value between any two percentages: 1%, 2%, 5%, 10%, 15%, 20%, 25%, and 30% of the dimension of the silicon wafer 100 in the same direction. The width direction of the edge portion 102 is parallel to and perpendicular to the edge of the silicon wafer 100. In this embodiment, since the edge portion 102 surrounds the middle portion 101, the width direction of the edge portion 102 may have different directions. Figure 3 As shown, the width direction of the left and right edge portions 102, i.e., the left and right direction, is parallel to the width direction of the silicon wafer 100. The width of the edge portion 102 at this point ( Figure 3 As shown in W1, it occupies 100 of the width of the silicon wafer. Figure 3 (As shown in L1) 1%~30%. The width direction of the upper and lower edge portions 102, i.e., the vertical direction, is parallel to the length direction of the silicon wafer 100. The width of these edge portions 102 (as shown in L1) Figure 3 As shown in W2, it occupies 100 of the length of the silicon wafer. Figure 3 (As shown in L2) 1%~30%.

[0038] Optionally, the edge portion 102 has a dimension of 1 to 70 mm in its width direction. For example, the width of the edge portion 102 can be any one of the following values ​​or the value between any two points: 1 mm, 2 mm, 5 mm, 10 mm, 15 mm, 20 mm, 30 mm, 40 mm, 50 mm, 60 mm, and 70 mm.

[0039] In this embodiment, trenches are formed in the non-gateline region 120 on the back side of the silicon wafer 100. This is due to excessive etching during the wet etching process to ensure complete removal of the doped polysilicon layer (specifically, the n-type doped polysilicon layer 400 in this embodiment) on the back side. In other optional embodiments, some non-gateline regions 120 of the silicon wafer 100 may not be etched, and trenches may not be formed; for example, the non-gateline region 120 in the edge portion 102 of the silicon wafer 100 may not be etched (i.e., just etched to the surface of the silicon wafer 100). It is understood that when the silicon wafer 100 is not etched, its thickness can be uniform, while the trench depth can be adjusted by adjusting the etching depth of the silicon wafer 100 in the non-gateline region 120. Figure 2 As shown in Figure D), the thickness of silicon wafer 100 at the non-gate area 120 can be adjusted.

[0040] In this embodiment, the depth of the trench in the edge portion 102 is less than the depth of the trench in the middle portion 101. Therefore, the thickness of the silicon wafer 100 in the non-gate line region 120 of the edge portion 102 is greater than the thickness of the silicon wafer 100 in the non-gate line region 120 of the middle portion 101. Optionally, the depth of the trench in the edge portion 102 is 0.1~3μm, such as any one of 0.1μm, 0.2μm, 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm or any value between any two of these values; the depth of the trench in the middle portion 101 is 1~5μm, such as any one of 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm or any value between any two of these values. It is understandable that if the trench depth is too deep, it can easily lead to a decrease in the strength of the silicon wafer 100; if the trench depth is too shallow, it can easily lead to incomplete removal of the doped polysilicon layer. In other optional embodiments, the trench depth can also be selected outside the above range according to the actual product needs. For example, when using a thicker silicon wafer 100, the trench depth can be increased.

[0041] The above Figure 2 The embodiments are described using TOPCon batteries as an example. The solar cell 010 provided in this application embodiment can also be a back contact battery (i.e., a BC battery). Figure 4 This is a partial cross-sectional view of the solar cell 010 (i.e., BC cell) in another embodiment of this application. Figure 4 As shown, the solar cell 010 includes a silicon wafer 100, a doped polycrystalline silicon layer disposed on the silicon wafer 100, and grid lines 200. Figure 4In the solar cell 010, the front side of the silicon wafer 100 faces upwards, corresponding to the light-facing side, and the back side of the silicon wafer 100 faces downwards, corresponding to the back-lighting side. The doped polycrystalline silicon layer includes a p-type doped polycrystalline silicon layer 300 and an n-type doped polycrystalline silicon layer 400. The solar cell 010 also includes a first dielectric layer 310, a second dielectric layer 410, a first passivation layer 610, and a second passivation layer 620. The first passivation layer 610 is disposed on the front side of the silicon wafer 100. The first dielectric layer 310 and the p-type doped polycrystalline silicon layer 300 are sequentially stacked on a portion of the gate line area 110 on the back side of the silicon wafer 100, and the second dielectric layer 410 and the n-type doped polycrystalline silicon layer 400 are sequentially stacked on another portion of the gate line area 110 on the back side of the silicon wafer 100. The second passivation layer 620 is disposed on the side of the p-type doped polysilicon layer 300 away from the silicon wafer 100, the side of the n-type doped polysilicon layer 400 away from the silicon wafer 100, and the non-gate region 120 on the back side of the silicon wafer 100.

[0042] exist Figure 4 In the illustrated embodiment, the grid line 200 specifically includes a first grid line 201 and a second grid line 202, wherein the first grid line 201 is connected to the p-type doped polycrystalline silicon layer 300, and the second grid line 202 is connected to the n-type doped polycrystalline silicon layer 400. In this embodiment, the back-contact battery is characterized by the absence of grid lines 200 on the light-facing side; all grid lines 200 (including the first grid line 201 and the second grid line 202) are located on the back of the battery. This means that the light-facing side of the battery is not blocked by grid lines 200, allowing the entire area of ​​the light-facing side of the solar cell 010 to receive sunlight, resulting in higher photoelectric conversion efficiency and increased photocurrent. Furthermore, since the grid lines 200 are all located on the back-facing side, the front of the battery is simpler, flatter, and more aesthetically pleasing, making it suitable for applications with high aesthetic requirements, such as building-integrated photovoltaic (BIPV) systems. Figure 4 In the illustrated embodiment, trenches are also formed in the non-gateline region 120 on the back side of the silicon wafer 100, with a depth of [missing information]. Figure 4 As shown in D.

[0043] Figure 5 This is a flowchart illustrating a method for fabricating a solar cell 010 according to one embodiment of this application. Figure 5 As shown, the method for preparing the solar cell 010 provided in this application embodiment can be used to prepare the solar cell 010 provided in the above embodiments of this application. The method for preparing the solar cell 010 includes the following steps: Step S100: Obtain silicon wafer 100.

[0044] In this embodiment, the silicon wafer 100 obtained is n-type doped single-crystal silicon. (For fabrication...) Figure 2Taking the TOPCon cell shown as an example, optionally, the front side of the silicon wafer 100 can be textured to form a textured surface, thereby reducing light reflection loss, improving light absorption efficiency, reducing surface recombination, and thus improving cell performance. Optionally, an alkaline solution (e.g., sodium hydroxide solution) can be used to etch the surface of the silicon wafer 100 to form the textured surface.

[0045] Step S200: Deposit a doped polycrystalline silicon layer on silicon wafer 100.

[0046] by Figure 2 Taking the TOPCon cell shown as an example, a p-type doped polycrystalline silicon layer 300 needs to be deposited on the front side of the silicon wafer 100, and an n-type doped polycrystalline silicon layer 400 needs to be deposited on the front side of the silicon wafer 100. Furthermore, before depositing the n-type doped polycrystalline silicon layer 400, a tunneling oxide layer 500 needs to be fabricated on the back side of the silicon wafer 100. Optionally, the doped polycrystalline silicon layer can be fabricated using a chemical vapor deposition (CVD) process; the tunneling oxide layer 500 can be fabricated using a thermal oxidation process or a chemical vapor deposition process. For example, the silicon wafer 100 is first placed in a chemical vapor deposition apparatus, and a silicon source (such as high-purity SiH4) is introduced to grow an intrinsic polycrystalline silicon layer on the front side of the silicon wafer 100. Then, the above structure is placed in a boron diffusion furnace tube, and BCl3 is introduced for boron diffusion to transform the intrinsic polycrystalline silicon layer into a p-type doped polycrystalline silicon layer 300. The previously prepared structure was placed in a CVD apparatus, and high-purity oxygen was introduced to grow a tunneling oxide layer 500 on the back side of silicon wafer 100. Then, a silicon source (such as high-purity SiH4) was introduced to grow an intrinsic polycrystalline silicon layer on the surface of the tunneling oxide layer 500. The structure was then placed in a phosphorus diffusion furnace tube, and POCl3 was introduced for phosphorus diffusion, transforming the intrinsic polycrystalline silicon layer into an n-type doped polycrystalline silicon layer 400. It can be understood that the process gases used in the above doping process can be selected according to the n-type and p-type doping elements to be doped, and are not limited to BCl3 and POCl3. After the doped polycrystalline silicon layer is prepared, the following is obtained: Figure 6 The structure shown.

[0047] by Figure 4 Taking the BC battery shown as an example, a first dielectric layer 310 and a p-type doped polycrystalline silicon layer 300 can be sequentially deposited on the back side of the silicon wafer 100. This can be achieved using a chemical vapor deposition (CVD) process. Specifically, the silicon wafer 100 is first placed in a CVD apparatus, and high-purity oxygen is introduced to grow the first dielectric layer 310 on the back side of the silicon wafer 100. Then, a silicon source (such as high-purity SiH4) is introduced to grow an intrinsic polycrystalline silicon layer on the first dielectric layer 310. The above structure is then placed in a boron diffusion furnace tube, and BCl3 is introduced for boron diffusion to transform the intrinsic polycrystalline silicon layer into a p-type doped polycrystalline silicon layer 300, resulting in the desired structure. Figure 7The structure is shown below. Subsequently, a portion of the first dielectric layer 310 and the p-type doped polysilicon layer 300 can be removed using a laser to expose a portion of the back side of the silicon wafer 100. Then, a second dielectric layer 410 and an n-type doped polysilicon layer 400 are sequentially grown on the exposed surface of the silicon wafer 100. Specifically, the steps for growing the second dielectric layer 410 and the n-type doped polysilicon layer 400 include: placing the previously fabricated structure in a vapor deposition apparatus, introducing high-purity oxygen to grow the second dielectric layer 410 on the exposed back side of the silicon wafer 100, then introducing a silicon source (such as high-purity SiH4) to grow an intrinsic polysilicon layer on the second dielectric layer 410, and then placing the above structure in a phosphorus diffusion furnace tube and introducing POCl3 for phosphorus diffusion to transform the intrinsic polysilicon layer into an n-type doped polysilicon layer 400, resulting in the structure shown below. Figure 8 The structure shown is illustrated. It can be understood that the process gases used in the above doping process can be selected based on the n-type and p-type doping elements to be doped, and are not limited to POCl3 and BCl3.

[0048] In step S300, the doped polysilicon layer and part of the silicon wafer 100 in the non-gate region 120 are etched away, wherein the etching depth of the silicon wafer 100 in the middle part 101 is greater than the etching depth of the silicon wafer 100 in the edge part 102.

[0049] Figure 9 This is a flowchart illustrating the etching process to remove the doped polysilicon layer and a portion of the silicon wafer 100 from the non-gate region 120 in one embodiment of this application. Figure 9 As shown in the embodiment of this application, step S300 specifically includes: Step S310: Irradiate the doped polysilicon layer in the non-gate region 120 with a laser.

[0050] It is understood that in the process of preparing the doped polycrystalline silicon layers (including p-type doped polycrystalline silicon layer 300 and n-type doped polycrystalline silicon layer 400), a phosphosilicate glass (PSG) film is formed on the surface of the n-type doped polycrystalline silicon layer 400, and a borosilicate glass (BSG) film is formed on the surface of the p-type doped polycrystalline silicon layer 300. By irradiating all non-gateline regions 120 on the back side of the solar cell 010 with a laser, the doped polycrystalline silicon layer and the PSG film (and / or BSG film) on its surface in the non-gateline regions 120 are affected. Under the action of the laser, the PSG film can melt, vaporize, or peel off from the doped polycrystalline silicon layer, thereby achieving laser film opening. Laser film opening facilitates the subsequent use of wet etching to completely remove the doped polycrystalline silicon layer in the non-gateline regions 120, leaving only the doped polycrystalline silicon layer in the gateline regions 110.

[0051] To achieve a greater etching depth for the silicon wafer 100 in the middle portion 101 than for the silicon wafer 100 in the edge portion 102, non-uniform laser irradiation can be used in step S310. For example, in the step of irradiating the doped polysilicon layer in the non-gate region 120 with a laser, the laser energy per unit area in the non-gate region 120 of the middle portion 101 is greater than that in the non-gate region 120 of the edge portion 102. Through the aforementioned non-uniform laser irradiation, the doped polysilicon layer and PSG film (and / or BSG film) in the non-gate region 120 of the middle portion 101 are more affected by the laser, generating more heat and undergoing more melting and vaporization. Consequently, in subsequent etching processes, the doped polysilicon layer in the middle portion 101 is more easily etched than that in the edge portion 102.

[0052] Optionally, the laser energy per unit area of ​​the non-grid region 120 in the middle portion 101 is 210 mJ / cm². 2 ~380mJ / cm 2 For example, 210mJ / cm 2 230mJ / cm 2 250mJ / cm 2 270mJ / cm 2 290mJ / cm 2 310mJ / cm 2 330mJ / cm 2 350mJ / cm 2 370mJ / cm 2 380mJ / cm 2 The value at any point in the region or the value between any two points. The laser energy per unit area of ​​the non-grid region 120 of the edge portion 102 is 180 mJ / cm². 2 ~350 mJ / cm 2 For example, 180mJ / cm 2 200mJ / cm 2 220mJ / cm 2 240mJ / cm 2 260mJ / cm 2 280mJ / cm 2 300mJ / cm 2 320mJ / cm 2 340mJ / cm 2 350mJ / cm 2 The value of any point in the array or the value between any two points.

[0053] It is understood that the difference in laser energy per unit area received by the middle portion 101 and the edge portion 102 can be achieved by irradiating the middle portion 101 and the edge portion 102 with lasers of the same power for different durations; or by irradiating the middle portion 101 and the edge portion 102 with lasers of different powers for the same duration; or by irradiating the middle portion 101 and the edge portion 102 with different laser powers and different irradiation durations. Therefore, in the optional embodiments of this application, the irradiation duration of the non-gateline region 120 of the middle portion 101 is greater than the irradiation duration of the non-gateline region 120 of the edge portion 102, and / or, the irradiation power of the non-gateline region 120 of the middle portion 101 is greater than the irradiation power of the non-gateline region 120 of the edge portion 102.

[0054] It is understood that the scanning speed, frequency, power, and spot size of the laser can directly affect the energy of the laser effect. In one optional embodiment, the initial frequency of the laser can be 600K, and the scanning speed can be 45~60m / s. Optionally, the laser used in step S310 can be a green laser. Optionally, by improving the control algorithm and hardware performance of the scanning galvanometer, it can dynamically adjust the scanning speed and angle of the laser beam according to the preset energy distribution pattern during the scanning process. For example, when scanning the edge portion 102, the scanning speed can be appropriately increased to reduce the laser's action time on the edge portion 102, thereby reducing the laser energy received by the edge portion 102; while in the middle portion 101, the scanning speed can be reduced to allow more energy to accumulate in the middle portion 101.

[0055] In step S320, a wet etching process is used to remove the doped polysilicon layer and part of the silicon wafer 100 in the non-gate region 120.

[0056] It is understandable that the non-gate region 120 irradiated by the laser can be etched away, while the non-gate region 120 not irradiated by the laser will not be etched. In order to ensure that the doped polysilicon layer of the non-gate region 120 is completely removed and the silicon wafer 100 is exposed, the back side of the silicon wafer 100 (especially the non-gate region 120 in the middle part 101) is usually also etched to a certain extent, thereby forming trenches. If non-uniform laser irradiation has been performed on the middle portion 101 and the edge portion 102 in step S310, for example, the laser energy per unit area of ​​the non-gate region 120 of the middle portion 101 is greater than the laser energy per unit area of ​​the non-gate region 120 of the edge portion 102, then when the middle portion 101 and the edge portion 102 are subjected to the same wet etching process with the same technical parameters, the non-gate region 120 of the middle portion 101 of the silicon wafer 100 will generate a deeper trench, which will make the thickness of the silicon wafer 100 at the non-gate region 120 of the middle portion 101 less than the thickness of the silicon wafer 100 at the non-gate region 120 of the edge portion 102.

[0057] In other embodiments, non-uniform etching can also be achieved by using different wet etching processes for the middle portion 101 and the edge portion 102. For example, a first etching solution can be used to etch the non-gateline region 120 of the middle portion 101, and a second etching solution can be used to etch the non-gateline region 120 of the edge portion 102; wherein the corrosiveness of the first etching solution is stronger than that of the second etching solution, and / or the concentration of the first etching solution is greater than that of the second etching solution. The comparison of the corrosiveness should be based on the corrosiveness of the etching solution to the doped polysilicon layer; for example, at the same concentration, the alkalinity of the effective component in the first etching solution is stronger than that in the second etching solution (e.g., the first etching solution uses a strong base, and the second etching solution uses a weak base). In one optional embodiment, a mold can be used to form a barrier between the edge portion 102 and the middle portion 101, confining the first etching solution to the middle portion 101 and the second etching solution to the edge portion 102. This allows the first etching solution to etch the non-gateline region 120 of the middle portion 101, and the second etching solution to etch the non-gateline region 120 of the edge portion 102. In another optional embodiment, a temporary mask can be used to cover the edge portion 102, and the first etching solution can be used to etch the non-gateline region 120 of the middle portion 101. Then, the temporary mask on the edge portion 102 is removed, and a temporary mask is instead laid on the middle portion 101. The second etching solution is then used to etch the non-gateline region 120 of the edge portion 102. Finally, the temporary mask on the middle portion 101 is removed.

[0058] In other alternative embodiments, different etching durations can be used for the etching of the non-gateline regions 120 of the middle portion 101 and the edge portion 102 to achieve non-uniform etching. For example, the etching duration of the middle portion 101 can be longer than that of the edge portion 102. In this case, the non-gateline regions 120 of the middle portion 101 of the silicon wafer 100 will be etched deeper than those of the edge portion 102. Optionally, the etching durations of the non-gateline regions 120 of the middle portion 101 and the edge portion 102 should be selected based on factors such as the parameters of the etching solution, the thickness of the doped polysilicon layer, and the allowable etching depth of the silicon wafer 100. For example, the etching duration of the middle portion 101 can be 3 min to 5 min, and the etching duration of the edge portion 102 can be 2 min to 4 min. In one optional embodiment, all non-grid area 120 on the back of the solar cell 010 can be etched for a first duration (e.g., 2 min to 4 min); then, a mold is used to form a barrier between the edge portion 102 and the middle portion 101 to confine the etching solution to the middle portion 101, and the non-grid area 120 of the middle portion 101 is further etched for a second duration (e.g., 30 s to 180 s). In another optional embodiment, all non-grid area 120 on the back of the solar cell 010 can be etched for a first duration (e.g., 2 min to 4 min), then a temporary mask is used to cover the edge portion 102; then, the non-grid area 120 of the middle portion 101 is further etched with etching solution for a second duration (e.g., 30 s to 180 s), during which the non-grid area 120 of the edge portion 102 is not etched due to the presence of the temporary mask; finally, the temporary mask is removed.

[0059] In other alternative embodiments, different process temperatures can be used to achieve non-uniform etching for the non-gateline regions 120 of the middle portion 101 and the edge portion 102. For example, the etching temperature of the middle portion 101 can be higher than that of the edge portion 102. It is understood that, generally, higher temperatures result in better thermodynamic and kinetic conditions for the chemical reaction, making the reaction easier and faster. Therefore, when the etching temperature of the middle portion 101 is higher than that of the edge portion 102, the non-gateline regions 120 of the middle portion 101 of the silicon wafer 100 will be etched more deeply than those of the edge portion 102. For example, the etching temperature of the edge portion 102 can be room temperature, while the etching temperature of the middle portion 101 can be 30°C to 60°C. A heating device can be used to simultaneously heat the middle portion 101 of the silicon wafer 100 during the etching process; alternatively, the middle portion 101 of the silicon wafer 100 can be heated first to raise its temperature to the target etching temperature, and then the doped polysilicon layer on the silicon wafer 100 can be wet-etched.

[0060] When making such Figure 2 When processing the solar cell 010 (TOPCon cell) shown, the wet etching process removes not only the doped polysilicon layer in the non-gateway region 120, but also the tunneling oxide layer 500 in the non-gateway region 120, resulting in the following: Figure 10 The structure shown.

[0061] When making such Figure 4 When processing the solar cell 010 (BC cell) shown, a portion of the n-type doped polysilicon layer 400 and a corresponding portion of the second dielectric layer 410 can be removed using a wet etching process to expose the non-gateway region 120 of the silicon wafer 100; alternatively, a portion of the p-type doped polysilicon layer 300 and a corresponding portion of the first dielectric layer 310 can be removed to expose the non-gateway region 120 of the silicon wafer 100; or, a portion of the n-type doped polysilicon layer 400 and a corresponding portion of the second dielectric layer 410, as well as a portion of the p-type doped polysilicon layer 300 and a corresponding portion of the first dielectric layer 310, can be removed to expose the non-gateway region 120 of the silicon wafer 100. The final result is as follows: Figure 11 The structure shown.

[0062] In this embodiment, trenches are formed in both the non-gateway region 120 of the middle portion 101 and the non-gateway region 120 of the edge portion 102 of the silicon wafer 100 using a wet etching process. The trench depth of the non-gateway region 120 in the middle portion 101 is 1 μm to 5 μm, and the trench depth of the non-gateway region 120 in the edge portion 102 is 0.1 μm to 3 μm. Because the non-gateway region 120 in the middle portion 101 of the silicon wafer 100 is etched more deeply, the thickness of the non-gateway region 120 in the middle portion 101 is less than the thickness of the non-gateway region 120 in the edge portion 102. This "thick at the edge, thin in the middle" structure helps to improve the warping problem of the silicon wafer 100, facilitating subsequent processing and assembly; furthermore, the thicker edge thickness effectively reduces the risk of damage to the solar cell 010 due to impacts. Optionally, the etching solution used in the wet etching process includes at least one of sodium hydroxide and potassium hydroxide.

[0063] Step S400: Fabricate gate line 200 connected to the doped polysilicon layer.

[0064] In this embodiment, the first gate line 201 is connected to the p-type doped polysilicon layer 300, and the second gate line 202 is connected to the n-type doped polysilicon layer 400.

[0065] To make such Figure 2Taking the solar cell 010 (TOPCon cell) shown as an example, before fabricating the first grid line 201 and the second grid line 202, a first passivation layer 610 can be fabricated on the side of the p-type doped polycrystalline silicon layer 300 facing away from the silicon wafer 100, and a second passivation layer 620 can be fabricated on the non-grid line region 120 on the back side of the silicon wafer 100 and on the side of the n-type doped polycrystalline silicon layer 400 facing away from the silicon wafer 100; then the first grid line 201 and the second grid line 202 are fabricated to obtain the following: Figure 2 The solar cell 010 shown.

[0066] To make such Figure 4 Taking the solar cell 010 (BC cell) shown as an example, before fabricating the first grid line 201 and the second grid line 202, a first passivation layer 610 can be fabricated on the front side of the silicon wafer 100, and a second passivation layer 620 can be fabricated on the non-grid line region 120 on the back side of the silicon wafer 100 and on the side of the p-type doped polycrystalline silicon layer 300 and the n-type doped polycrystalline silicon layer 400 facing away from the silicon wafer 100; then the first grid line 201 and the second grid line 202 are fabricated to obtain the following: Figure 4 The solar cell 010 shown.

[0067] Optionally, the first passivation layer 610 and the second passivation layer 620 can be prepared by vapor deposition or atomic layer deposition. The first passivation layer 610 and the second passivation layer 620 can be a single-layer structure formed by a single material (such as an alumina layer, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer), or a composite layer structure formed by multiple materials.

[0068] During the fabrication of gate line 200, a second gate line 202 can be printed on the second passivation layer 620 in the region corresponding to the n-type doped polysilicon layer 400; subsequently, a first gate line 201 is printed on the first passivation layer 610 in the region corresponding to the p-type doped polysilicon layer 300; finally, the first gate line 201 and the second gate line 202 are sintered. The final result is as follows: Figure 2 or Figure 4 The solar cell 010 shown.

[0069] This application also provides a photovoltaic module (not shown in the figure), which includes the solar cell 010 provided in the above embodiments of this application, or includes the solar cell 010 prepared by the preparation method provided in the above embodiments of this application.

[0070] In summary, this application provides a method for fabricating a solar cell and a photovoltaic module. The method for fabricating a solar cell includes: obtaining a silicon wafer 100, the silicon wafer 100 having a middle portion 101 and an edge portion 102, the edge portion 102 forming the edge of the silicon wafer 100 and surrounding the middle portion 101, and at least one side of the silicon wafer 100 having a gate line region 110 and a non-gate line region 120; depositing a doped polycrystalline silicon layer on the silicon wafer 100; etching away the doped polycrystalline silicon layer and a portion of the silicon wafer 100 in the non-gate line region 120, wherein the etching depth of the silicon wafer 100 in the middle portion 101 is greater than the etching depth of the silicon wafer 100 in the edge portion 102; and fabricating gate lines 200 connected to the doped polycrystalline silicon layer. Through the fabrication method provided by this application, the non-gate line region 120 of the edge portion 102 of the silicon wafer 100 can have a thicker thickness than the non-gate line region 120 of the middle portion 101, thus its structural strength is better than that of the middle portion 101. The edge portion 102 is precisely where warping and microcracks are prone to occur, and it is also susceptible to impacts. Therefore, in this embodiment, reinforcing the edge portion 102 of the silicon wafer 100 can improve the reliability of the entire silicon wafer 100 and even the entire solar cell 010, making the silicon wafer 100 and solar cell 010 less prone to warping, microcracks, or fragmentation, and less susceptible to damage from impacts. During the processing of the solar cell 010, the assembly of the photovoltaic module, and subsequent use of the photovoltaic module, a more reliable silicon wafer 100 enables the solar cell 010 to have a higher product yield, better performance, and a longer service life.

[0071] The method for preparing the solar cell 010 provided in this application embodiment can be used to prepare the solar cell 010 described above. The photovoltaic module provided in this application embodiment includes the solar cell 010 described above or the solar cell 010 prepared by the above method, and therefore also has the characteristics of high product yield, good reliability and long service life.

[0072] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

[0073] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for preparing a solar cell, characterized in that, include: A silicon wafer is obtained having a central portion and an edge portion, the edge portion forming an edge of the silicon wafer and surrounding the central portion, and at least one side of the silicon wafer having a gate line region and a non-gate line region; A doped polycrystalline silicon layer is deposited on the silicon wafer; The doped polysilicon layer and a portion of the silicon wafer in the non-gate region are etched away, wherein the etching depth of the silicon wafer in the middle portion is greater than the etching depth of the silicon wafer in the edge portion; A gate line is fabricated to connect to the doped polysilicon layer.

2. The method for preparing a solar cell according to claim 1, characterized in that, The step of etching away the doped polysilicon layer and a portion of the silicon wafer in the non-gateline region includes: The doped polysilicon layer in the non-gateline region is irradiated with a laser. The doped polysilicon layer and part of the silicon wafer in the non-gate area are removed using a wet etching process.

3. The method for preparing a solar cell according to claim 2, characterized in that, In the step of irradiating the doped polysilicon layer in the non-gate region with a laser, the laser energy per unit area of ​​the non-gate region in the middle portion is greater than the laser energy per unit area of ​​the non-gate region in the edge portion.

4. The method for preparing a solar cell according to claim 3, characterized in that, The laser energy per unit area of ​​the non-grid region in the middle portion is 210 mJ / cm2 to 380 mJ / cm2; the laser energy per unit area of ​​the non-grid region in the edge portion is 180 mJ / cm2 to 350 mJ / cm2.

5. The method for preparing a solar cell according to claim 3, characterized in that, In the step of irradiating the doped polysilicon layer in the non-gate region with a laser, the irradiation duration of the non-gate region in the middle portion is greater than the irradiation duration of the non-gate region in the edge portion, and / or, the irradiation power of the non-gate region in the middle portion is greater than the irradiation power of the non-gate region in the edge portion.

6. The method for preparing a solar cell according to claim 2, characterized in that, The step of removing the doped polysilicon layer and a portion of the silicon wafer in the non-gateline region using a wet etching process includes: The non-gateline region of the middle portion is etched using a first etching solution, and the non-gateline region of the edge portion is etched using a second etching solution. Wherein, the corrosiveness of the first etching solution is stronger than that of the second etching solution, and / or, the concentration of the first etching solution is greater than that of the second etching solution.

7. The method for preparing a solar cell according to claim 2, characterized in that, In the step of removing the doped polysilicon layer and part of the silicon wafer in the non-gate area using a wet etching process, the etching duration of the middle portion is longer than that of the edge portion, and / or the etching temperature of the middle portion is higher than that of the edge portion.

8. The method for preparing a solar cell according to any one of claims 2-7, characterized in that, The laser in question is a green-skinned laser.

9. The method for preparing a solar cell according to any one of claims 2-7, characterized in that, The etching solution used in the wet etching process contains at least one of sodium hydroxide and potassium hydroxide.

10. The method for preparing a solar cell according to any one of claims 2-7, characterized in that, The solar cell (010) is a tunneling oxide passivated contact cell or a back contact cell, and the grid line region (110) and the non-grid line region (120) are located on the back side of the silicon wafer (100).

11. A photovoltaic module, characterized in that, The solar cell includes those prepared by the method described in any one of claims 1-10.

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