Display device and electronic device

Abstract

A display device and an electronic device are provided, the display device including: a display panel including a display module and a window module, a window module over the display module and including a first polarizing film over the display module, a first phase retardation film over the first polarizing film, a window over the first phase retardation film, and a semi-transmissive reflective film over the window; and an optical module over the display panel and including a first optical module including a first lens over the semi-transmissive reflective film, and a second optical module including a second phase retardation film over the first lens, a second polarizing film over the second phase retardation film, and a second lens over the second polarizing film.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0061048, filed on May 9, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device. Background Technology

[0003] A head-mounted display (HMD) is an image display device worn on a user's head in the form of glasses or a helmet, and focused on in front of the user's eyes at a certain distance. Head-mounted displays can enable virtual reality (VR) or augmented reality (AR).

[0004] Head-mounted displays use multiple lenses to magnify and display images from small display devices. Therefore, display devices used in head-mounted displays need to provide relatively high-resolution images, for example, images with a resolution of approximately 3000 pixels per inch (PPI) or greater. For this purpose, silicon-based organic light-emitting diodes (OLEDoS), as small organic light-emitting display devices with high resolution, have been used in head-mounted displays. OLEDoS is a device that displays images by placing organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate including complementary metal-oxide-semiconductor (CMOS). Summary of the Invention

[0005] This disclosure provides a display device in which the thickness of the optical module is reduced or minimized.

[0006] This disclosure also provides a display device with improved light output rate.

[0007] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below.

[0008] According to one aspect of this disclosure, a display device is provided, the display device comprising: a display panel including a display module and a window module, the window module being above the display module and including a first polarizing film above the display module, a first phase retardation film above the first polarizing film, a window above the first phase retardation film, and a semi-transparent reflective film above the window; and an optical module being above the display panel and including a first optical module including a first lens above the semi-transparent reflective film and a second optical module including a second phase retardation film above the first lens, a second polarizing film above the second phase retardation film, and a second lens above the second polarizing film.

[0009] Semitransmissive reflective films can include curved surfaces.

[0010] The window may include a curved first surface adjacent to the semi-transparent reflective film.

[0011] The radius of curvature of the first surface can be approximately 100 mm or greater.

[0012] The first polarizing film and the second polarizing film may include linear polarizing films, wherein the first polarization axis of the first polarizing film and the second polarization axis of the second polarizing film are substantially perpendicular.

[0013] The first polarizing film may include an absorptive polarizing film, while the second polarizing film includes a reflective polarizing film.

[0014] The display device may also include a third polarizing film above the second lens and having a third polarizing axis extending in a direction parallel to the second polarizing axis.

[0015] The third polarizing film may include an absorption-type polarizing film.

[0016] The first phase retardation film and the second phase retardation film may include a quarter-wave plate, wherein the first optical axis of the first phase retardation film and the second optical axis of the second phase retardation film are offset in opposite directions.

[0017] The first and second lenses may include magnifying lenses.

[0018] A semi-transparent reflective film may include a plurality of layers having alternately stacked a first material layer having a first refractive index and a second material layer having a second refractive index greater than the first refractive index, wherein the bottommost of the plurality of layers is one of the first material layers.

[0019] The number of first material layers can be greater than the number of second material layers.

[0020] The number of the first material layer can be one more than the number of the second material layer.

[0021] The first material layer may include silicon oxide, and the second material layer includes titanium oxide.

[0022] The number of layers can be nine or more.

[0023] The first refractive index may be from about 1.91 to about 1.93, and the second refractive index may be from about 3.45 to about 3.47.

[0024] The window module and the first optical module can be separated, wherein the first optical module and the second optical module are separated.

[0025] The display device may also include a coating film on the surface of the first optical module or the surface of the second optical module.

[0026] The display device may also include a third phase retardation film between the display module and the first polarizing film, and including a quarter-wave plate.

[0027] The display panel may further include: a semiconductor substrate; a conductive layer sequentially stacked over the semiconductor substrate; a reflective electrode layer over the conductive layer; an insulating film covering at least a portion of the reflective electrode layer; and a light-emitting element over the insulating film, including a first electrode, a light-emitting stack, and a second electrode.

[0028] According to one aspect of this disclosure, an electronic device includes a display device, the display device comprising: a display panel including a display module and a window module, the window module being above the display module and including a first polarizing film above the display module, a first phase retardation film above the first polarizing film, a window above the first phase retardation film, and a semi-transparent reflective film above the window; and an optical module being above the display panel and including a first optical module including a first lens above the semi-transparent reflective film and a second optical module including a second phase retardation film above the first lens, a second polarizing film above the second phase retardation film, and a second lens above the second polarizing film.

[0029] According to one or more embodiments of the present disclosure, the thickness of the optical module can be reduced or minimized.

[0030] The light output rate can be improved by using a display device according to one or more embodiments of the present disclosure.

[0031] However, the aspects of the embodiments according to this disclosure are not limited to the above aspects, and various other aspects are included herein. Attached Figure Description

[0032] The above and other aspects of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments; Figure 2 This is a block diagram illustrating a display device according to one or more embodiments; Figure 3 It is an equivalent circuit diagram of the first sub-pixel according to one or more embodiments; Figure 4 This is a plan view showing an example of a display panel according to one or more embodiments; Figure 5 and Figure 6 It is shown Figure 4 A plan view of an embodiment of the display area; Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel, taken by line X1-X1'; Figure 8 and Figure 9 This is a cross-sectional view of a display device according to one or more embodiments; Figure 10 It is a schematic diagram used to explain the path and polarization state of light emitted from a display device according to one or more embodiments; Figure 11 This is a cross-sectional view showing a stacked structure of a translucent reflective film according to one or more embodiments; Figure 12 This is a cross-sectional view showing a display device according to one or more other embodiments; Figure 13 This is a cross-sectional view showing a display device according to yet another or one other embodiment; Figure 14 This is a cross-sectional view showing a display device according to one or more other embodiments; Figure 15 This is a perspective view showing a head-mounted display device according to one or more embodiments; Figure 16 It is shown Figure 15 An exploded perspective view of an example of a head-mounted display device; and Figure 17 This is a perspective view illustrating a head-mounted display device according to one or more other embodiments. Detailed Implementation

[0033] Aspects of some embodiments of this disclosure and methods of implementing them can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments or unnecessary for those skilled in the art to fully understand aspects of this disclosure may be omitted. Unless otherwise stated, the same reference numerals, symbols, or combinations thereof denote the same elements throughout the drawings and written description, and therefore, their repeated description may be omitted.

[0034] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "may," "may," or "may not" in describing embodiments corresponds to one or more embodiments of this disclosure.

[0035] In view of the entire contents of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in a variety of suitable ways. Unless otherwise stated or implied, each embodiment may be implemented independently of one another or in combination with one another in any suitable way.

[0036] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, the disclosure is not limited thereto because the dimensions and thicknesses of elements in the drawings are arbitrarily shown for ease of description. Additionally, crosshairs and / or shading are typically used in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities among the elements shown, and / or any other characteristics, properties, etc.

[0037] Various embodiments are described herein with reference to cross-sectional views as schematic illustrations of examples and / or intervening structures. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances will be expected. Furthermore, the specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the illustrated shapes of elements, layers, or regions, but will include deviations in shape due to, for example, manufacturing processes.

[0038] For example, an injection region shown as rectangular will typically have circular or curved features at its edges and / or a gradient of injection concentration, rather than a binary variation from the injection region to the non-injection region. Similarly, the buried region formed by injection can induce some injection in the region between the buried region and the surface through which the injection occurs.

[0039] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “below,” “below,” “above,” “upper,” “above,” “higher,” “upper,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another element or feature. It will be understood that, in addition to the orientations depicted in the accompanying drawings, the spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be positioned “above” said other elements or features. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged on the upper or lower side of the second part, and is not limited to the upper side of the second part based on the direction of gravity.

[0040] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic sectional view" means when viewing a schematic section taken by vertically cutting the portion of the object from the side. The terms "overlapping" or "coinciding" mean that the first object may be above, below, or to the side of the second object, or vice versa. Additionally, the term "overlapping" can include stacking, facing or confronting, extending over (overgoing), covering or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include meanings such as "separated from," "offset from," or "offset from," and any other suitable equivalent as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "confronting" can mean that the first object may be directly or indirectly opposite the second object. In the case where a third object is located between the first and second objects, although the first and second objects still face each other, they can be understood as being indirectly opposite each other.

[0041] It will be understood that when a component, layer, region, or assembly (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as being "formed on," "on," "connected to," or "(operably, functionally, or communicatively) incorporated into" another component, layer, region, or assembly, it can be directly formed on, directly connected to, or directly incorporated into, the other component, layer, region, or assembly, or indirectly formed on, indirectly connected to, or indirectly incorporated into, the other component, layer, region, or assembly, such that one or more intermediary components, layers, regions, or assemblies may exist. Furthermore, this can uniformly mean direct or indirect incorporation or connection, as well as integral or non-integral incorporation or connection. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically bonded" to another layer, region, or component, it can be directly electrically connected or directly bonded to said other layer, region, and / or component, or one or more intermediary layers, regions, or components may be present. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Therefore, the connection is not limited to the connections shown in the figures or detailed description, and may include other types of connections. In the described embodiments, unless explicitly described as a direct connection, the expression for a connection indicates an electrical connection, and "directly connected / directly bonded" or "directly on..." means that one component is directly connected or directly bonded to another component or directly on another component, without an intermediary component.

[0042] Furthermore, in this specification, when a portion of a layer, film, region, plate, etc., is formed on another portion, the formation direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, plate, etc., is formed "below" another portion, this includes not only the case where the portion is "directly" "below" the other portion, but also the case where there is another portion between the portion and the other portion. Similarly, other expressions describing relationships between components, such as "between," "immediately between," "adjacent to," and "directly adjacent to," can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0043] For the purposes of this disclosure, when expressions such as “at least one of…” or “any one of…” or “one or more of…” follow a list of elements, they modify the entire list of elements without modifying any individual elements in that list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ) or any variations thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, when expressions such as “at least one of…”, “multiple (species / beings)…”, “one of…”, and other prepositional phrases follow (before) a list of elements, they modify the entire list of elements, not individual elements within that list. When “C to D” is stated, unless otherwise specified, it means C or greater and D or less.

[0044] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms do not correspond to a particular order, position, or priority, and are used only to distinguish one element, component, assembly, region, area, layer, part, or component from another. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or part described below may be designated as a second element, component, region, layer, or part. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0045] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction DR1, the second direction DR2, and / or the third direction DR3.

[0046] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well. It will also be understood that when the terms “comprising,” “having,” “including,” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0047] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than as terms of degree and are intended to explain the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. For example, “substantially” can include a range of + / - 5% of the corresponding value. As used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviations of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value. Furthermore, in describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.”

[0048] In some embodiments, well-known structures and arrangements may be described in the accompanying drawings with respect to one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuitry, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connections, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled by software to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware performing some functions and processors performing functions different from those of the dedicated hardware (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, in some embodiments, blocks, units, and / or modules may be physically divided into two or more interactively discrete blocks, units, and / or modules without departing from the scope of this disclosure. In addition, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of this disclosure.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0050] Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments. Figure 2 This is a block diagram illustrating a display device according to one or more embodiments.

[0051] Reference Figure 1 and Figure 2The display device 10 according to one or more embodiments can be a device for displaying moving or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, ultra-mobile PCs (UMPCs), etc. For example, the display device 10 according to one or more embodiments can be applied as a display unit in a television, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. Optionally, the display device 10 according to one or more embodiments can be applied to smartwatches, smartwatch phones, head-mounted displays (HMDs) for realizing virtual and augmented reality, etc.

[0052] The display device 10 according to one or more embodiments may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, a power supply circuit 500, and an optical module 800.

[0053] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side on a first direction DR1 and a long side on a second direction DR2 intersecting the first direction DR1. In the display panel 100, the angle where the short side on the first direction DR1 and the long side on the second direction DR2 intersect may be a right angle or a rounded corner with a curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to other polygonal shapes, circular shapes, or elliptical shapes. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but this specification is not limited thereto.

[0054] In the accompanying drawings, the first direction DR1 and the second direction DR2 intersect each other as horizontal directions. For example, the first direction DR1 and the second direction DR2 may be orthogonal to each other. Additionally, the third direction DR3 intersects the first direction DR1 and the second direction DR2, and they may be substantially perpendicular directions, for example, orthogonal to each other. Unless otherwise defined, in this specification, the direction indicated by the arrows from the first direction to the third directions DR1, DR2, and DR3 may be referred to as one side, and the direction opposite to it may be referred to as the other side. Furthermore, as used herein, the terms "above," "upper side," "upper part," "top," and "top surface" refer to the direction indicated by the arrows in the accompanying drawings on the third direction DR3, and the terms "below," "lower side," "lower part," "bottom," and "bottom surface" refer to the direction opposite to the direction indicated by the arrows on the third direction DR3, based on the accompanying drawings.

[0055] like Figure 2 As shown, the display panel 100 may include a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0056] The display area (DAA) can include multiple pixels (PX), multiple scan lines (SL), multiple emission control lines (EL), and multiple data lines (DL).

[0057] Multiple pixels (PX) can be arranged in a matrix on the first direction DR1 and the second direction DR2. Multiple scan lines (SL) and multiple emission control lines (EL) can extend on the first direction DR1 and be arranged on the second direction DR2. Multiple data lines (DL) can extend on the second direction DR2 and be positioned on the first direction DR1.

[0058] Multiple scan lines SL can include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. Multiple emit control lines EL can include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0059] Multiple pixels PX may include multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 may include, as described later... Figure 3 The multiple pixel transistors shown can be formed and positioned on a semiconductor substrate SSUB using semiconductor processes (see [reference]). Figure 7 For example, the multiple pixel transistors of the data driver 700 can be formed of complementary metal-oxide-semiconductor (CMOS).

[0060] Each of the multiple sub-pixels SP1, SP2, and SP3 can be connected to any one of the multiple write scan lines GWL, any one of the multiple control scan lines GCL, any one of the multiple bias scan lines GBL, any one of the multiple first emission control lines EL1, any one of the multiple second emission control lines EL2, and any one of the multiple data lines DL. Each of the multiple sub-pixels SP1, SP2, and SP3 can receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0061] The non-display area NDA may include a scan driver 610, a transmit driver 620, and a data driver 700.

[0062] The scan driver 610 may include multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed using semiconductor processes and can be positioned on a semiconductor substrate SSUB (see [link to SSUB]). Figure 7 On ), for example, multiple scanning transistors and multiple light-emitting transistors can be formed by CMOS. Although in Figure 2 The diagram shows a scan driver 610 positioned to the left of the display area DAA and a transmit driver 620 positioned to the right of the display area DAA, but this disclosure is not limited thereto. For example, the scan driver 610 and the transmit driver 620 may be positioned to the left and right of both the display area DAA.

[0063] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit 400, and may output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS, and may output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS, and may output them sequentially to the bias scan line GBL.

[0064] The transmit driver 620 may include a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 may receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 may generate a first transmit control signal based on the transmit timing control signal ECS and may output them sequentially to a first transmit control line EL1. The second transmit control driver 622 may generate a second transmit control signal based on the transmit timing control signal ECS and may output them sequentially to a second transmit control line EL2.

[0065] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed by semiconductor processes and positioned on a semiconductor substrate SSUB (see [link to SSUB]). Figure 7 For example, multiple data transistors can be formed using CMOS.

[0066] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 can convert the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and can output the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0067] The heat dissipation layer 200 may be stacked on the display panel 100 in a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be positioned on one surface of the display panel 100 (e.g., on the rear surface of the display panel 100). The heat dissipation layer 200 may be used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include graphite or a metal layer such as silver (Ag), copper (Cu), or aluminum (Al) with high thermal conductivity.

[0068] Circuit board 300 can be electrically connected to the first pad (or "soldering pad") portion of display panel 100 PDA1 (see [link to circuit board 300]) using a conductive adhesive component such as an anisotropic conductive film. Figure 4 Multiple first pads PD1 (see) Figure 4 Circuit board 300 can be a flexible printed circuit board or a flexible film made of flexible material. Although circuit board 300 is in Figure 1 The circuit board 300 is shown unfolded, but it can be bent. In this case, one end of the circuit board 300 can be positioned on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 can be a first pad portion PDA1 of the circuit board 300 connected to the display panel 100 using conductive adhesive members (see...). Figure 4 Multiple first pads PD1 (see) Figure 4 The opposite end of the other end of the ).

[0069] The timing control circuit 400 can receive externally supplied digital video data DATA and timing signals. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0070] The power supply circuit 500 can generate multiple panel driving voltages based on external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later. Figure 3 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0071] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0072] Optionally, similar to the scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 can be located in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include a plurality of timing transistors, and each power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors can be formed by semiconductor processes and located on a semiconductor substrate SSUB (see [link to semiconductor substrate]). Figure 7 On the data driver 700. For example, multiple sequential transistors and multiple power transistors can be formed by CMOS. Each of the timing control circuit 400 and the power supply circuit 500 can be located on the data driver 700 and the first pad PDA1 (see...). Figure 4 )between.

[0073] The optical module 800 can be positioned on the display panel 100. The optical module 800 can adjust the path and polarization state of light emitted from the display panel 100. The optical module 800 can realize a folded optical device with a folded optical path. See below for further details. Figure 8 The optical module 800 is described.

[0074] Figure 3 It is an equivalent circuit diagram of the first sub-pixel according to one or more embodiments.

[0075] Apart from Figure 1 and Figure 2 External reference Figure 3The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to the first driving voltage line VSL, the second driving voltage line VDL, and the third driving voltage line VIL. A first driving voltage VSS, corresponding to a low potential voltage, is applied to the first driving voltage line VSL; a second driving voltage VDD, corresponding to a high potential voltage, is applied to the second driving voltage line VDL; and a third driving voltage VINT, corresponding to the initialization voltage, is applied to the third driving voltage line VIL. That is, the first driving voltage line VSL can be a low potential voltage line, the second driving voltage line VDL can be a high potential voltage line, and the third driving voltage line VIL can be an initialization voltage line. In this case, the first driving voltage VSS can be lower than the third driving voltage VINT, and the second driving voltage VDD can be higher than the third driving voltage VINT.

[0076] The first sub-pixel SP1 may include multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0077] The light-emitting element LE can emit light in response to a drive current (source-drain current) flowing through the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE can be proportional to the drive current. The light-emitting element LE can be positioned between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE can be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer positioned between the first electrode and the second electrode, but this specification is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor layer positioned between the first electrode and the second electrode, and the light-emitting element LE can be, for example, a miniature light-emitting diode.

[0078] The first transistor T1 may be a drive transistor that controls the drive current flowing between its source and drain electrodes according to the voltage applied to its gate electrode. The first transistor T1 may include a gate electrode connected to a first node N1, a source electrode connected to the drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0079] The second transistor T2 can be positioned between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 can be turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 may include a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0080] A third transistor T3 can be positioned between the first node N1 and the second node N2. The third transistor T3 can be turned on by a write control signal controlling the scan line GCL to connect the first node N1 to the second node N2. For this purpose, because the gate and drain electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 may include a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0081] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 can be turned on by a first emitter control signal on the first emitter control line EL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 may include a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0082] The fifth transistor T5 can be positioned between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 can be turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 may include a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0083] A sixth transistor T6 can be positioned between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 can be turned on by a second emitter control signal on the second emitter control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, a second drive voltage VDD on the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 may include a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0084] The first capacitor CP1 can be positioned between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 may include one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0085] The second capacitor CP2 can be positioned between the gate electrode of the first transistor T1 and the second drive voltage line VDL. The second capacitor CP2 may include one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second drive voltage line VDL.

[0086] The first node N1 can be the node between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 can be the node between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 can be the node between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0087] Each of the first transistors T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 can be a P-type MOSFET, but this specification is not limited thereto. Each of the first transistors T1 to the sixth transistor T6 can be an N-type MOSFET. Optionally, one or more of the first transistors T1 to the sixth transistor T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0088] Although Figure 3 The diagram shows the first sub-pixel SP1 comprising six transistors T1 to T6 and two capacitors CP1 and CP2, but the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 3 The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 can be changed in various ways.

[0089] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can be combined with... Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 is omitted in this specification.

[0090] Figure 4 This is a plan view showing an example of a display panel according to one or more embodiments.

[0091] Reference Figure 4 The display area DAA of the display panel 100 according to one or more embodiments may include a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments may include a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad PDA1, and a second pad PDA2.

[0092] The scan driver 610 can be positioned on a first side of the display area DAA, and the transmit driver 620 can be positioned on a second side of the display area DAA. For example, the scan driver 610 can be positioned on the other side of the display area DAA in the first direction DR1, and the transmit driver 620 can be positioned on one side of the display area DAA in the first direction DR1. That is, the scan driver 610 can be positioned on the left side of the display area DAA, and the transmit driver 620 can be positioned on the right side of the display area DAA.

[0093] The first pad portion PDA1 may include a plurality of first pads PD1 connected to the circuit board 300 by a conductive adhesive member. The first pad portion PDA1 may be positioned on the third side of the display area DAA. For example, the first pad portion PDA1 may be positioned on the other side of the display area DAA in the second direction DR2. That is, the first pad portion PDA1 may be positioned on the underside of the display area DAA.

[0094] The first pad PDA1 can be positioned outside the data driver 700 in the second direction DR2. That is, the first pad PDA1 can be positioned closer to the edge of the display panel 100 than the data driver 700.

[0095] The second pad PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to a fixture or probe pins during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a rigid printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0096] The first distribution circuit 710 can distribute the data voltage applied through the first pad PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one of the first pads PD1 of the first pad PDA1 to P (P is a positive integer of 2 or greater) data lines DL, thereby reducing the number of multiple first pads PD1. The first distribution circuit 710 can be positioned on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be positioned on the other side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 can be positioned on the lower side of the display area DAA.

[0097] The second distribution circuit 720 can distribute the signal applied through the second pad PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be positioned on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be positioned on one side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be positioned on the upper side of the display area DAA.

[0098] Figure 5 and Figure 6 It is shown Figure 4 A plan view of an embodiment of the display area.

[0099] Reference Figure 5 and Figure 6 Each of the pixels PX may include a first emission region EA1 as the emission region of the first sub-pixel SP1, a second emission region EA2 as the emission region of the second sub-pixel SP2, and a third emission region EA3 as the emission region of the third sub-pixel SP3.

[0100] In some embodiments, such as Figure 5 and Figure 6 As shown, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a hexagonal shape formed by six straight lines in the plan view, but this specification is not limited to this. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may have polygonal shapes, circular shapes, elliptical shapes, or irregular shapes other than hexagons in the plan view.

[0101] In some embodiments, such as Figure 5As shown, the maximum length of the third transmission region EA3 in the first direction DR1 can be less than the maximum length of the first transmission region EA1 in the first direction DR1, and less than the maximum length of the second transmission region EA2 in the first direction DR1. The maximum length of the first transmission region EA1 in the first direction DR1 and the maximum length of the second transmission region EA2 in the first direction DR1 can be substantially the same.

[0102] In some embodiments, such as Figure 5 As shown, the maximum length of the third transmission region EA3 in the second direction DR2 can be greater than the maximum length of the first transmission region EA1 in the second direction DR2, and also greater than the maximum length of the second transmission region EA2 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 can be greater than the maximum length of the second transmission region EA2 in the second direction DR2.

[0103] In one or more embodiments, such as Figure 5 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 can be adjacent to each other in the second direction DR2. The first emission region EA1 and the third emission region EA3 can be adjacent to each other in the first direction DR1. The second emission region EA2 and the third emission region EA3 can be adjacent to each other in the first direction DR1. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be different.

[0104] In one or more other embodiments, such as Figure 6 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1, but the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the first diagonal direction DD1, and the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the second diagonal direction DD2.

[0105] In the accompanying drawings, the first oblique direction DD1 intersects each of the first direction DR1 and the second direction DR2, which are horizontal directions. For example, the first oblique direction DD1 may be a direction inclined at approximately 45 degrees relative to the first direction DR1 and the second direction DR2, but the present disclosure is not limited thereto. The second oblique direction DD2 intersects each of the first direction DR1 and the second direction DR2, which are horizontal directions. For example, the second oblique direction DD2 may be a direction inclined at approximately 45 degrees relative to the opposite direction of the first direction DR1 and the second direction DR2, but the present disclosure is not limited thereto. The second oblique direction DD2 may be a direction substantially perpendicular to the first oblique direction DD1.

[0106] The first emission region EA1 can emit light of a first color, the second emission region EA2 can emit light of a second color, and the third emission region EA3 can emit light of a third color. Here, the first color light can be light in the red band, the second color light can be light in the green band, and the third color light can be light in the blue band. For example, the blue band can be a band of light whose main peak wavelength is in the range of approximately 370 nm to approximately 460 nm, the green band can be a band of light whose main peak wavelength is in the range of approximately 480 nm to approximately 560 nm, and the red band is a band of light whose main peak wavelength is in the range of approximately 600 nm to approximately 750 nm.

[0107] exist Figure 5 and Figure 6 The diagram shows each of a plurality of pixels PX comprising three emission regions EA1, EA2, and EA3, but this specification is not limited thereto. That is, each of the plurality of pixels PX may include four or more emission regions.

[0108] Furthermore, the shape and arrangement of the emission regions of multiple pixel PXs are not limited to Figure 5 and Figure 6 The shapes and arrangements shown are illustrated. For example, the emission regions of multiple pixels PX can be positioned as a stripe structure in which the emission regions are arranged in a first direction DR1, or as a PenTile in which the emission regions are arranged in a diamond shape. ® Structure (PenTile) ® (It is a registered trademark of Samsung Display Co., Ltd. of South Korea) or one of them, such as Figure 6 The diagram shows a hexagonal structure with hexagonal emission regions arranged side by side in a plan view.

[0109] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line X1-X1'.

[0110] Reference Figure 7 The display panel 100 may include a display module 110 and a window module 120. The display module 110 may include a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), and an optical layer (OPL).

[0111] A semiconductor backplane (SBP) may include a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) may be referenced... Figure 3 The first transistor T1 to the sixth transistor T6 described (see Figure 3 ).

[0112] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be located on the top surface of the semiconductor substrate SSUB (as used herein, "located on" can mean "above"). The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. For example, when the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. Optionally, when the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity.

[0113] Each of the multiple well regions WA may include a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH located between the source region SA and the drain region DA.

[0114] The lower insulating film (BINS) can be positioned between the gate electrode GE and the well region WA. The side insulating film (SINS) can be positioned on the side surface of the gate electrode GE. The side insulating film (SINS) can also be positioned on the lower insulating film (BINS).

[0115] Each of the source region SA and drain region DA can be a region doped with type I impurities. The gate electrode GE of the pixel transistor PTR can be stacked with the well region WA on the third-direction DR3. The channel region CH can be stacked with the gate electrode GE on the third-direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0116] Each of the multiple well regions WA may further include a first low-concentration impurity region LDD1 located between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 located between the channel region CH and the drain region DA. Due to the lower insulating film BINS, the first low-concentration impurity region LDD1 may be a region with a lower impurity concentration than the source region SA. Due to the lower insulating film BINS, the second low-concentration impurity region LDD2 may be a region with a lower impurity concentration than the drain region DA. The distance between the source region SA and the drain region DA may be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH in each of the pixel transistors PTRs can be increased, thereby reducing or preventing punch-through and hot carrier phenomena that may be caused by short channels.

[0117] The first semiconductor insulating film SINS1 can be positioned on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but this specification is not limited to this.

[0118] The second semiconductor insulating film SINS2 can be positioned on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but this specification is not limited to this.

[0119] Multiple contact terminals (CTEs) can be positioned on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2) to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR). The multiple contact terminals (CTEs) can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them.

[0120] The third semiconductor insulating film (SINS3) can be positioned on the side surface of each of the multiple contact terminals (CTEs). The top surface of each of the multiple contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3). The third semiconductor insulating film (SINS3) can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but this specification is not limited to this.

[0121] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate (such as polyimide). In this case, the thin-film transistor can be positioned on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0122] The backplane (EBP) of the light-emitting element may include multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9.

[0123] The first conductive layer ML1 to the eighth conductive layer ML8 can be used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving Figure 3 The pixel circuit of the first sub-pixel SP1 is shown. For example, the first transistor T1 to the sixth transistor T6 are located only on the semiconductor backplane SBP, and the connection lines between the first transistor T1 to the sixth transistor T6 and the first capacitor CP1 and the second capacitor CP2 can be located in the first conductive layer ML1 to the eighth conductive layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE can also be located in the first conductive layer ML1 to the eighth conductive layer ML8.

[0124] A first insulating film INS1 may be positioned on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first insulating film INS1 to connect to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be positioned on the first insulating film INS1 and may connect to the first via VA1.

[0125] The second insulating film INS2 can be positioned on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 can penetrate the second insulating film INS2 and can be connected to the exposed first conductive layer ML1. Each of the second conductive layers ML2 can be positioned on the second insulating film INS2 and can be connected to the second via VA2.

[0126] The third insulating film INS3 can be positioned on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 can penetrate the third insulating film INS3 and can be connected to the exposed second conductive layer ML2. Each of the third conductive layers ML3 can be positioned on the third insulating film INS3 and can be connected to the third via VA3.

[0127] A fourth insulating film INS4 can be positioned on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 can penetrate the fourth insulating film INS4 and can be connected to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 can be positioned on the fourth insulating film INS4 and can be connected to the fourth via VA4.

[0128] A fifth insulating film INS5 can be positioned on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 can penetrate the fifth insulating film INS5 and can be connected to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 can be positioned on the fifth insulating film INS5 and can be connected to the fifth via VA5.

[0129] The sixth insulating film INS6 can be positioned on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 can penetrate the sixth insulating film INS6 and can be connected to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 can be positioned on the sixth insulating film INS6 and can be connected to the sixth via VA6.

[0130] A seventh insulating film INS7 can be positioned on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 can penetrate the seventh insulating film INS7 and can be connected to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 can be positioned on the seventh insulating film INS7 and can be connected to the seventh via VA7.

[0131] The eighth insulating film INS8 can be positioned on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 can penetrate the eighth insulating film INS8 and can be connected to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 can be positioned on the eighth insulating film INS8 and can be connected to the eighth via VA8.

[0132] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first insulating film INS1 to INS8 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but this specification is not limited to this.

[0133] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately 1360 Å. For example, the thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately 1440 Å. For example, the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be approximately 1150 Å.

[0134] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately 9000 Å, and the thickness of each of the seventh via VA7 and the eighth via VA8 can be approximately 6000 Å.

[0135] The ninth insulating film INS9 can be positioned on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but this specification is not limited to this.

[0136] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 and can connect to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The thickness of the ninth via VA9 can be approximately 16500 Å.

[0137] The display element layer (EML) can be positioned on the light-emitting element backplane (EBP). The EML may include a reflective electrode layer (RL), a tenth insulating film (INS10) and an eleventh insulating film (INS11), a tenth via (VA10), and light-emitting elements (LE) each including a first electrode (AND), a light-emitting stack (IL), and a second electrode (CAT). The EML may also include a pixel-defining film (PDL) and multiple trenches (TRC).

[0138] The reflective electrode layer RL can be positioned on the ninth insulating film INS9. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RL may include, for instance... Figure 7 The first to fourth reflective electrodes RL1, RL2, RL3 and RL4 are shown, but are not limited thereto.

[0139] Each of the first reflective electrodes RL1 can be positioned on the ninth insulating film INS9 and can be connected to the ninth via VA9. The first reflective electrodes RL1 can be formed of any one or an alloy or compound of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the first reflective electrodes RL1 may include titanium nitride (TiN).

[0140] Each of the second reflective electrodes RL2 can be positioned on a corresponding first reflective electrode RL1. The second reflective electrode RL2 can be formed of any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the second reflective electrode RL2 may include aluminum (Al).

[0141] Each of the third reflective electrodes RL3 can be positioned on a corresponding second reflective electrode RL2. The third reflective electrode RL3 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound comprising any one of them. For example, the third reflective electrode RL3 may comprise titanium nitride (TiN).

[0142] Each of the fourth reflective electrodes RL4 can be positioned on the corresponding third reflective electrode RL3. The fourth reflective electrode RL4 can be formed of any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0143] Because the second reflective electrode RL2 is the electrode that essentially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately 100 Å, and the thickness of the second reflective electrode RL2 can be approximately 850 Å.

[0144] The tenth insulating film INS10 can be positioned on the ninth insulating film INS9. The tenth insulating film INS10 can be positioned between adjacent reflective electrode layers RL along the horizontal direction. The tenth insulating film INS10 can be made of silicon oxide (SiO2). x( ) type inorganic film formation, but this specification is not limited thereto. In some embodiments, the tenth insulating film INS10 may be positioned not only between the reflective electrode layers RL, but also on the reflective electrode layers RL.

[0145] The eleventh insulating film INS11 can be positioned on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 can be made of silicon oxide (SiO2). x ( ) Inorganic film formation, but this specification is not limited to this. The tenth insulating film INS10 and the eleventh insulating film INS11 can be optical auxiliary layers through which light emitted from the light-emitting element LE is reflected by the reflective electrode layer RL.

[0146] In some embodiments, in order to adjust the resonant distance of the light emitted from the light-emitting element LE, the total thickness of the insulating film positioned between the first electrode AND and the reflective electrode layer RL may be different in at least one of the first sub-pixels SP1, SP2 and SP3.

[0147] In one or more embodiments, as shown in the accompanying drawings, when the tenth insulating film INS10 is not positioned between the first electrode AND and the reflective electrode layer RL, but the eleventh insulating film INS11 is positioned between the first electrode AND and the reflective electrode layer RL, the thickness of the eleventh insulating film INS11 positioned in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be different. For example, the thickness of the eleventh insulating film INS11 positioned in the first sub-pixel SP1 can be less than the thickness of the eleventh insulating film INS11 positioned in the second sub-pixel SP2, and the thickness of the eleventh insulating film INS11 positioned in the second sub-pixel SP2 can be less than the thickness of the eleventh insulating film INS11 positioned in the third sub-pixel SP3.

[0148] In one or more other embodiments, in the first sub-pixel SP1, the tenth insulating film INS10 and the eleventh insulating film INS11 may not be positioned between the first electrode AND and the reflective electrode layer RL; in the second sub-pixel SP2, either the tenth insulating film INS10 or the eleventh insulating film INS11 may be positioned between the first electrode AND and the reflective electrode layer RL; and in the third sub-pixel SP3, both the tenth insulating film INS10 and the eleventh insulating film INS11 may be positioned between the first electrode AND and the reflective electrode layer RL.

[0149] In one or more other embodiments, the twelfth insulating film may be further positioned between the first electrode AND and the reflective electrode layer RL. In this case, in the first sub-pixel SP1, any one of the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be positioned between the first electrode AND and the reflective electrode layer RL; in the second sub-pixel SP2, any two of the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be positioned between the first electrode AND and the reflective electrode layer RL; and in the third sub-pixel SP3, all of the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be positioned between the first electrode AND and the reflective electrode layer RL.

[0150] In summary, the distance between the first electrode AND and the reflective electrode layer RL can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the dominant wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence / absence or thickness of the tenth insulating film INS10 and the eleventh insulating film INS11 can be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0151] Although the accompanying drawings show that the total thickness of the insulating film positioned between the first electrode AND and the reflective electrode layer RL increases in the order of first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3, this disclosure is not limited thereto. That is, it is shown that the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, and it is shown that the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, this disclosure is not limited thereto. The dimensional relationship of the total thickness of the insulating film positioned between the first electrode AND and the reflective electrode layer RL in each of the first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3 can vary depending on the resonant distance.

[0152] Each of the tenth vias VA10 can be connected to the reflective electrode layer RL exposed through the tenth insulating film INS10 and / or the eleventh insulating film INS11. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. The thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the third sub-pixel SP3, and the thickness of the tenth via VA10 in the first sub-pixel SP1 can be less than the thickness of the tenth via VA10 in the second sub-pixel SP2, but this disclosure is not limited thereto.

[0153] The first electrode AND of each of the light-emitting elements LE can be positioned on the eleventh insulating film INS11 and can be connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR via the tenth via VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound comprising any one of them. For example, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0154] A pixel-defining film (PDL) can be positioned on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can be used to separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0155] The first emission region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0156] The pixel-defining film (PDL) may include first pixel-defining films to third pixel-defining films PDL1, PDL2, and PDL3. The first pixel-defining film PDL1 may be positioned on the edge of the first electrode AND of each of the light-emitting elements (LEs), the second pixel-defining film PDL2 may be positioned on the first pixel-defining film PDL1, and the third pixel-defining film PDL3 may be positioned on the second pixel-defining film PDL2. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 may be made of silicon oxide (SiO2). x The inorganic layer is formed, but this specification is not limited to this. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may each have a thickness of approximately 500 Å.

[0157] When the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 form a single pixel defining film, the height of this single pixel defining film increases, making the first encapsulating inorganic film TFE1 potentially cut due to step coverage. Step coverage refers to the ratio of the degree to which the film is coated on the inclined portion to the degree to which it is coated on the flat portion. The lower the step coverage, the higher the likelihood that the film will be cut at the inclined portion.

[0158] Therefore, to reduce or prevent the possibility of the first encapsulated inorganic film TFE1 being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 can have a cross-sectional structure with stepped portions. For example, the width of the first pixel defining film PDL1 can be greater than the width of the second pixel defining film PDL2 and the width of the third pixel defining film PDL3, and the width of the second pixel defining film PDL2 can be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1, the width of the second pixel defining film PDL2, and the width of the third pixel defining film PDL3 refer to the length in the horizontal direction that is substantially perpendicular to the third direction DR3.

[0159] Each of the plurality of trench TRCs can penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. Furthermore, each of the plurality of trench TRCs can penetrate the eleventh insulating film INS11. The eleventh insulating film INS11 can be partially recessed at each of the plurality of trench TRCs.

[0160] At least one trench TRC can be located between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 7 Two trench TRCs are shown positioned between adjacent sub-pixels SP1, SP2, and SP3, but this specification is not limited thereto.

[0161] The light-emitting stack (IL) can include multiple intermediate layers. Figure 7 The illustration shows a light-emitting stack IL with a triple-tandem structure including a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but this specification is not limited thereto. For example, the light-emitting stack IL may have a double-tandem structure including two intermediate layers.

[0162] In a three-stage cascade structure, the light-emitting stack IL can have a cascade structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different colors of light. For example, the light-emitting stack IL may include a first stacked layer IL1 that emits light of a first color, a second stacked layer IL2 that emits light of a third color, and a third stacked layer IL3 that emits light of a second color. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0163] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0164] A first charge-generating layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be positioned between the first stacked layer IL1 and the second stacked layer IL2. The first charge-generating layer may include an N-type charge-generating layer for supplying electrons to the first stacked layer IL1 and a P-type charge-generating layer for supplying holes to the second stacked layer IL2. The N-type charge-generating layer may include a dopant of a metallic material.

[0165] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be positioned between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0166] A first stacked layer IL1 can be positioned on the first electrode AND and the pixel defining film PDL, and can be positioned on the bottom surface of each trench TRC. Due to the trench TRC, the first stacked layer IL1 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 can be positioned on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS or empty space can be positioned between the first stacked layer IL1 and the second stacked layer IL2. A third stacked layer IL3 can be positioned on the second stacked layer IL2. The third stacked layer IL3 is not cut by the trench TRC and can be positioned to cover the second stacked layer IL2 in each of the trench TRCs. That is, in a three-in-a-row structure, each of the plurality of trench TRCs can be a structure for cutting the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer, and the second charge generation layer between the display element layers EML of adjacent sub-pixels SP1, SP2, and SP3. Additionally, in the dual-series structure, each of the trench TRCs can be a structure used to cut off the charge-generating layer and the lower intermediate layer located between the lower intermediate layer and the upper intermediate layer.

[0167] To stably cut the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. Other structures can exist to replace the trench TRCs in order to cut the first to third stacked layers IL1, IL2, and IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. For example, instead of trench TRCs, inverted conical partition walls can be positioned on the pixel defining film PDL.

[0168] The number of stacked layers IL1, IL2, and IL3 that emit different light is not limited to Figure 7 The quantities shown are as described. For example, the light-emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first stack layer IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge-generating layer for supplying electrons to one intermediate layer and holes to the other intermediate layer may be positioned between the two intermediate layers.

[0169] in addition, Figure 7The diagram shows that all three stacked layers IL1, IL2, and IL3 are located within the first emission region EA1, the second emission region EA2, and the third emission region EA3; however, this specification is not limited to this. For example, the first stacked layer IL1 can be located within the first emission region EA1 and can be omitted from the second emission region EA2 and the third emission region EA3. Similarly, the second stacked layer IL2 can be located within the second emission region EA2 and can be omitted from the first emission region EA1 and the third emission region EA3. Furthermore, the third stacked layer IL3 can be located within the third emission region EA3 and can be omitted from both the first emission region EA1 and the second emission region EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layers OPL can be omitted.

[0170] The second electrode CAT can be positioned on the third stacked layer IL3. The second electrode CAT can be positioned on the third stacked layer IL3 in each of the multiple trench TRCs. The second electrode CAT can be formed of a transparent conductive material (TCO) that can transmit light (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, the luminous efficiency can be improved in each of the first to third sub-pixels SP1, SP2, and SP3 due to the microcavity effect.

[0171] The encapsulation layer TFE can be positioned on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 and TFE2 to reduce or prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0172] The first encapsulating inorganic film TFE1 can be positioned on the second electrode CAT. The first encapsulating inorganic film TFE1 can be formed in which silicon nitride (SiN) is selected. x ), silicon oxynitride (SiON) and silicon oxide (SiO) x A multilayer of one or more inorganic films alternately stacked. The first encapsulating inorganic film TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0173] The second encapsulating inorganic film TFE2 can be positioned on top of the first encapsulating inorganic film TFE1. The second encapsulating inorganic film TFE2 can be made of titanium oxide (TiO2). x ) or aluminum oxide (AlO x The second encapsulation inorganic film TFE2 can be formed by atomic layer deposition (ALD). The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0174] The display panel 100 may also include an organic film APL. The organic film APL may be a layer used to increase the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic film APL may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0175] The optical layer OPL may include multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may be positioned on the organic film APL.

[0176] A first color filter CF1 may be superimposed on a first emission region EA1 of a first sub-pixel SP1. The first color filter CF1 may transmit light of a first color (e.g., light in the red band). The red band may be approximately 600 nm to approximately 750 nm. Therefore, the first color filter CF1 may transmit light of the first color emitted from the first emission region EA1.

[0177] The second color filter CF2 can be superimposed on the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color (e.g., light in the green band). The green band can be approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0178] The third color filter CF3 can be superimposed on the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of a third color (e.g., light in the blue band). The blue band can be approximately 370 nm to approximately 460 nm. Therefore, the third color filter CF3 can transmit light of a third color emitted from the third emission region EA3.

[0179] Multiple lenses LNS can be positioned on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the multiple lenses LNS can be a structure for increasing the proportion of light directed to the front of the display device 10. Each of the multiple lenses LNS can have a profile shape that convexes in the upward direction.

[0180] The filler layer (FIL) can be positioned on multiple lens lenses (LNS). The filler layer (FIL) can have a refractive index (e.g., a predetermined refractive index) such that light travels in the third direction (DR3) at the interface between the filler layer (FIL) and the multiple lens lenses (LNS). Furthermore, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0181] Window module 120 can be positioned on the filler layer FIL. Window module 120 can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to attach window module 120. Window module 120 can protect display module 110 from external impacts. Window module 120 may include an optical layer and regulate the path and polarization state of light emitted from display module 110.

[0182] In some embodiments, window module 120 may include window 123 comprising a glass substrate or a polymer resin (such as resin) (see Figure 9 ). In window 123 (see Figure 9 In the case of a glass substrate, it can be used as an encapsulation substrate. In window 123 (see...) Figure 9 In the case of a polymer resin such as a resin, it can be applied directly onto the filler layer FIL. In some embodiments, the upper surface 120a of the window module 120 may be a curved surface recessed toward the display module 110.

[0183] The window module 120 and the optical module 800 will be described below.

[0184] Figure 8 and Figure 9 It is a cross-sectional view of a display device according to one or more embodiments.

[0185] Reference Figure 8 and Figure 9 The display panel 100 may include a display module 110 and a window module 120. The display module 110 has already been described above, so its description will be omitted. The optical module 800 may include a first optical module 810 and a second optical module 820. The first optical module 810 may be positioned on the display module 110, and the second optical module 820 may be positioned on the first optical module 810.

[0186] In some embodiments, the display module 110 and the first optical module 810 may be separated from each other, and the first optical module 810 and the second optical module 820 may be separated from each other. Air may be filled between the display module 110 and the first optical module 810, and between the first optical module 810 and the second optical module 820.

[0187] Window module 120 may include a first polarizing film 121, a first phase retardation film 122, a window 123, and a semi-transparent reflective film 124. First optical module 810 may include a first lens 811, a first coating film AR1, and a second coating film AR2. Second optical module 820 may include a second phase retardation film 821, a second polarizing film 822, a second lens 823, a third coating film AR3, and a fourth coating film AR4.

[0188] The first polarizing film 121 may be positioned on the display module 110. For example, the first polarizing film 121 may be positioned on the fill layer FIL of the display module 110. The first polarizing film 121 may have a first polarization axis extending in one direction. The first polarizing film 121 may be a linear polarizing film. The first polarizing film 121 may linearly polarize light in the direction of the first polarization axis. For example, the first polarizing film 121 may allow light vibrating in a direction parallel to the first polarization axis to pass through, and may block light vibrating in directions other than parallel to the first polarization axis. In one or more embodiments, the thickness TH_121 of the first polarizing film 121 may be approximately 100 μm to approximately 300 μm.

[0189] In one or more embodiments, the first polarizing film 121 may be an absorptive polarizing film. In this case, the first polarizing film 121 allows light vibrating in a direction parallel to the first polarization axis to pass through, and can absorb light vibrating in a direction not parallel to the first polarization axis.

[0190] A first phase retardation film 122 may be positioned on the first polarizing film 121. The first phase retardation film 122 can delay the phase of light passing through it. When linearly polarized light passes through the first phase retardation film 122, it can be circularly polarized or elliptically polarized; when circularly polarized or elliptically polarized light passes through the first phase retardation film 122, it can be linearly polarized. In one or more embodiments, the first phase retardation film 122 may be a quarter-wave plate (λ / 4 plate). In one or more embodiments, the thickness TH_122 of the first phase retardation film 122 may be approximately 100 μm to approximately 300 μm.

[0191] Window 123 may be positioned on the first phase retardation film 122. Window 123 may protect the display module 110 from external impacts. As described above, window 123 may include a glass substrate or a polymer resin (such as resin). Window 123 may include a first surface 123a positioned on the user-facing side of the light-emitting surface and a second surface 123b positioned on one side of the display module 110 as the opposite side of the first surface 123a. A semi-transmissive reflective film 124 may be positioned on the first surface 123a of window 123, and the first phase retardation film 122 and the first polarizing film 121 may be positioned on the second surface 123b of window 123.

[0192] In some embodiments, the first surface 123a of the window 123 may be a curved surface recessed toward the display module 110. The radius of curvature of the first surface 123a may be approximately 100 mm or greater, but is not limited thereto. Since the first surface 123a of the window 123 is a curved surface, the upper and lower surfaces of the transflective film 124 positioned on the first surface 123a of the window 123 may be curved.

[0193] In one or more embodiments, the thickness TH_123 of window 123 may be approximately 2 mm. The thickness TH_123 of window 123 may refer to the thickness from a point on the second surface 123b in a direction substantially perpendicular to the second surface 123b, and may refer to the average thickness of the entire portion.

[0194] A semi-transmissive reflective film 124 can be positioned on window 123. The semi-transmissive reflective film 124 can transmit a portion of the light and reflect the remainder. Light transmitted through the semi-transmissive reflective film 124 can be transmitted without changing its phase. Light reflected from the semi-transmissive reflective film 124 can be reflected with its phase reversed. For example, left-handed circularly polarized light can be reflected from the semi-transmissive reflective film 124 to become right-handed circularly polarized light, and right-handed circularly polarized light can be reflected from the semi-transmissive reflective film 124 to become left-handed circularly polarized light.

[0195] In some embodiments, the transflective film 124 can be formed by a deposition process. For example, the transflective film 124 can be formed by depositing silicon oxide (SiO2) on the window 123. x ) and titanium dioxide (TiO2) x A film formed by at least one of the following. In some embodiments, the semi-transparent reflective film 124 may have a multilayer structure in which multiple layers are stacked. Referring later... Figure 11 Describe the detailed structure of the semi-transparent reflective film 124.

[0196] The transflective film 124 may include a first surface 124a positioned on the user-facing side of the light-emitting surface and a second surface 124b positioned on one side of the display module 110, which is the opposite side of the first surface 124a. In some embodiments, the first surface 124a and the second surface 124b of the transflective film 124 may be curved surfaces recessed toward the display module 110. The transflective film 124 may be conformally formed according to the shape of the first surface 123a of the window 123. Since the first surface 124a of the transflective film 124 is curved, the viewing angle and magnification can be increased. Therefore, the number of components in the optical module 800 can be reduced and the thickness of the display device 10 can be reduced.

[0197] The first lens 811 can be positioned on the semi-transparent reflective film 124. The first lens 811 can be arranged to be separated from the semi-transparent reflective film 124. The first lens 811 can magnify the image formed by light generated from the display module 110. Lenses of various shapes, such as convex lenses, meniscus lenses, and Fresnel lenses, can be used as the first lens 811, and the shape of the first lens 811 is not limited. In one or more embodiments, the thickness TH_811 of the first lens 811 can be approximately 5 mm to approximately 20 mm. For example, the thickness TH_811 of the first lens 811 can be approximately 7 mm to approximately 15 mm.

[0198] The first coating AR1 can be positioned on one surface of the first lens 811. For example, the first coating AR1 can be positioned on the lower surface of the first lens 811. The first coating AR1 can be positioned between the first lens 811 and the window module 120. The first coating AR1 can be an anti-reflective layer. The first coating AR1 can be formed of an anti-reflective coating. The first coating AR1 can reduce or prevent the reflection of light incident on the incident surface of the first optical module 810 (e.g., the lower surface of the first lens 811). Therefore, the light output rate can be improved, and the occurrence of stray light can be reduced or minimized.

[0199] The second coating AR2 can be positioned on another surface of the first lens 811. For example, the second coating AR2 can be positioned on the upper surface of the first lens 811. The second coating AR2 can be positioned between the first lens 811 and the second optical module 820. The second coating AR2 can be an anti-reflection layer. The second coating AR2 can be formed of an anti-reflection coating. The second coating AR2 can reduce or prevent the reflection of light incident on the incident surface of the first optical module 810 (e.g., the upper surface of the first lens 811). Therefore, the light output rate can be improved, and the occurrence of stray light can be reduced or minimized.

[0200] A second phase retardation film 821 may be positioned on the first lens 811. The second phase retardation film 821 can delay the phase of light passing through it. When linearly polarized light passes through the second phase retardation film 821, it can be circularly polarized or elliptically polarized; when circularly polarized or elliptically polarized light passes through the second phase retardation film 821, it can be linearly polarized. In one or more embodiments, the second phase retardation film 821 may be a quarter-wave plate (λ / 4 plate). In one or more embodiments, the thickness TH_821 of the second phase retardation film 821 may be approximately 100 μm to approximately 300 μm.

[0201] The second polarizing film 822 can be positioned on the second phase retardation film 821. The second polarizing film 822 can have a second polarization axis extending in one direction. The second polarizing film 822 can be a linear polarizing film. The second polarizing film 822 can linearly polarize light in the direction of the second polarization axis. For example, the second polarizing film 822 can allow light vibrating in a direction parallel to the second polarization axis to pass through, and can block light vibrating in directions other than parallel to the second polarization axis. In one or more embodiments, the thickness TH_822 of the second polarizing film 822 can be approximately 100 μm to approximately 300 μm.

[0202] In one or more embodiments, the second polarizing film 822 may be a reflective polarizing film. In this case, the second polarizing film 822 allows light vibrating in a direction parallel to the second polarization axis to pass through, and reflects light vibrating in a direction not parallel to the second polarization axis.

[0203] The second lens 823 can magnify the image formed by the light generated from the display module 110. Lenses of various shapes, such as convex lenses, meniscus lenses, and Fresnel lenses, can be used as the second lens 823, and the shape of the second lens 823 is not limited. The second lens 823 may include the same lens as the first lens 811 or a lens of a different type. In one or more embodiments, the thickness TH_823 of the second lens 823 may be approximately 1 mm to approximately 15 mm. For example, the thickness TH_823 of the second lens 823 may be approximately 3 mm to approximately 10 mm.

[0204] The third coating AR3 can be positioned on one surface of the second lens 823. For example, the third coating AR3 can be positioned on the lower surface of the second lens 823. The third coating AR3 can be positioned between the first optical module 810 and the second lens 823. The third coating AR3 can be an anti-reflection layer. The third coating AR3 can be formed of an anti-reflection coating. The third coating AR3 can reduce or prevent the reflection of light incident on the incident surface of the second optical module 820 (e.g., the lower surface of the second phase retardation film 821). Therefore, the light output rate can be improved, and the occurrence of stray light can be reduced or minimized.

[0205] The fourth coating AR4 can be positioned on another surface of the second lens 823. For example, the fourth coating AR4 can be positioned on the upper surface of the second lens 823. The fourth coating AR4 can be an anti-reflective layer. The fourth coating AR4 can be formed of an anti-reflective coating. The fourth coating AR4 can reduce or prevent the reflection of light incident from the outside onto the light-emitting surface of the display device 10 (e.g., the upper surface of the second lens 823). Therefore, external reflection can be reduced or minimized, and visibility can be improved.

[0206] In some embodiments, depending on the degree of improvement in the transmittance and reflectance of each component, at least one of the first to fourth coating films AR1, AR2, AR3 and AR4 may be omitted.

[0207] The first polarization axis of the first polarizing film 121 and the second polarization axis of the second polarizing film 822 can be substantially perpendicular to each other. For example, when the first polarization axis extends in the third direction DR3 as the vertical direction, the second polarization axis can extend in the horizontal direction substantially perpendicular to the third direction DR3.

[0208] The first phase retardation film 122 may have a first optical axis. The first optical axis of the first phase retardation film 122 may be offset from the first polarization axis of the first polarization film 121 and / or the second polarization axis of the second polarization film 822 by an angle greater than 0 degrees and less than about 90 degrees. In one or more embodiments, the first optical axis may be offset by approximately 45 degrees relative to the first polarization axis and / or the second polarization axis, but this disclosure is not limited thereto.

[0209] The second phase retardation film 821 may have a second optical axis. The second optical axis of the second phase retardation film 821 may be offset from the first polarization axis of the first polarization film 121 and / or the second polarization axis of the second polarization film 822 by an angle greater than 0 degrees and less than about 90 degrees. In one or more embodiments, the second optical axis may be offset by approximately 45 degrees relative to the first polarization axis and / or the second polarization axis, but this disclosure is not limited thereto.

[0210] The direction in which the first optical axis of the first phase retardation film 122 is offset relative to the first polarization axis and / or the second polarization axis may be opposite to the direction in which the second optical axis of the second phase retardation film 821 is offset relative to the first polarization axis and / or the second polarization axis. For example, the first phase retardation film 122 may be offset by approximately -45 degrees relative to the first polarization axis and / or the second polarization axis, and the second phase retardation film 821 may be offset by approximately +45 degrees relative to the first polarization axis and / or the second polarization axis. Optionally, the first phase retardation film 122 may be offset by +45 degrees relative to the first polarization axis and / or the second polarization axis, and the second phase retardation film 821 may be offset by approximately -45 degrees relative to the first polarization axis and / or the second polarization axis.

[0211] The phase delay direction of light passing through the first phase retardation film 122 may be different from the phase delay direction of light passing through the second phase retardation film 821. For example, light passing through the first phase retardation film 122 may be delayed by -λ / 4, and light passing through the second phase retardation film 821 may be delayed by +λ / 4.

[0212] As described above, the display module 110 and the first optical module 810 can be separated from each other, and the first optical module 810 and the second optical module 820 can be separated from each other. For example, the distance D1 between the first lens 811 and the semi-transparent reflective film 124 can be approximately 0.5 mm or greater, and the distance D2 between the first lens 811 and the second lens 823 can be approximately 0.3 mm or greater. The distance D1 between the first lens 811 and the semi-transparent reflective film 124 refers to the shortest distance between the first lens 811 and the semi-transparent reflective film 124, and the distance D2 between the first lens 811 and the second lens 823 refers to the shortest distance between the first lens 811 and the second lens 823.

[0213] The display device 10 includes a window module 120 and an optical module 800, thereby realizing a folded optical device with a folded optical path. Therefore, the total track length, which is the total length of the optical path, can be increased, and the thickness of the display device 10 can be reduced or minimized.

[0214] Furthermore, since optical elements such as the first polarizing film 121, the first phase retardation film 122, and the semi-transmissive reflective film 124, which are part of the folded optical structure, are mounted on the window module 120 together with the window 123, the number of components located in the optical module 800 can be reduced or minimized.

[0215] For example, if a separate optical element with the same function as the semi-transparent reflective film 124 is placed between the first optical module 810 and the window 123, the thickness of the separate optical element itself and additional space for positioning the separate optical element may be required.

[0216] On the other hand, in the display device 10, the thickness of the optical module 800 and the thickness of the display device 10 can be reduced or minimized by directly mounting the semi-transparent reflective film 124 on the upper surface of the window 123. Additionally, the light output rate can be improved by reducing the number of optical elements.

[0217] In the following text, reference will be made to Figure 10 Describe the path and polarization state of light moving through the folded optics of the display device 10.

[0218] Figure 10 This is a schematic diagram used to explain the path and polarization state of light emitted from a display device according to one or more embodiments.

[0219] Reference Figure 10 The diagram shows that the first polarization axis of the first polarizing film 121 extends in the vertical direction, and the second polarization axis of the second polarizing film 822 extends in the horizontal direction. Furthermore, it shows that the first polarizing film 121 is an absorptive polarizing film, and the second polarizing film 822 is a reflective polarizing film. Additionally, it shows that the first optical axis of the first phase retardation film 122 is offset by approximately -45 degrees relative to the vertical direction, and the second optical axis of the second phase retardation film 821 is offset by approximately +45 degrees relative to the vertical direction.

[0220] The light emitted from the display module 110 can be unpolarized light①.

[0221] Unpolarized light ① can pass through a first polarizing film 121 having a first polarization axis in the vertical direction, and can be converted into vertically polarized light ② that vibrates in the vertical direction.

[0222] Vertically polarized light ② passing through the first polarizing film 121 can pass through the first phase retardation film 122 having a first optical axis offset by about -45 degrees relative to the vertical direction, and can be converted into left-hand circularly polarized light ③.

[0223] Some of the left-handed circularly polarized light ③ that passes through the first phase retardation film 122 can pass through the semi-transparent reflective film 124. The left-handed circularly polarized light ③ that passes through the semi-transparent reflective film 124 can have the same polarization state as the left-handed circularly polarized light ③ that passes through the first phase retardation film 122 without changing its polarization state. Although in Figure 10 Not shown, but other portions of the left-handed circularly polarized light ③ that passes through the first phase retardation film 122 can be reflected on the semi-transparent reflective film 124.

[0224] Left-handed circularly polarized light ③ passing through the semi-transparent reflective film 124 can be magnified when it passes through the first lens 811. Left-handed circularly polarized light ④ passing through the first lens 811 can have the same polarization state as the left-handed circularly polarized light ③ passing through the semi-transparent reflective film 124 without changing its polarization state.

[0225] Left-handed circularly polarized light ④ passing through the first lens 811 can pass through the second phase retardation film 821, which has a second optical axis offset by about +45 degrees relative to the vertical direction, and can be converted back into vertically polarized light ⑤.

[0226] Because the vertically polarized light ⑤ passing through the second phase retardation film 821 is polarized in a direction different from the second polarization axis in the vertical direction, it can be reflected from the second polarization film 822. The vertically polarized light ⑥ reflected from the second polarization film 822 can have the same polarization state as the vertically polarized light ⑤ passing through the second phase retardation film 821 without changing its polarization state.

[0227] Vertically polarized light ⑥ reflected from the second polarizing film 822 can pass through the second phase retardation film 821, which has a second optical axis offset by approximately +45 degrees relative to the vertical direction, and can be converted into left-handed circularly polarized light ⑦. When passing through the first phase retardation film 122, the vertically polarized light ② passing through the first polarizing film 121 passes through the first phase retardation film 122, which has a first optical axis offset by approximately -45 degrees relative to the vertical direction, in the third direction DR3, thereby being converted into left-handed circularly polarized light ③. However, when passing through the first phase retardation film 122, the vertically polarized light ⑥ reflected from the second polarizing film 822 passes through the second phase retardation film 821, which has a second optical axis offset by approximately +45 degrees relative to the vertical direction, in the opposite direction of the third direction DR3, thereby being converted into left-handed circularly polarized light ⑦.

[0228] Left-handed circularly polarized light ⑦ passing through the second phase retardation film 821 can pass through the first lens 811 and the image can be magnified. Left-handed circularly polarized light ⑦ passing through the first lens 811 can have the same polarization state as left-handed circularly polarized light ⑦ passing through the second phase retardation film 821 without changing its polarization state.

[0229] Some of the left-handed circularly polarized light ⑦ passing through the first lens 811 can be reflected by the semi-transparent reflective film 124 and can be converted into right-handed circularly polarized light ⑧ through the left-right reversal effect.

[0230] Right-handed circularly polarized light ⑧ reflected from the semi-transparent reflective film 124 can pass through the first lens 811, and the image can be magnified. The right-handed circularly polarized light ⑧ passing through the first lens 811 can have the same polarization state as the right-handed circularly polarized light ⑧ reflected from the semi-transparent reflective film 124 without changing its polarization state.

[0231] Some of the right-hand circularly polarized light ⑧ passing through the first lens 811 can pass through the second phase retardation film 821, which has a second optical axis offset by about +45 degrees relative to the vertical direction, and can be converted into horizontally polarized light ⑨.

[0232] Because the horizontally polarized light ⑨ passing through the second phase retardation film 821 is polarized in the same direction as the second polarization axis in the horizontal direction, it can pass through the second polarization film 822. The horizontally polarized light ⑨ passing through the second polarization film 822 can have the same polarization state as the horizontally polarized light ⑨ passing through the second phase retardation film 821 without changing its polarization state.

[0233] Horizontally polarized light ⑨ passing through the second polarizing film 822 can pass through the second lens 823, and the image can be magnified. Horizontally polarized light ⑩ passing through the second lens 823 can have the same polarization state as the horizontally polarized light ⑨ passing through the second polarizing film 822 without changing its polarization state. Horizontally polarized light ⑩ passing through the second lens 823 can be provided to the user.

[0234] The display device 10 includes folded optics that allow light to pass through two lenses four times, thereby increasing the frequency of image magnification and increasing the degree of image magnification by increasing the optical path. Therefore, the thickness of the display device 10 is reduced, but a further magnified image can be obtained.

[0235] Figure 11 This is a cross-sectional view showing a stacked structure of a translucent reflective film according to one or more embodiments.

[0236] Reference Figure 11 The semi-transparent reflective film 124 may have a multilayer structure in which multiple layers are stacked. The semi-transparent reflective film 124 may have a structure in which a first material layer and a second material layer are alternately stacked. The first material layer may include silicon oxide, and the second material layer may include titanium oxide. For example, the first material layer may include Si. x O y (x and y are natural numbers), the second material layer may include Ti x O y (x and y are natural numbers). The semi-transparent reflective film 124 can be formed by a deposition process, but is not limited to this.

[0237] The first material layer may have a lower refractive index than the second material layer. For example, the refractive index of the first material layer may be approximately 1.91 to approximately 1.93, and the refractive index of the second material layer may be approximately 3.45 to approximately 3.47. In this specification, the refractive indices of the first and second material layers refer to values ​​measured at 20°C and 1 atm using light with a peak wavelength of approximately 550 nm.

[0238] For example, the semi-transparent reflective film 124 may include a first layer 124_1 to an eleventh layer 124_11. The first layer 124_1, the third layer 124_3, the fifth layer 124_5, the seventh layer 124_7, the ninth layer 124_9, and the eleventh layer 124_11 will be composed of a first material layer. The second layer 124_2, the fourth layer 124_4, the sixth layer 124_6, the eighth layer 124_8, and the tenth layer 124_10 may be composed of a second material layer.

[0239] The thickness of the first layer 124_1, THa_1, can be approximately 58 nm to approximately 65 nm. The thickness of the second layer 124_2, THa_2, can be approximately 69 nm to approximately 77 nm. The thickness of the third layer 124_3, THa_3, can be approximately 92 nm to approximately 103 nm. The thickness of the fourth layer 124_4, THa_4, can be approximately 69 nm to approximately 77 nm. The thickness of the fifth layer 124_5, THa_5, can be approximately 99 nm to approximately 111 nm. The thickness of the sixth layer 124_6, THa_6, can be approximately 37 nm to approximately 42 nm. The thickness of the seventh layer 124_7, THa_7, can be approximately 43 nm to approximately 49 nm. The thickness of the eighth layer 124_8, THa_8, can be approximately 48 nm to approximately 54 nm. The thickness of the ninth layer 124_9, THa_9, can be approximately 69 nm to approximately 77 nm. The thickness of the tenth layer 124_10, THa_10, can be approximately 8 nm to approximately 10 nm. The thickness of the eleventh layer 124_11, THa_11, can be approximately 113 nm to approximately 126 nm. The total thickness of the semi-transparent reflective film 124, TH_124, can be approximately 705 nm to approximately 791 nm.

[0240] In the accompanying drawings, the transflective film 124 is shown as having a structure in which a total of eleven layers, including six first material layers and five second material layers, are stacked, but this disclosure is not limited thereto. The number of stacks of the transflective film 124 can vary. For example, the number of stacks of the transflective film 124 can be nine or more. For example, the number of stacks of the first material layers can be five or more, and the number of stacks of the second material layers can be four or more, that is, the number of stacks of the first material layers can be one more than the number of stacks of the second material layers.

[0241] In the display device 10, by directly mounting the semi-transparent reflective film 124 onto the window 123, the number of components located in the optical module 800 can be reduced or minimized. Therefore, the thickness of the display device 10 can be reduced or minimized, and the light output rate can be improved.

[0242] In the following description, other embodiments of the display device according to one or more embodiments will be described. In the following embodiments, the description of components that are the same as those in the above embodiments and are indicated by the same reference numerals will be omitted or simplified, and the differences will be mainly described.

[0243] Figure 12 This is a cross-sectional view showing a display device according to one or more other embodiments.

[0244] Reference Figure 12 , refer to Figure 12 The described display device 10 and reference Figure 9 The difference between the display device 10 described in one or more embodiments is that it also includes a third polarizing film 824.

[0245] For example, the display device 10 may further include a third polarizing film 824. The third polarizing film 824 may be positioned on the second lens 823. For example, the third polarizing film 824 may be positioned between the second lens 823 and the fourth coating film AR4. The third polarizing film 824 may have a third polarization axis extending in one direction. The third polarizing film 824 may be a linear polarizing film. The third polarizing film 824 may linearly polarize light in the direction of the third polarization axis. For example, the third polarizing film 824 may allow light vibrating in a direction parallel to the third polarization axis to pass through, and may block light vibrating in directions other than parallel to the third polarization axis. In one or more embodiments, the thickness TH_824 of the third polarizing film 824 may be approximately 100 μm to approximately 300 μm.

[0246] In one or more embodiments, the third polarizing film 824 may be an absorptive polarizing film. In this case, the third polarizing film 824 allows light vibrating in a direction parallel to the third polarization axis to pass through, and absorbs light vibrating in a direction not parallel to the third polarization axis.

[0247] The third polarization axis of the third polarizing film 824 may extend in a direction parallel to the second polarization axis of the second polarizing film 822. The third polarization axis of the third polarizing film 824 may be substantially perpendicular to the first polarization axis of the first polarizing film 121. For example, if the second polarization axis extends in the third direction DR3, the third polarization axis may extend in the third direction DR3.

[0248] The display device 10 can reduce external reflections by including a third polarizing film 824. In addition, because the third polarizing film 824 blocks stray light that does not vibrate in the same direction as the second polarization axis of the second polarizing film 822, visibility can be improved.

[0249] Figure 13 This is a cross-sectional view showing a display device according to yet another or one other embodiment.

[0250] Combination Figure 10 Reference Figure 13 The display device 10 described here is the same as the one referenced above. Figure 9 The display device 10 of the embodiments described above differs in that it also includes a third phase delay film 125.

[0251] For example, the display device 10 may further include a third phase retardation film 125. The third phase retardation film 125 may be positioned on the display module 110. For example, the third phase retardation film 125 may be positioned between the display module 110 and the first polarizing film 121. The third phase retardation film 125 can delay the phase of light passing through it. When linearly polarized light passes through the third phase retardation film 125, it can be circularly polarized or elliptically polarized; when circularly polarized or elliptically polarized light passes through the third phase retardation film 125, it can be linearly polarized. In one or more embodiments, the third phase retardation film 125 may be a quarter-wave plate (λ / 4 plate). In one or more embodiments, the thickness TH_125 of the third phase retardation film 125 may be approximately 100 μm to approximately 300 μm.

[0252] The third phase retardation film 125 may have a third optical axis. The third optical axis of the third phase retardation film 125 may be offset from the first polarization axis of the first polarization film 121 and / or the second polarization axis of the second polarization film 822 by an angle greater than 0 degrees and less than about 90 degrees. In one or more embodiments, the third optical axis may be offset by approximately 45 degrees relative to the first polarization axis and / or the second polarization axis, but this disclosure is not limited thereto.

[0253] The direction in which the third optical axis of the third phase retardation film 125 is offset relative to the first polarization axis and / or the second polarization axis can be the same as the direction in which either the first optical axis of the first phase retardation film 122 or the second optical axis of the second phase retardation film 821 is offset relative to the first polarization axis and / or the second polarization axis. As an example, the third phase retardation film 125 can be offset relative to the first polarization axis and / or the second polarization axis in a direction of approximately -45 degrees. As another example, the third phase retardation film 125 can be offset relative to the first polarization axis and / or the second polarization axis in a direction of approximately +45 degrees.

[0254] The phase delay direction of light passing through the third phase retardation film 125 can be the same as the phase delay direction of light passing through the first phase retardation film 122 and the phase delay direction of light passing through the second phase retardation film 821. As an example, light passing through the third phase retardation film 125 can be delayed by -λ / 4. As another example, light passing through the third phase retardation film 125 can be delayed by +λ / 4.

[0255] When the display device 10 includes a third phase retardation film 125, visibility can be improved by suppressing the reflection of stray light.

[0256] For example, some of the light emitted from the display module 110 can be reflected by the semi-transparent reflective film 124, or it can pass through the semi-transparent reflective film 124 and move towards the display module 110. Such stray light STL can be linearly polarized in one direction while passing through the first polarizing film 121. The linearly polarized stray light STL can be circularly polarized by passing through the third phase retardation film 125. The circularly polarized stray light STL can be reflected by the display module 110, pass through the third phase retardation film 125 again, and can be linearly polarized in a direction substantially perpendicular to said one direction. Therefore, the linearly polarized stray light STL in a direction substantially perpendicular to the first polarization axis of the first polarizing film 121 can be blocked by the first polarizing film 121 and can not be emitted to the outside. Therefore, the visibility of the display device 10 can be improved.

[0257] Figure 14 This is a cross-sectional view showing a display device according to one or more other embodiments.

[0258] Reference Figure 14 The display device 10 described here is the same as the one referenced above. Figure 9 The display device 10 of the embodiments described above differs in that it also includes a third polarizing film 824 and a third phase retardation film 125.

[0259] For example, the display device 10 may include both a third polarizing film 824 and a third phase retardation film 125. Therefore, as described above, in the display device 10, external reflection can be reduced and visibility can be improved by including the third polarizing film 824, and visibility can be improved by including the third phase retardation film 125.

[0260] Figure 15 This is a perspective view showing a head-mounted display device according to one or more embodiments. Figure 16 It is shown Figure 15 An exploded perspective view of an example of a head-mounted display device.

[0261] Reference Figure 15 and Figure 16 A head-mounted display device 1000 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0262] The first display device 10_1 can provide an image to the user's left eye, and the second display device 10_2 can provide an image to the user's right eye. This is because each of the first display device 10_1 and the second display device 10_2 is combined with... Figures 1 to 14 The display devices 10 described are essentially the same, so the descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0263] The first optical component 1510 may be positioned between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be positioned between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0264] The intermediate frame 1400 can be positioned between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0265] The control circuit board 1600 can be positioned between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data DATA, and can transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via connectors.

[0266] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Optionally, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0267] The display device housing 1100 can accommodate a first display device 10_1, a second display device 10_2, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. The housing cover 1200 can be positioned to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 positioned for the user's left eye and a second eyepiece 1220 positioned for the user's right eye. Figure 15 and Figure 16The first eyepiece 1210 and the second eyepiece 1220 are shown positioned separately, but this specification is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0268] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0269] The headband 1300 can secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned on the user's left and right eyes, respectively. When the display device housing 1100 is made lightweight and compact, the head-mounted display device 1000 can be configured as follows: Figure 17 The eyeglasses frame shown is not the headband 1300.

[0270] Additionally, the head-mounted display device 1000 may also include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, or a Wi-Fi module. ® Module or Bluetooth ® Module (Wi-Fi) ® Bluetooth is a registered trademark of the non-profit Wi-Fi Alliance. ® It is a registered trademark of Bluetooth Sig, Inc., Kirkland, Washington.

[0271] Figure 17 This is a perspective view illustrating a head-mounted display device according to one or more other embodiments.

[0272] Reference Figure 17The head-mounted display device 1000_1 according to one or more other embodiments may be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display device 1000_1 according to one or more other embodiments may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, an optical path conversion component 1070, and a display device housing 1200_1.

[0273] The display device housing 1200_1 can accommodate the display device 10_3, the optical component 1060, and the optical path conversion component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060, and the optical path can be converted by the optical path conversion component 1070 to provide the image to the user's right eye through the right eye lens 1020. As a result, the user can view an augmented reality image that combines the real image displayed on the display device 10_3 and the virtual image seen through the right eye lens 1020 through their right eye.

[0274] Figure 17 The illustration shows the display device housing 1200_1 positioned at the right end of the support frame 1030, but this specification is not limited thereto. For example, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, in which case the image displayed on the display device 10_3 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030, in which case the user can view the image displayed on the display device 10_3 through both the left and right eyes.

[0275] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the aspects of this disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A display device, the display device comprising: A display panel includes a display module and a window module. The window module is located above the display module and includes: a first polarizing film above the display module; a first phase retardation film above the first polarizing film; a window above the first phase retardation film; and a semi-transmissive reflective film above the window. An optical module is located above the display panel and includes: a first optical module including a first lens above the semi-transparent reflective film; and a second optical module including a second phase retardation film above the first lens, a second polarizing film above the second phase retardation film, and a second lens above the second polarizing film.

2. The display device according to claim 1, wherein, The semi-transparent reflective film includes a curved surface.

3. The display device according to claim 2, wherein, The window includes a curved first surface adjacent to the semi-transparent reflective film.

4. The display device according to claim 3, wherein, The radius of curvature of the first surface is 100 mm or greater.

5. The display device according to claim 1, wherein, The first polarizing film and the second polarizing film include linear polarizing films, and The first polarization axis of the first polarizing film is perpendicular to the second polarization axis of the second polarizing film.

6. The display device according to claim 5, wherein, The first polarizing film includes an absorption-type polarizing film, and The second polarizing film includes a reflective polarizing film.

7. The display device according to claim 5, further comprising a third polarizing film, the third polarizing film being above the second lens and having a third polarizing axis extending in a direction parallel to the second polarizing axis.

8. The display device according to claim 7, wherein, The third polarizing film includes an absorption polarizing film.

9. The display device according to claim 1, wherein, The first phase retardation film and the second phase retardation film include quarter-wave plates, and The first optical axis of the first phase retardation film and the second optical axis of the second phase retardation film are offset in opposite directions.

10. The display device according to claim 1, wherein, The first lens and the second lens include magnifying lenses.

11. The display device according to claim 1, wherein, The semi-transparent reflective film comprises multiple layers in which a plurality of first material layers having a first refractive index and a plurality of second material layers having a second refractive index greater than the first refractive index are alternately stacked. The lowest layer among the plurality of layers is one of the plurality of first material layers.

12. The display device according to claim 11, wherein, The number of the plurality of first material layers is greater than the number of the plurality of second material layers.

13. The display device according to claim 12, wherein, The number of the plurality of first material layers is one more than the number of the plurality of second material layers.

14. The display device according to claim 11, wherein, The plurality of first material layers include silicon oxide, and The plurality of second material layers include titanium oxide.

15. The display device according to claim 11, wherein, The number of the multiple layers is nine or more.

16. The display device according to claim 11, wherein, The first refractive index is 1.91 to 1.93, and The second refractive index is 3.45 to 3.

47.

17. The display device according to claim 1, wherein, The window module and the first optical module are separated, and The first optical module and the second optical module are separated.

18. The display device according to claim 1, further comprising a coating film on the surface of the first optical module or the surface of the second optical module.

19. The display device according to claim 1, further comprising a third phase retardation film between the display module and the first polarizing film and including a quarter-wave plate.

20. The display device according to claim 1, wherein, The display panel also includes: Semiconductor substrate; Conductive layers are sequentially stacked on top of the semiconductor substrate; A reflective electrode layer is located above the conductive layer; An insulating film covering at least a portion of the reflective electrode layer; and A light-emitting element is located above the insulating film and includes a first electrode, a light-emitting stack, and a second electrode.

21. An electronic device, the electronic device including a display device, the display device comprising: A display panel includes a display module and a window module. The window module is located above the display module and includes: a first polarizing film above the display module; a first phase retardation film above the first polarizing film; a window above the first phase retardation film; and a semi-transmissive reflective film above the window. An optical module is located above the display panel and includes: a first optical module including a first lens above the semi-transparent reflective film; and a second optical module including a second phase retardation film above the first lens, a second polarizing film above the second phase retardation film, and a second lens above the second polarizing film.

Images