Interconnect overlay with integrated process steps

Abstract

A cluster tool for forming an interconnect structure includes a pre-cleaning chamber; a selective chemical vapor deposition (CVD) chamber; a plasma enhanced CVD (PECVD) chamber; one or more transfer chambers coupled to the pre-cleaning chamber, the selective CVD chamber, and the PECVD chamber, and configured to transfer the interconnect structure between the pre-cleaning chamber, the selective CVD chamber, and the PECVD chamber without disrupting a vacuum environment; and a controller configured such that an exposed surface of a metal layer formed within a first dielectric layer of the interconnect structure is pre-cleaned in the pre-cleaning chamber, selective deposition of a capping layer on the pre-cleaned surface of the metal layer is performed in the selective CVD chamber, and depositing a second dielectric layer on exposed surfaces of the capping layer and the first dielectric layer in the PECVD chamber.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to a method of forming an interconnect structure for semiconductor applications. Background Technology

[0002] As the size of integrated circuit (IC) components in peripheral complementary metal-oxide-semiconductor (CMOS) devices, such as 3D NAND, shrinks (e.g., to submicron dimensions), copper (Cu) wires have been used to replace aluminum (Al) in the fabrication of such components due to their low sheet resistance and high electromigration (EM) resistance. A typical back-end-of-line (BEOL) interconnect consists of copper (Cu) wires encapsulated by a metal overlay to improve EM performance, and a dielectric layer serving as a diffusion barrier.

[0003] Conventionally, dielectric layers (e.g., silicon carbonitride (SiCN)) are deposited in clustering tools different from those used for depositing metal overlays (e.g., cobalt (Co)) onto copper (Cu) interconnects. To reduce oxidation of the metal overlays, wafers can be transported between clustering tools via a nitrogen (N2)-purified front-opening unified pod (FOUP). However, oxidation of the metal overlays cannot be eliminated, and therefore a pre-cleaning process for the metal overlays may be required before dielectric deposition, which can damage the underlying layer. Furthermore, the queuing time of the clustering tools needs to be controlled.

[0004] Therefore, there is a need for methods and systems for forming metal interconnects with metal overlays and dielectric layers in simplified steps without exposing them to the surrounding environment. Summary of the Invention

[0005] Embodiments of this disclosure provide a clustering tool for forming interconnect structures. The clustering tool includes: a pre-cleaning chamber configured to pre-clean exposed surfaces of a metal layer formed within a first dielectric layer of the interconnect structure; a selective chemical vapor deposition (CVD) chamber configured to selectively deposit a capping layer on the pre-cleaned surface of the metal layer; and plasma-enhanced chemical vapor deposition (PVD). The PECVD chamber is configured to deposit a second dielectric layer on the exposed surfaces of the capping layer and the first dielectric layer; one or more transfer chambers are coupled to the pre-cleaning chamber, the selective CVD chamber and the PECVD chamber and are configured to transfer the interconnect structure between the pre-cleaning chamber, the selective CVD chamber and the PECVD chamber without disrupting the vacuum environment; and a controller is configured to perform the pre-cleaning of the metal layer in the pre-cleaning chamber, the selective deposition of the capping layer in the selective CVD chamber and the deposition of the second dielectric layer in the PECVD chamber.

[0006] Embodiments of this disclosure provide a method for forming an interconnect structure. The method includes: performing a pre-cleaning process in a pre-cleaning chamber to remove oxides formed on exposed surfaces of a metal layer formed within a first dielectric layer of the interconnect structure; performing a selective deposition process in a selective chemical vapor deposition (CVD) chamber to deposit a capping layer on the pre-cleaned surface of the metal layer; and performing a capping deposition process in a plasma-enhanced CVD (PECVD) chamber to deposit a second dielectric layer on the exposed surfaces of the capping layer and the first dielectric layer, wherein the pre-cleaning process, the selective deposition process, and the capping deposition process are all performed within a clustering tool without exposure to the surrounding environment outside the clustering tool.

[0007] Embodiments of this disclosure provide a method for forming an interconnect structure. The method includes: performing a selective deposition process in a selective chemical vapor deposition (CVD) chamber to deposit a capping layer on an exposed surface of a metal layer formed within a first dielectric layer of the interconnect structure; and performing a capping deposition process in a plasma-enhanced CVD (PECVD) chamber to deposit a second dielectric layer on the exposed surfaces of the capping layer and the first dielectric layer, wherein both the selective deposition process and the capping deposition process are performed within a clustering tool without exposure to the surrounding environment outside the clustering tool. Attached Figure Description

[0008] To gain a more detailed understanding of the features described above, a more specific description of the present disclosure can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only exemplary embodiments and should not be considered as limiting the scope of the present disclosure, as other equally effective embodiments are permissible.

[0009] Figure 1 This is a schematic top view of a multi-chamber cluster tool according to one or more embodiments of this disclosure.

[0010] Figure 2 The illustration shows a flowchart of a method for manufacturing an interconnect structure according to one embodiment of the present disclosure.

[0011] Figure 3A , Figure 3A '、 Figure 3B , Figure 3B '、 Figure 3C , Figure 3C '、 Figure 3D and Figure 3D 'is with Figure 2 A cross-sectional view of a portion of a semiconductor structure corresponding to various states of the method.

[0012] To facilitate understanding of the embodiments, the same reference numerals are used to denote common elements in the drawings, where possible. Elements and features of one embodiment are contemplated to be advantageously incorporated into other embodiments without further description. Detailed Implementation

[0013] Systems and methods are provided for covering back-end-of-line (BEOL) interconnects (e.g., copper (Cu)) with a metal capping layer (e.g., cobalt (Co)) and a dielectric layer (e.g., silicon carbonitride (SiCN)) integrated in a single cluster tool, without exposing them to the surrounding environment outside the cluster tool. Because exposure to the surrounding environment is eliminated, contamination of the metal capping layer prior to dielectric layer deposition is avoided, which leads to improved adhesion of the dielectric layer to the metal capping layer and consequently, improved time-dependent dielectric breakdown (TDDB) lifetime of the low-dielectric-constant dielectric layer around the interconnects. Furthermore, the use of a metal capping layer (e.g., cobalt (Co)) between the metal layer (e.g., copper (Cu)) and the dielectric layer improves the electromigration (EM) performance of the metal layer.

[0014] Figure 1This is a schematic top view of a multi-chamber cluster tool 100 according to one or more embodiments of this disclosure. The cluster tool 100 typically includes a factory interface 102; load locking chambers 104, 106; a transfer chamber 108; a transfer robot 110 having one or more transfer blades 112 (two shown); and one or more dual-chamber processing systems 114, 116, 118 (three shown), each dual-chamber processing system including two processing chambers 120 and 122, 124 and 126, 128 and 130. Each of the dual-chamber processing systems 114, 116, 118 includes an independent processing volume that can be isolated from each other and can share resources (e.g., processing gas supply, vacuum pump) between the two processing chambers. As detailed herein, the substrate W in the cluster tool 100 can be processed in and transferred between individual chambers without exposing the substrate W to the surrounding environment outside the cluster tool 100 (e.g., the atmospheric environment that may exist in a semiconductor foundry). For example, the substrate W can be processed in and transferred between individual chambers maintained in a low-pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without disrupting the low-pressure or vacuum environment between the various processes performed on the substrate W in the cluster tool 100. Therefore, the cluster tool 100 can provide an integrated solution for some processing of the substrate W.

[0015] Examples of processing systems that can be appropriately modified based on the teachings provided in this article include Centura. ® or Producer ® The integrated processing system or other suitable processing systems are commercially available from Applied Materials, Inc., located in Santa Clara, California. It is conceivable that other processing systems (including those from other manufacturers) may be suitable for benefiting from the aspects described herein.

[0016] exist Figure 1 In the example shown, factory interface 102 includes docking station 132 and factory interface robot 134 to facilitate the transfer of substrate W. Docking station 132 is adapted to accept one or more front-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 typically includes blades 138 disposed at one end of the respective factory interface robot 134, which are adapted to transfer substrate W from factory interface 102 to load-locking chambers 104, 106.

[0017] Load-locking chambers 104 and 106 have corresponding ports 140 and 142 coupled to the factory interface 102, and corresponding ports 144 and 146 coupled to the transfer chamber 108. The transfer chamber 108 further has corresponding ports 148, 150, 152, 154, 156, and 158 coupled to the processing chambers 120, 122, 124, 126, 128, and 130. Ports 144, 146, 148, 150, 152, 154, 156, and 158 may be, for example, slit valve openings with slit valves for passing the substrate W through the transfer robot 110 and for providing a seal between the respective chambers to prevent gas from flowing between them. Generally, any port is open for transferring the substrate through that port. Otherwise, the port is closed.

[0018] Load locking chambers 104, 106, transfer chamber 108, and processing chambers 120, 122, 124, 126, 128, 130 can be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryogenic pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to each chamber. In operation, the factory interface robot 134 transfers a substrate from FOUP 136 through port 140 or 142 to load locking chambers 104 or 106. The gas and pressure control system then evacuates load locking chambers 104 or 106. The gas and pressure control system further maintains a low-pressure or vacuum environment (which may include an inert gas) inside transfer chamber 108. Therefore, evacuation of load locking chambers 104 or 106 facilitates substrate transfer between the atmospheric environment of, for example, factory interface 102 and the low-pressure or vacuum environment of transfer chamber 108.

[0019] When the substrate is in a evacuated load-locking chamber 104 or 106, the transfer robot 110 transfers the substrate from the load-locking chamber 104 or 106 to the transfer chamber 108 via port 144 or 146. The transfer robot 110 can then transfer the substrate via corresponding ports 148, 150, 152, 154, 156, 158 to any of the processing chambers 120, 122, 124, 126, 128, 130 and / or between any of these processing chambers for processing. The transfer of the substrate within and between the various chambers can be carried out in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0020] Processing chambers 120, 122, 124, 126, 128, and 130 can be any suitable chamber for processing a substrate. In some examples, processing chamber 120 can be used to perform etching processes, processing chamber 122 can be used to perform cleaning processes, and processing chambers 124, 126, 128, and 130 can be used to perform deposition processes. Processing chamber 120 can be a Selectra type available from Applied Materials Inc. in Santa Clara, California. ™ Etching chamber. Processing chamber 122 may be an Aktiv™ pre-cleaning (APC) chamber available from Applied Materials, Santa Clara, California. Processing chambers 124 and 126 may be Volta [equipment name missing] available from Applied Materials, Santa Clara, California. ® Cobalt CVD chamber. Processing chamber 128 can be a Blok™ PECVD chamber available from Applied Materials, Santa Clara, California.

[0021] System controller 160 is coupled to cluster tool 100 for controlling cluster tool 100 or its components. For example, system controller 160 may control the operation of cluster tool 100 by directly controlling chambers 104, 106, 108, 120, 122, 124, 126, 128, and 130 of cluster tool 100, or by controlling controllers associated with chambers 104, 106, 108, 120, 122, 124, 126, 128, and 130. In operation, system controller 160 enables data collection and feedback from the respective chambers to coordinate the performance of cluster tool 100.

[0022] System controller 160 typically includes a central processing unit (CPU) 162, memory 164, and support circuitry 166. CPU 162 can be one of any type of general-purpose processor that can be used in an industrial environment. Memory 164, or a non-transitory computer-readable medium, can be accessed by CPU 162 and can be one or more memory modules, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage device. Support circuitry 166 is coupled to CPU 162 and may include cache, clock circuitry, input / output subsystems, power supply, and the like. The various methods disclosed herein can generally be implemented by CPU 162 executing computer instruction code, for example, stored as software routines in memory 164 (or in the memory of a specific processing chamber), under the control of CPU 162. When CPU 162 executes the computer instruction code, CPU 162 controls the chamber to perform the process according to various methods.

[0023] Other processing systems can have different configurations. For example, more or fewer processing chambers can be coupled to a transfer device. In the illustrated example, the transfer device includes a transfer chamber 108. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chamber) can be implemented as transfer devices in a processing system.

[0024] Figure 2 The illustration shows a process flow diagram of a method 200 for forming a semiconductor structure 300 according to one or more embodiments of the present disclosure, the semiconductor structure including a dual damascene interconnect structure utilized in a back-end process (BEOL). Figure 3A , Figure 3A '、 Figure 3B , Figure 3B '、 Figure 3C , Figure 3C '、 Figure 3D and Figure 3D This is a cross-sectional view of a portion of the semiconductor structure 300 corresponding to the various states of method 200. It should be understood that... Figure 3A , Figure 3A '、 Figure 3B , Figure 3B '、 Figure 3C , Figure 3C '、 Figure 3D and Figure 3DOnly a partial schematic diagram of semiconductor structure 300 is shown, and semiconductor structure 300 may contain any number of transistor segments and additional material having the aspects shown in the figures. It should also be noted that, although... Figure 2 The methods shown are described sequentially, but other process sequences that include one or more operations that have been omitted and / or added and / or rearranged in another desired order also fall within the scope of the embodiments of this disclosure provided herein.

[0025] like Figure 3A As shown, the semiconductor structure 300 includes metal layers 302, each metal layer being encapsulated within a metal seed layer 304 and a barrier layer and pad (shown as a combination in the figure) 306 within a dielectric layer 308 formed on a substrate (not shown). In some embodiments, the metal layer 302 is recessed from the top surface 308S of the dielectric layer 308, such as... Figure 3A As shown.

[0026] The dielectric layer 308 can be made of silicon oxide (SiO2) or a low dielectric constant dielectric material, such as silicon oxide containing carbon (SiOC), such as Black Diamond available from Applied Materials, Inc. ® It is formed from a dielectric film or other low dielectric constant polymer (such as polyamide) and patterned with openings 310 (e.g., damascene features, such as grooves above through holes) by a suitable photolithography method.

[0027] The barrier layer can be formed of a transition metal (such as tantalum (Ta) or titanium (Ti)) and its nitrides (such as tantalum nitride (TaN) or titanium nitride (TiN)). The pad can be formed of cobalt (Co) or ruthenium (Ru). The barrier layer and the pad 306 are deposited on the patterned dielectric layer 308 using a suitable deposition process (such as chemical vapor deposition (CVD) or physical vapor deposition (PVD)).

[0028] The metal layer 302 and the metal seed layer 304 can be formed from metals such as copper (Cu), copper-aluminum (CuAl) alloys (0.1-5 atomic% Al), or copper-manganese (CuMn) alloys (0.1-5 atomic% Mn). Due to the low conductivity and poor nucleation of the metal (e.g., copper (Cu)) on the barrier layer 306 (e.g., Ta / TaN), the metal seed layer 304 can be deposited in the metallization process by CVD, PVD, atomic layer deposition (ALD), electrophoretic deposition (ED), or other suitable deposition processes to ensure that the opening 310 is filled with metal without defects.

[0029] The semiconductor structure 300 can be planarized by chemical mechanical polishing (CMP) to remove overfilled metal (e.g., copper (Cu)).

[0030] The substrate can be, for example, crystalline silicon (e.g., Si). <100> or Si <111> Materials include silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, and sapphire. The substrate can have various sizes, such as wafers with diameters of 200 mm, 300 mm, or 450 mm, and rectangular or square panels. Unless otherwise stated, the embodiments and examples described herein are performed on substrates with diameters of 300 mm or 450 mm.

[0031] Method 200 begins at block 210, in which a pre-cleaning process is performed to remove oxides 312 (e.g., copper oxide (CuO)) formed on the exposed surface 302S of the metal layer 302. x )),like Figure 3B and Figure 3B As shown in the image. The pre-cleaning process can be performed in a pre-cleaning chamber, such as... Figure 1 The processing chamber 122 in the middle or available from Aktiv, Applied Materials, Santa Clara, California. ™ Performed in an APC (Advanced Pre-cleaning) chamber, which can be appropriately adapted to cluster tools, such as... Figure 1 The clustering tool 100 shown or the Producer available from Applied Materials, Santa Clara, California, is also shown. ® Clustering tools.

[0032] The pre-cleaning process includes providing reactive hydrogen radicals (H2O) generated by a remote plasma source in a pre-cleaning chamber. * Compared with the use of hydrogen ions (H+) + Compared to cleaning with hydrogen radicals (H), * Performing cleaning reduces damage to the underlying dielectric layer 308. In some embodiments, an inert gas, such as argon (Ar) or helium (He), is also provided in the pre-cleaning chamber.

[0033] Reducing the oxide 312 on the surface 302S of the metal layer 302 can increase the metal surface area of ​​the metal layer 302, which improves the adhesion of the metal coating on the metal surface during the selective deposition process in frame 220.

[0034] In box 220, a selective deposition process is performed to deposit a capping layer 314 on the pre-cleaned surface of metal layer 302, such as Figure 3C and Figure 3C As shown in the figure. Selective deposition processes can be performed in selective CVD chambers (such as processing chambers 124 or 126, or Volta, available from Applied Materials, Santa Clara, California). ® A selective CVD deposition process is performed in a cobalt CVD chamber, which can be suitably adapted to the clustering tool. The selective deposition process in box 220 is performed within the clustering tool without exposing the semiconductor structure 300 to the surrounding environment outside the clustering tool after the pre-cleaning process in box 210.

[0035] A capping layer 314 is deposited to improve the wiring reliability, such as electromigration (EM) performance, of interconnects (e.g., metal layer 302) when the metal layers are completed in the back-end process (BEOL). EM (i.e., a large amount of metal transport caused by high current density) in thin metal interconnects can occur by diffusion at the interface between the metal and dielectric layers, creating atomic vacancies and voids or bumps in the interconnects. Void formation can lead to open circuits and increase line resistance. Bump formation can lead to short circuits between adjacent interconnects. The capping layer 314 between metal layer 302 and the dielectric layer reduces EM between metal layer 302 and the dielectric layer, thereby improving EM resistance.

[0036] The capping layer 314 may be formed of a metal capping layer selectively deposited directly onto a pre-cleaned surface of the metal layer 302. The metal capping layer may include at least one of cobalt (Co), titanium (Ti), manganese (Mn), ruthenium (Ru), cobalt tungsten phosphide (CoWP), tungsten (W), nickel (Ni), platinum (Pt), and copper (Cu) alloys thereof (such as titanium-copper (TiCu) alloys), and has a thickness between about 1 nm and about 10 nm, for example, about 2 nm. In some embodiments, the capping layer 314 further includes a dielectric capping layer selectively deposited on the metal capping layer. The dielectric capping layer may comprise a dielectric material such as silicon nitride (SiN), nitrogen-doped silicon carbonitride (e.g., silicon carbonitride (SiCN)), or silicon carbonitride (e.g., silicon carbide (SiC)).

[0037] In some other embodiments, the capping layer 314 is formed of a dielectric capping layer selectively deposited directly onto a pre-cleaned surface of the metal layer 302. The dielectric capping layer may comprise a dielectric material such as silicon nitride (SiN), nitrogen-doped silicon carbon (e.g., silicon carbonitride (SiCN)), or silicon carbon (e.g., silicon carbide (SiC)).

[0038] In box 230, a capping deposition process is performed to deposit dielectric layer 316 on the exposed surfaces of capping layer 314 and dielectric layer 308, as follows: Figure 3D and Figure 3D As shown in the figure. The overlay deposition process can be performed in a PECVD chamber, such as the BLOk, available from Applied Materials Inc. in Santa Clara, California. ™ Plasma-enhanced CVD (PECVD) processes are performed in a PECVD chamber that can be appropriately adapted and pre-cleaned with a chamber such as Aktiv, available from Applied Materials, Santa Clara, California. ™ Pre-cleaning (APC) chambers and selective CVD chambers (such as the Volta, available from Applied Materials, Santa Clara, California) ® The cobalt CVD chamber is integrated within the cluster tool. The overlay deposition process in box 230 is performed within the cluster tool without exposing the semiconductor structure 300 to the surrounding environment outside the cluster tool following the selective deposition process in box 220.

[0039] In conventional clustering tools, the processing chamber adapted for depositing low-dielectric-constant dielectric materials is not compared with a pre-cleaning chamber (such as Aktiv, available from Applied Materials, Santa Clara, California). ™ Pre-cleaning (APC) chambers and selective CVD chambers (such as the Volta, available from Applied Materials, Santa Clara, California) ® The cobalt CVD chamber is integrated together. Therefore, after the selective deposition process in box 220, the semiconductor structure 300 needs to be transferred from one cluster tool to another via a nitrogen-purified FOUP to minimize oxidation or other effects caused by exposure to the surrounding environment outside the cluster tool. Furthermore, since the capping layer 314 (e.g., cobalt (Co)) is easily oxidized even in a nitrogen-purified FOUP, another pre-cleaning process can be performed after the transfer via the nitrogen-purified FOUP to remove oxides and contaminants from the exposed surfaces of the capping layer 314. This pre-cleaning process can use capacitively coupled plasma (CCP) ammonia (NH3) plasma, which damages the underlying dielectric layer 308 and / or increases the dielectric constant of low-dielectric-constant dielectric materials in the dielectric layer 308. Breakdown of the underlying dielectric layer 308 can lead to short circuits between adjacent interconnects and increase resistance-capacitance (RC) delay.

[0040] In clustering tools according to embodiments described herein, plasma-enhanced CVD (PECVD) chambers (such as BLOk, available from Applied Materials, Santa Clara, California) ™PECVD chambers and pre-cleaning chambers (such as Aktiv, available from Applied Materials, Santa Clara, California) ™ Pre-cleaning (APC) chambers and selective CVD chambers (such as the Volta, available from Applied Materials, Santa Clara, California) ® The cobalt CVD chamber is integrated, allowing the semiconductor structure 300 to be transferred from the pre-cleaning chamber to the selective CVD chamber and from the selective CVD chamber to the PECVD chamber without exposure to the surrounding environment outside the clustering tool. Therefore, oxidation of the capping layer 314 can be avoided, and a pre-cleaning process (using CCP ammonia (NH3) plasma) to remove oxides from the capping layer 314 is unnecessary. Furthermore, a FOUP with nitrogen flow capability is not required, nor is the queue time for controlling the residence of the semiconductor structure 300 outside the processing chamber or controlled environment unnecessary.

[0041] Eliminating exposure to the surrounding environment can enhance component reliability, such as the time-dependent dielectric breakdown (TDDB) lifetime of dielectric layer 308 (i.e., dielectric degradation due to an electric field), because the absence of contamination (e.g., moisture or carbon) from the surrounding environment exposed to capping layer 314 improves the adhesion of dielectric layer 316 to the capping layer.

[0042] The dielectric layer 316 can be made of a low dielectric constant dielectric material (e.g., a dielectric constant of about 5.5 or lower), such as BLOk, which is available from Applied Materials. ® Formation of low dielectric constant dielectric film.

[0043] The dielectric layer 316 acts as a diffusion barrier layer to prevent metallic elements (e.g., copper (Cu)) from diffusing from the metal layer 302, which could lead to short circuits or other component defects. The dielectric layer 316 can also serve as an etch stop layer in subsequent patterning processes. The thickness of the dielectric layer 316 can be between approximately 1 nm and approximately 100 nm.

[0044] In some implementations, dielectric layer 316 includes an enhanced nitrogen interface (ENI) to further improve reliability.

[0045] Following the capping deposition process in box 230, other layers, such as an ILD (interlayer dielectric) layer (not shown), can be deposited on dielectric layer 316 in the same cluster tool or another cluster tool. During transfer to another tool, dielectric layer 316 protects capping layer 314 from oxidation.

[0046] The embodiments provided herein offer systems and methods for covering back-end process (BEOL) interconnects (e.g., copper (Cu)) with a metal overlay (e.g., cobalt (Co)) and a dielectric layer (e.g., silicon carbonitride (SiCN)) within a single cluster tool, without exposing them to the surrounding environment outside the cluster tool. The use of the metal overlay can improve the electromigration (EM) performance of the interconnects. Because exposure to the surrounding environment is eliminated, the time-dependent dielectric breakdown (TDDB) lifetime of the low-dielectric-constant dielectric layer surrounding the metal layer can be improved. The process steps for covering the interconnects are integrated into a single cluster tool, eliminating the need for queue time control.

[0047] Although the foregoing embodiments of this disclosure are described, other and further embodiments of this disclosure may be designed without departing from the basic scope of this disclosure, and the scope of this disclosure is defined by the appended claims.

Claims

1. A clustering tool for forming an interconnected structure, the clustering tool comprising: A pre-cleaning chamber configured to pre-clean the exposed surfaces of a metal layer formed within a first dielectric layer of the interconnect structure; A selective chemical vapor deposition (CVD) chamber configured to selectively deposit a capping layer on the pre-cleaned surface of the metal layer; A plasma-enhanced chemical vapor deposition (PECVD) chamber, the PECVD chamber being configured to deposit a second dielectric layer on the exposed surfaces of the capping layer and the first dielectric layer; One or more transfer chambers, the one or more transfer chambers being coupled to the pre-cleaning chamber, the selective CVD chamber and the PECVD chamber, and configured to transfer the interconnect structure between the pre-cleaning chamber, the selective CVD chamber and the PECVD chamber without disrupting the vacuum environment; as well as A controller configured to perform the pre-cleaning of the metal layer in the pre-cleaning chamber, the selective deposition of the overlay layer in the selective CVD chamber, and the deposition of the second dielectric layer in the PECVD chamber.

2. The clustering tool of claim 1, wherein the pre-cleaning of the exposed surface of the metal layer comprises providing reactive hydrogen radicals H generated by a remote plasma source in the pre-cleaning chamber. * .

3. The clustering tool as described in claim 1, wherein The metal layer comprises at least one of copper (Cu), copper-aluminum (CuAl) alloy, and copper-manganese (CuMn) alloy. The first dielectric layer comprises silicon oxide (SiO2) or a low dielectric constant dielectric material, and The second dielectric layer comprises a low dielectric constant dielectric material.

4. The clustering tool of claim 1, wherein the overlay comprises a metal overlay selectively deposited on the pre-cleaned surface of the metal layer, the metal overlay comprising at least one of cobalt (Co), titanium (Ti), manganese (Mn), ruthenium (Ru), cobalt tungsten phosphide (CoWP), tungsten (W), nickel (Ni), platinum (Pt), and copper (Cu) alloys thereof.

5. The clustering tool of claim 4, wherein the overlay further comprises a first dielectric overlay selectively deposited on the metal overlay, wherein the first dielectric overlay comprises at least one of silicon nitride, nitrogen-doped silicon carbon, and silicon carbon.

6. The clustering tool of claim 1, wherein the overlay includes a second dielectric overlay selectively deposited on the pre-cleaned surface of the metal layer, wherein the second dielectric overlay comprises at least one of silicon nitride, nitrogen-doped silicon carbon, and silicon carbon.

7. A method for forming an interconnect structure, the method comprising: A pre-cleaning process is performed in a pre-cleaning chamber to remove oxides formed on the exposed surface of a metal layer formed within the first dielectric layer of the interconnect structure. A selective deposition process is performed in a selective chemical vapor deposition (CVD) chamber to deposit a capping layer on the pre-cleaned surface of the metal layer; as well as A capping deposition process is performed in a plasma-enhanced CVD (PECVD) chamber to deposit a second dielectric layer on the exposed surfaces of the capping layer and the first dielectric layer, wherein... The pre-cleaning process, the selective deposition process, and the overlay deposition process are all performed within the cluster tool without being exposed to the surrounding environment outside the cluster tool.

8. The method of claim 7, wherein The metal layer comprises at least one of copper (Cu), copper-aluminum (CuAl) alloy, and copper-manganese (CuMn) alloy. The first dielectric layer comprises silicon oxide (SiO2) or a low dielectric constant dielectric material, and The second dielectric layer comprises a low dielectric constant dielectric material.

9. The method of claim 7, wherein the capping layer comprises a metal capping layer selectively deposited on the pre-cleaned surface of the metal layer, the metal layer comprising at least one of cobalt (Co), titanium (Ti), manganese (Mn), ruthenium (Ru), tungsten cobalt phosphide (CoWP), tungsten (W), nickel (Ni), platinum (Pt), and copper (Cu) alloys thereof.

10. The method of claim 9, wherein the capping layer further comprises a first dielectric capping layer selectively deposited on the metal capping layer, wherein the first dielectric capping layer comprises at least one of silicon nitride, nitrogen-doped silicon carbon, and silicon carbon.

11. The method of claim 7, wherein the capping layer comprises a second dielectric capping layer selectively deposited on the pre-cleaned surface of the metal layer, wherein the second dielectric capping layer comprises at least one of silicon nitride, nitrogen-doped silicon carbon, and silicon carbon.

12. The method of claim 7, wherein the pre-cleaning process includes providing reactive hydrogen radicals H generated by a remote plasma source in the pre-cleaning chamber. * .

13. The method of claim 7, wherein the selective deposition process comprises a selective CVD process.

14. The method of claim 7, wherein the overlay deposition process includes a PECVD process.

15. A method for forming an interconnect structure, the method comprising: A selective deposition process is performed in a selective chemical vapor deposition (CVD) chamber to deposit a capping layer on the exposed surface of a metal layer formed within the first dielectric layer of the interconnect structure. as well as A capping deposition process is performed in a plasma-enhanced CVD (PECVD) chamber to deposit a second dielectric layer on the exposed surfaces of the capping layer and the first dielectric layer, wherein... Both the selective deposition process and the overlay deposition process are performed within the clustering tool without being exposed to the surrounding environment outside the clustering tool.

16. The method of claim 15, wherein The metal layer comprises at least one of copper (Cu), copper-aluminum (CuAl) alloy, and copper-manganese (CuMn) alloy. The first dielectric layer comprises silicon oxide (SiO2) or a low dielectric constant dielectric material, and The second dielectric layer comprises a low dielectric constant dielectric material.

17. The method of claim 15, wherein the capping layer comprises a metal capping layer selectively deposited on the pre-cleaned surface of the metal layer, the metal capping layer comprising at least one of cobalt (Co), titanium (Ti), manganese (Mn), ruthenium (Ru), cobalt tungsten phosphide (CoWP), tungsten (W), nickel (Ni), platinum (Pt), and copper (Cu) alloys thereof.

18. The method of claim 17, wherein the capping layer further comprises a first dielectric capping layer selectively deposited on the metal capping layer, wherein the first dielectric capping layer comprises at least one of silicon nitride, nitrogen-doped silicon carbon, and silicon carbon.

19. The method of claim 15, wherein the capping layer comprises a second dielectric capping layer selectively deposited on the pre-cleaned surface of the metal layer, wherein the second dielectric capping layer comprises at least one of silicon nitride, nitrogen-doped silicon carbon, and silicon carbon.

20. The method of claim 15, wherein the selective deposition process includes a selective CVD process, and the overlay deposition process includes a PECVD process.

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