Semiconductor device

Abstract

The invention provides a semiconductor device capable of improving the reliability of the semiconductor device. According to one embodiment, a semiconductor device includes: at least one first transistor and at least one second transistor each having a first terminal connected to a first node and a second terminal connected to a second node; at least one third transistor and at least one fourth transistor each having a first terminal connected to the second node and a second terminal connected to the third node; a fifth transistor disposed between a gate terminal of the at least one first transistor and the second node; a sixth transistor disposed between a gate terminal of the at least one second transistor and the second node; a seventh transistor disposed between a gate terminal of the at least one third transistor and the third node; and an eighth transistor disposed between the gate terminal of the at least one fourth transistor and the third node.

Description

Technical Field

[0001] The implementation relates to a semiconductor device. Background Technology

[0002] Power modules are known as semiconductor devices that achieve high output. A power module is configured as a package that houses multiple power semiconductor elements.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent No. 7157046 Summary of the Invention

[0004] The problem the invention aims to solve Improve the reliability of semiconductor devices.

[0005] means for solving problems The semiconductor device of the embodiment includes: at least one first transistor and at least one second transistor, each having a first terminal connected to a first node and a second terminal connected to a second node; at least one third transistor and at least one fourth transistor, each having a first terminal connected to a second node and a second terminal connected to a third node; a fifth transistor, disposed corresponding to the at least one first transistor, having a first terminal connected to the gate terminal of the at least one first transistor and a second terminal connected to the second node; a sixth transistor, disposed corresponding to the at least one second transistor, having a first terminal connected to the gate terminal of the at least one second transistor and a second terminal connected to the second node; a seventh transistor, disposed corresponding to the at least one third transistor, having a first terminal connected to the gate terminal of the at least one third transistor and a second terminal connected to the third node; and an eighth transistor, disposed corresponding to the at least one fourth transistor, having a first terminal connected to the gate terminal of the at least one fourth transistor and a second terminal connected to the third node. Attached Figure Description

[0006] Figure 1 This is a circuit diagram illustrating an example of the circuit configuration of a semiconductor device in an embodiment.

[0007] Figure 2 This is a top view showing the configuration of the semiconductor device in the embodiment.

[0008] Figure 3 This is an example of the cross-sectional structure of a semiconductor device illustrating an embodiment. Figure 2 A sectional view along line III-III.

[0009] Figure 4 This is a top view showing the configuration of the semiconductor device in the first modified example.

[0010] Figure 5 This is a top view showing the configuration of the semiconductor device in the second variation.

[0011] Figure 6 This is a top view showing the configuration of the semiconductor device in the third variation.

[0012] Figure 7 This is an example of the cross-sectional structure of a semiconductor device representing the third variation. Figure 6 A sectional view of line VII-VII.

[0013] Figure 8 This is a top view showing the configuration of the semiconductor device in the fourth variation. Detailed Implementation

[0014] The embodiments will now be described with reference to the accompanying drawings. The dimensions and scale of the drawings may not be identical to reality. Furthermore, in the following description, constituent elements having substantially the same function and structure are labeled with the same symbols. When elements having the same structure are specifically distinguished from each other, sometimes different words or numbers are appended to the end of the same symbol.

[0015] 1 Implementation Method The semiconductor device of the embodiment will be described.

[0016] The semiconductor device in this embodiment is a power module. Examples of such semiconductor devices include power conversion devices for railway vehicles and industrial equipment for renewable energy power generation systems.

[0017] The configuration of the semiconductor device in the embodiment will be described.

[0018] use Figure 1 The circuit configuration of the semiconductor device in the embodiment will be described. Figure 1 This is a circuit diagram illustrating an example of the circuit configuration of a semiconductor device according to an embodiment. Figure 1 In the example shown, semiconductor device 1 includes multiple transistors TU, TL, TCU, and TCL as internal semiconductor elements. Furthermore, in the following description, without distinguishing between the multiple transistors TU, TL, TCU, and TCL, the multiple transistors TU, TL, TCU, and TCL will be simply referred to as transistor T.

[0019] The plurality of transistors T are MOS (Metal-Oxide-Semiconductor) transistors. The plurality of transistors T are n-type transistors. Each transistor T is, for example, a MOS transistor using silicon carbide (SiC), a MOS transistor using silicon (Si), or a transistor using gallium nitride (GaN). Alternatively, each transistor T may also be an IGBT (Insulated-Gate Bipolar Transistor). The drain-source breakdown voltage of each of the plurality of transistors TCU and TCL is, for example, higher than the gate-source breakdown voltage of each of the plurality of transistors TU and TL. The drain-source breakdown voltage of each of the plurality of transistors TCU and TCL is, for example, around 30V. Furthermore, in the embodiment, the number of transistors TU, TL, TCU, and TCL are each two or more. Figure 1 In this diagram, the circuit configuration is simplified, with only one transistor each of the multiple transistors TU, TL, TCU, and TCL shown.

[0020] Multiple transistors TU are connected in parallel between node P and node AC (Alternating Current). Node P is the input terminal of semiconductor device 1. Node P has, for example, a positive polarity in the circuit configuration of semiconductor device 1. Node AC is the output terminal of semiconductor device 1. Additionally, as described later, node AC is connected to a monitoring terminal. Each transistor TU has a drain terminal connected to node P, a source terminal connected to node AC, and a gate terminal connected to node GU. Node GU is a control terminal. Furthermore, in the following description, each transistor TU will also be referred to as the upper semiconductor element.

[0021] Multiple transistor TCUs are connected between the gate terminals and source terminals of multiple transistor TUs, respectively. More specifically, each transistor TCU has a drain terminal connected to the gate terminals (node ​​GU) of the multiple transistor TUs, a source terminal connected to the source terminals (node ​​AC) of the multiple transistor TUs, and a gate terminal connected to the node GCU. The node GCU is a control terminal. Additionally, in the following description, each transistor TCU will also be referred to as an upper clamping element.

[0022] Multiple transistors TL are connected in parallel between node AC and node N. Node N is the input terminal of semiconductor device 1. Node N has, for example, a negative polarity in the circuit configuration of semiconductor device 1. Furthermore, as described later, node N is connected to a different monitoring terminal than the monitoring terminal connected to node AC. Each transistor TL has a drain terminal connected to node AC, a source terminal connected to node N, and a gate terminal connected to node GL. Node GL is a control terminal. Additionally, in the following description, each transistor TL will also be referred to as a lower semiconductor element.

[0023] Multiple transistors TCL are connected between the gate terminals and source terminals of multiple transistors TL. More specifically, each transistor TCL has a drain terminal connected to the gate terminals (node ​​GL) of the multiple transistors TL, a source terminal connected to the source terminals (node ​​N) of the multiple transistors TL, and a gate terminal connected to node GCL. Node GCL is a control terminal. Additionally, in the following description, each transistor TCL will also be referred to as a lower-side clamping element.

[0024] Based on the above configuration, the semiconductor elements inside the semiconductor device 1 can be controlled by a voltage supplied from outside the semiconductor device 1. Different signals are input from the outside to nodes GU, GL, GCU, and GCL, for example.

[0025] More specifically, when transistor TU is set to the ON state and transistor TL is set to the OFF state, for example, nodes GU and GCL are supplied with "H" (High) level signals, and nodes GL and GCU are supplied with "L" (Low) level signals. Conversely, when transistor TU is set to the OFF state and transistor TL is set to the ON state, for example, nodes GU and GCL are supplied with "L" level signals, and nodes GL and GCU are supplied with "H" level signals.

[0026] Next, the structure of the semiconductor device 1 according to the embodiment will be described.

[0027] First, use Figure 2 The planar structure of the semiconductor device 1 in the embodiment will be described. Figure 2 This is a top view showing the configuration of the semiconductor device in the embodiment.

[0028] The semiconductor device 1 also includes an insulating component 10 and conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36. Additionally, the semiconductor device 1 also includes... Figure 2 The substrate (base) is not shown in the figure.

[0029] An insulating component 10 is disposed on a substrate. The substrate is a support having a flat, plate-like portion. The substrate may contain, for example, copper or ceramic. The insulating component 10 may contain, for example, resin or ceramic. The resin may be, for example, polyphenylene sulfide (PPS). Furthermore, the structure of the semiconductor device 1 will be described below using the X direction in a plane parallel to the upper surface of the substrate and the insulating component 10, the Y direction orthogonal to the X direction in that plane, and the Z direction perpendicular to the aforementioned plane.

[0030] Conductors 21, 22, 23, 24, and 25 are disposed on the insulating member 10. Conductors 21, 22, 23, 24, and 25 are disposed separately from each other. Each conductor 21, 22, 23, 24, and 25 has, for example, a portion extending along the X direction. The portions of conductor 22 extending along the X direction, the portions of conductor 21 extending along the X direction, the portions of conductor 23 extending along the X direction, the portions of conductor 24 extending along the X direction, and the portions of conductor 25 extending along the X direction are arranged sequentially along the Y direction. Furthermore, in the following description, the side of the portions of conductors 22 and 25 where the portion of conductor 22 extending along the X direction is disposed is referred to as one end side in the Y direction. Additionally, the side of the portions of conductors 22 and 25 where the portion of conductor 25 extending along the X direction is disposed is referred to as the other end side in the Y direction. Conductors 21, 23, and 24 also have portions extending in the Y direction. The portion of conductor 23 extending in the Y direction is disposed at a different end along the X direction from the portions of conductors 21 and 24 extending in the Y direction. Furthermore, in the following description, the side of the portions of conductors 21, 23, and 24 where the portion of conductor 23 extending in the Y direction is disposed is referred to as one end side in the X direction. Conversely, the side of the portions of conductors 21, 23, and 24 where the portions of conductors 21 and 24 extending in the Y direction are disposed is referred to as the other end side in the X direction.

[0031] On the upper surface of the portion of the conductor 21 extending along the X direction, a plurality of transistors TU are arranged in the X direction. The plurality of transistors TU are arranged, for example, at approximately equal intervals in the X direction. Figure 2The diagram shows an example of nine transistors TU arranged in a specific configuration. Hereinafter, the three transistors TUs on one side of the nine transistors TUs along the X direction will be referred to as transistor TU1. Additionally, the three transistors TUs on one side of the six transistors TUs (excluding TU1) along the X direction will be referred to as transistor TU2. Furthermore, the three transistors TUs on the other side of the nine transistors TUs along the X direction will be referred to as transistor TU3. The drain terminal of each transistor TU is located on its lower surface. The source terminal and gate terminal of each transistor TU are located on its upper surface. The drain terminal of each transistor TU is electrically connected to conductor 21. The source terminal of each transistor TU is electrically connected to conductor 23 via a wire. The gate terminal of each transistor TU is electrically connected to conductor 22 via a wire.

[0032] In addition, Figure 2 The following description illustrates a scenario where semiconductor device 1 includes three transistors TU1, three transistors TU2, and three transistors TU3, but is not limited to this. The number of transistors TU1, TU2, and TU3 may also be one, two, or more than four, respectively.

[0033] On the upper surface of the portion of conductor 22 extending along the X direction, a plurality of transistor TCUs are arranged in the X direction. The plurality of transistor TCUs are arranged, for example, at approximately equal intervals in the X direction. Figure 2 The diagram shows an example of three transistor TCUs arranged in a specific configuration. Hereinafter, the three transistor TCUs will be referred to as transistor TCU1, TCU2, and TCU3, respectively, from one end in the X direction towards the other. Transistors TCU1, TCU2, and TCU3 correspond to transistors TU1, TU2, and TU3, respectively. The drain terminal of each transistor TCU is located on the lower surface of the transistor TCU. The source terminal and gate terminal of each transistor TCU are located on the upper surface of the transistor TCU. The drain terminal of each transistor TCU is electrically connected to conductor 22. The gate terminal of each transistor TCU is connected to node GCU. The source terminal of transistor TCU1 is electrically connected to the source terminal of each transistor TU1 via a wire. The source terminal of transistor TCU2 is electrically connected to the source terminal of each transistor TU2 via a wire. The source terminal of transistor TCU3 is electrically connected to the source terminal of each transistor TU3 via a wire.

[0034] Multiple transistor TCUs are configured in such a way that the deviation in length between the source terminals of each transistor TCU and the source terminals of the transistor TUs corresponding to that transistor TCU is minimized. For example, multiple transistor TCUs are configured such that the average length along the extension direction of the wires connecting the source terminals of each transistor TCU and the source terminals of the multiple transistor TUs corresponding to that transistor TCU is approximately equal.

[0035] In addition, Figure 2 The following description focuses on the case where semiconductor device 1 includes three transistor TCUs, but is not limited to this. The number of transistor TCUs can also be two or more. Each transistor TCU is electrically connected to the source terminal of at least one of the plurality of transistor TUs.

[0036] On the upper surface of the portion of conductor 23 extending along the X direction, a plurality of transistors TL are arranged in the X direction. The plurality of transistors TL are arranged, for example, at approximately equal intervals in the X direction. Figure 2 The diagram shows an example of nine transistors TL arranged in a row. Hereinafter, the three transistors TL on one side of the nine transistors TL in the X direction will be referred to as transistor TL1. Additionally, the three transistors TL on one side of the six transistors TL excluding TL1 will be referred to as transistor TL2. Furthermore, the three transistors TL on the other side of the nine transistors TL in the X direction will be referred to as transistor TL3. The drain terminal of each transistor TL is located on the lower surface of the transistor TL. The source terminal and gate terminal of each transistor TL are located on the upper surface of the transistor TL. The drain terminal of each transistor TL is electrically connected to conductor 23. The source terminal of each transistor TL is electrically connected to conductor 24 via a wire. The gate terminal of each transistor TL is electrically connected to conductor 25 via a wire.

[0037] In addition, Figure 2 The following description describes the semiconductor device 1 as including three transistors TL1, three transistors TL2, and three transistors TL3, but is not limited thereto. The number of transistors TL1, TL2, and TL3 may also be one, two, or more than four, respectively.

[0038] On the upper surface of the portion of the conductor 25 extending along the X direction, a plurality of transistors TCLs are arranged in the X direction. The plurality of transistors TCLs are arranged, for example, at approximately equal intervals in the X direction. Figure 2The diagram shows an example of three transistors TCL arranged in a specific configuration. Hereinafter, the three transistors TCL will be referred to as transistors TCL1, TCL2, and TCL3, respectively, from one end in the X direction towards the other. Transistors TCL1, TCL2, and TCL3 correspond to transistors TL1, TL2, and TL3, respectively. The drain terminal of each transistor TCL is located on the lower surface of the transistor TCL. The source terminal and gate terminal of each transistor TCL are located on the upper surface of the transistor TCL. The drain terminal of each transistor TCL is electrically connected to conductor 25. The gate terminal of each transistor TCL is connected to node GCL. The source terminal of transistor TCL1 is electrically connected to the source terminal of each transistor TL1 via a wire. The source terminal of transistor TCL2 is electrically connected to the source terminal of each transistor TL2 via a wire. The source terminal of transistor TCL3 is electrically connected to the source terminal of each transistor TL3 via a wire.

[0039] Multiple transistor TCLs are configured in such a way that the deviation in length between the source terminals of each transistor TCL and the source terminals of the corresponding transistor TLs is minimized. For example, multiple transistor TCLs are configured such that the average length along the extension direction of the wires connecting the source terminals of each transistor TCL and the source terminals of the corresponding transistor TLs is approximately equal.

[0040] In addition, Figure 2 The following description illustrates the case where semiconductor device 1 includes three transistors TCL, but is not limited to this. The number of transistors TCL can also be two or more. Each transistor TCL only needs to be electrically connected to the source terminal of at least one of the plurality of transistors TL.

[0041] Furthermore, in this embodiment, the plurality of transistors TU and TL are arranged in the same manner as when viewed from above, with each transistor TU having the same configuration as each transistor TL. More specifically, the gate terminal of each transistor TU is, for example, disposed on the end side further in the Y direction than the source terminal of the transistor TU. Similarly, the gate terminal of each transistor TL is also, for example, disposed on the end side further in the Y direction than the source terminal of the transistor TL.

[0042] Conductor 26 is electrically connected at its other end along the X direction to the portion of conductor 21 extending in the Y direction. Conductor 26 functions as node P. That is, conductor 26 is a positive polarity input terminal.

[0043] Conductor 27 is electrically connected at its other end along the X direction to the portion of conductor 24 extending in the Y direction. Conductor 27 functions as node N. That is, conductor 27 is a negative polarity input terminal.

[0044] Conductors 28a and 28b are electrically connected at one end in the X direction to the portion of conductor 23 extending in the Y direction. Conductors 28a and 28b function as nodes AC. That is, conductors 28a and 28b are output terminals.

[0045] Conductors 31, 32, 33, 34, 35, and 36 are similarly disposed on the insulating member 10 as conductors 21, 22, 23, 24, and 25. Conductor 31 is electrically connected to conductor 22 via a wire. Conductor 31 functions as a node GU, that is, conductor 31 corresponds to the control terminal of the plurality of transistors TU. Conductor 32 is electrically connected to conductor 23 via a wire. Conductor 32 functions as a monitoring terminal SSH connected to node AC. Conductor 33 is electrically connected to conductor 25 via a wire. Conductor 33 functions as a node GL, that is, conductor 33 corresponds to the control terminal of the plurality of transistors TL. Conductor 34 is electrically connected to conductor 24 via a wire. Conductor 34 functions as a monitoring terminal SSL connected to node N. Conductor 35 is electrically connected to the gate terminals of the plurality of transistors TCU via wires. Conductor 36 is electrically connected to the gate terminals of the plurality of transistors TCL via wires.

[0046] Next, use Figure 3 The cross-sectional structure of the semiconductor device 1 according to the embodiment will be described. Figure 3 This is an example of the cross-sectional structure of a semiconductor device illustrating an embodiment. Figure 2 A sectional view along line III-III.

[0047] The semiconductor device 1 may also include a heat dissipation component HS.

[0048] The heat dissipation component HS is a heat sink. The heat dissipation component HS is integrally disposed on the lower surface of the substrate B, which serves as, for example, the aforementioned support. The heat dissipation component HS has a relatively large surface area due to its uneven lower surface. The heat dissipation component HS may, for example, contain copper or ceramic. Alternatively, the heat dissipation component HS may be integrally formed with the substrate B.

[0049] On the upper surface of the conductor 21, each transistor TU is disposed via an adhesive member 41. The adhesive member 41 physically and electrically connects the drain terminal of each transistor TU to the conductor 21.

[0050] On the upper surface of the conductor 22, each transistor TCU is disposed via an adhesive member 43. The adhesive member 43 physically and electrically connects the drain terminal of each transistor TCU to the conductor 22.

[0051] On the upper surface of the conductor 23, each transistor TL is disposed via an adhesive member 42. The adhesive member 42 physically and electrically connects the drain terminal of each transistor TL to the conductor 23.

[0052] On the upper surface of the conductor 25, each transistor TCL is disposed via an adhesive member 44. The adhesive member 44 physically and electrically connects the drain terminal of each transistor TCL to the conductor 25.

[0053] According to the embodiment, the reliability of semiconductor device 1 can be improved. Hereinafter, the improvement of the reliability of semiconductor device 1 according to the embodiment will be explained.

[0054] In the semiconductor device 1 of this embodiment, one or more source terminals of transistor TU1 are electrically connected to the source terminal of transistor TCU1. Additionally, one or more source terminals of transistor TU2 are electrically connected to the source terminal of transistor TCU2. Furthermore, one or more source terminals of transistor TL1 are electrically connected to the source terminal of transistor TCL1. Additionally, one or more source terminals of transistor TL2 are electrically connected to the source terminal of transistor TCL2. With this configuration, compared to a semiconductor device including only one upper clamping element and one lower clamping element, the increase in impedance of the wiring between the gate terminal and source terminal of the upper semiconductor element via the upper clamping element, and the wiring between the gate terminal and source terminal of the lower semiconductor element via the lower clamping element, can be suppressed. Therefore, the malfunction suppression effect can be improved.

[0055] To elaborate further, in a semiconductor device including an upper semiconductor element and a lower semiconductor element, when one of these semiconductor elements is turned on, a transient gate current flows through the other semiconductor element, causing a voltage rise at the gate terminal of the other semiconductor element. Therefore, when control is performed to turn on only one semiconductor element, there is a possibility that the other semiconductor element may also turn on. In such cases, to suppress the voltage rise at the gate terminal, for example, an upper clamping element and a lower clamping element are provided on the upper and lower semiconductor elements, respectively. The source terminal of the upper clamping element is electrically connected to the source terminals of all upper semiconductor elements. Similarly, the source terminal of the lower clamping element is electrically connected to the source terminals of all lower semiconductor elements. In such a case (a comparative example), for instance, as the number of semiconductor elements increases, the length of the wiring between the upper clamping element and the upper semiconductor element, and the length of the wiring between the lower clamping element and the lower semiconductor element, both increase. This results in an increase in the impedance of the wiring between the gate and source terminals of the upper semiconductor element and the lower semiconductor element. Consequently, the effectiveness of the clamping elements in suppressing voltage rise at the gate terminal decreases.

[0056] According to an embodiment, the semiconductor device 1 includes a plurality of transistor TCUs and a plurality of transistor TCLs. This allows for the suppression of increases in the length of the wiring between the upper clamping element and the upper semiconductor element, as well as the length of the wiring between the lower clamping element and the lower semiconductor element. In other words, by distributing the plurality of transistor TCUs and the plurality of transistor TCLs separately, the increase in wiring length within each transistor TCU and TCL can be suppressed. Therefore, the increase in impedance of the wiring between the gate and source terminals of the upper semiconductor element via the clamping element and the wiring between the gate and source terminals of the lower semiconductor element can be suppressed.

[0057] Furthermore, according to the embodiment, compared to the comparative example described above, the increase in the size of the semiconductor device 1 can be suppressed. To further explain, according to the embodiment, compared to the comparative example, the number of upper clamping elements relative to the number of upper semiconductor elements and the number of lower clamping elements relative to the number of lower semiconductor elements can be increased. This suppresses the increase in the on-resistance of both the upper and lower clamping elements. Therefore, compared to the comparative example, the increase in the size of both the upper and lower clamping elements can be suppressed. Thus, the increase in the size of the semiconductor device 1 is suppressed.

[0058] 2. Variations Next, the modified semiconductor device will be described. Hereinafter, descriptions of configurations identical to those in the embodiment will be omitted, and descriptions will primarily focus on configurations different from those in the embodiment.

[0059] 2.1 First Variation Example In this embodiment, an example is shown where multiple transistors TU and TL are configured such that the configuration of each transistor TU is the same when viewed from above, but this is not a limitation. The multiple transistors TU and TL can also be configured such that the configuration within each transistor TU is symmetrical to the configuration within each transistor TL in the Y direction.

[0060] use Figure 4 The configuration of the semiconductor device 1 in the first modified example will be described. Figure 4 This is a top view showing the configuration of the semiconductor device in the first modified example. Furthermore, the configurations of the plurality of transistors TU, TL, TCU and TCL, insulating component 10, and conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36 in the first modified example are the same as those in the embodiment, except for the configuration of each transistor TL.

[0061] like Figure 4As shown, in the first variation, the gate terminal of each transistor TL is, for example, located on the opposite side in the Y direction from the source terminal of the transistor TL. Thus, the source and gate terminals in each transistor TU are symmetrically arranged in the Y direction with the source and gate terminals in each transistor TL.

[0062] According to the first variation, it also achieves the same effect as the implementation method.

[0063] 2.2 Second variation In the embodiments and the first variation, an example is shown where the source terminal of transistor TCL is directly connected to the source terminal of transistor TL, but this is not a limitation. The source terminals of transistor TCL and transistor TL can also be indirectly connected via a conductor.

[0064] use Figure 5 The configuration of the semiconductor device 1 in the second modified example will be described. Figure 5 This is a top view showing the configuration of the semiconductor device in the second modification example. Furthermore, the configuration of the plurality of transistors TU, TL, TCU and TCL, insulating component 10, and conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35 and 36 in the second modification example is the same as those in the embodiment, except for the connection between the source terminals of transistor TCL and transistor TL.

[0065] like Figure 5 As shown, in the second variation, the source terminals of each transistor TCL are connected to the conductor 24 via wires. Thus, the source terminals of transistor TCL are indirectly connected to the source terminals of transistor TL via wires and conductor 24.

[0066] The lengths or average values ​​of the wires connecting the multiple transistors TCL to the conductor 24 are approximately equal.

[0067] According to the second variation, it also achieves the same effect as the implementation method and the first variation.

[0068] 2.3 Third variation In the embodiments, the first modification, and the second modification, a case is shown where multiple transistors TCU and TCL are both vertically oriented transistors, but this is not a limitation. The semiconductor device can also be a case where multiple transistors TCU and TCL are both horizontally oriented transistors. Hereinafter, the configuration of the semiconductor device in the third modification will be described, mainly focusing on the configuration that differs from the semiconductor devices in the embodiments, the first modification, and the second modification.

[0069] use Figure 6 and Figure 7 The configuration of the semiconductor device 1 in the third modified example will be described. Figure 6 This is a top view showing the configuration of the semiconductor device in the third variation. Figure 7 This is an example of the cross-sectional structure of a semiconductor device representing the third variation, along... Figure 6 A sectional view of line VII-VII.

[0070] The configuration of the plurality of transistors TU and TL, insulating component 10, and conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36 in the third modification example is the same as that in the embodiment. Hereinafter, the configuration of the plurality of transistors TCU and TCL will be mainly described.

[0071] In the third variation, the multiple transistors TCU and TCL are horizontally oriented transistors. That is, the source, drain, and gate terminals of each of the multiple transistors TCU and TCL are disposed on the upper surface of the transistor. The drain terminal of each transistor TCU is connected to conductor 22, for example, via a wire. The drain terminal of each transistor TCL is connected to conductor 25, for example, via a wire.

[0072] In addition, such as Figure 7 As shown, each transistor TCU is disposed on the upper surface of the conductor 22 via an adhesive member 51. The adhesive member 51 is an insulator that physically connects the lower surface of each transistor TCU to the conductor 22.

[0073] On the upper surface of the conductor 25, each transistor TCU is disposed via an adhesive member 52. The adhesive member 52 is an insulator that physically and electrically connects the drain terminals of each transistor TCU to the conductor 25.

[0074] According to the third variation, it also achieves the same effect as the implementation method, the first variation, and the second variation.

[0075] 2.4 Fourth Variation In the third variation, a case is shown where transistors TCU and TCL are mounted on a conductor via an insulator, but this is not the only variation. Transistors TCU and TCL can also be mounted via the same adhesive component as transistors TU and TL, instead of an insulator.

[0076] The configuration of the plurality of transistors TU, TL, TCU, and TCL, insulating component 10, and conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36 in the fourth modification is the same as that in the third modification, except for the arrangement of the plurality of TCUs and TCLs. The arrangement of the plurality of TCUs and TCLs will be described below.

[0077] In the fourth variation, multiple transistors TCU are disposed on the upper surface of conductor 23. Additionally, multiple transistors TCL are disposed on the upper surface of conductor 24. Furthermore, although not shown, the multiple transistors TCU and TCL are mounted on the upper surfaces of conductors 23 and 24 via adhesive members identical to those in the embodiment (adhesive members 41-44). Furthermore, the lower surface of each of the multiple transistors TCU is set to the same potential as the source terminal of transistor TU or is an insulator. Similarly, the lower surface of each of the multiple transistors TCL is set to the same potential as the source terminal of transistor TL or is an insulator.

[0078] According to the fourth variation, it also achieves the same effect as the implementation method, the first variation, the second variation, and the third variation.

[0079] Furthermore, according to the fourth modification, by mounting multiple transistors TCU on the upper surface of a conductor 23 connected to the source terminals of node AC and multiple transistors TU, and mounting multiple transistors TCL on the upper surface of a conductor 24 connected to the source terminals of node N and multiple transistors TL, the bonding component can be mounted on the upper surface of the conductor without the use of an insulator. This reduces the complexity of the manufacturing process.

[0080] 3 Other In the above-described embodiments, first modifications, second modifications, third modifications, and fourth modifications, the number of wires connecting one component to other components is only one or more, and the number of wires is not limited. Furthermore, the wires included in the semiconductor device 1 of the embodiments, first modifications, second modifications, third modifications, and fourth modifications can be replaced with other conductors. For example, the wires in the embodiments, first modifications, second modifications, third modifications, and fourth modifications can be replaced with conductors such as ribbons and lead frames.

[0081] Furthermore, in the second, third, and fourth modifications, examples are shown where the configurations of each transistor TU and each transistor TL are identical when viewed from above, similar to the embodiment, but this is not a limitation. Although not illustrated, in the second, third, and fourth modifications, the plurality of transistors TU and TL may also be arranged symmetrically in the Y direction with the source and gate terminals of each transistor TU and the source and gate terminals of each transistor TL, similar to the first modification.

[0082] Furthermore, in the first, third, and fourth modifications, similar to the embodiment, examples are shown where the source terminals of each transistor TCL are directly connected to the source terminals of the transistor TL via wires, but this is not a limitation. Although not illustrated, in the first, third, and fourth modifications, the source terminals of each transistor TCL can also be indirectly connected via conductor 24, similar to the second modification. That is, the source terminals of each transistor TCL can also be connected to conductor 24 via wires, thereby connecting to the source terminals of the transistor TL.

[0083] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, have: At least one first transistor and at least one second transistor, each having a first end connected to a first node and a second end connected to a second node; At least one third transistor and at least one fourth transistor each have a first end connected to the second node and a second end connected to the third node; The fifth transistor is provided corresponding to the at least one first transistor, and has a first end connected to the gate end of the at least one first transistor and a second end connected to the second node; A sixth transistor, provided corresponding to the at least one or more second transistors, has a first end connected to the gate end of the at least one or more second transistors and a second end connected to the second node; A seventh transistor, provided corresponding to the at least one or more third transistors, has a first end connected to the gate end of the at least one or more third transistors and a second end connected to the third node; as well as The eighth transistor, provided corresponding to the at least one or more fourth transistors, has a first end connected to the gate end of the at least one or more fourth transistors and a second end connected to the third node.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a plurality of the at least one first transistor and the at least one second transistor.

3. The semiconductor device according to claim 2, characterized in that, The second terminal of the fifth transistor is electrically connected to the second terminal of each of the at least one first transistor via a plurality of first conductors. The second terminal of the sixth transistor is electrically connected to the second terminal of each of the at least one second transistor via a plurality of second conductors.

4. The semiconductor device according to claim 3, characterized in that, The average length of the plurality of first conductors is approximately equal to the average length of the plurality of second conductors.

5. The semiconductor device according to claim 3, characterized in that, The plurality of first conductors and the plurality of second conductors are respectively wires, strips or lead frames.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes multiple third transistors and multiple fourth transistors.

7. The semiconductor device according to claim 6, characterized in that, The second terminal of the seventh transistor is electrically connected to the second terminal of each of the at least one third transistor via a plurality of first conductors. The second terminal of the eighth transistor is electrically connected to the second terminal of each of the at least one fourth transistor via a plurality of second conductors.

8. The semiconductor device according to claim 7, characterized in that, The average length of the plurality of first conductors is approximately equal to the average length of the plurality of second conductors.

9. The semiconductor device according to claim 1, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are respectively a MOS transistor (metal oxide semiconductor transistor) using silicon carbide (SiC), a MOS transistor using silicon (Si), an IGBT (insulated gate bipolar transistor) using silicon carbide (SiC), an IGBT using silicon (Si), or a transistor using gallium nitride (GaN).

10. The semiconductor device according to claim 1, characterized in that, The fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are respectively silicon (Si) MOS transistors or gallium nitride (GaN) transistors, and are either vertical or horizontal transistors.

11. The semiconductor device according to claim 1, characterized in that, The gate terminals of each of the at least one first transistor and the gate terminals of each of the at least one second transistor are connected to the fourth node. The gate terminals of each of the at least one third transistor and the gate terminals of each of the at least one fourth transistor are connected to the fifth node.

12. The semiconductor device according to claim 11, characterized in that, The gate terminals of the fifth transistor and the sixth transistor are connected to the sixth node. The gate terminals of the seventh transistor and the eighth transistor are connected to the seventh node.

13. The semiconductor device according to claim 12, characterized in that, The fourth node, the fifth node, the sixth node, and the seventh node are control terminals for receiving signals from the outside.

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