Imaging element and imaging device

Abstract

An imaging element includes: a plurality of pixels that output a signal based on a charge obtained by photoelectric conversion; a first signal processing unit having a first signal processing circuit that performs first signal processing for generating image data for display on signals output from the pixels; a second signal processing unit that includes a second signal processing circuit that performs second signal processing for generating image data for recording on a signal output from the pixel, and a recording circuit that records the signal subjected to the second signal processing; a first output unit that outputs a signal output from the first signal processing unit; and a second output unit that outputs the signal output from the second signal processing unit.

Description

Technical Field

[0001] This invention relates to imaging elements and imaging devices.

[0002] This application claims priority based on Japan Patent Application No. 2023-051434 filed on March 28, 2023, the contents of which are incorporated herein by reference. Background Technology

[0003] Imaging elements that simultaneously read live view images and still images are known (e.g., Patent Document 1). However, in the prior art, there is a problem of interruption in the display of the live view image.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2012-165193 Summary of the Invention

[0007] According to a first aspect of the present invention, an imaging element includes: a plurality of pixels that output signals based on charges obtained by photoelectric conversion; a first signal processing unit having a first signal processing circuit that performs first signal processing on the signals output from the pixels for generating image data for display; a second signal processing unit having a second signal processing circuit and a recording circuit that performs second signal processing on the signals output from the pixels for generating image data for recording, and the recording circuit records the signals on which the second signal processing has been performed; a first output unit that outputs the signals output from the first signal processing unit; and a second output unit that outputs the signals output from the second signal processing unit.

[0008] According to a second aspect of the present invention, the imaging device includes an imaging element of the first aspect and a display unit for displaying the image data. Attached Figure Description

[0009] Figure 1 This is a diagram showing an example of the configuration of a camera device equipped with the camera element of the first embodiment.

[0010] Figure 2 This is a diagram illustrating an example of the pixel configuration of the imaging element according to the first embodiment.

[0011] Figure 3 This is a diagram showing an example of the configuration of the processing unit of the camera element in the first embodiment.

[0012] Figure 4 This is a diagram illustrating an example of the operation of the camera element according to the first embodiment.

[0013] Figure 5 This is a diagram showing an example of the configuration of the processing unit of the camera element in the second embodiment.

[0014] Figure 6 This is a diagram illustrating an example of the operation of the camera element according to the second embodiment.

[0015] Figure 7 This is a diagram showing an example of the configuration of the processing unit of the camera element in the third embodiment.

[0016] Figure 8 This is a diagram illustrating an example of the operation of the camera element according to the third embodiment.

[0017] Figure 9 This is a diagram showing an example of the configuration of the processing unit of the camera element in a modified example of the third embodiment.

[0018] Figure 10 This is a diagram showing an example of the configuration of the processing unit of the camera element according to the fourth embodiment.

[0019] Figure 11 This is a diagram illustrating an example of the operation of the camera element according to the fourth embodiment.

[0020] Figure 12 This is a diagram illustrating an example of the operation of the imaging element in Modification 1 of the fourth embodiment.

[0021] Figure 13 This is a diagram illustrating an example of the operation of the camera element in Modification 2 of the fourth embodiment. Detailed Implementation

[0022] <First Implementation>

[0023] Hereinafter, the imaging element of the first embodiment of the present invention will be described with reference to the accompanying drawings. Figure 1 This is a diagram showing a schematic configuration of a camera device 1 equipped with the image sensor 100 of the first embodiment. The camera device 1 is, for example, a digital camera (or webcam), and includes an image optical system 10, an operation unit 20, a recording unit 30, a control unit 40, a display unit 50, and an image sensor 100.

[0024] The camera optical system 10 consists of multiple lenses, including a focus adjustment lens (focusing lens), and an aperture, which images the subject on the imaging surface of the imaging element 100. The operation unit 20 includes a release button, a recording button, and various setting switches. Operation signals corresponding to operations performed on the operation unit 20 are sent to a control unit 40, such as a CPU. The control unit 40 controls the operation of various components of the imaging device 1 based on the received operation signals. For example, the control unit 40 controls the camera optical system 10 and the imaging element 100. Furthermore, as described later, the control unit 40 sets the exposure period and the number of exposures.

[0025] The control unit 40 includes an image generation unit (LSI) 42. The image generation unit 42 generates live view (LV) image data, still image data, and moving image data based on image data output from the imaging element 100. The control unit 40 outputs the generated LV image data, still image data, or moving image data to the display unit 50. The LV image data output to the display unit 50 is an example of "image data for display." Additionally, the control unit 40 outputs the generated still image data or moving image data to the recording unit 30. The image data output to the recording unit 30 is an example of "image data for recording."

[0026] The display unit 50 is, for example, an electronic viewfinder (EVF) or a rear monitor. The display unit 50 displays images based on LV image data, still image data, and moving image data output from the control unit 40.

[0027] The recording unit 30 causes the recording medium, such as the memory card installed in the camera device 1, to record static image data and dynamic image data generated by the control unit 40.

[0028] The control unit 40 reads image data (still image data or moving image data) from the memory card according to the operation of the operation unit 20 performed by the user. The control unit 40 outputs the read image data to the display unit 50. The display unit 50 displays (plays) an image based on the image data output from the control unit 40.

[0029] The imaging element 100 is, for example, an image sensor such as a CCD or CMOS, which captures an image of a subject imaged by the imaging optical system 10. The imaging element 100 performs exposure (imaging) during the exposure period set by the control unit 40. The imaging element 100 has a plurality of pixels 110, a plurality of AD converters (AD conversion units) 120, and a processing unit 130. The plurality of pixels 110 are arranged in a two-dimensional (row and column direction) configuration in the imaging element 100. Each of the plurality of pixels 110 has a color filter, a photoelectric conversion unit 112, and a readout circuit. The color filter is, for example, an optical component that transmits light of specific wavelengths of R (red), G (green), and B (blue).

[0030] Pixel 110 receives the light beam passing through the imaging optical system 10 and outputs an analog signal corresponding to the amount of light received. The AD converter 120 converts the analog signal output from pixel 110 into a digital signal. The processing unit 130 processes the digital signal converted by the AD converter 120. It should be noted that... Figure 1 In this configuration, the AD converter 120 is represented as a single block, but the imaging element 100 contains multiple AD converters 120. The AD converters 120 are arranged in columns of pixels 110.

[0031] Figure 2 This diagram illustrates an example of the configuration of pixel 110. Pixel 110 has a photoelectric conversion unit 112 and a readout circuit 114. The photoelectric conversion unit 112 performs photoelectric conversion on incident light to generate and store electrical charge. The photoelectric conversion unit 112 is, for example, composed of a photodiode. The readout circuit 114 reads the pixel signal (analog signal) generated by the charge obtained through photoelectric conversion by the photoelectric conversion unit 112. The readout circuit 114 outputs the read pixel signal to the AD converter 120. The image data described above is generated based on multiple pixel signals converted into digital signals, each output from multiple pixels 110. It should be noted that the exposure period is the charge storage period during which the photoelectric conversion unit 112 performs photoelectric conversion on light and stores electrical charge.

[0032] The readout circuit 114 includes a transmission section 115, a discharge section 116, a floating diffusion section 117, and an output section 118. The transmission section 115 transmits the charge obtained by photoelectric conversion by the photoelectric conversion section 112 to the floating diffusion section 117. The floating diffusion section 117 stores the charge transmitted through the transmission section 115 after photoelectric conversion by the photoelectric conversion section 112. That is, the floating diffusion section 117 is a charge storage section.

[0033] The output unit 118 includes an amplification unit 118A, which functions as an amplification transistor, and a selection unit 118B, which functions as a selection transistor. The amplification unit 118A generates a pixel signal using the charge of the floating diffusion unit 117. The selection unit 118B controls the connection between the pixel 110 and the signal line 119. When the selection unit 118B is set to be on, the pixel signal generated by the amplification unit 118A is output to the signal line 119.

[0034] The discharge section 116 discharges the charge in the floating diffuser section 117 to the power supply VDD. By discharging the charge, the discharge section 116 resets the potential of the floating diffuser section 117 to the reference potential.

[0035] Figure 3This diagram illustrates an example of the configuration of the processing unit 130 of the imaging element 100. In the first embodiment, the processing unit 130 includes a first signal processing circuit 131, a first output circuit 132, a second signal processing circuit 133, a memory 134, and a second output circuit 135. Hereinafter, the combination of the first signal processing circuit 131 and the first output circuit 132 is sometimes referred to as the "first channel," and the combination of the second signal processing circuit 133, the memory 134, and the second output circuit 135 is sometimes referred to as the "second channel." In the first embodiment, the first channel is a circuit for outputting signals used to generate LV images. The second channel is a circuit for outputting signals used to generate still images. Furthermore, the first output circuit 132 is an example of a "first output unit." The second output circuit 135 is an example of a "second output circuit." Because the imaging element 100 has a first channel and a second channel, it can process the signals used for generating LV images and the signals used for generating still images simultaneously (in parallel), and can output them to the image generation unit 42 simultaneously (in parallel).

[0036] The first signal processing circuit 131 includes an inter-frame divider 131A, an inter-pixel divider 131B, and a pixel summer 131C. The first signal processing circuit 131 processes the digital signal output from the AD converter 120. The first signal processing circuit 131 receives a digital signal corresponding to a plurality of pixels 110 contained in the imaging area (effective pixel area) of the imaging element 100. The first signal processing circuit 131 performs first signal processing on the input digital signal using the inter-frame divider 131A, the inter-pixel divider 131B, and the pixel summer 131C.

[0037] The inter-frame division unit 131A performs inter-frame division processing on the input digital signal as a first signal processing step. Here, a frame refers to the frame (image data) used to generate LV image data, still image data, and moving image data. Frames are output from multiple pixels 110, and each frame is generated from multiple pixel signals converted into digital signals by the AD converter 120. In other words, the digital signal input to the first signal processing circuit 131 is the frame used to generate the image data, and the first signal processing circuit 131 performs first signal processing on the input frame. "Inter-frame division" means using only a portion of the multiple frames, or not using any other frames. Specifically, the inter-frame division unit 131A selects frames generated during a portion of the multiple frames generated during multiple exposure periods (for example, a "first period," a "second period," and a "third period"). Alternatively, the inter-frame division unit 131A does not select frames generated during a portion of the multiple frames generated during the multiple exposure periods. The inter-frame division unit 131A performs inter-frame division processing on multiple signals output during multiple exposure periods. By performing inter-frame division, the amount of image data to be processed is reduced, and the amount of image data output from the imaging element 100 is also reduced. It should be noted that the exposure period and the number of exposures are controlled by the control unit 40.

[0038] The pixel division unit 131B performs pixel division processing on the digital signals output from the AD converter 120 that correspond to the plurality of pixels 110 included in the imaging area, as a first signal processing step. Here, "pixel division" means using signals output from a portion of the pixels 110. Alternatively, it means not using signals output from other pixels 110. Specifically, the pixel division unit 131B selects pixel signals output from a portion of the pixels 110 from among the plurality of pixel signals output from the plurality of pixels 110 respectively during a specified exposure period. Alternatively, the pixel division unit 131B does not select pixel signals output from a portion of the plurality of pixel signals output from the plurality of pixels 110 respectively during the specified exposure period. The pixel division unit 131B performs pixel division processing on the plurality of signals output during multiple exposure periods (as an example of "first signal", "second signal" and "third signal"). Through the pixel division processing, the number of pixel signals to be processed is reduced, and the amount of image data output from the imaging element 100 is reduced.

[0039] The pixel addition unit 131C performs pixel addition processing on the input digital signal as a first signal processing step. Here, "pixel addition" means adding the signals output from any number of pixels (e.g., 3 pixels). Specifically, the pixel addition unit 131C adds the pixel signals output from a portion of the pixels 110 (e.g., 3 pixels) from a plurality of pixel signals output from a plurality of pixels 110 during a specified exposure period. By performing pixel division, the number of pixel signals to be processed is reduced, and the amount of image data output from the imaging element 100 is reduced.

[0040] In the first embodiment, after performing inter-frame division using the inter-frame division unit 131A, the first signal processing circuit 131 performs inter-pixel division using the inter-pixel division unit 131B or pixel addition using the pixel addition unit 131C. It should be noted that the order of inter-frame division, inter-pixel division, and pixel addition is not limited to this. The first signal processing circuit 131 may also perform inter-frame division using the inter-frame division unit 131A or pixel addition using the pixel addition unit 131C after performing inter-pixel division using the inter-pixel division unit 131B. Alternatively, the first signal processing circuit 131 may not perform all of the inter-frame division, inter-pixel division, and pixel addition processes. The first signal processing circuit 131 only needs to perform at least one of the inter-frame division, inter-pixel division, and pixel addition. Therefore, the first signal processing circuit 131 only needs to have at least one of the inter-frame division unit A, the inter-pixel division unit 131B, and the pixel addition unit C.

[0041] The inter-frame division, inter-pixel division, and pixel addition processes are implemented to reduce the amount of image data and lower the processing load. LV images rarely require high image quality. Therefore, LV image data does not need to be generated using all pixel signals (digital signals) output from the multiple pixels 110 contained in the imaging area. On the other hand, LV images require high-speed display of new images on the display unit 50. Therefore, the imaging element 100 is required to output image data at high speed. At the same time, the control unit 40 is required to generate LV image data at high speed. By performing the above processing on the imaging element 100, the amount of image data is reduced within the imaging element 100, so that the communication between the imaging element 100 and the control unit 40 (image generation unit 42) is less likely to be limited by the upper limit of the interface bandwidth. As a result, the imaging element 100 can output image data to the control unit 40 at high speed. In addition, since the amount of image data is small, the control unit 40 can reduce its processing load and generate LV image data at high speed.

[0042] After performing first signal processing on the input digital signal, the first signal processing circuit 131 outputs the processed digital signal (frame) to the first output circuit 132. The first output circuit 132 then outputs the digital signal (frame) output from the first signal processing circuit 131 to the image generation unit 42. Through the above processing in the first channel, a digital signal (frame) for generating an LV image is output to the image generation unit 42.

[0043] The second signal processing circuit 133 includes a frame summing unit 133A. The second signal processing circuit 133 processes the digital signal output from the AD converter 120. The second signal processing circuit 133 receives a digital signal corresponding to a pixel 110 contained in the imaging area of ​​the imaging element 100. The second signal processing circuit 133 performs second signal processing on the input digital signal using the frame summing unit 133A.

[0044] The frame summing unit 133A, acting as a second signal processing unit, performs summing processing on the digital signal output from the AD converter 120. In other words, the frame summing unit 133A performs summing processing on multiple input frames as a second signal processing unit. The frame summing unit 133A sums multiple frames generated in multiple exposures. Specifically, the second signal processing circuit 133 acquires the first frame generated during the first exposure period from the AD converter 120 and outputs it to the memory 134. The memory 134 stores the first frame output from the second signal processing circuit 133. The second signal processing circuit 133 acquires the second frame generated during the second exposure period following the first exposure period from the AD converter 120. At this time, the second output circuit 135 reads the first frame from the memory 134. The second output circuit 135 outputs the read first frame to the second signal processing circuit 133. The frame summing unit 133A adds the first frame and the second frame. The second signal processing circuit 133 outputs the first summed frame obtained by the summation to the memory 134. Memory 134 stores the first summed frame output from the second signal processing circuit 133. The second signal processing circuit 133 obtains the third frame generated by exposure during a third exposure period following the second exposure period from the AD converter 120. At this time, the second output circuit 135 reads the first summed frame from memory 134. The second output circuit 135 outputs the read first summed frame to the second signal processing circuit 133. The frame summing unit 133A adds the first summed frame to the third frame. The second signal processing circuit outputs the second summed frame obtained by the addition to memory 134. Memory 134 stores the second summed frame output from the second signal processing circuit 133. The second signal processing circuit 133, memory 134, and second output circuit 135 repeatedly perform the above processing, thereby enabling the frame summing unit 133A to add multiple frames generated during multiple exposure periods. The frame summing unit 133A performs the second signal processing of adding frames to the number of exposures set by the control unit 40. It should be noted that the exposure period and the number of exposures are controlled by the control unit 40.

[0045] After performing second signal processing on the input digital signal, the second signal processing circuit 133 outputs the processed digital signal (the frame obtained by addition) to the second output circuit 135. The second output circuit 135 outputs the digital signal (the frame obtained by addition) output from the second signal processing circuit 133 to the image generation unit 42. Through the above processing in the second channel, a digital signal (frame) for generating a still image is output to the image generation unit 42.

[0046] Figure 4 This is a diagram illustrating an example of the operation of the imaging element 100 according to the first embodiment. Figure 4This illustrates the output of still image data when the release button is pressed to capture a still image during the period when LV image data is being output (while the display unit 50 is displaying an LV image).

[0047] like Figure 4 As shown, LV image data is continuously output at regular time intervals, and LV images are continuously displayed on the display unit 50 at regular time intervals. The imaging element 100 of this embodiment outputs LV image data continuously at an interval of 8.34 ms, for example. In other words, the imaging element 100 continuously outputs frames for generating LV image data at a frame rate of 120 fps (frames per second). Therefore, the imaging element 100 repeatedly performs exposure / reading for a certain exposure period (e.g., 4.17 ms) at regular time intervals (8.34 ms). In other words, the imaging element 100 repeatedly performs exposure / reading for a certain exposure period at a frame rate of 120 fps. As mentioned above, LV images rarely require high image quality. Therefore, the imaging element 100 reads pixel signals only from a portion of the pixels 110 in the imaging area and outputs them to the AD converter 120 (inter-pixel reading). Alternatively, the imaging element 100 adds the pixel signals output from multiple pixels 110 and reads them, then outputs them to the AD converter 120 (pixel sum reading). The pixel signal output to the AD converter 120 is output to the first signal processing circuit 131. The first output circuit 132 outputs the signal output from the first signal processing circuit 131 to the image generation unit 42. The first channel outputs image data used to generate an LV image to the image generation unit 42.

[0048] It should be noted that the first signal processing circuit 131 does not perform the first signal processing on the pixel signal before the release button is pressed. However, the imaging element 100 may also output pixel signals from all pixels 110 included in the imaging area to the AD converter 120 without performing inter-pixel division or pixel addition readings. In this case, the first signal processing circuit 131 (inter-pixel division unit 131B or pixel addition unit 131C) performs the first signal processing (inter-pixel division processing or pixel addition processing) on ​​the pixel signal before the release button is pressed. Alternatively, the imaging element 100 may output frames for generating LV image data at a frame rate of 240fps. In this case, the imaging element 100 repeatedly performs exposure / reading for a certain exposure period (e.g., 4.17ms) at a certain time interval (e.g., 4.17ms). In this case, the first signal processing circuit 131 (inter-frame division unit A) performs the first signal processing (inter-frame division processing).

[0049] When the release button is pressed to capture a still image, the image sensor 100 continuously outputs frames for generating LV image data and still image data. Therefore, the image sensor 100 repeatedly performs exposure / readout for a certain exposure period (e.g., 4.17ms) at regular time intervals (e.g., 4.17ms). In other words, the image sensor 100 repeatedly performs exposure / readout for a certain exposure period at a frame rate of 240fps. Additionally, when the release button is pressed, the image sensor 100 outputs pixel signals from all pixels 110 contained in the imaging area to the AD converter 120. The pixel signals output to the AD converter 120 are output to the first signal processing circuit 131. The first output circuit 132 outputs the signal output from the first signal processing circuit 131 to the image generation unit 42. The first channel outputs image data for generating the LV image to the image generation unit 42.

[0050] It should be noted that the first signal processing circuit 131 does not perform first signal processing on the pixel signal before the release button is pressed. However, the imaging element 100 may also output pixel signals to the AD converter 120 from all pixels 110 included in the imaging area without performing inter-pixel division or pixel addition. In this case, the first signal processing circuit 131 (inter-pixel division unit 131B or pixel addition unit 131C) also performs first signal processing (inter-pixel division or pixel addition) on the pixel signal before the release button is pressed. Figure 4 The image sensor 100 is shown as an example of continuously performing six exposures / reads within a certain exposure period. The image sensor 100 continuously performs six exposures / reads, sequentially outputting six frames for generating an LV image and a still image. Furthermore, if the release button is pressed, the image sensor 100 exposes all pixels contained in the imaging area and outputs pixel signals. The six frames are sequentially output to the first channel and the second channel.

[0051] Here, the reason why the imaging element 100 continuously performs six exposures / reads for a certain exposure period will be explained. When capturing a still image of a dark subject, the exposure period of the imaging element 100 is sometimes longer than the exposure period used to acquire the LV image. If the exposure period for capturing the still image is, for example, 25 ms, then the exposure period of the imaging element 100 is longer than the exposure period for acquiring the LV image (4.17 ms). If the exposure period is longer than the exposure period for acquiring the LV image, the imaging element 100 cannot perform the repeated exposures / reads to acquire the LV image as it did before the release button was pressed. In other words, the imaging element 100 cannot continuously output LV image data at a certain time interval (8.34 ms). As a result, the imaging device 1 cannot continuously display the LV image on the display unit 50. Or, the frame rate (120 fps) at which the imaging device 1 displays the LV image on the display unit 50 becomes slower compared to before the release button was pressed. Therefore, in this embodiment, a still image with an exposure period of 25ms is obtained by adding six frames (4.17 × 6 = 25.02ms). This allows for capturing a still image while maintaining the display of the LV image. It should be noted that the exposure period of the still image and the number of frames added are not limited to these. The exposure period of the still image and the number of frames added are appropriately set by the control unit 40 based on the shooting conditions (brightness of the subject, etc.).

[0052] The six frames sequentially output to the first channel undergo first signal processing (inter-frame division, inter-pixel division, and pixel addition) by the first signal processing circuit 131 (inter-frame division unit 131A, inter-pixel division unit 131B, and pixel addition unit 131C). The first signal processing circuit 131 performs first signal processing on the input frames and outputs them to the first output circuit 132. The first output circuit 132 outputs the frames that have undergone first signal processing to the image generation unit 42. The first channel outputs image data used to generate the LV image to the image generation unit 42. It should be noted that the six frames sequentially output to the first channel are inter-divided by the inter-frame division unit 131A. The result is as follows: Figure 4 As shown, the frames output to the first channel are continuously output at a frame rate of 120fps, just like before the release button is pressed.

[0053] The six frames output to the second channel undergo second signal processing (frame addition) by the second signal processing circuit 133 (frame addition unit 133A). The second signal processing circuit 133 performs second signal processing on the input frames and outputs them to the second output circuit 135. The second output circuit 135 outputs the frames that have undergone second signal processing to the image generation unit 42. The second channel outputs image data used to generate still images to the image generation unit 42.

[0054] According to the first embodiment, even when the release button is pressed, the imaging element 100 repeatedly performs exposure / reading for the same exposure period as before the release button was pressed. Therefore, the imaging element 100 can continuously output LV image data in the same manner as before the release button was pressed, and the imaging device 1 can display the LV image on the display unit 50.

[0055] According to the first embodiment, if the release button is pressed, the imaging element 100 performs inter-frame division processing via the inter-frame division unit 131A. Therefore, even if the imaging element 100 is exposed / read at a frame rate of 240fps, the imaging element 100 can continuously output frames to the first channel at a frame rate of 120fps, just as before the release button was pressed. Therefore, the processing load of the control unit 40 can be reduced. Furthermore, if the release button is pressed, the imaging element 100 performs inter-pixel division processing or pixel addition processing via the pixel division unit 131B or the pixel addition unit 131C. Therefore, even if all pixels in the imaging area of ​​the imaging element 100 output pixel signals, the imaging element 100 can output frames to the first channel at high speed with the same amount of image data as before the release button was pressed. Therefore, the processing load of the control unit 40 can be reduced, and the control unit 40 can generate LV image data at high speed. Therefore, even if a still image is captured while displaying an LV image, the display unit 50 can display the LV image at high speed without interrupting the display of the LV image.

[0056] According to the first embodiment, the imaging element 100 adds multiple frames together via the frame summing unit 133A. Therefore, even if the subject is dark, the imaging device 1 obtains an image comparable to a still image with a long exposure time. In order to capture a still image of a dark subject, the imaging device 1 can capture a still image even if the exposure period of the imaging element 100 is longer than the exposure period used to obtain an LV image. In other words, the imaging device 1 can capture a still image while maintaining the display of an LV image.

[0057] According to the first embodiment, the imaging element 100 processes multiple frames in parallel in the first and second channels, and outputs still image data and LV image data in parallel. Therefore, even if the release button is pressed, the imaging device 1 can continuously display the LV image without interruption, just as before the release button was pressed. Furthermore, the imaging device 1 can record still image data in the recording unit 30.

[0058] According to the first embodiment, the processing unit 130 is mounted on the imaging element 100 (on-chip) rather than on the image generation unit 42. Therefore, the imaging element 100 can reduce the amount of LV image data or still image data internally before outputting it to the image generation unit 42. Consequently, the time interval for outputting LV image data or still image data is less likely to be limited by the upper limit of the bandwidth of the interface between the imaging element 100 and the image generation unit 42. Therefore, the number of exposures per unit time (number of shots per unit time) for obtaining LV image data and still image data can be increased. If the number of exposures per unit time increases, the number of frames output per unit time increases, thus enabling faster processing for generating still image data.

[0059] <Second Implementation>

[0060] The imaging element 100 of the first embodiment adds multiple frames output to the second channel from the frames output to the first and second channels, thereby achieving both LV image display and still image data recording. The imaging element 100A of the second embodiment also adds the frames output to the first channel.

[0061] Figure 5 This diagram illustrates an example of the configuration of the processing unit 130 of the imaging element 100A according to the second embodiment. In the second embodiment, the configuration of the second channel of the processing unit 130 is the same as that of the second channel of the processing unit 130 in the first embodiment. On the other hand, the first channel of the processing unit 130 further includes an adder circuit 136 and a memory 137 in addition to the first signal processing circuit 131 and the first output circuit 132. It should be noted that in this embodiment, the frame processed using the first channel is called an LV image frame, and the frame processed using the second channel is called a still image frame.

[0062] Adder circuit 136 performs addition processing on the LV image frames output from first signal processing circuit 131. Adder circuit 136 adds multiple LV image frames generated in multiple exposures. Specifically, first signal processing circuit 131 obtains a first frame generated during the first exposure period from AD converter 120 and performs first signal processing. First signal processing circuit 131 outputs the first LV image frame with first signal processing performed to memory 137 via adder circuit 136. Memory 137 stores the first LV image frame output from first signal processing circuit 131. First signal processing circuit 131 obtains a second frame generated during the second exposure period after the first exposure period from AD converter 120 and performs first signal processing. First signal processing circuit 131 outputs the second LV image frame with first signal processing performed to adder circuit 136. At this time, first output circuit 132 reads the first LV image frame from memory 137. First output circuit 132 outputs the read first LV image frame to adder circuit 136. Adder circuit 136 adds the first LV image frame to the second LV image frame. Adder circuit 136 outputs the first added LV image frame obtained by the addition to memory 137. Memory 137 stores the first added LV image frame output from adder circuit 136. First signal processing circuit 131 obtains the third frame generated by exposure during the third exposure period following the second exposure period from AD converter 120 and performs first signal processing. First signal processing circuit 131 outputs the third LV image frame with the first signal processing performed to adder circuit 136. At this time, first output circuit 132 reads the first added LV image frame from memory 137. First output circuit 132 outputs the read first added LV image frame to adder circuit 136. Adder circuit 136 adds the first added LV image frame to the third LV image frame. Adder circuit 136 outputs the second added LV image frame obtained by the addition to memory 137. Memory 137 stores the second added LV image frame output from adder circuit 136. The first signal processing circuit 131, the adder circuit 136, the memory 137, and the first output circuit 132 repeatedly perform the above-described processing, thereby enabling the adder circuit 136 to add multiple LV image frames generated during multiple exposure periods. The adder circuit 136A performs the process of adding frames based on the number of exposures set by the control unit 40. It should be noted that the exposure period and the number of exposures are controlled by the control unit 40. Through the above processing in the first channel, image data for generating an LV image is output to the image generation unit 42. The second signal processing circuit, the memory 134, and the second output circuit 135 perform the same processing on the still image frames as in the first embodiment.

[0063] Figure 6 This is a diagram illustrating an example of the operation of the camera element 100A according to the second embodiment. Figure 6This shows the output of static image data when the release button is pressed during the period when LV image data is being output (while the display unit 50 is displaying an LV image).

[0064] like Figure 6 As shown, LV image data is continuously output at certain time intervals, and LV images are continuously displayed on the display unit 50 at certain time intervals. The imaging element 100 of this embodiment outputs LV image data continuously at an interval of 16.68 ms, for example. In other words, the imaging element 100 continuously outputs frames for generating LV image data at a frame rate of 60 fps. Therefore, the imaging element 100 repeatedly performs exposure / readout for a certain exposure period (e.g., 4.17 ms). In other words, the imaging element 100 repeatedly performs exposure / readout for a certain exposure period at a frame rate of 240 fps. The adder circuit 136 adds the frames output from the first signal processing circuit 131 sequentially. The first output circuit 132 outputs the frame obtained by adding four frames as LV image data to the image generation unit 42. This is because, in the case of capturing a still image of a dark subject, for example, during an exposure period of 4.17 ms, sometimes the charge accumulation in the photoelectric conversion unit 112 is insufficient, making it impossible to output an LV image of sufficient quality. Unlike the first embodiment, by adding the four frames together by the adder circuit 136 and outputting them as an LV image, a high-quality LV image can be displayed even when the subject is dark.

[0065] When the release button is pressed to capture a still image, the imaging element 100 continuously outputs frames for generating still image data. That is, the imaging element 100 sequentially outputs six frames that are exposed / read at regular intervals (e.g., 4.17 ms). The six frames output to the second channel undergo second signal processing (frame addition) by the second signal processing circuit 133 (frame addition unit 133A). The second signal processing circuit 133 performs second signal processing on the input frames and outputs them to the second output circuit 135. The second output circuit 135 outputs the frames that have undergone second signal processing to the image generation unit 42. The second channel outputs image data for generating a still image to the image generation unit 42.

[0066] According to the second embodiment, the imaging element 100A performs addition processing on the frames used to generate the LV image. As a result, the noise in the LV image data is averaged out, and compared to when no addition processing is performed, the imaging device 1 can obtain LV image data with reduced noise. Therefore, the display unit 50 can display a high-quality LV image.

[0067] Furthermore, according to the second embodiment, by performing addition processing on the frames used to generate the LV image, the display unit 50 is able to display an LV image that increases the signal value of the LV image data. Therefore, even with a dark subject, the user can identify the subject in the LV image.

[0068] <Third Implementation Method>

[0069] The imaging element 100 of the first embodiment and 100A of the second embodiment output frames for generating still images to the second channel and perform summation processing after the release button of the operation unit 20 is pressed (fully pressed). However, in actual shooting situations, a time lag sometimes occurs between the timing when the user feels they want to take a still image and the timing when the user fully presses the release button. That is, the timing when the user feels they want to take a still image is sometimes earlier than the timing when the user fully presses the release button. The imaging element 100B of the third embodiment detects the case where the release button is half-pressed and performs summation processing on frames for generating still images that are output during a predetermined period earlier than the timing when the release button is fully pressed.

[0070] Figure 7 This diagram illustrates an example of the configuration of the processing unit 130 of the imaging element 100B according to the third embodiment. In the third embodiment, the configuration of the first channel of the processing unit 130 is the same as that of the first channel of the processing unit 130 in the first embodiment. On the other hand, the second channel of the processing unit 130 further includes a write circuit 138, a selection circuit 139, a memory 140, and a read circuit 141 in addition to the second signal processing circuit 133 and the second output circuit 135. It should be noted that the half-press / full-press of the release button of the operation unit 20 is detected by the control unit 40 based on the user's operation of the release button.

[0071] When a half-press of the release button is detected, the write circuit 138 sequentially outputs frames to the second channel and stores them sequentially in the memory 140 selected by the selection circuit 139.

[0072] Memory 140 is capable of storing multiple frames output to the second channel. During the period when the release button is half-pressed, memory 140 stores the frames output to the second channel in the order they were output. When a full press of the release button is detected, read circuit 141 reads from memory 140 multiple frames output to the second channel a predetermined period earlier than the timing of the full press detection. Read circuit 141 also reads from memory 140 multiple frames output to the second channel and stored in memory 140 between the timing of the full press detection and the timing of the full press detection. Read circuit 141 outputs the read multiple frames to the second signal processing circuit 133.

[0073] The second signal processing circuit 133 uses a frame summing unit 133A to perform second signal processing on multiple frames output from the readout circuit 141. The second signal processing circuit 133 performs summing processing on the multiple frames output from the readout circuit 141 as a second signal processing step. The frame summing unit 133A performs second signal processing by summing the number of frames set by the control unit 40. The second signal processing circuit 133 outputs the summed frames to the second output circuit 135. The second output circuit 135 outputs the frames output from the second signal processing circuit 133 to the image generation unit 42. Through the above processing in the second channel, frames for generating still images are output to the image generation unit 42.

[0074] Figure 8 This is a diagram illustrating an example of the operation of the camera element 100B according to the third embodiment. Figure 8 This shows the output of still image data when the release button is half-pressed during the period when the display unit 50 displays an LV image, and the half-pressed state continues for a predetermined period, and then the release button is fully pressed in order to perform still image capture.

[0075] It should be noted that, Figure 8 The operation of the camera element 100B is the same as that of the camera element 100 in the first embodiment, except for the operations related to the half-press and full-press of the release button. The differences in operation from the camera element 100 in the first embodiment will be explained below.

[0076] When a half-press of the release button is detected, the imaging element 100 continuously outputs frames for generating LV image data and still image data. The continuously output frames are sequentially output to the first and second channels. The multiple frames output to the second channel are stored in the memory 140 in time sequence. It should be noted that the multiple frames output to the first channel are the same as in the first embodiment, so the description is omitted.

[0077] When the release button is detected to be fully pressed after being half-pressed, the reading circuit 141 reads six frames from the memory 140, starting from the frame three frames prior to the timer that detected the full press. The reading circuit 141 outputs the read frames to the second signal processing circuit 133. When six frames are input from the reading circuit 141, the second signal processing circuit 133 adds the six frames together via the frame adder 133A. The second signal processing circuit 133 outputs the frame obtained by the addition to the second output circuit 135. The second output circuit 135 outputs the frame input from the second signal processing circuit 133 to the image generation unit 42.

[0078] According to the third embodiment, when the camera element 100B detects a half-press of the release button, it stores multiple frames in the memory 140 starting from the timing of the half-press detection. Then, when the release button is fully pressed, the camera element 100B adds the multiple frames stored in the memory 140, starting with the frame output a predetermined period earlier than the timing of the full press detection. Thus, the camera device 1 can obtain static image data that eliminates the time lag between the actual release timing and the user-desired release timing.

[0079] <Modifications of the Third Embodiment>

[0080] In the third embodiment, the second signal processing circuit 133 of the imaging element 100B simultaneously inputs multiple frames from the reading circuit 141, and the frame summing unit 133A adds the input multiple frames together. However, the method of frame input and summing is not limited to this configuration. In a modified example of the third embodiment, the second signal processing circuit 133 of the imaging element 100B includes a memory 133B. The second signal processing circuit 133 sums the frames by storing the multiple frames sequentially input from the reading circuit 141 in the memory 133B.

[0081] Figure 9 This is a diagram illustrating an example of the configuration of the processing unit 130 of the imaging element 100 in a modified example of the third embodiment. (See diagram below.) Figure 9 As shown, in the modified embodiment of the third embodiment, when the image sensor 100B's readout circuit 141 detects a full press of the release button, it sequentially reads multiple frames from the memory 140, starting with a frame output a predetermined period earlier than the timing of the full press detection. The readout circuit 141 sequentially inputs the read frames to the second signal processing circuit 133. The second signal processing circuit 133 sequentially stores the input frames in the memory 133B and adds them together. The second signal processing circuit 133 outputs the frame obtained by adding the frames in the memory 133B to the second output circuit 135. With this configuration, similar to the third embodiment, it is possible to obtain static image data that eliminates the time lag between the actual release timing and the desired release timing.

[0082] <Fourth Implementation>

[0083] In the first to third embodiments, by performing successive addition processing on the frames output to the second channel according to the time-division exposure time, a still image for recording is generated without interrupting the LV display of the display unit 50. The fourth embodiment balances the maintenance of the LV display and the recording of the still image, and applies the remaining frames to other processing.

[0084] Figure 10This diagram illustrates an example of the configuration of the processing unit 130 of the imaging element 100C according to the fourth embodiment. In the fourth embodiment, the configuration of the first channel of the processing unit 130 is the same as that of the first channel of the processing unit 130 in the first embodiment. On the other hand, regarding the second channel of the processing unit 130, the second signal processing circuit 133 replaces the frame summing unit 133A and has a reading unit 133C and a motion vector discrimination unit 133D.

[0085] The reading unit 133C reads frames stored in the memory 140 at a predetermined frame rate and outputs the read frames to the second output circuit 135. The second output circuit 135 outputs the frames received from the reading unit 133C as still images for recording to the image generation unit 42. The motion vector discrimination unit 133D discriminates motion vectors based on the frames stored in the memory 140 and outputs a signal representing the pixel region corresponding to the motion vector to the second output circuit 135. The second output circuit 135 outputs the received signal as a frame corresponding to a locally magnified image to the image generation unit 42.

[0086] Figure 11 This is a diagram illustrating an example of the operation of the imaging element 100C according to the fourth embodiment. Figure 11 As shown, each pixel 110 of the imaging element 100 is divided into a certain time-division exposure time (e.g., a 4.17ms interval) for exposure. Frames corresponding to still images for recording are output to the memory 134 of the second channel, and after being read by the read-out unit 133C at a frame rate of 20fps, they are output to the image generation unit 42. Frames corresponding to LV images for display are output to the first channel at intervals of 16.7ms (=4.17×4), and after performing the first signal processing, they are output to the image generation unit 42. Other frames are output to the memory 134 of the second channel as frames corresponding to locally magnified images. After motion vector discrimination is performed by the motion vector discrimination unit 133D, frames representing the pixel area corresponding to the motion vector (in the figure, the pixel area corresponding to 3000px×2000px) are output to the image generation unit 42.

[0087] According to the fourth embodiment, it is possible to apply the remaining frames to other processing while maintaining the LV display and recording static images.

[0088] <Modification 1 of the Fourth Embodiment>

[0089] In the fourth embodiment, while maintaining the LV display and recording still images, the remaining frames are used to generate a magnified image related to a moving part. However, the generation of the magnified image is not limited to a single moving part. A variation of the fourth embodiment, 1, generates two magnified images related to two moving parts while maintaining the LV display and recording still images. The configuration of the imaging element 100 is the same as in the fourth embodiment, therefore, illustrations are omitted.

[0090] Figure 12 This is a diagram illustrating an example of the operation of the imaging element 100C, a modified example of the fourth embodiment. (See diagram below.) Figure 12 As shown, each pixel 110 of the imaging element 100 is divided into a certain time-division exposure time (e.g., 2.08ms interval) for exposure. Frames corresponding to still images for recording are output to the memory 134 of the second channel, and after being read by the read-out unit 133C at a frame rate of 20fps, they are output to the image generation unit 42. Frames corresponding to LV images for display are output to the first channel at intervals of 16.7ms (=4.17×4), and after being subjected to the first signal processing, they are output to the image generation unit 42. Other frames are output to the memory 134 of the second channel as frames corresponding to locally magnified images. After the motion vector discrimination unit 133D identifies two motion vectors, frames representing the two pixel regions corresponding to the two motion vectors (in the figure, the two pixel regions corresponding to 1500px×1000px) are output to the image generation unit 42.

[0091] According to Variation 1 of the fourth embodiment, multiple magnified images can be generated while maintaining LV display and recording static images. It should be noted that in this variation, the generation of two magnified images related to two moving parts is described, but the present invention is not limited to this configuration. When multiple magnified images related to three or more moving parts are generated, the frames corresponding to the magnified images are also output to the memory 134 of the second channel at a predetermined frame rate, thereby representing frames representing multiple pixel regions corresponding to multiple motion vectors being output to the image generation unit 42.

[0092] <Modification 2 of the Fourth Embodiment>

[0093] In the fourth embodiment and its variation 1, the remaining frames are used for generating locally magnified images while maintaining the LV display and recording still images. However, the application of the remaining frames is not limited to generating locally magnified images. Variation 2 of the fourth embodiment can detect flicker while maintaining the LV display and recording still images. Figure 10In the configuration shown, the camera element 100C of the fourth embodiment, in variation 2, replaces the motion vector discrimination unit 133D and has a flicker detection unit.

[0094] Figure 13 This is a diagram illustrating an example of the operation of the imaging element 100C, a modified example of the fourth embodiment. (See diagram below.) Figure 13 As shown, each pixel 110 of the imaging element 100 is divided into a certain time-division exposure time (e.g., 1.04ms interval) for exposure. Frames corresponding to still images for recording are output to the memory 134 of the second channel, and after being read by the read-out unit 133C at a frame rate of 20fps, they are output to the image generation unit 42. Frames corresponding to LV images for display are output to the first channel at 16.7ms intervals (=4.17×4), and after performing the first signal processing, they are output to the image generation unit 42. Other frames are output to the memory 134 of the second channel as frames corresponding to images for flicker detection. The flicker detection unit detects the period of brightness change of the light source, i.e., flicker, based on these frames. The flicker detection unit outputs a frame representing the pixel area corresponding to the detected flicker (in the figure, two pixel areas corresponding to 1500px×1000px) to the second output circuit 135. The second output circuit 135 outputs the frame representing the flicker to the image generation unit 42. At this time, the frame indicating flicker is also output to a control unit located outside the imaging element 100. The control unit can also control the imaging element 100 based on the received frame, for example, by adjusting the shutter speed, to eliminate flicker. Alternatively, the frame indicating flicker is also output to a control unit located inside the imaging element 100, such as a vertical scanning circuit, and the control unit can also control the imaging element 100 to eliminate flicker.

[0095] According to a variation of the fourth embodiment, flicker can be detected while maintaining the LV display and recording static images.

[0096] <Modification 3 of the Fourth Embodiment>

[0097] In the fourth embodiment, the second signal processing circuit 133 for recording still images reads the remaining frames from the AD converter 120 and uses them for generating a partially magnified image or detecting flicker. That is, the second signal processing circuit 133 reads both the frames used for recording still images and the remaining frames used for generating a partially magnified image or detecting flicker. However, the present invention is not limited to this configuration. As a variation 3 of the fourth embodiment, the processing unit 130 may also independently include the second signal processing circuit 133 for recording still images and the third signal processing circuit for generating a partially magnified image or detecting flicker. In this case, the processing unit 130 may also further include a third output unit that outputs the signal output by the third signal processing circuit to the image generation unit 42.

[0098] At this time, the processing unit 130 has a first signal processing circuit 131, a first output circuit 132, a second signal processing circuit 133, a second output circuit 135, a third signal processing circuit, and a third output unit. However, alternatively, the processing unit 130 may not have the second signal processing circuit 133 and the second output circuit 135 for recording still images, but only has the first signal processing circuit 131, the first output circuit 132, the third signal processing circuit, and the third output unit.

[0099] It should be noted that, in the embodiment described above, as the first signal processing, the first signal processing circuit 131 outputs a portion of the multiple signals output from the AD converter 120 to the image generation unit 42. However, the present invention is not limited to this configuration; as the first signal processing, the first signal processing circuit 131 may also perform predetermined processing on a portion of the multiple signals output from the AD converter 120. In this case, as the first signal processing, the first signal processing circuit 131 may also perform processing such as development processing, color interpolation processing, and grayscale correction on that portion of the signal.

[0100] Furthermore, in the embodiment described above, the second signal processing circuit 133 adds together frames from multiple different exposure periods output from the AD converter 120 as the second signal processing. However, the present invention is not limited to this configuration. As the second signal processing, the second signal processing circuit 133 may also perform, for example, the process of recording (outputting) the added frames to a recording circuit. Furthermore, as the second signal processing, the second signal processing circuit 133 may also perform development processing, color interpolation processing, grayscale correction, etc., on the added frames or the multiple frames before addition.

[0101] Furthermore, in the embodiments described above, each component of the pixel 110 and the processing unit 130 is disposed on a single substrate. However, the present invention is not limited to this configuration, and each component of the pixel 110 and the processing unit 130 may also be disposed on multiple substrates bonded to each other. In other words, the imaging element 100 may also have a stacked structure of multiple substrates.

[0102] For example, the camera element 100 may have a first substrate having a plurality of pixels 110, and a second substrate bonded to the first substrate and having a plurality of AD converters 120 and a processing unit 130. Alternatively, the camera element 100 may have a first substrate having a plurality of pixels 110 and a plurality of AD converters 120, and a second substrate bonded to the first substrate and having a processing unit 130. Alternatively, the camera element 100 may have a first substrate having a plurality of pixels 110, a plurality of AD converters 120, a first signal processing circuit 131 and a first output circuit 132, and a second substrate bonded to the first substrate and having a second signal processing circuit 133 and a second output circuit 135.

[0103] Furthermore, the image sensor 100 is not limited to a two-layer structure; it may also have a three-, four-, or more-layered stacked structure. For example, the image sensor 100 may have a first substrate with a plurality of pixels 110, a second substrate bonded to the first substrate and having a plurality of AD converters 120, and a third substrate bonded to the second substrate and having a processing unit 130. Alternatively, the image sensor 100 may have a first substrate with a plurality of pixels 110 and a plurality of AD converters 120, a second substrate bonded to the first substrate and having a first signal processing circuit 131 and a first output circuit 132, and a third substrate bonded to the second substrate and having a second signal processing circuit 133 and a second output circuit 135. Alternatively, the image sensor 100 may have a first substrate with a plurality of pixels 110, a second substrate bonded to the first substrate and having a plurality of AD converters 120, a third substrate bonded to the second substrate and having a first signal processing circuit 131 and a first output circuit 132, and a fourth substrate bonded to the third substrate and having a second signal processing circuit 133 and a second output circuit 135. The constituent elements of the pixel 110 and the processing unit 130 can be arranged on any number of substrates in any combination.

[0104] The above embodiments illustrate the methods for implementing the present invention, but the present invention is not limited to these embodiments and various modifications and substitutions can be made without departing from the spirit of the present invention.

[0105] Explanation of reference numerals in the attached figures

[0106] 10 Camera optical system, 20 Operation unit, 30 Recording unit, 40 Control unit, 42 Image generation unit, 50 Display unit, 100 Camera element, 110 Pixel, 112 Photoelectric conversion unit, 120 AD converter, 130 Processing unit, 131 First signal processing circuit, 131A Inter-frame divider, 131B Inter-pixel divider, 132 First output circuit, 133 Second signal processing circuit, 133A Frame adder, 133B Memory, 133C Reader, 133D Motion vector discrimination unit, 134 Memory, 135 Second output circuit, 136 Adder circuit, 137 Memory, 138 Write circuit, 139 Selection circuit, 140 Memory, 141 Reader circuit.

Claims

1. A camera element, comprising: Multiple pixels, whose output is a signal based on the charge obtained by photoelectric conversion; A first signal processing unit has a first signal processing circuit, which performs first signal processing on a signal output from the pixel for generating image data for display. The second signal processing unit has a second signal processing circuit and a recording circuit. The second signal processing circuit performs second signal processing on the signal output from the pixel to generate image data for recording. The recording circuit records the signal that has been subjected to the second signal processing. The first output unit outputs the signal output from the first signal processing unit; as well as The second output unit outputs the signal from the second signal processing unit.

2. The imaging element according to claim 1, wherein, While the first signal processing unit performs the first signal processing on the signal output from the pixel, the second signal processing unit performs the second signal processing on the signal output from the pixel.

3. The imaging element according to claim 1, wherein, During the period when the first signal processing unit performs the first signal processing on the signal output from the pixel, the second signal processing unit performs the second signal processing on the signal output from the pixel and records the signal that has undergone the second signal processing in the recording circuit.

4. The imaging element according to claim 1, wherein, The second output unit outputs the signal recorded in the recording circuit.

5. The imaging element according to claim 1, wherein, During the period when the first output unit outputs the signal output from the first signal processing unit, the second output unit outputs the signal output from the second signal processing unit.

6. The imaging element according to claim 1, wherein, The pixel output is based on a first signal of charge obtained by photoelectric conversion during a first period and a second signal of charge obtained by photoelectric conversion during a second period after the first period. The second signal processing unit adds the first signal and the second signal as the second signal processing.

7. The imaging element according to claim 6, wherein, The first signal processing unit outputs the first signal, one of the first signal and the second signal, to the first output unit as the first signal processing unit.

8. The imaging element according to claim 1, wherein, The pixel output is based on a first signal of charge obtained by photoelectric conversion during a first period and a third signal of charge obtained by photoelectric conversion during a third period prior to the first period. The second signal processing unit adds the first signal to the third signal as the second signal processing.

9. The imaging element according to claim 6, wherein, The pixel outputs the first signal based on the charge obtained by photoelectric conversion during the first period, which begins from the time an operation is received by the operation unit, which is operated to generate image data for recording.

10. The imaging element according to claim 8, wherein, The first signal processing unit outputs the first signal, one of the first signal and the third signal, to the first output unit as the first signal processing unit.

11. The imaging element according to claim 6, wherein, The plurality of said pixels have a first pixel and a second pixel, The first signal processing unit outputs the signal output from the first pixel to the first output unit, which is one of the signals output from the first pixel and the second pixel during the first period, as the first signal processing unit.

12. The imaging element according to claim 6, wherein, The plurality of said pixels have a first pixel and a second pixel, The first signal processing unit, as the first signal processing, adds the signal output from the first pixel and the signal output from the second pixel during the first period.

13. The imaging element according to claim 11 or 12, wherein, The first signal processing unit adds the first signal, which has undergone the first signal processing, to the second signal.

14. The imaging element according to claim 1, comprising: A third signal processing unit has a third signal processing circuit that performs third signal processing on the signal output from the pixel for generating dynamic image data. as well as The third output unit outputs the signal from the third signal processing unit. The first signal processing unit performs the first signal processing on signals output from the plurality of pixels contained in the first region and the second region. The third signal processing unit performs the third signal processing on the signals output from the plurality of pixels contained in the first region.

15. The imaging element according to claim 1, comprising: A detection unit for detecting the periodicity of changes in the brightness of a light source; as well as A third output unit that outputs the detection results of the detection unit.

16. The imaging element according to claim 15, wherein, The first signal processing unit performs the first signal processing on signals output from the plurality of pixels contained in the first region and the second region. The detection unit detects the period of brightness change of the light source based on signals output from the plurality of pixels contained in the first region.

17. The imaging element according to claim 1, comprising: A first substrate having a plurality of said pixels; as well as A second substrate that is bonded to the first substrate and has the second signal processing unit thereon.

18. The imaging element according to claim 1, comprising: A first substrate having a plurality of said pixels; A second substrate bonded to the first substrate and provided with the recording circuit; as well as A third substrate that is bonded to the second substrate and has the second signal processing circuitry thereon.

19. A camera device comprising: The imaging element as described in claim 1; as well as The generation unit generates image data based on the signal output from the first output unit or the signal output from the second output unit.

Images