Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device including a transistor section and a diode section includes: a drift region of a first conductivity type provided on a semiconductor substrate; and a plurality of trench portions extending in a predetermined trench extension direction, the transistor portion having: a base region of a second conductivity type; a plurality of emitter regions of the first conductivity type, which are discretely provided along the trench extension direction, and which have a higher doping concentration than the drift region; a contact region of a second conductivity type, the doping concentration of which is higher than that of the base region; a trench contact portion provided on a mesa portion between two adjacent trench portions among the plurality of trench portions so as to extend from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate; and a spacer region which is provided between two adjacent emitter regions in the extending direction of the trench among the plurality of emitter regions and has a doping concentration of the second conductivity type lower than a doping concentration of the second conductivity type of the contact region.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] Previously, semiconductor devices having IGBT regions and FWD regions were known (see, for example, Patent Documents 1 and 2).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2021-144998 Patent Document 2: Japanese Patent Application Publication No. 2022-181457 Summary of the Invention

[0004] In a first aspect of the present invention, a semiconductor device is provided, comprising a transistor portion and a diode portion. The semiconductor device includes: a drift region of a first conductivity type disposed on a semiconductor substrate; and a plurality of trench portions extending along a predetermined trench extension direction on the front side of the semiconductor substrate. The transistor portion may include: a base region of a second conductivity type disposed above the drift region; a plurality of emitter regions of the first conductivity type discretely disposed along the trench extension direction, and having a higher doping concentration than the drift region; a contact region of the second conductivity type having a higher doping concentration than the base region; a trench contact portion disposed on a mesa between two adjacent trench portions of the plurality of trench portions, extending from the front side of the semiconductor substrate along the depth direction of the semiconductor substrate; and a spacer rejection region disposed between two adjacent emitter regions of the plurality of emitter regions in the trench extension direction, and having a lower doping concentration of the second conductivity type than the contact region.

[0005] In the aforementioned semiconductor device, the spaced-out region may be the base region.

[0006] In any of the aforementioned semiconductor devices, the spacer rejection region may have a first spacer rejection portion disposed between the two adjacent emitter regions, such that it contacts the contact region on the front side of the semiconductor substrate. The spacer rejection region may also have a second spacer rejection portion disposed between the two adjacent emitter regions, such that it contacts the first spacer rejection portion on the front side of the semiconductor substrate, and having a doping concentration different from that of the first spacer rejection portion.

[0007] In any of the aforementioned semiconductor devices, the first gap rejection portion may include a plurality of first gap rejection portions. The second gap rejection portion may be disposed on the front side between two adjacent first gap rejection portions in the trench extension direction.

[0008] In any of the above-described semiconductor devices, the first spacer rejection portion may be the base region. The second spacer rejection portion may have a doping concentration of a first conductivity type that is lower than the doping concentration of the emitter region.

[0009] In any of the above semiconductor devices, the second gap rejection section may be the drift region.

[0010] In any of the aforementioned semiconductor devices, the first spacer rejection portion may be the base region. The second spacer rejection portion may have a doping concentration of a second conductivity type that is lower than the doping concentration of the base region.

[0011] In any of the aforementioned semiconductor devices, the diode portion may have a second conductivity type anode region disposed above the drift region. The second gap-removing portion may be the anode region.

[0012] In any of the above-described semiconductor devices, the contact region may have multiple contact regions. The multiple contact regions may be disposed at both ends of the emitter region in the trench extension direction and contact the emitter region on the front side.

[0013] In any of the above-described semiconductor devices, the contact area is disposed between the emitter region and the first spacer rejection portion adjacent in the trench extension direction, on the front side, one end of the contact area contacts the emitter region, and the other end of the contact area contacts the first spacer rejection portion.

[0014] In any of the aforementioned semiconductor devices, the first spacer rejection portion may be disposed below the contact area. The length of the trench extending in the first spacer rejection portion disposed on the front side may be greater than or equal to the thickness in the depth direction of the semiconductor substrate in which the first spacer rejection portion is disposed below the contact area.

[0015] In any of the above-described semiconductor devices, the length of the first spaced rejection portion disposed on the front side in the trench extension direction can be 0.1 μm or more and 2.0 μm or less.

[0016] In any of the above-described semiconductor devices, on the front side, the length of the second spacer rejection portion in the trench extension direction may be greater than the length of the first spacer rejection portion in the trench extension direction.

[0017] In any of the above semiconductor devices, on the front side, the length of the second spaced rejection portion in the trench extension direction may be greater than the length of the emitter region in the trench extension direction.

[0018] Any of the above-described semiconductor devices may include an interlayer insulating film disposed above the first spacer rejection portion and the second spacer rejection portion, and covering both the first spacer rejection portion and the second spacer rejection portion disposed on the front side.

[0019] In any of the aforementioned semiconductor devices, the interlayer insulating film may have contact holes. The trench contact portion can be formed in the area where the contact hole is provided when viewed from above, and the area where the contact hole is not provided when viewed from above is a trench contact non-forming area where the trench contact portion is not provided.

[0020] In any of the above semiconductor devices, the ratio α can be greater than 1.5 and less than 20, where the ratio α is the ratio of the interval between two adjacent emitter regions in the trench extension direction to the length of the non-interval rejection region formed by continuously forming one or more emitter regions and one or more contact regions in the trench extension direction.

[0021] The aforementioned semiconductor device may have an accumulation region of a first conductivity type above the drift region, which has a higher doping concentration than the drift region.

[0022] Any of the above-mentioned semiconductor devices may have a second conductivity type plug region, which is disposed at the lower end of the trench contact portion and has a higher doping concentration than the base region.

[0023] In any of the above semiconductor devices, the diode portion may have an anode region of a second conductivity type with a lower doping concentration than the base region.

[0024] In any of the above-described semiconductor devices, the transistor portion may have a boundary region disposed on the side of the transistor portion adjacent to the diode portion.

[0025] In any of the above semiconductor devices, a lifetime inhibitor region may not be present at a position closer to the front side than the center in the depth direction of the semiconductor substrate.

[0026] In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided, which is a method for manufacturing a semiconductor device having a transistor portion and a diode portion. The method for manufacturing the semiconductor device includes: forming a base region of a second conductivity type above a drift region of a first conductivity type disposed on a semiconductor substrate; forming a plurality of trench portions extending along a predetermined trench extension direction on the front side of the semiconductor substrate; discretely forming a plurality of emitter regions of the first conductivity type with a doping concentration higher than that of the drift region along the trench extension direction; forming a contact region of the second conductivity type with a doping concentration higher than that of the base region; forming a trench contact portion in the transistor portion at a mesa between two adjacent trench portions of the plurality of trench portions, such that it extends from the front side of the semiconductor substrate along the depth direction of the semiconductor substrate; and forming a spaced rejection region between two adjacent emitter regions of the plurality of emitter regions in the trench extension direction, wherein the doping concentration of the second conductivity type is lower than that of the contact region.

[0027] In the above-described method for manufacturing a semiconductor device, the spacer rejection region includes the base region, and the step of forming the spacer rejection region may include the step of forming the base region by ion implantation of a dopant of a second conductivity type into the anode region of the transistor portion after forming the anode region in the transistor portion and the diode portion.

[0028] It should be noted that the above description of the invention does not list all the features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0029] Figure 1 An example of a top view of a semiconductor device 100 is shown.

[0030] Figure 2A yes Figure 1 An enlarged view of region A in the image.

[0031] Figure 2B It shows including Figure 2A A diagram of an example of the XZ section of section a-a' in the figure.

[0032] Figure 3A Showing includes Figure 2A An example of the YZ section of section b-b' in the diagram.

[0033] Figure 3B Showing includes Figure 2A Example of deformation of the YZ section of section b-b' in the diagram.

[0034] Figure 3C Showing includes Figure 2AExample of deformation of the YZ section of section b-b' in the diagram.

[0035] Figure 4A yes Figure 1 A modified example of an enlarged view of region A in the image.

[0036] Figure 4B Showing includes Figure 4A An example of the YZ section of the d-d' section.

[0037] Figure 4C Showing includes Figure 4A Example of deformation of the YZ section of the d-d' section.

[0038] Figure 4D Showing includes Figure 4A Example of deformation of the YZ section of the d-d' section.

[0039] Figure 4E Showing includes Figure 4A Example of deformation of the YZ section of the d-d' section.

[0040] Figure 4F Showing includes Figure 4A Example of deformation of the YZ section of the d-d' section.

[0041] Figure 4G Showing includes Figure 4A Example of deformation of the YZ section of the d-d' section.

[0042] Figure 5A A modified example of the top view of the platform 71 is shown.

[0043] Figure 5B A modified example of the top view of the platform 71 is shown.

[0044] Figure 6A The ratio α dependence of the switching loss Err during reverse recovery is shown.

[0045] Figure 6B The ratio α dependence of the collector current on the saturation current Isat is shown.

[0046] Figure 7 An example of a method for manufacturing a semiconductor device 100 is shown.

[0047] Symbol Explanation 10. Semiconductor substrate; 12. Emitter region; 13. Plug region; 14. Base region; 15. Contact region; 16. Accumulation region; 17. Well region; 18. Drift region; 19. Anode region; 20. Buffer zone; 21. Front side; 22. Collector region; 23. Back side; 24. Collector electrode; 25. Connector; 30. • Dummy trench portion, 31··· Extension portion, 32··· Dummy insulating film, 33··· Connection portion, 34··· Dummy conductive portion, 38··· Interlayer insulating film, 40··· Gate trench portion, 41··· Extension portion, 42··· Gate insulating film, 43··· Connection portion, 44··· Gate conductive portion, 50··· Gate metal layer, 51··· Gate flow channel portion, 52·· ··Emitter electrode, 53···Barrier metal, 54···Contact hole, 55···Contact hole, 56···Contact hole, 58···Trench contact, 59···Plug, 60···Gap rejection area, 61···First gap rejection area, 62···Second gap rejection area, 65···Non-gap rejection area, 67···Non-gap rejection area, 70···Transistor section, 71···Mesa section, 78···Boundary, 80···Diode section, 81···Mesa section, 82···Cathode region, 90···Boundary region, 91···Mesa section, 100···Semiconductor device, 102···Edge edge, 112···Gate pad, 130···Gate wiring, 160···Active section, 162···First conductivity type region, 170···Edge termination structure Detailed Implementation

[0048] The present invention will now be described through embodiments thereof, but these embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the technical solution of the invention.

[0049] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when mounting the semiconductor device.

[0050] In this specification, rectangular coordinate axes of X, Y, and Z are sometimes used to illustrate technical matters. Rectangular coordinate axes only determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis is not limited to representing the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is not specified as positive or negative, it refers to a direction parallel to both the +Z-axis and -Z-axis.

[0051] In this specification, the right-angled axes parallel to the upper and lower surfaces of the semiconductor substrate are designated as the X-axis and Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is designated as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Additionally, in this specification, the direction including the X-axis and Y-axis and parallel to the upper and lower surfaces of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0052] When described as "the same" or "equal" in this specification, it may also include cases with errors caused by manufacturing deviations, etc. Such errors are, for example, within 10%.

[0053] In this specification, the conductivity type of the doped region is described as P-type or N-type. In this specification, "impurity" sometimes specifically refers to either an N-type donor or a P-type acceptor, and is sometimes referred to as a dopant. In this specification, doping means introducing a donor or acceptor into a semiconductor substrate to create a semiconductor exhibiting either an N-type or P-type conductivity type.

[0054] In this specification, doping concentration refers to the concentration of donors or acceptors at thermal equilibrium. In this specification, net doping concentration refers to the actual concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account charge polarity. As an example, if the donor concentration is set to N... D Set the acceptor concentration to N A Then the actual net doping concentration at any position is N. D -N A In this specification, the net doping concentration is sometimes described as the doping concentration only.

[0055] In this specification, "P+ type" or "N+ type" refers to a doping concentration higher than that of "P type" or "N type," while "P- type" or "N- type" refers to a doping concentration lower than that of "P type" or "N type." Similarly, "P++ type" or "N++ type" refers to a doping concentration higher than that of "P+ type" or "N+ type."

[0056] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electroactivated state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be determined by voltage-capacitance measurement (CV method). Alternatively, the carrier concentration measured by diffusion resistance measurement (SR method) can be used as the net doping concentration. A carrier refers to a charge carrier, either an electron or a hole. The carrier concentration measured by CV or SR methods can be set to a value under thermal equilibrium conditions. Furthermore, in the N-type region, since the donor concentration is significantly greater than the acceptor concentration, the carrier concentration in that region can be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region can be used as the acceptor concentration. In this specification, the doping concentration in the N-type region is sometimes referred to as the donor concentration, and the doping concentration in the P-type region is sometimes referred to as the acceptor concentration.

[0057] Furthermore, when the concentration distribution of donor, acceptor, or net dopant has a peak, the peak value can be taken as the concentration of donor, acceptor, or net dopant in that region. When the concentration of donor, acceptor, or net dopant is almost uniform, the average concentration of donor, acceptor, or net dopant in that region can be taken as the concentration of donor, acceptor, or net dopant.

[0058] The carrier concentration measured by the SR method can be lower than the donor or acceptor concentration. During the measurement of diffusion resistance, the carrier mobility of the semiconductor substrate is sometimes lower than the value in the crystalline state within the range of current flow. This decrease in carrier mobility is caused by the dispersion of carriers due to crystal structure disorder (disorder) caused by lattice defects, etc. The reason for the decrease in carrier concentration is as follows: In the SR method, the diffusion resistance is measured, and the carrier concentration is calculated based on the measured value of the diffusion resistance. At this time, the carrier mobility used is the mobility in the crystalline state. On the other hand, at locations where lattice defects are introduced, although the carrier mobility is lower, the carrier concentration is calculated based on the carrier mobility in the crystalline state. Therefore, it becomes a value lower than the actual carrier concentration, i.e., the donor or acceptor concentration.

[0059] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method can be lower than the chemical concentration of the element representing the donor or acceptor. As an example, in silicon semiconductors, the donor concentration of phosphorus or arsenic (which are donors) or the acceptor concentration of boron (which is an acceptor) is approximately 99% of their chemical concentration. On the other hand, the donor concentration of hydrogen (which is a donor) in silicon semiconductors is approximately 0.1% to 10% of the chemical concentration of hydrogen. SI units are used in this specification. In this specification, units of distance and length are sometimes expressed in cm (centimeter). In this case, calculations can be performed by converting to m (meter). Regarding the numerical representation of powers of 10, for example, 1E+16 represents 1 × 10⁻¹⁶.16 The 1E-16 display indicates 1×10 -16 .

[0060] Figure 1 An example top view of a semiconductor device 100 is shown. Figure 1 The image shows the positions of the components projected onto the upper surface of the semiconductor substrate 10. Figure 1 The diagram shows only a portion of the components of the semiconductor device 100, with some components omitted. The semiconductor device 100 is a semiconductor chip including a transistor section 70 and a diode section 80.

[0061] The transistor section 70 includes transistors such as IGBTs (Insulated Gate Bipolar Transistors). The diode section 80 includes diodes such as freewheeling diodes (FWDs). In this example, the semiconductor device 100 is a reverse-conducting IGBT (RC-IGBT) having both a transistor section 70 and a diode section 80 on the same chip.

[0062] Semiconductor substrate 10 is a substrate formed from semiconductor material. Semiconductor substrate 10 can be a silicon substrate, a silicon carbide substrate, a diamond substrate, a gallium nitride or other nitride semiconductor substrate, an inorganic compound semiconductor substrate such as gallium oxide, or an organic compound semiconductor substrate. In this example, semiconductor substrate 10 is a silicon substrate. Semiconductor substrate 10 can be a wafer cut from a semiconductor ingot, or a chip obtained by monolithizing a wafer. The semiconductor ingot can be manufactured by any of the following methods: Czochralski process (CZ process), magnetic field applied Czochralski process (MCZ process), or floating zone melting process (FZ process).

[0063] The semiconductor substrate 10 has end edges 102 when viewed from above. In this specification, "viewed from above" refers to the view from the top surface of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two sets of end edges 102 that are opposite each other when viewed from above. Figure 1 In this configuration, the X and Y axes are parallel to either end edge 102. Additionally, the Z axis is perpendicular to the upper surface of the semiconductor substrate 10. The semiconductor substrate 10 has an active portion 160 and an edge termination structure portion 170.

[0064] The active portion 160 is the region where the main current flows along the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is disposed above the active portion 160, but... Figure 1 Omitted in the text.

[0065] The active section 160 is provided with at least one of a transistor section 70 including transistor elements such as IGBTs and a diode section 80 including diode elements such as freewheeling diodes (FWDs). Figure 1 In this example, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10.

[0066] exist Figure 1 In this specification, the area where the transistor section 70 is arranged is marked with the symbol "I", and the area where the diode section 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction when viewed from above is sometimes referred to as the extension direction (in...). Figure 1 (The middle direction is the Y-axis direction). The transistor section 70 and the diode section 80 may each have a long side in the extending direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending directions of the transistor section 70 and the diode section 80 may be the same as the long side direction of each trench section described later.

[0067] The diode section 80 has an N+ type cathode region in the area that contacts the lower surface of the semiconductor substrate 10. In this specification, the area where the cathode region is provided is referred to as the diode section 80. That is, the diode section 80 is the area that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in the area other than the cathode region.

[0068] The transistor section 70 has a P+ type collector region in the region that contacts the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure periodically disposed on the upper surface side of the semiconductor substrate 10. The gate structure has an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film.

[0069] Semiconductor device 100 may have one or more pads above semiconductor substrate 10. In this example, semiconductor device 100 has a gate pad 112. Semiconductor device 100 may have pads such as anode pads, cathode pads, and current sensing pads. Each pad is located near the edge 102. "Near the edge 102" refers to the area between the edge 102 and the emitter electrode when viewed from above. When mounting semiconductor device 100, each pad can be connected to external circuitry via wiring such as wires.

[0070] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring 130 that connects the gate pad 112 and the gate trench portion.

[0071] The gate wiring 130 is electrically connected to the gate conductive portion of the transistor portion 70, and a gate voltage is applied to the transistor portion 70. The gate wiring 130 is configured to surround the outer periphery of the active portion 160 when viewed from above. The gate wiring 130 is electrically connected to the gate pad 112 provided on the edge terminal structure portion 170.

[0072] In addition, the semiconductor device 100 may also include a temperature sensing unit (not shown) that is a PN junction diode formed of polysilicon or the like, and a current sensing unit (not shown) that simulates the operation of the transistor unit provided in the active unit 160.

[0073] In this example, the semiconductor device 100, when viewed from above, has an edge termination structure 170 between the active portion 160 and the edge 102. The edge termination structure 170 is disposed between the gate wiring 130 and the edge 102. The edge termination structure 170 mitigates electric field concentration on the upper surface of the semiconductor substrate 10. The edge termination structure 170 may include at least one of a protective ring arranged in a ring around the active portion 160, a field plate, and a surface electric field reducing element.

[0074] Figure 2A yes Figure 1 An enlarged view of region A in the diagram. Region A includes the transistor section 70, the diode section 80, and the gate wiring 130. In this example, the gate wiring 130 includes a gate metal layer 50 and a gate channel section 51.

[0075] A boundary region 90 is provided between the transistor portion 70 and the diode portion 80 on the front side 21 of the semiconductor substrate 10. The front side 21 of the semiconductor substrate 10 refers to one of the two opposing main surfaces in the semiconductor substrate 10. The front side 21 will be described later.

[0076] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, a well region 17, an emitter region 12, a base region 14, a contact region 15, and an anode region 19 formed inside the front side 21 of the semiconductor substrate 10. Furthermore, the semiconductor device 100 in this example includes an emitter electrode 52 and a gate metal layer 50 disposed above the front side 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are disposed separately from each other.

[0077] An interlayer insulating film is formed between the emitter electrode 52 and the gate metal layer 50 and the front side 21 of the semiconductor substrate 10, but... Figure 2A The interlayer insulating film is omitted. In this example, the interlayer insulating film forms contact holes 54, 55, and 56 in a manner that penetrates the interlayer insulating film.

[0078] The emitter electrode 52 is electrically connected to the emitter region 12, contact region 15, base region 14, and anode region 19 of the front side 21 of the semiconductor substrate 10 through a contact hole 54 formed in the interlayer insulating film. Additionally, the emitter electrode 52 is connected to a dummy conductive portion within the dummy trench portion 30 through a contact hole 56. A connection portion 25 formed of a conductive material such as polycrystalline silicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion.

[0079] The gate metal layer 50 contacts the gate flow channel portion 51 through the contact hole 55. The gate flow channel portion 51 is formed of a semiconductor such as polysilicon doped with impurities. The gate flow channel portion 51 is connected to the gate conductive portion in the gate trench portion 40 on the front side 21 of the semiconductor substrate 10.

[0080] The emitter electrode 52 and the gate metal layer 50 are formed of a metal-containing material. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium or titanium compounds in the lower layer of the region formed of aluminum or the like. Each electrode may also have a plug formed by embedding tungsten or the like in a contact hole in a manner that contacts the barrier metal and aluminum or the like.

[0081] The well region 17 is provided in a manner that overlaps with the gate metal layer 50 and the gate flow channel portion 51. The well region 17 is configured to extend with a predetermined width even in areas where it does not overlap with the gate metal layer 50 and the gate flow channel portion 51. In this example, the well region 17 is configured to separate from the gate metal layer 50 side from one end of the contact hole 54 in the Y-axis direction. The well region 17 is a region of a second conductivity type with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 17 is P+ type.

[0082] The transistor section 70 and the diode section 80 each have multiple trench sections arranged along the alignment direction on the front side 21 of the semiconductor substrate 10. In this example, the transistor section 70 alternately has one or more gate trench sections 40 and one or more dummy trench sections 30 along the alignment direction. In this example, the diode section 80 has multiple dummy trench sections 30 along the alignment direction. In this example, the diode section 80 does not have gate trench sections 40.

[0083] In the transistor section 70, one or more gate trench sections 40 are arranged at predetermined intervals along the arrangement direction of each trench. The gate conductive portion inside the gate trench section 40 is electrically connected to the gate metal layer 50, thereby applying a gate potential. In the transistor section 70, one or more dummy trench sections 30 may be arranged at predetermined intervals along the arrangement direction. A potential different from the gate potential is applied to the dummy conductive portion inside the dummy trench section 30. In this example, the dummy conductive portion is electrically connected to the emitter electrode 52, thereby applying an emitter potential.

[0084] In the transistor section 70, one or more gate trench sections 40 and one or more dummy trench sections 30 may be alternately formed along the arrangement direction. Furthermore, the dummy trench sections 30 are arranged at predetermined intervals along the arrangement direction in the diode section 80 and the boundary region 90. It should be noted that the transistor section 70 may be constructed solely of gate trench sections 40 without the dummy trench sections 30.

[0085] In this example, the gate trench portion 40 may have two extension portions 41 (the trench portion that is straight along the extension direction) extending along an extension direction perpendicular to the arrangement direction and a connecting portion 43 connecting the two extension portions 41. Figure 2A The extension direction in the middle is the Y-axis direction.

[0086] Preferably, at least a portion of the connecting portion 43 is curved when viewed from above. By connecting the ends of the two extension portions 41 in the Y-axis direction to each other through the connecting portion 43, the electric field concentration at the ends of the extension portions 41 can be mitigated.

[0087] In the transistor section 70, dummy trench sections 30 are provided between the various extensions 41 of the gate trench section 40. One dummy trench section 30 may be provided between each extension 41, or multiple dummy trench sections 30 may be provided. The dummy trench section 30 may have a straight shape extending along the extension direction, or it may have an extension portion 31 and a connecting portion 33, similar to the gate trench section 40. The semiconductor device 100 may include both dummy trench sections 30 with a straight shape without the connecting portion 33 and dummy trench sections 30 with the connecting portion 33. The direction in which the extension portion 41 of the gate trench section 40 or the extension portion 31 of the dummy trench section 30 extends longer along the extension direction is defined as the long side direction of the trench section. The long side direction of the gate trench section 40 or the dummy trench section 30 may be consistent with the extension direction. In this example, the extension direction and the long side direction are both the Y-axis direction. The arrangement direction of the plurality of gate trench portions 40 or dummy trench portions 30 is defined as the short side direction of the trench portions. The short side direction can be consistent with the arrangement direction. Alternatively, the short side direction can be perpendicular to the long side direction. In this example, the long side direction is perpendicular to the short side direction. In this example, the arrangement direction and the short side direction are the X-axis direction.

[0088] At the connection portion 43 at the front end of the gate trench portion 40, the gate conductive portion within the gate trench portion 40 is connected to the gate flow channel portion 51. The gate trench portion 40 may be configured to protrude further toward the gate flow channel portion 51 in the extending direction (Y-axis direction) than the dummy trench portion 30. This protruding portion of the gate trench portion 40 is connected to the gate flow channel portion 51.

[0089] The diffusion depth of the well region 17 can be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located in the well region 17 when viewed from above. That is, at the Y-axis end of each trench portion, the bottom of each trench portion in the depth direction is covered by the well region 17. This mitigates the electric field concentration at the bottom of each trench portion.

[0090] Mesa-shaped portions are provided between the trench portions in the arrangement direction. A mesa-shaped portion refers to a region within the semiconductor substrate 10 that is sandwiched between two adjacent trench portions. As an example, the upper end of the mesa-shaped portion is the upper surface of the semiconductor substrate 10. The lower end of the mesa-shaped portion is at the same depth as the lower end of the trench portion. In this example, the mesa-shaped portions are provided on the upper surface of the semiconductor substrate 10 such that they extend along the trench portions in the extension direction (Y-axis direction).

[0091] Boundary region 90 is disposed in transistor section 70 on the side of diode section 80. That is, boundary region 90 is disposed adjacent to diode section 80 in transistor section 70. Boundary region 90 may be a region having dummy trench section 30 and a collector region 22 disposed on the back side of semiconductor substrate 10. The two ends of the trench arrangement direction of the mesa portion of boundary region 90 may respectively contact the dummy trench section 30. The trench portion of boundary region 90 may be entirely dummy trench section 30. Boundary region 90 may also include gate trench section 40. In this example, the boundary region 90 does not have a first conductivity type emitter region 12 disposed on the mesa portion of the front side 21 of semiconductor substrate 10. Boundary region 90 may have a base region 14 or an anode region 19 on the front side 21. Boundary region 90 may also have an emitter region 12 or a contact region 15 on the front side 21. In this example, boundary region 90 has an anode region 19 and a contact region 15 on the front side 21. It should be noted that in Figure 2A In the diagram, the positions of the collector region 22 and the cathode region 82 provided on the back side of the semiconductor substrate 10 are shown when the collector region 22 and the cathode region 82 are projected onto the front side 21.

[0092] Mesh surface 71 is a mesh surface provided on the transistor section 70. Mesh surface 81 is a mesh surface provided on the diode section 80. Mesh surface 91 is a mesh surface provided on the boundary region 90. In this specification, when simply referred to as a mesh surface, it may refer to mesh surface 71, mesh surface 81, or mesh surface 91 respectively. The extension portion of each trench portion can be defined as a single trench portion. That is, the area sandwiched between two extension portions can be defined as a mesh surface.

[0093] A base region 14 or an anode region 19 is provided on each mesa. The region of the base region 14 or anode region 19 exposed on the upper surface of the semiconductor substrate 10 that is closest to the gate metal layer 50 is designated as base region 14-e or anode region 19-e. Figure 2A The diagram shows a base region 14-e or an anode region 19-e disposed at one end of each isthmus in the extending direction, but a base region 14-e or an anode region 19-e is also disposed at the other end of each isthmus. In a top view, the area of ​​each isthmus sandwiched between the base region 14-e or the anode region 19-e may be provided with at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be disposed between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0094] The mesa portion 71 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is disposed in contact with the gate trench portion 40. The mesa portion 71 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0095] The contact area 15 and the emission area 12 in the platform surface 71 are respectively provided from one side of the groove in the X-axis direction to the other side of the groove. As an example, the contact area 15 and the emission area 12 of the platform surface 71 are alternately arranged along the groove extension direction (Y-axis direction).

[0096] In this example, the table surface 71 has an intermittent rejection area 60 and a non-intermittent rejection area 65. The intermittent rejection area 60 and the non-intermittent rejection area 65 are alternately arranged in the groove extension direction. The intermittent rejection area 60 will be described later.

[0097] The non-interval rejection region 65 has an emission region 12 and a contact region 15. One or more emission regions and one or more contact regions are arranged continuously and alternately in the trench extension direction. Contact regions 15 can be provided at both ends of the non-interval rejection region 65 in the trench extension direction. That is, the emission region 12 of the non-interval rejection region 65 can be sandwiched between two adjacent contact regions 15 in the trench extension direction. The number of repetitions of the emission region 12 and contact region 15 in the non-interval rejection region 65 is not limited to this example. In this example, one emission region 12 and two contact regions 15 are arranged continuously in the non-interval rejection region 65, but two emission regions 12 and three contact regions 15 can also be arranged continuously, or three emission regions 12 and four contact regions 15 can be arranged continuously.

[0098] The emitter region 12 is not provided on the mesa 81 of the diode section 80, but it may be provided. An anode region 19 is provided on the upper surface of the mesa 81. A contact region 15 may be provided on the upper surface of the mesa 81. A contact region 15 may be provided on the upper surface of the mesa 81 in the area sandwiched by the anode regions 19-e, in contact with each anode region 19-e. An anode region 19 may be provided on the upper surface of the mesa 81 in the area sandwiched by the contact region 15. The anode region 19 may be arranged in the trench extension direction over the entire area sandwiched by the contact region 15.

[0099] Contact holes 54 are provided above each mesa surface. The contact holes 54 are located in areas sandwiched between the base region 14-e or the anode region 19-e along the trench extension direction. In this example, the contact holes 54 are located above the contact region 15, the base region 14, the anode region 19, and the emitter region 12. The contact holes 54 are not located in the regions corresponding to the base region 14-e, the anode region 19-e, and the sink region 17. The contact holes 54 can be located at the center of the trench arrangement direction (X-axis direction) of the mesa surface 71. A trench contact portion 58 is provided in the contact hole 54. The trench contact portion 58 will be described later.

[0100] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. The doping concentration of the cathode region 82 is higher than that of the drift region 18. A P+ type collector region 22 can be provided in a region on the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the back surface 23 of the semiconductor substrate 10 and the buffer zone 20 described later. Figure 2A In the diagram, the boundary 78 between the cathode region 82 and the collector region 22 is shown by a dashed line.

[0101] The cathode region 82 is configured separately from the well region 17 in the Y-axis direction. This ensures a sufficient distance between the cathode region 82 and the P-type region (well region 17), which has a high doping concentration and is formed to a deep position, thereby improving breakdown voltage and suppressing hole injection from the well region 17. In this example, the end of the cathode region 82 in the Y-axis direction is configured further away from the well region 17 than the end of the contact hole 54 in the Y-axis direction. In other examples, the end of the cathode region 82 in the Y-axis direction may also be configured between the well region 17 and the contact hole 54.

[0102] An anode region 19 is provided on the mesa 91 of the boundary region 90. The boundary region 90 may have multiple mesa 91s. The mesa 91 may also have a base region 14 instead of the anode region 19. The anode region 19 will be described later.

[0103] Figure 2B It shows including Figure 2A A diagram showing an example of the XZ cross-section of the a-a' section. The XZ cross-section including the a-a' section is the XZ plane passing through the emitter region 12 in the transistor section 70. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the XZ cross-section including the a-a' section. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0104] Drift region 18 is a region of a first conductivity type disposed on semiconductor substrate 10. As an example, drift region 18 in this example is N-type. Drift region 18 can be a region remaining in semiconductor substrate 10 where no other doped regions are formed. That is, the doping concentration of drift region 18 can be the doping concentration of semiconductor substrate 10.

[0105] Buffer 20 is a region of the first conductivity type disposed on the back surface 23 side of the semiconductor substrate 10, which is closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18. In this example, buffer 20 is disposed closer to the back surface 23 of the semiconductor substrate 10 than the center in the depth direction of the semiconductor substrate 10. As an example, buffer 20 is N-type. The doping concentration of buffer 20 is higher than that of drift region 18. Buffer 20 can function as a field cutoff layer to prevent the depletion layer diffusing from the lower surface side of base region 14 to the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0106] Collector region 22 and cathode region 82 are disposed on the back surface 23 of semiconductor substrate 10. Collector region 22 is disposed below buffer zone 20 in transistor section 70. Cathode region 82 is disposed below buffer zone 20 in diode section 80. The boundary 78 between collector region 22 and cathode region 82 may be the boundary between transistor section 70 and diode section 80.

[0107] A collector electrode 24 is formed on the back side 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as a metal. At least a portion of the collector electrode 24 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu).

[0108] The base region 14 is a second conductivity type region disposed above the drift region 18 in the mesa 71 and mesa 91. The base region 14 is disposed in contact with the gate trench portion 40. The base region 14 may be disposed in contact with the dummy trench portion 30.

[0109] The anode region 19 is a second conductivity type region disposed above the drift region 18 in the mesa 91 and mesa 81. The anode region 19 is disposed in contact with the dummy trench portion 30. The anode region 19 may be disposed in contact with the gate trench portion 40. The doping concentration of the anode region 19 may be the same as or lower than that of the base region 14. The maximum doping concentration of the anode region 19 may be less than or equal to the maximum doping concentration of the base region 14. In this example, the maximum doping concentration of the anode region 19 is less than the maximum doping concentration of the base region 14. In the depth direction of the semiconductor substrate 10, the depth of the anode region 19 may be deeper than, shallower than, or equal to the depth of the base region 14. In this example, the depth of the anode region 19 is substantially equal to the depth of the base region 14. The integral value obtained by integrating the doping concentration of the anode region 19 along the depth direction of the semiconductor substrate 10 can be less than or equal to the integral value obtained by integrating the doping concentration of the base region 14. In this example, the integral value of the doping concentration of the anode region 19 is less than the integral value of the doping concentration of the base region 14.

[0110] The emitter region 12 is located closer to the front side 21 than the drift region 18, and its doping concentration is higher than that of the drift region 18. In this example, the emitter region 12 is located above the base region 14 in the mesa 71. The emitter region 12 may be disposed in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. It should be noted that the emitter region 12 may not be disposed in the mesa 91.

[0111] The contact area 15 is disposed above the base region 14 in the mesa 71. The contact area 15 is disposed in contact with the gate trench portion 40 in the mesa 91. In other cross-sections, the contact area 15 may be disposed on the front surface 21 of the mesa 71.

[0112] The accumulation region 16 is a first conductivity type region located closer to the front side 21 of the semiconductor substrate 10 than the drift region 18. As an example, the accumulation region 16 in this example is N+ type. The accumulation region 16 is located on the mesa 71. The accumulation region 16 can also be located on the mesa 81 and the mesa 91.

[0113] Furthermore, the accumulation region 16 is disposed in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than that of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be improved, thereby reducing the turn-on voltage of the transistor portion 70.

[0114] One or more gate trench portions 40 and one or more dummy trench portions 30 are disposed on the front side 21. Each trench portion extends from the front side 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and accumulation region 16 is disposed, each trench portion also extends through these regions to reach the drift region 18. The case where the trench portion extends through the doped region is not limited to the manufacturing sequence of forming the trench portion after forming the doped region. The method of forming the doped region between the trench portions after forming the trench portion also includes the method of the trench portion extending through the doped region.

[0115] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front side 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench at a position further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front side 21 by an interlayer insulating film 38.

[0116] The gate conductive portion 44 includes a region opposite the base region 14 on the mesa 71 side, which is separated from the semiconductor substrate 10 by the gate insulating film 42 in the depth direction. If a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in the base region 14 that contacts the gate trench.

[0117] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front side 21. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and at a position further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front side 21 by an interlayer insulating film 38.

[0118] An interlayer insulating film 38 is disposed on the front side 21. An emitter electrode 52 is disposed above the interlayer insulating film 38. One or more contact holes 54 are provided on the interlayer insulating film 38 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided in a manner that penetrates through the interlayer insulating film 38.

[0119] The trench contact portion 58 is provided on a mesa between two adjacent trench portions in a plurality of trench portions, extending from the front side 21 of the semiconductor substrate 10 along the depth direction of the semiconductor substrate 10. The trench contact portion 58 may be provided to extend from the upper end of the interlayer insulating film 38 to the inner side of the semiconductor substrate 10. In this example, the trench contact portion 58 is provided in the contact hole 54. The trench contact portion 58 may have a plug portion 59. The plug portion 59 may be tungsten. The trench contact portion 58 may have a barrier metal 53 formed of titanium or titanium compounds.

[0120] The plug region 13 is a region of the second conductivity type disposed at the lower end of the trench contact portion 58 and having a higher doping concentration than the base region 14. The plug region 13 may be disposed at the lower end of the trench contact portion 58 such that it extends along the trench extension direction. The plug region 13 may be disposed on the entire surface of the lower end of the trench contact portion 58. The plug region 13 may be formed in a region overlapping with a region formed by ion implantation of a dopant of the first conductivity type used to form the emitter region 12, or it may be formed in a region overlapping with a region formed by ion implantation of a dopant of the second conductivity type used to form the contact region 15. The plug region 13 may also be disposed in the boundary region 90 and the diode portion 80.

[0121] The semiconductor device 100 in this example does not have a lifetime control section with a lifetime inhibitor, but it may have one. The semiconductor device 100 may not have a lifetime inhibitor region located closer to the front side 21 than the center in the depth direction of the semiconductor substrate 10. By providing the gap rejection region 60, the semiconductor device 100 in this example can suppress hole injection without forming a lifetime control section, thereby reducing the switching loss Err during reverse recovery.

[0122] Furthermore, the semiconductor device 100 in this example improves latch-up tolerance by providing the trench contact portion 58. Thus, by providing the interval rejection region 60 and the trench contact portion 58, the semiconductor device 100 can suppress the decrease in latch-up tolerance caused by the provision of the interval rejection region 60, and can reduce the switching loss Err during reverse recovery.

[0123] Figure 3A Showing includes Figure 2A An example of the YZ cross section of the b-b' section. The YZ cross section including the b-b' section is the YZ plane of the mesa 71 of the transistor section 70. The b-b' section is the cross section that does not pass through the contact hole 54. The lower end of the trench contact section 58 is indicated by a dashed line.

[0124] The interval rejection area 60 is disposed between two adjacent non-interval rejection areas 65 in the trench extension direction. The interval rejection area 60 may be disposed between two adjacent emission areas 12 in the trench extension direction among a plurality of emission areas 12. In addition, the interval rejection area 60 may be disposed between two adjacent contact areas 15 in the trench extension direction among a plurality of contact areas 15.

[0125] The spacer rejection region 60 can be of a first conductivity type or a second conductivity type, and may include both regions of the first conductivity type and regions of the second conductivity type. The doping concentration of the second conductivity type in the spacer rejection region 60 may be lower than the doping concentration of the second conductivity type in the contact region 15. Lower doping concentration of the second conductivity type can mean that, when the spacer rejection region 60 is of the second conductivity type, the doping concentration of the second conductivity type is lower than the doping concentration of the second conductivity type in the contact region 15. Alternatively, it can mean that, when the spacer rejection region 60 is of the first conductivity type, the doping concentration of the second conductivity type is lower than the doping concentration of the second conductivity type in the contact region 15. The spacer rejection region 60 may include at least one of the base region 14, the drift region 18, and the anode region 19. In this example, the spacer rejection region 60 is the base region 14.

[0126] The spacing P12 is the interval between two adjacent emitter regions 12 in the trench extension direction. The spacing P12 can be the interval between the emitter region 12 of one of the two adjacent non-spaced rejection regions 65 and the emitter region 12 of the other non-spaced rejection region 65. Since the spacing P12 affects the saturation voltage of the transistor section 70 and the magnitude of the main current flowing in the transistor section 70 during a short circuit, it can be determined according to the required electrical characteristics of the transistor section 70.

[0127] The ratio α is the ratio of the spacing P12 to the length L65 of the trench extension direction of the non-spacing rejection area 65. The ratio α can be greater than 1.5 and less than 20. The ratio α can be greater than 2 or greater than 2.5. The ratio α can be less than 5 or less than 3. The spacing P12 can be greater than 3 μm or less than 10 μm. If the spacing P12 increases and the area of ​​the contact region 15 increases, holes are more easily injected; however, by setting the spacing rejection area 60, hole injection can be more effectively suppressed.

[0128] Length L15 is the length of the contact area 15 in the groove extension direction of the front side 21. Length L12 is the length of the emission area 12 in the groove extension direction of the front side 21. Length L15 can be larger than length L12.

[0129] Length L60 is the length of the intermittent rejection area 60 in the groove extension direction of the front side 21. Length L65 is the length of the non-intermittent rejection area 65 in the groove extension direction of the front side 21. Length L60 can be shorter or longer than length L65.

[0130] Thickness Z14 is the thickness of the base region 14 below the contact region 15. In this example, thickness Z14 is the distance from the lower end of the contact region 15 in the depth direction of the semiconductor substrate 10 to the upper end of the accumulation region 16. In this example, the base region 14 covers both the lower and side surfaces of the non-spaced rejection region 65.

[0131] It should be noted that multiple contact regions 15 can be disposed at both ends of the emitter region 12 in the trench extension direction. The contact regions 15 can contact the emitter region 12 on the front side 21. When the emitter region 12 and the contact regions 15 are not in contact on the front side 21, the size of the emitter region 12 is prone to deviation due to the diffusion of implanted ions. On the other hand, by making the emitter region 12 and the contact regions 15 in contact on the front side 21, the size of the emitter region 12 can be determined using the position of the contact regions 15, making it easier to reduce deviations in the saturation current.

[0132] In this example, the accumulation region 16 is positioned above the drift region 18. The accumulation region 16 is positioned between the base region 14 and the drift region 18, but this can be omitted. The contact region 15 can cover the end of the emitter region 12 extending in the direction of its lower surface. This reduces the voltage drop during hole passage and suppresses latch-up.

[0133] Figure 3B Showing includes Figure 2A Example of deformation of the YZ section of the b-b' section. The structure of the spacer rejection region 60 of the semiconductor device 100 in this example is similar to... Figure 3A The structure of the spaced rejection region 60 of the semiconductor device 100 is different. In this example, it is particularly important to compare it with... Figure 3AThe semiconductor device has 100 different points described, and other points can be compared with... Figure 3A The semiconductor device 100 is the same. In this example, the gap rejection region 60 has a first gap rejection section 61 and a second gap rejection section 62.

[0134] A first spacer rejection portion 61 is disposed between two adjacent emitter regions 12. The first spacer rejection portion 61 may be disposed in such a way that it contacts the contact region 15 on the front side 21 of the semiconductor substrate 10. The spacer rejection region 60 may have a plurality of first spacer rejection portions 61 sandwiched between second spacer rejection portions 62 in the trench extension direction. The first spacer rejection portion 61 may be a base region 14 or an anode region 19. In this example, the first spacer rejection portion 61 is a base region 14.

[0135] The second spacer rejection section 62 is disposed between two adjacent emitter regions 12, in contact with the first spacer rejection section 61 on the front side 21. The doping concentration of the second spacer rejection section 62 is different from that of the first spacer rejection section 61. The second spacer rejection section 62 may be disposed on the front side 21 between two adjacent first spacer rejection sections 61 in the trench extension direction. In this example, the second spacer rejection section 62 has a first conductivity type doping concentration lower than that of the emitter region 12. In this example, the second spacer rejection section 62 is a drift region 18. In this example, the drift region 18, which is the second spacer rejection section 62, is disposed between a plurality of base regions 14, which are first spacer rejection sections 61, in the trench extension direction. The length L14 is the length of the base region 14 in the trench extension direction. The length L14 may be greater than the length L65. The second spacer rejection section 62 may be held by the first spacer rejection section 61 along the extension direction of the gate trench portion 40.

[0136] The contact area 15 is disposed between the adjacent emission area 12 and the first spacer rejection portion 61 in the trench extension direction. On the front side 21, one end of the contact area 15 can contact the emission area 12, and the other end of the contact area 15 can contact the first spacer rejection portion 61. The first spacer rejection portion 61 can be disposed below the contact area 15. In this example, the first spacer rejection portion 61 covers the side and bottom surfaces of the contact area 15.

[0137] If the drift region 18, which serves as the second gap rejection section 62, comes into direct contact with the contact region 15, the electric field strength increases. In this case, the electric field strength can be mitigated by clamping the first gap rejection section 61 between the second gap rejection section 62 and the contact region 15.

[0138] The length L60 is the length of the trench extending in the spacer rejection area 60 of the front side 21. The length L61 is the length of the trench extending in the first spacer rejection portion 61 of the front side 21. The thickness Z61 is the thickness of the first spacer rejection portion 61 located below the contact area 15 in the depth direction of the semiconductor substrate 10. The length L61 can be greater than or equal to the thickness Z61. The length L61 can be greater than or equal to 0.1 μm and less than or equal to 2.0 μm. Thus, by adjusting the length L61, the electric field concentration at the side of the contact area 15 can be mitigated, and the electric field strength can be increased.

[0139] Length L61 is the length of the first spacer rejection portion 61 in the groove extension direction of the front surface 21. Length L62 is the length of the second spacer rejection portion 62 in the groove extension direction of the front surface 21. On the front surface 21, the length L62 of the second spacer rejection portion 62 in the groove extension direction can be greater than the length L61 of the first spacer rejection portion 61 in the groove extension direction. On the front surface 21, the length L62 of the second spacer rejection portion 62 in the groove extension direction can be greater than the length L12 of the emission region 12 in the groove extension direction.

[0140] Figure 3C Showing includes Figure 2A Example of a deformation of the YZ section of the b-b' section. The structure of the second spacer removal section 62 of the semiconductor device 100 in this example is similar to... Figure 3B The structure of the second spacer rejection section 62 of the semiconductor device 100 is different. In this example, it is particularly important to compare it with... Figure 3B The semiconductor device has 100 different points described, and other points can be compared with... Figure 3B The semiconductor device 100 is the same.

[0141] The second spacer rejection section 62 can have a doping concentration of a second conductivity type that is lower than the doping concentration of the base region 14. In this example, the second spacer rejection section 62 is the anode region 19. In one example, the anode region 19 is P-type. By setting the second spacer rejection section 62 to be the anode region 19 with a doping concentration lower than that of the base region 14, hole injection can be suppressed compared to the case where the second spacer rejection section 62 is the base region 14.

[0142] The lower ends of the first interval rejection section 61 and the second interval rejection section 62 can be at the same depth. In this example, the lower end of the anode region 19, which is the second interval rejection section 62, coincides with the lower end of the base region 14. The lower end of the anode region 19, which is the second interval rejection section 62, can be the upper end of the accumulation region 16.

[0143] Figure 4A yes Figure 1 A modified example of an enlarged view of region A in this example. The location of the contact hole 54 in the semiconductor device 100 in this example is... Figure 2A The positions of the contact holes 54 in the semiconductor device 100 differ. In this example, the positions are particularly different from those in the semiconductor device 100. Figure 2A The semiconductor device has 100 different points described, and other points can be compared with... Figure 2A The semiconductor device 100 is the same. The structure of the c-c' cross section can be the same as... Figure 2A The structure of section a-a' is the same, and it can also be the same as... Figure 2A The structures of the a-a' sections are different.

[0144] In this example, the contact hole 54 is located above the non-interval rejection area 65, but not above the interval rejection area 60. Similarly, in this example, the groove contact portion 58 is located above the non-interval rejection area 65, but not above the interval rejection area 60. The areas forming the contact hole 54 and the groove contact portion 58 can be the same.

[0145] The trench contact portion 58 can be formed using the interlayer insulating film 38 as a mask. When the trench contact portion 58 is formed using the interlayer insulating film 38 as a mask, the area where the contact hole 54 is provided in top view can be called the trench contact forming area, and the area where the contact hole 54 is not provided in top view can be called the trench contact non-forming area. It should be noted that in this specification, the area where the trench contact portion 58 is provided is referred to as the trench contact forming area, and the area where the trench contact portion 58 is not provided in top view is referred to as the trench contact non-forming area.

[0146] Similarly, the plugging region 13 can be formed using the interlayer insulating film 38 as a mask. When the plugging region 13 is formed using the interlayer insulating film 38 as a mask, in top view, the plugging region 13 is formed in the area where the contact hole 54 is provided, but not in the area where the contact hole 54 is not provided. In this example, since the contact hole 54 is not provided in the spacer rejection region 60, the plugging region 13 can be omitted in the spacer rejection region 60. By omitting the plugging region 13 in the spacer rejection region 60, it is easier to suppress hole injection.

[0147] Here, if a contact hole 54 is provided in the spacer rejection region 60, a Schottky junction may be formed, which would increase the leakage current. Since the semiconductor device 100 in this example does not provide a contact hole 54 in the spacer rejection region 60 in the mesa 71, the leakage current from the spacer rejection region 60 is easily suppressed.

[0148] Figure 4B Showing includes Figure 4A An example of the YZ section of the d-d' section. The YZ section including the d-d' section is the YZ plane of the mesa 71 of the transistor section 70. The d-d' section is the section through the contact hole 54. (The last sentence appears to be incomplete and possibly contains errors.) Figure 3BSimilarly, the gap rejection region 60 in this example has a base region 14 as a first gap rejection section 61 and a drift region 18 as a second gap rejection section 62. The semiconductor device 100 in this example does not have an accumulation region 16, but it may also have an accumulation region 16.

[0149] In this example, the semiconductor device 100 has a plug region 13 below the trench contact portion 58. Below the trench contact portion 58, the plug region 13 extends from one end of the trench contact portion 58 along the trench extension direction to the other end of the trench contact portion 58. The plug region 13 may also be configured such that the end of the trench contact portion 58 in the trench extension direction contacts the sidewall of the trench contact portion 58. In this example, the plug region 13 is located in the non-interval rejection region 65, but a portion may also be located in the interval rejection region 60.

[0150] An interlayer insulating film 38 is disposed above the spacer rejection area 60 on the front side 21. In this example, the interlayer insulating film 38 is disposed above the first spacer rejection portion 61 and the second spacer rejection portion 62. In this example, the interlayer insulating film 38 covers both the first spacer rejection portion 61 and the second spacer rejection portion 62 disposed on the front side 21. On the other hand, the interlayer insulating film 38 has a contact hole 54 formed above the non-spacer rejection area 65, and does not cover the non-spacer rejection area 65 in the d-d' section.

[0151] Since the semiconductor device 100 in this example does not have a Schottky junction that allows the drift region 18, which serves as the second spacer rejection section 62, to contact the emitter electrode 52, leakage current is easily suppressed. It should be noted that in this example, the contact hole 54 and the trench contact section 58 are only provided above the non-spacer rejection section 65, but the contact hole 54 and the trench contact section 58 could also be provided above the first spacer rejection section 61, or even above the second spacer rejection section 62.

[0152] Figure 4C Showing includes Figure 4A Example of deformation of the YZ section of the d-d' section. In this example, the semiconductor device 100 and... Figure 4B The difference in the semiconductor device 100 lies in having an accumulation region 16. In this example, particularly for... Figure 4B The semiconductor device has 100 different points described, and other points can be compared with... Figure 4B The semiconductor device 100 is the same.

[0153] The accumulation zone 16 is configured to extend along the trench extension direction below the intermittent rejection zones 60 and non-intermittent rejection zones 65, which are repeatedly arranged along the trench extension direction. The lower end of the base zone 14 is configured to contact the upper end of the accumulation zone 16. The lower end of the second intermittent rejection section 62, which serves as the drift zone 18, is configured to contact the upper end of the accumulation zone 16. The lower end of the base zone 14 may be the same as the lower end of the second intermittent rejection section 62, which serves as the drift zone 18. It should be noted that in this example, the accumulation zone 16 is configured below both the intermittent rejection zones 60 and non-intermittent rejection zones 65, but it may also be configured below only one of them.

[0154] Figure 4D Showing includes Figure 4A Example of deformation of the YZ section of the d-d' section. In this example, the semiconductor device 100 and... Figure 4C The difference in the semiconductor device 100 lies in having a first conductivity type region 162 as a second spacer rejection section 62. In this example, this is particularly relevant to... Figure 4C The semiconductor device has 100 different points described, and other points can be compared with... Figure 4C The semiconductor device 100 is the same.

[0155] The first conductivity type region 162 is a region of the first conductivity type with a higher doping concentration than the drift region 18. The first conductivity type region 162 can be formed by ion implantation of a first conductivity type dopant relative to the accumulation region 16. The first conductivity type dopant used to form the first conductivity type region 162 can be selectively ion implanted using a mask. The first conductivity type dopant used to form the first conductivity type region 162 can be selectively ion implanted only into the region where the second spacer rejection portion 62 is to be formed. The first conductivity type dopant used to form the first conductivity type region 162 can also be ion implanted into regions other than the second spacer rejection portion 62, such as the first spacer rejection portion 61 or the non-spacer rejection region 65.

[0156] Figure 4E Showing includes Figure 4A Example of deformation of the YZ section of the d-d' section. In this example, the semiconductor device 100 and... Figure 4B The difference in the semiconductor device 100 is that it includes an anode region 19 as a second spacer rejection section 62. In this example, it is particularly relevant to... Figure 4B The semiconductor device has 100 different points described, and other points can be compared with... Figure 4B The semiconductor device 100 is the same.

[0157] The anode region 19 can be configured to be sandwiched between two adjacent base regions 14 in the trench extension direction. The base regions 14 and the anode region 19 can be formed by selectively ion-implanting dopants for forming the base regions 14 after ion-implanting the dopant for forming the anode region 19 into the entire surface of the mesa 71. It should be noted that the base regions 14 and the anode region 19 can be formed by selectively ion-implanting dopants for forming the anode region 19 into the region where the anode region 19 is to be formed, and then selectively ion-implanting dopants for forming the base regions 14 into the region where the base regions 14 are to be formed.

[0158] Depth D19 is the distance in the depth direction of the semiconductor substrate 10 from the front side 21 to the lower end of the anode region 19. Depth D14 is the distance in the depth direction of the semiconductor substrate 10 from the front side 21 to the lower end of the base region 14. Depth D19 can be greater than depth D14. That is, in the depth direction of the semiconductor substrate 10, the lower end of the anode region 19 can be deeper than the lower end of the base region 14. In the depth direction of the semiconductor substrate 10, the lower end of the anode region 19 can be deeper than the lower ends of the emitter region 12 and the contact region 15. In the depth direction of the semiconductor substrate 10, the lower end of the anode region 19 can be deeper than the lower end of the trench contact portion 58.

[0159] Figure 4F Showing includes Figure 4A A variation of the YZ section of the d-d' section. In the semiconductor device 100 of this example, the depth of the anode region 19 is... Figure 4E The depth of the anode region 19 of the semiconductor device 100 differs. In this example, it is particularly relevant to... Figure 4E The semiconductor device has 100 different points described, and other points can be compared with... Figure 4E The semiconductor device 100 is the same.

[0160] Depth D19 is less than depth D14. That is, in the depth direction of the semiconductor substrate 10, the lower end of the anode region 19 is shallower than the lower end of the base region 14. In the depth direction of the semiconductor substrate 10, the lower end of the anode region 19 may be deeper than the lower ends of the emitter region 12 and the contact region 15. In the depth direction of the semiconductor substrate 10, the lower end of the anode region 19 may be deeper than the lower end of the trench contact portion 58.

[0161] Figure 4G Showing includes Figure 4A Example of deformation of the YZ section of the d-d' section. In this example, the semiconductor device 100 and... Figure 4F The difference in the semiconductor device 100 is that it has an accumulation region 16. In this example, it is particularly relevant to... Figure 4F The semiconductor device has 100 different points described, and other points can be compared with... Figure 4F The semiconductor device 100 is the same.

[0162] The accumulation zone 16 is configured to extend along the trench extension direction below the intermittent rejection zones 60 and non-intermittent rejection zones 65, which are repeatedly arranged along the trench extension direction. The lower end of the base zone 14 is positioned to contact the upper end of the accumulation zone 16. The lower end of the anode zone 19 is positioned to contact the upper end of the accumulation zone 16. Thus, the lower end of the base zone 14 can be the same as the lower end of the anode zone 19. It should be noted that in this example, the accumulation zone 16 is positioned below both the intermittent rejection zones 60 and non-intermittent rejection zones 65, but it can also be positioned below only one of them.

[0163] Figure 5A A modified top view of the mesa 71 is shown. This example illustrates one structure of the mesa 71, which can be applied to the mesa 71 of other semiconductor devices 100. The semiconductor device 100 in this example includes a non-interval rejection region 67.

[0164] The non-spaced rejection region 67 is a region obtained by changing a portion of the spaced rejection regions 60, which are regularly arranged in the trench extension direction, into a non-spaced rejection region 65. The non-spaced rejection region 67 includes an emitter region 12 and a contact region 15. In this example, the emitter region 12 of the non-spaced rejection region 67 is sandwiched between two adjacent contact regions 15 in the trench extension direction. The non-spaced rejection region 67 in this example has the same structure as the non-spaced rejection region 65, but it can also be different. The doping concentration of each region of the non-spaced rejection region 67 and the width of each region in the trench extension direction can be the same as those of the non-spaced rejection region 65.

[0165] Length L67 is the length of the non-interval rejection zone 67 in the groove extension direction of the front side 21. Length L67 can be the same as or different from length L65. In this example, length L67 is the same as length L65.

[0166] The length L12' of the emission region 12 in the non-interval rejection region 67 can be the same as or different from the length L12 of the emission region 12 in the non-interval rejection region 65. In this example, the length L12' of the emission region 12 in the non-interval rejection region 67 is the same as the length L12 of the emission region 12 in the non-interval rejection region 65. Similarly, the length L15' of the contact region 15 in the non-interval rejection region 67 can be the same as or different from the length L15 of the contact region 15 in the non-interval rejection region 65. In this example, the length L15' of the contact region 15 in the non-interval rejection region 67 is the same as the length L15 of the contact region 15 in the non-interval rejection region 65.

[0167] Figure 5BA modified top view of the mesa 71 is shown. This example illustrates a structure of the mesa 71 that can be applied to the mesa 71 of other semiconductor devices 100. The structure of the non-interval rejection region 67 of the mesa 71 in this example is similar to... Figure 5A The structure of the non-interval removal area 67 on the platform surface 71 is different. In this example, it is particularly important to compare it with... Figure 5A The 71 different points on the platform surface will be explained, and the other points can be compared with... Figure 5A The 71 surfaces are identical.

[0168] The non-spaced rejection region 67 has a different structure than the non-spaced rejection region 65. At least one of the doping concentration of each region of the non-spaced rejection region 67 and the width of each region in the trench extension direction may differ from that of the non-spaced rejection region 65. In this example, each region of the non-spaced rejection region 67 has the same doping concentration as each region of the non-spaced rejection region 65, but may also have different doping concentrations.

[0169] The length L15' of the contact area 15 in the non-interval rejection region 67 is different from the length L15 of the contact area 15 in the non-interval rejection region 65. In this example, the length L15' of the contact area 15 in the non-interval rejection region 67 is shorter than the length L15 of the contact area 15 in the non-interval rejection region 65, but it can also be longer than the length L15. On the other hand, the length L12' of the emission region 12 in the non-interval rejection region 67 in this example is the same as the length L12 of the emission region 12 in the non-interval rejection region 65, but it can also be different from the length L12. The length L12' of the emission region 12 in the non-interval rejection region 67 can be longer than the length L12 of the emission region 12 in the non-interval rejection region 65, or it can be shorter than the length L12. In addition to adjusting the area of ​​the contact area 15 by setting the interval rejection region 60, the area of ​​the contact area 15 in the non-interval rejection region 67 is also adjusted, thereby making it easy to adjust the size of hole injection.

[0170] Figure 6AThe ratio α dependence of the switching loss Err during reverse recovery is shown. The vertical axis represents the switching loss Err (au) during reverse recovery, and the horizontal axis represents the ratio α. Curve Gc represents the characteristics of the semiconductor device of the comparative example, and curve G100 represents the characteristics of the semiconductor device 100. The semiconductor device of the comparative example is a semiconductor device without the spacer rejection region 60. If the ratio α of the length L65 of the spacer P12 relative to the trench extension direction of the non-spacer rejection region 65 becomes larger, the P-type region in the transistor section 70 increases and the hole injection increases, thus tending to increase the switching loss Err during reverse recovery. By having the spacer rejection region 60, the semiconductor device 100 can easily reduce the switching loss Err during reverse recovery even when the ratio α becomes larger. In particular, if the ratio α exceeds 1.5, the effect of reducing the switching loss Err during reverse recovery in curve G100 of the semiconductor device 100 becomes significant compared to curve Gc of the semiconductor device of the comparative example. The ratio α can be above 1.5, above 2.0, above 2.5, or above 3.0. The ratio α can be below 20, below 10, below 7.0, below 5.0, or below 3.0.

[0171] Figure 6B This shows the ratio α dependence of the collector current's saturation current Isat. The vertical axis represents the collector current's saturation current Isat (au), and the horizontal axis represents the ratio α. If the ratio α of the spacing P12 relative to the length L65 in the trench extension direction of the non-spacing rejection region 65 increases, the saturation current Isat decreases. Short-circuit withstand capability is improved by reducing the saturation current Isat.

[0172] Because the semiconductor device 100 has an interval rejection region 60, the short-circuit withstand capability can be increased by increasing the ratio α, and the switching loss Err during reverse recovery can be suppressed. In addition, because the semiconductor device 100 has a trench contact portion 58, the latch-up withstand capability can be further improved.

[0173] Figure 7 An example of a method for manufacturing a semiconductor device 100 is shown. In this example, an example of a method for manufacturing a semiconductor device 100 is shown, and the order of each step can be appropriately changed.

[0174] Steps S100 and S102 are an example of the stages for forming the spaced-out region 60. In step S100, an anode region 19 is formed above the drift region 18. In step S102, a base region 14 is formed above the drift region 18. When the base region 14 and the anode region 19 have the same doping concentration, the base region 14 and the anode region 19 can be formed simultaneously using a common process.

[0175] The base region 14 and the anode region 19 can be formed by selectively ion-implanting a dopant of a second conductivity type, depending on the structure of the spacer-knockout region 60. In this example, the base region 14 is formed after the anode region 19 is formed, but the anode region 19 can also be formed after the base region 14 is formed. Regions with low doping concentrations in the base region 14 and the anode region 19 can be formed first. The spacer-knockout region 60 can be formed by ion-implanting a dopant of a second conductivity type into the anode region 19 of the transistor section 70 after the anode region 19 is formed in the transistor section 70 and the diode section 80. The doping concentration of the base region 14 can be higher than that of the anode region 19.

[0176] In step S104, a plurality of trench portions are formed on the front side 21 of the semiconductor substrate 10. The dummy trench portions 30 and the gate trench portions 40 can be formed simultaneously using a common process, or they can be formed separately. Alternatively, an interleaved rejection region 60 can be formed after the plurality of trench portions are formed.

[0177] In step S106, a non-spaced rejection region 65 is formed on the front side 21 of the semiconductor substrate 10. The non-spaced rejection region 65 is formed on the mesa 71 between a plurality of trench portions. The contact region 15 may be formed after the emitter region 12 is formed, or the emitter region 12 may be formed after the contact region 15 is formed. In the case of forming the non-spaced rejection region 67, the non-spaced rejection region 67 may be formed simultaneously with the non-spaced rejection region 65.

[0178] In step S108, a trench contact portion 58 is formed. The plug region 13 can be formed by ion implanting a dopant of a second conductivity type into the lower end of the contact hole 54 after forming the trench contact portion 58. The trench contact portion 58 can also be formed by filling the contact hole 54 with barrier metal 53 and the plug portion 59 after forming the plug region 13.

[0179] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. Various modifications or improvements to the above embodiments will be apparent to those skilled in the art. As will be clearly understood from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

[0180] It should be noted that the execution order of actions, sequences, steps, stages, etc., in the apparatus, system, program, and method shown in the claims, specification, and drawings can be implemented in any order, as long as there is no specific indication of "before" or "before," and as long as the output of the previous process is not used in the later process. Even if the flow of actions in the claims, specification, and drawings is described using terms such as "firstly," "next," etc., for convenience, it does not mean that they must be implemented in that order. Claims (as amended under Article 19 of the Treaty) 1. A semiconductor device, characterized in that it comprises a transistor portion and a diode portion, said semiconductor device comprising: A drift region of a first conductivity type is disposed on a semiconductor substrate; and Multiple trench portions extend along a predetermined trench extension direction on the front side of the semiconductor substrate. The transistor section has: The base region of the second conductivity type is disposed above the drift region; The first conductivity type has multiple emitter regions discretely arranged along the trench extension direction, and the doping concentration is higher than that of the drift region; The contact region of the second conductivity type has a higher doping concentration than the base region; A trench contact portion, which is provided in a mesa-shaped portion between two adjacent trench portions in a manner extending from the front side of the semiconductor substrate along the depth direction of the semiconductor substrate; and An interval rejection region is disposed between two adjacent emitter regions in the trench extension direction among the plurality of emitter regions, and the doping concentration of the second conductivity type is lower than the doping concentration of the second conductivity type in the contact region. 2. The semiconductor device according to claim 1, characterized in that, The interval removal region is the base region. 3. The semiconductor device according to claim 1, characterized in that, The interval rejection region has: A first spacer rejection portion is disposed between two adjacent emitter regions, arranged to contact the contact region on the front side of the semiconductor substrate; and The second spacer rejection portion is disposed between the two adjacent emitter regions, in such a way that it contacts the first spacer rejection portion on the front side of the semiconductor substrate, and the doping concentration is different from that of the first spacer rejection portion. 4. The semiconductor device according to claim 3, characterized in that, The first interval rejection section includes a plurality of first interval rejection sections. The second interval rejection portion is disposed on the front side between two adjacent first interval rejection portions in the groove extension direction among the plurality of first interval rejection portions. 5. The semiconductor device according to claim 3, characterized in that, The first interval rejection portion is the base region. The second gap rejection section has a doping concentration of a first conductivity type that is lower than the doping concentration of the emitter region. 6. The semiconductor device according to claim 5, characterized in that, The second interval rejection section is the drift region. 7. The semiconductor device according to claim 3, characterized in that, The first interval rejection portion is the base region. The second gap removal portion has a doping concentration of a second conductivity type that is lower than the doping concentration of the base region. 8. The semiconductor device according to claim 7, characterized in that, The diode section has an anode region of a second conductivity type disposed above the drift region. The second interval rejection section is the anode region. 9. The semiconductor device according to claim 1, characterized in that, The contact area has multiple contact zones. The plurality of contact areas are disposed at both ends of the emission area in the direction of the trench extension and are in contact with the emission area on the front side. 10. The semiconductor device according to claim 3, characterized in that, The contact area is disposed between the emission area and the first interval rejection portion adjacent to each other in the trench extension direction. On the front side, one end of the contact area contacts the emission area, and the other end of the contact area contacts the first interval rejection portion. 11. The semiconductor device according to claim 10, characterized in that, The first interval rejection section is disposed below the contact area. The length of the trench in the first spacer rejection portion on the front side in the extension direction is greater than or equal to the thickness in the depth direction of the semiconductor substrate in the first spacer rejection portion below the contact area. 12. The semiconductor device according to claim 11, characterized in that, The length of the first spaced-out portion disposed on the front side in the groove extension direction is more than 0.1 μm and less than 2.0 μm. 13. The semiconductor device according to claim 3, characterized in that, On the front side, the length of the second spaced rejection portion in the trench extension direction is greater than the length of the first spaced rejection portion in the trench extension direction. 14. The semiconductor device according to claim 3, characterized in that, On the front side, the length of the second spaced rejection portion in the trench extension direction is greater than the length of the emission region in the trench extension direction. 15. The semiconductor device according to claim 3, characterized in that, The semiconductor device includes an interlayer insulating film disposed above the first spacer rejection portion and the second spacer rejection portion, and covering both the first spacer rejection portion and the second spacer rejection portion disposed on the front side. 16. The semiconductor device according to claim 15, characterized in that, The interlayer insulating film has contact holes. When viewed from above, the grooved contact portion is provided in the area where the contact hole is provided, and the area where the contact hole is not provided when viewed from above is the grooved contact non-forming area where the grooved contact portion is not provided. 17. The semiconductor device according to any one of claims 1 to 16, characterized in that, The ratio α is greater than 1.5 and less than 20, where the ratio α is the ratio of the interval between two adjacent emission regions in the trench extension direction to the length of the non-interval rejection region formed by continuously forming one or more emission regions and one or more contact regions in the trench extension direction. 18. The semiconductor device according to any one of claims 1 to 16, characterized in that, Above the drift region is an accumulation region of a first conductivity type with a higher doping concentration than the drift region. 19. The semiconductor device according to any one of claims 1 to 16, characterized in that, The semiconductor device includes a second conductivity type plug region disposed at the lower end of the trench contact portion, and the doping concentration of the second conductivity type plug region is higher than that of the base region. 20. The semiconductor device according to any one of claims 1 to 16, characterized in that, The diode portion has an anode region of a second conductivity type with a lower doping concentration than the base region. 21. The semiconductor device according to any one of claims 1 to 16, characterized in that, The transistor section has a boundary region disposed on the side of the transistor section adjacent to the diode section. 22. The semiconductor device according to any one of claims 1 to 16, characterized in that, There is no lifetime inhibitor region located closer to the front side than the center in the depth direction of the semiconductor substrate. 23. [After correction] The semiconductor device according to claim 2, characterized in that, The sidewall of the groove contact portion contacts the base region of the interval rejection area. 24. [After correction] The semiconductor device according to any one of 1 to 16, characterized in that, The semiconductor device includes a non-spaced rejection region, wherein one or more emitter regions and one or more contact regions are continuously formed in the non-spaced rejection region. The length of the spaced rejection area on the front side in the trench extension direction is less than the length of the non-spaced rejection area on the front side in the trench extension direction. 25. [Additional] The semiconductor device according to claim 16, characterized in that, The groove contact portion and the groove contact non-forming area are alternately provided along the extension direction of the groove. 26. [Additional] The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a plug region of a second conductivity type, which is disposed at the lower end of the trench contact portion and has a higher doping concentration than the base region. The interval rejection region is the base region. The plug region is in contact with the base region of the interval removal region. 27. [Additional] The semiconductor device according to claim 1, characterized in that, The plug region has a second conductivity type, which is located at the lower end of the trench contact portion and has a higher doping concentration than the base region. The interval rejection region includes the base region and the drift region. The plug area is in contact with the drift area of ​​the interval rejection area. 28. [Additional] The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a plug region of a second conductivity type, which is disposed at the lower end of the trench contact and has a higher doping concentration than the base region. The diode portion has an anode region of a second conductivity type with a lower doping concentration than the base region. The interval rejection region includes the base region and the anode region. The plug area is in contact with the anode area of ​​the interval rejection area. 29. [Additional] The semiconductor device according to claim 1, characterized in that it comprises: A non-interval rejection region, which continuously forms one or more emission regions and one or more contact regions; and An interlayer insulating film is disposed above the spacer rejection area. The groove contact portion is located in the non-interval rejection area. The groove contact portion is held between two adjacent interlayer insulating films in the groove extension direction. 30. [Additional] The semiconductor device according to any one of claims 1 to 16, characterized in that, The semiconductor device includes a plug region of a second conductivity type, which is disposed at the lower end of the trench contact and has a higher doping concentration than the base region. The lower end of the plug area is shallower than the lower end of the contact area. 31. [Additional] The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a non-spaced rejection region, wherein one or more emitter regions and one or more contact regions are continuously formed in the non-spaced rejection region. In the depth direction of the semiconductor substrate, the upper depth of the spaced rejection region is shallower than the upper depth of the non-spaced rejection region. 32. [Additional] A method for manufacturing a semiconductor device, characterized in that it is a method for manufacturing a semiconductor device comprising a transistor portion and a diode portion, the method comprising: The step of forming a base region of a second conductivity type above a drift region of a first conductivity type disposed on a semiconductor substrate; The step of forming a plurality of trench portions extending along a predetermined trench extension direction on the front side of a semiconductor substrate; The step of discretely forming multiple emitter regions of a first conductivity type with a doping concentration higher than that of the drift region along the trench extension direction; The step of forming a contact region of a second conductivity type with a doping concentration higher than that of the base region; The step of forming a trench contact portion in the transistor portion at the mesa between two adjacent trench portions of the plurality of trench portions, extending from the front side of the semiconductor substrate along the depth direction of the semiconductor substrate; and The step of forming a gap rejection region between two adjacent emitter regions in the trench extension direction, wherein the doping concentration of the second conductivity type is lower than that of the contact region. 33. [Additional] The method for manufacturing a semiconductor device according to claim 32, characterized in that, The interval rejection region includes the base region. The step of forming the spaced-out region includes forming the base region by ion implantation of a dopant of a second conductivity type into the anode region of the transistor portion after forming the anode region in the transistor portion and the diode portion.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes a transistor section and a diode section, and includes: A drift region of a first conductivity type is disposed on a semiconductor substrate; and Multiple trench portions extend along a predetermined trench extension direction on the front side of the semiconductor substrate. The transistor section has: The base region of the second conductivity type is disposed above the drift region; The first conductivity type has multiple emitter regions discretely arranged along the trench extension direction, and the doping concentration is higher than that of the drift region; The contact region of the second conductivity type has a higher doping concentration than the base region; A trench contact portion is provided in a mesa between two adjacent trench portions in a manner that extends from the front side of the semiconductor substrate along the depth direction of the semiconductor substrate. as well as An interval rejection region is disposed between two adjacent emitter regions in the trench extension direction among the plurality of emitter regions, and the doping concentration of the second conductivity type is lower than the doping concentration of the second conductivity type in the contact region.

2. The semiconductor device according to claim 1, characterized in that, The interval removal region is the base region.

3. The semiconductor device according to claim 1, characterized in that, The interval rejection region has: A first spacer rejection portion is disposed between two adjacent emitter regions, arranged to contact the contact region on the front side of the semiconductor substrate; and The second spacer rejection portion is disposed between the two adjacent emitter regions, in such a way that it contacts the first spacer rejection portion on the front side of the semiconductor substrate, and the doping concentration is different from that of the first spacer rejection portion.

4. The semiconductor device according to claim 3, characterized in that, The first interval rejection section includes a plurality of first interval rejection sections. The second interval rejection portion is disposed on the front side between two adjacent first interval rejection portions in the groove extension direction among the plurality of first interval rejection portions.

5. The semiconductor device according to claim 3, characterized in that, The first interval rejection portion is the base region. The second gap rejection section has a doping concentration of a first conductivity type that is lower than the doping concentration of the emitter region.

6. The semiconductor device according to claim 5, characterized in that, The second interval rejection section is the drift region.

7. The semiconductor device according to claim 3, characterized in that, The first interval rejection portion is the base region. The second gap removal portion has a doping concentration of a second conductivity type that is lower than the doping concentration of the base region.

8. The semiconductor device according to claim 7, characterized in that, The diode section has an anode region of a second conductivity type disposed above the drift region. The second interval rejection section is the anode region.

9. The semiconductor device according to claim 1, characterized in that, The contact area has multiple contact zones. The plurality of contact areas are disposed at both ends of the emission area in the direction of the trench extension and are in contact with the emission area on the front side.

10. The semiconductor device according to claim 3, characterized in that, The contact area is disposed between the emission area and the first interval rejection portion adjacent to each other in the trench extension direction. On the front side, one end of the contact area contacts the emission area, and the other end of the contact area contacts the first interval rejection portion.

11. The semiconductor device according to claim 10, characterized in that, The first interval rejection section is disposed below the contact area. The length of the trench in the first spacer rejection portion on the front side in the extension direction is greater than or equal to the thickness in the depth direction of the semiconductor substrate in the first spacer rejection portion below the contact area.

12. The semiconductor device according to claim 11, characterized in that, The length of the first spaced-out portion disposed on the front side in the groove extension direction is 0.1 μm or more and 2.0 μm or less.

13. The semiconductor device according to claim 3, characterized in that, On the front side, the length of the second spaced rejection portion in the trench extension direction is greater than the length of the first spaced rejection portion in the trench extension direction.

14. The semiconductor device according to claim 3, characterized in that, On the front side, the length of the second spaced rejection portion in the trench extension direction is greater than the length of the emission region in the trench extension direction.

15. The semiconductor device according to claim 3, characterized in that, The semiconductor device includes an interlayer insulating film disposed above the first spacer rejection portion and the second spacer rejection portion, and covering both the first spacer rejection portion and the second spacer rejection portion disposed on the front side.

16. The semiconductor device according to claim 15, characterized in that, The interlayer insulating film has contact holes. When viewed from above, the grooved contact portion is provided in the area where the contact hole is provided, and the area where the contact hole is not provided when viewed from above is the grooved contact non-forming area where the grooved contact portion is not provided.

17. The semiconductor device according to any one of claims 1 to 16, characterized in that, The ratio α is greater than 1.5 and less than 20, where the ratio α is the ratio of the interval between two adjacent emission regions in the trench extension direction to the length of the non-interval rejection region formed by continuously forming one or more emission regions and one or more contact regions in the trench extension direction.

18. The semiconductor device according to any one of claims 1 to 16, characterized in that, Above the drift region is an accumulation region of a first conductivity type with a higher doping concentration than the drift region.

19. The semiconductor device according to any one of claims 1 to 16, characterized in that, The semiconductor device includes a second conductivity type plug region disposed at the lower end of the trench contact portion, and the doping concentration of the second conductivity type plug region is higher than that of the base region.

20. The semiconductor device according to any one of claims 1 to 16, characterized in that, The diode portion has an anode region of a second conductivity type with a lower doping concentration than the base region.

21. The semiconductor device according to any one of claims 1 to 16, characterized in that, The transistor section has a boundary region disposed on the side of the transistor section adjacent to the diode section.

22. The semiconductor device according to any one of claims 1 to 16, characterized in that, There is no lifetime inhibitor region located closer to the front side than the center in the depth direction of the semiconductor substrate.

23. A method for manufacturing a semiconductor device, characterized in that, This is a method for manufacturing a semiconductor device comprising a transistor section and a diode section, the method comprising: The step of forming a base region of a second conductivity type above a drift region of a first conductivity type disposed on a semiconductor substrate; The step of forming a plurality of trench portions extending along a predetermined trench extension direction on the front side of a semiconductor substrate; The step of discretely forming multiple emitter regions of a first conductivity type with a doping concentration higher than that of the drift region along the trench extension direction; The step of forming a contact region of a second conductivity type with a doping concentration higher than that of the base region; The step of forming a trench contact portion in the transistor portion on the mesa between two adjacent trench portions in the plurality of trench portions, in a manner extending from the front side of the semiconductor substrate along the depth direction of the semiconductor substrate; as well as The step of forming a gap rejection region between two adjacent emitter regions in the trench extension direction, wherein the doping concentration of the second conductivity type is lower than that of the contact region.

24. The method for manufacturing a semiconductor device according to claim 23, characterized in that, The interval rejection region includes the base region. The step of forming the spaced-out region includes forming the base region by ion implantation of a dopant of a second conductivity type into the anode region of the transistor portion after forming the anode region in the transistor portion and the diode portion.

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