Semiconductor device

Abstract

The semiconductor device is provided with an RC-IGBT. A first electrode in contact with the front surface of the semiconductor substrate; a second electrode in contact with the back surface of the semiconductor substrate; a plurality of trenches formed on the front surface side of the semiconductor substrate; and a third electrode covered with an insulating film in the trenches. A first semiconductor layer of a second conductivity type in contact with the second electrode in the IGBT region; a second semiconductor layer of the first conductivity type in contact with the second electrode in the diode region; and a third semiconductor layer of the first conductivity type in contact with the upper surfaces of the first semiconductor layer and the second semiconductor layer. The semiconductor substrate includes a first semiconductor layer of the second conductivity type in contact with the first electrode and the insulating film in the trench, a fourth semiconductor layer of the second conductivity type in contact with the first electrode and the insulating film in the trench, and a fifth semiconductor layer of the first conductivity type in contact with the first electrode and the insulating film in the trench in the IGBT region and surrounded by the fourth semiconductor layer, and has a low-lifetime region in the semiconductor substrate in the vicinity of the center of the IGBT region.

Description

Technical Field

[0001] This invention relates to a semiconductor device that incorporates an IGBT and a diode within the same semiconductor device. Background Technology

[0002] The peripheral breakdown voltage structure of an IGBT (Insulated Gate Bipolar Transistor) and a reverse-conducting IGBT (RC-IGBT), which integrates both an IGBT and a diode connected in reverse parallel to the IGBT, can be shared within a single semiconductor device. Therefore, the RC-IGBT reduces the chip area compared to combining separately manufactured IGBTs and diodes.

[0003] In addition, the RC-IGBT dissipates heat generated in the IGBT region to the diode side and heat generated in the diode region to the IGBT side, thus enabling it to operate with higher current density and heat density than before.

[0004] On the other hand, it is also required to improve the reverse bias safe operating area (RBSOA), which is an indicator of the IGBT's current interruption capability, so that the device will not be damaged even if the current density increases.

[0005] For example, Patent Document 1 describes how by forming the p+ type contact layer of the IGBT into a p-type well layer that penetrates the outer peripheral region, the overlapping part of the p+ type contact layer and the p-type well layer becomes low resistance, making it difficult for the potential to increase, and reducing the inflow of hole current into the n+ type emitter layer, thereby minimizing the reduction of the reverse bias safe operating area (RBSOA).

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2022-59487 Summary of the Invention

[0009] The problem that the invention aims to solve

[0010] However, the structure described in Patent Document 1 has the effect of preventing the reduction of RBSOA in the boundary region between the IGBT and the peripheral region, but Patent Document 1 does not propose a method to prevent the reduction of RBSOA in the active region of the IGBT that occupies a large area in the RC-IGBT.

[0011] To address the aforementioned problems, the present invention aims to provide a semiconductor device for an RC-IGBT with an improved reverse bias safety operating area (RBSOA).

[0012] Furthermore, the above-mentioned and other objectives of the present invention, as well as the novel features of the present invention, become clear from the description and drawings herein.

[0013] Methods for solving problems

[0014] The semiconductor device of the present invention is a semiconductor device having an IGBT and a diode formed on the same semiconductor substrate, which is a reverse-conducting IGBT.

[0015] Furthermore, the semiconductor device of the present invention comprises: a semiconductor substrate of a first conductivity type; a first electrode in contact with the surface of the semiconductor substrate; a second electrode in contact with the back side of the semiconductor substrate; a plurality of trenches formed on the surface side of the semiconductor substrate; an insulating film formed in the trenches; and a third electrode covered by the insulating film.

[0016] Furthermore, the semiconductor device of the present invention comprises: a first semiconductor layer of a second conductivity type, which is connected to a second electrode in the IGBT region where an IGBT is formed; a second semiconductor layer of a first conductivity type, which is connected to the second electrode in the diode region where a diode is formed; a third semiconductor layer of a first conductivity type, which is connected to the upper surfaces of the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer of a second conductivity type, which is connected to the first electrode and the insulating film in the trench; and a fifth semiconductor layer of a first conductivity type, which is connected to the first electrode and the insulating film in the trench in the IGBT region and is surrounded by the fourth semiconductor layer.

[0017] The first semiconductor device of the present invention has a structure in which the semiconductor substrate of the IGBT cell near the center of the IGBT region also has a low lifetime region.

[0018] The second semiconductor device of the present invention is further configured such that a fifth semiconductor layer is formed in the IGBT cells in the portion of the IGBT region other than the center, and no fifth semiconductor layer is formed in the IGBT cells in the IGBT region near the center.

[0019] Invention Effects

[0020] According to the structure of the semiconductor device of the first invention, a low-lifetime region is present in the semiconductor substrate of the IGBT cell near the center of the IGBT region.

[0021] In IGBT cells near the center of the IGBT region, the amount of charge carriers accumulated due to the conductivity modulation effect is reduced through the low lifetime region. Therefore, the total amount of charge carriers discharged during turn-off can be reduced, and the base current supplied to the parasitic thyristors present in the IGBT can be reduced.

[0022] This prevents latch-up failure in the IGBT region and improves the reverse bias safe operating area (RBSOA).

[0023] According to the structure of the semiconductor device of the second invention, a fifth semiconductor layer is formed in the IGBT cell in the portion of the IGBT region other than the center, and no fifth semiconductor layer is formed in the IGBT cell near the center of the IGBT region.

[0024] In the IGBT cell near the center of the IGBT region, no parasitic thyristor is formed in the IGBT because no fifth semiconductor layer is formed.

[0025] This prevents latch-up failure in the IGBT region and improves the reverse bias safe operating area (RBSOA).

[0026] Furthermore, the issues, structures, and effects other than those described above will be clarified through the following description of the implementation methods. Attached Figure Description

[0027] Figure 1 This is an enlarged cross-sectional view of the main part of the semiconductor device in Example 1.

[0028] Figure 2 This is an enlarged cross-sectional view of the main part of the semiconductor device in Example 2.

[0029] Figure 3 This is an enlarged cross-sectional view of the main part of the semiconductor device in Example 3.

[0030] Figure 4 This is an enlarged cross-sectional view of the main part of the semiconductor device in Example 4.

[0031] Figure 5 yes Figure 4 A horizontal sectional view of XX′.

[0032] Figure 6 This is an enlarged cross-sectional view of the main part of an existing semiconductor device with a reverse-conducting IGBT.

[0033] Figure 7 yes Figure 6 A horizontal sectional view of XX′. Detailed Implementation

[0034] The embodiments and examples of the present invention will be described below using text and accompanying drawings. However, the structures, materials, and other specific configurations shown in the present invention are not limited to the embodiments and examples presented herein, and can be appropriately combined and modified without changing the spirit of the invention. Furthermore, elements not directly related to the present invention are omitted from the illustrations.

[0035] The semiconductor device of the present invention is a semiconductor device having an IGBT and a diode formed on the same semiconductor substrate, which is a reverse-conducting IGBT.

[0036] Furthermore, the semiconductor device of the present invention comprises: a semiconductor substrate of a first conductivity type; a first electrode which is in contact with the surface of the semiconductor substrate; a second electrode which is in contact with the back side of the semiconductor substrate; a plurality of trenches which are formed on the surface side of the semiconductor substrate; an insulating film which is formed in the trenches; and a third electrode which is covered by the insulating film.

[0037] Furthermore, the semiconductor device of the present invention comprises: a first semiconductor layer of a second conductivity type, which is connected to a second electrode in the IGBT region where an IGBT is formed; a second semiconductor layer of a first conductivity type, which is connected to the second electrode in the diode region where a diode is formed; a third semiconductor layer of a first conductivity type, which is connected to the upper surfaces of the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer of a second conductivity type, which is connected to the first electrode and the insulating film in the trench; and a fifth semiconductor layer of a first conductivity type, which is connected to the first electrode and the insulating film in the trench in the IGBT region and is surrounded by the fourth semiconductor layer.

[0038] The first semiconductor device of the present invention has a structure in which the semiconductor substrate of the IGBT cell near the center of the IGBT region also has a low lifetime region.

[0039] The second semiconductor device of the present invention is further configured such that a fifth semiconductor layer is formed in the IGBT cells in the portion of the IGBT region other than the center, and no fifth semiconductor layer is formed in the IGBT cells in the IGBT region near the center.

[0040] According to the structure of the semiconductor device of the first invention, a low-lifetime region is present in the semiconductor substrate of the IGBT cell near the center of the IGBT region.

[0041] Because the semiconductor substrate of the IGBT cell near the center of the IGBT region has a low lifetime region, the amount of carriers accumulated due to the conductivity modulation effect can be reduced in the IGBT cell near the center of the IGBT region. Since the amount of carrier accumulation can be reduced, the total amount of carriers discharged during turn-off is reduced, and the base current supplied to the pnpn parasitic thyristor present in the IGBT is reduced.

[0042] Therefore, latch-up damage in the IGBT region caused by the aforementioned base current can be prevented, and the reverse bias safe operating area (RBSOA) can be improved.

[0043] According to the structure of the semiconductor device of the second invention, a fifth semiconductor layer is formed in the IGBT cell in the portion of the IGBT region other than the center, and no fifth semiconductor layer is formed in the IGBT cell near the center of the IGBT region.

[0044] In the IGBT cell near the center of the IGBT region, no parasitic thyristor is formed in the IGBT because no fifth semiconductor layer is formed.

[0045] This prevents latch-up damage in the IGBT region caused by the base current of the parasitic thyristor and improves the reverse bias safe operating area (RBSOA).

[0046] In the first semiconductor device of the present invention described above, the impurity concentration of the first semiconductor layer near the center of the IGBT region can be configured to be lower than the impurity concentration of the first semiconductor layer in the portion outside the center of the IGBT region.

[0047] In this structure, the impurity concentration of the first semiconductor layer near the center of the IGBT region is lower than that of the first semiconductor layer in other parts of the IGBT region, thus reducing the injection of minority carriers during forward current conduction. Consequently, by turning off, fewer minority carriers are discharged to the main layer (fourth semiconductor layer) near the center of the IGBT region, suppressing the base current of the parasitic thyristor and further improving RBSOA.

[0048] In the semiconductor device of the first invention described above, it is possible to configure an IGBT cell in the portion of the IGBT region other than the center of the IGBT region to have a fifth semiconductor layer formed, while an IGBT cell in the portion of the IGBT region near the center of the IGBT region does not have a fifth semiconductor layer formed.

[0049] In this configuration, similar to the semiconductor device of the second invention described above, no parasitic thyristors are formed in the IGBT cells near the center of the IGBT region. This prevents latch-up failure in the IGBT region caused by the base current of the parasitic thyristors, further improving the reverse bias safe operating area (RBSOA).

[0050] In the semiconductor device of the first invention described above, the number of fifth semiconductor layers is less compared to IGBT cells that can be configured near the center of the IGBT region and those that are located outside the center of the IGBT region.

[0051] In this structure, the number of fifth semiconductor layers is less in the IGBT cells near the center of the IGBT region compared to the IGBT cells outside the center of the IGBT region, making it difficult to form parasitic thyristor structures and suppressing latch-up failure. This further improves the reverse bias safe operating area (RBSOA).

[0052] In the semiconductor device of the second invention described above, the impurity concentration of the first semiconductor layer near the center of the IGBT region can be configured to be lower than the impurity concentration of the first semiconductor layer in the portion outside the center of the IGBT region.

[0053] In this structure, the impurity concentration of the first semiconductor layer near the center of the IGBT region is lower than that of the first semiconductor layer in other parts of the IGBT region, thus reducing the injection of minority carriers during forward current conduction. Consequently, by turning off, fewer minority carriers are discharged to the main layer (fourth semiconductor layer) near the center of the IGBT region, suppressing the base current of the parasitic thyristor and further improving RBSOA.

[0054] Example

[0055] Next, specific embodiments of the semiconductor device will be described.

[0056] (Example 1)

[0057] The following is for reference Figure 1 The structure of the semiconductor device in Example 1 will be described.

[0058] Figure 1 This is an enlarged cross-sectional view of the main part of the semiconductor device in Example 1.

[0059] Figure 1 An enlarged cross-sectional view of the IGBT region and diode region in a semiconductor device equipped with a reverse-conducting IGBT (RC-IGBT) is shown.

[0060] This embodiment illustrates an example of applying the semiconductor device of the present invention to a trench IGBT.

[0061] like Figure 1 As shown, the semiconductor device of this embodiment has a structure having an IGBT region 100 and a diode region 200 that are adjacent to each other.

[0062] An IGBT is formed in the IGBT region 100.

[0063] A diode is formed in diode region 200.

[0064] Furthermore, the semiconductor device of this embodiment includes a first conductivity type semiconductor substrate 1, an emitter electrode 10 connected to the surface of the semiconductor substrate 1, a collector electrode 11 connected to the back side of the semiconductor substrate 1, a second conductivity type collector layer 2, a first conductivity type cathode layer 3, and a first conductivity type buffer layer 4.

[0065] The emitter electrode 10 and the collector electrode 11 are formed by extending over the IGBT region 100 and the diode region 200, respectively.

[0066] A collector layer 2 of the second conductivity type (e.g., p-type) is formed on the back side of the semiconductor substrate 1 of the IGBT region 100 and is connected to the collector 11.

[0067] A cathode layer 3 of the first conductivity type (e.g., n-type) is formed on the back side of the semiconductor substrate 1 of the diode region 200 and is connected to the collector 11.

[0068] The buffer layer 4 of the first conductivity type (e.g., n-type) is grounded on the opposite side of the surface of the collector layer 2 and the cathode layer 3 that are connected to the collector 11.

[0069] In both the IGBT region 100 and the diode region 200, a second conductivity type (e.g., p-type) main layer 5 is formed on the surface side of the semiconductor substrate 1.

[0070] Additionally, in the IGBT region 100, a first conductivity type (e.g., n-type) emitter layer 6 is formed on the surface side of the main body layer 5.

[0071] The portion between the buffer layer 4 and the main layer 5 in the semiconductor substrate 1 becomes a barrier layer 7 of a first conductivity type (e.g., n-type). This barrier layer 7 of the first conductivity type functions as a hole barrier layer when the first conductivity type is n-type, and as an electron barrier layer when the first conductivity type is p-type.

[0072] The semiconductor device of this embodiment also has trenches 20 formed in the IGBT region 100 and the diode region 200, respectively, in a manner that extends from the surface of the semiconductor substrate 1 toward the back side. The trenches 20 are formed from the surface of the semiconductor substrate 1 through the main body layer 5 to the upper part of the barrier layer 7.

[0073] Furthermore, an insulating film 21 and a gate electrode 12 formed on the inner side of the trench 20 in the IGBT region 100 are provided.

[0074] In addition, an insulating film 21 and an emitter electrode 13 formed inside the trench 20 of the diode region 200 are provided.

[0075] The first conductive type of the emitter layer 6 of the IGBT region 100 is formed on the left and right sides by being connected to the outer side of the trench 20.

[0076] The gate electrode 12 and the emitter electrode 13 and emitter electrode 10 inside the trench 20 are electrically separated by an interlayer insulating film 22 formed on the trench 20.

[0077] Here, on Figure 1 The movement of charge carriers in a semiconductor device having an IGBT region 100 and a diode region 200, as shown, will be explained. Here, the configuration described above is an n-type first conductivity type, a p-type second conductivity type, with electrons as the majority charge carriers and holes as the minority charge carriers.

[0078] When a forward current is turned on, holes, which are minority carriers, are injected into the semiconductor substrate 1 of the IGBT region 100 through the conductivity modulation effect, thereby creating a state in which carriers (electrons and holes) are stored.

[0079] During the turn-off operation, which transitions from the on state to the off state, holes accumulated in the charge carriers of the IGBT region 100 flow into the emitter electrode 10 through the body layer 5 of the IGBT cell. Furthermore, some of the accumulated holes also flow into the body layer 5 on the diode region 200 side. Therefore, fewer holes are discharged from the body layer 5 within the IGBT cell near the diode region 200, and the base current of the parasitic thyristor structure (emitter layer 6 / body layer 5 / semiconductor substrate 1 and buffer layer 4 / collector layer 2) present in the IGBT is reduced.

[0080] The base current of the IGBT cell near diode region 200 is reduced due to latch-up caused by the parasitic thyristor structure, thus improving the reverse bias safe operating area (RBSOA).

[0081] On the other hand, near the center 100C of the IGBT region 100, which is located far from the diode region 200 ( Figure 1 In the IGBT cell at the left end, a portion of the holes cannot flow to the main layer 5 of the diode region 200. Therefore, in the IGBT cell near the center 100C of the IGBT region 100, the reverse bias safe operating area (RBSOA) is not enhanced, and damage may be concentrated.

[0082] Therefore, in this embodiment, as Figure 1 As shown, a low lifetime region 300 that shortens the carrier lifetime is provided in the semiconductor substrate 1 of the IGBT cell (i.e., the IGBT cell disposed at the center of the IGBT region 100) near the center 100C of the IGBT region 100.

[0083] The low-lifetime region 300 has a shorter carrier lifetime compared to other parts of the semiconductor substrate 1, thus having the characteristic that holes or electrons, which are carriers, disappear in a short time.

[0084] By forming this low-lifetime region 300, the carrier lifetime is shortened, thus reducing the number of carriers stored in the IGBT region 100 when the current is turned on.

[0085] Because the number of accumulated charge carriers decreases, the number of charge carriers flowing from the body layer 5 of the IGBT cell near the center of the IGBT region 100 to the emitter electrode 10 decreases during the turn-off operation, and the base current of the parasitic thyristor also decreases. This prevents latch-up failure near the center 100C of the IGBT region 100.

[0086] Furthermore, even with the aforementioned structure where the first conductivity type is p-type, the second conductivity type is n-type, the majority carriers are holes, and the minority carriers are electrons, a low-lifetime region 300 can still be provided in the semiconductor substrate 1 near the center 100C of the IGBT region 100. Moreover, by providing the low-lifetime region 300, latch-up failure near the center 100C of the IGBT region 100 can be prevented.

[0087] The low-lifetime region 300 can be fabricated, for example, by providing a mask on the back side other than the portion forming the low-lifetime region 300 and implanting light ions such as protons into the semiconductor substrate 1. Since light ions are implanted into the semiconductor substrate 1, lattice defects are introduced into the implanted portion of the semiconductor substrate 1, and the carrier lifetime is shortened.

[0088] According to the semiconductor device of this embodiment, a low lifetime region 300 that shortens the carrier lifetime is provided in the semiconductor substrate 1 of the IGBT cell near the center 100C of the IGBT region 100.

[0089] Because the carrier lifetime is shortened by passing through the low-lifetime region 300, the number of carriers accumulated in the IGBT region 100 when the current is turned on can be reduced.

[0090] Therefore, during the turn-off operation, the number of charge carriers flowing from the main layer 5 of the IGBT cell near the center 100C of the IGBT region 100 to the emitter electrode 10 is reduced, and the base current of the parasitic thyristor is also reduced, thus preventing latch-up failure near the center 100C of the IGBT region 100.

[0091] (Example 2)

[0092] Next, refer to Figure 2 The structure of the semiconductor device in Example 2 will be described.

[0093] Figure 2 This is an enlarged cross-sectional view of the main parts of the semiconductor device in Embodiment 2. Furthermore, regarding the semiconductor device in Embodiment 1... Figure 1 The same structures are labeled with the same reference numerals, and repeated descriptions are omitted.

[0094] like Figure 2 As shown, the semiconductor device in this embodiment and Figure 1 Similarly, in Embodiment 1 shown, a low lifetime region 300 that shortens the carrier lifetime is provided in the semiconductor substrate 1 of the IGBT cell near the center 100C of the IGBT region 100.

[0095] The semiconductor device in this embodiment also includes, for example Figure 2 As shown, the collector layer 2 is formed as a low-concentration collector layer 2a near the center 100C of the IGBT region 100 (i.e., the center of the IGBT region 100), and a high-concentration collector layer 2b is formed in the remaining portion of the IGBT region 100. Furthermore, the high-concentration collector layer 2b has the same impurity concentration as the collector layer 2 of Example 1, while the low-concentration collector layer 2a has a lower impurity concentration than the collector layer 2 of Example 1.

[0096] According to the semiconductor device of this embodiment, near the center 100C of the IGBT region 100, the collector layer becomes a low-concentration collector layer 2a, thereby reducing the amount of minority carriers injected when the forward current is turned on.

[0097] Therefore, by turning off, fewer minority carriers (e.g., holes) are discharged to the main layer 5 near the center 100C of the IGBT region 100, and the base current of the parasitic thyristor is suppressed, which can further improve the RBSOA.

[0098] (Example 3)

[0099] Next, refer to Figure 3 The structure of the semiconductor device in Example 3 will be described.

[0100] Figure 3 This is an enlarged cross-sectional view of the main part of the semiconductor device in Embodiment 3. Furthermore, regarding the semiconductor device in Embodiment 1... Figure 1 The same structures are labeled with the same reference numerals, and repeated descriptions are omitted.

[0101] like Figure 3 As shown, the semiconductor device in this embodiment and Figure 1Similarly, in the embodiment 1 shown, a low lifetime region 300 that shortens the carrier lifetime is provided in the semiconductor substrate 1 of the IGBT cell (i.e., the IGBT cell disposed at the center of the IGBT region 100) near the center 100C of the IGBT region 100.

[0102] like Figure 3 As shown, the semiconductor device in this embodiment is further configured such that the IGBT cell near the center 100C of the IGBT region 100 (i.e., the IGBT cell disposed in the center of the IGBT region 100) does not have an emitter layer 6.

[0103] In the IGBT cell near the center 100C of the IGBT region 100, as mentioned above, the risk of damage in the RBSOA is high, but since there is no emitter layer 6, no parasitic thyristor structure is formed, and therefore latch-up damage will not occur.

[0104] Furthermore, the IGBT cell located closer to the diode region 200 than the center 100C of the IGBT region 100 is... Figure 1 Similarly, in Embodiment 1 shown, an emitter layer 6 covered by the main body layer 5 is formed in connection with the insulating film 21.

[0105] According to the semiconductor device of this embodiment, the IGBT cells near the center 100C of the IGBT region 100 are configured without the emitter layer 6, thereby preventing the formation of parasitic thyristor structures and thus avoiding latch-up failure. This further improves RBSOA.

[0106] As a variation of Example 3, the structure of Example 3 without emitter layer 6 can also be combined with the structure of Example 2 with low-concentration collector layer 2a.

[0107] By combining it with the structure of Example 2, which has a low-concentration collector layer 2a, the RBSOA can be further improved.

[0108] In Example 3, with Figure 1 Similarly, in the semiconductor device of Embodiment 1 shown, a low lifetime region 300 is provided in the semiconductor substrate 1 of the IGBT cell near the center 100C of the IGBT region 100, and a structure without an emitter layer 6 in the IGBT cell is combined.

[0109] In contrast, as another variation of Embodiment 3, a structure can be adopted in which the low-lifetime region 300 is not provided and the emitter layer 6 is absent in the IGBT cell near the center 100C of the IGBT region 100. Moreover, this structure can also improve RBSOA.

[0110] Alternatively, the low-concentration collector layer 2a of Example 2 can be combined with the structure of Example 3 in which the low-lifetime region 300 is removed.

[0111] In Example 3, as Figure 3 As shown, the IGBT cells near the center 100C of the IGBT region 100 are configured to have no emitter layer 6.

[0112] In contrast, by reducing the number of IGBT cells in the IGBT cells near the center 100C of the IGBT region 100 compared to other parts of the IGBT region 100, an improvement in RBSOA can also be achieved. This situation will be described below as Example 4.

[0113] (Previous construction)

[0114] Here, before describing the semiconductor device of Embodiment 4, refer to Figures 6-7 This illustrates the comparison with existing semiconductor devices of the same construction.

[0115] Figure 6 This is an enlarged cross-sectional view of the main part of an existing semiconductor device with a reverse-conducting IGBT.

[0116] in addition, Figure 7 yes Figure 6 Horizontal cross-sectional view at XX′ (viewed from above) Figure 6 (Diagram of the horizontal plane at point XX′).

[0117] Figure 6 The existing structure shown is as follows: from Figure 1 The structure of Embodiment 1 shown has the low-lifetime region 300 removed.

[0118] like Figure 7 As shown, a certain number of emitter layers 6 of the first conductivity type are disposed in the IGBT region 100. That is, regardless of Figure 6 The IGBT cells near the center 100C of the IGBT region 100, and the IGBT cells near the boundary between the IGBT region 100 and the diode region 200, have the same structure and the same number of emitter layers 6.

[0119] In Figures 6-7 In the existing structure shown, due to the lack of formation Figure 1As shown in the low-lifetime region 300, in the IGBT cells near the center 100C of the IGBT region 100, the charge carriers accumulated in the semiconductor substrate 1 when the current is turned on are not easily released when the current is turned off. Furthermore, in the IGBT cells near the center 100C of the IGBT region 100, the base current of the parasitic thyristor structure built into the IGBT (emitter layer 6 / body layer 5 / semiconductor substrate 1 and buffer layer 4 / collector layer 2) becomes a cause of latch-up.

[0120] therefore, Figures 6-7 In the conventional configuration shown, the reverse bias safe operating area (RBSOA) is not improved in the IGBT cell near the center 100C of the IGBT region 100, and damage may be concentrated.

[0121] (Example 4)

[0122] Next, refer to Figures 4-5 The structure of the semiconductor device in Example 4 will be described.

[0123] Figure 4 This is an enlarged cross-sectional view of the main part of the semiconductor device in Example 4. Figure 4 The enlarged cross-sectional view is the same as that of Example 1. Figure 1 The enlarged sectional view has the same structure.

[0124] in addition, Figure 5 yes Figure 4 Horizontal cross-sectional view at XX′ (viewed from above) Figure 4 (Diagram of the horizontal plane at point XX′).

[0125] Furthermore, regarding Example 1 Figure 1 The same structures are labeled with the same reference numerals, and repeated descriptions are omitted.

[0126] like Figure 4 As shown, the semiconductor device in this embodiment and Figure 1 Similarly, in the embodiment 1 shown, a low lifetime region 300 that shortens the carrier lifetime is provided in the semiconductor substrate 1 of the IGBT cell (i.e., the IGBT cell disposed at the center of the IGBT region 100) near the center 100C of the IGBT region 100.

[0127] Furthermore, such as Figure 5 As shown, the semiconductor device in this embodiment is configured such that the number of IGBT cells near the center 100C of the IGBT region 100 (i.e., the IGBT cells disposed in the center of the IGBT region 100) is less than the number of emitter layers 6 in other parts of the IGBT region 100.

[0128] exist Figure 5In the IGBT cell near the center 100C of the IGBT region 100, by extending... Figure 5 The spacing of the emitter layers 6 in the vertical direction reduces the number of emitter layers 6 to 2 / 3 of the number of IGBT cells in other parts of the IGBT region 100.

[0129] Furthermore, the ratio of the emitter layer 6 in the IGBT cells near the center 100C of the IGBT region 100 to that in the IGBT cells in other parts of the IGBT region 100 is not limited to... Figure 5 The ratio shown as 2:3 can also be set to other ratios.

[0130] According to the semiconductor device of this embodiment, the IGBT cells near the center 100C of the IGBT region 100 are configured such that the emitter layer 6 has fewer IGBT cells than other parts of the IGBT region 100, thereby making it difficult to form a parasitic thyristor structure and suppressing latch-up failure.

[0131] Therefore, it is possible to... Figure 4 The low lifetime region 300 shown further improves RBSOA.

[0132] As a variation of Example 4, the structure of Example 4 with fewer emitter layers 6 can also be combined with the structure of Example 2 with a low concentration of collector layer 2a.

[0133] By combining it with the structure of Example 2, which has a low-concentration collector layer 2a, the RBSOA can be further improved.

[0134] Furthermore, the present invention is not limited to the embodiments and examples described above, and includes various modifications. For example, the embodiments and examples described above are given in detail for the purpose of readily understanding the present invention, and are not limited to having all the structures described.

[0135] Symbol Explanation

[0136] 1: Semiconductor substrate, 2: Collector layer, 2a: Low-concentration collector layer, 2b: High-concentration collector layer, 3: Cathode layer, 4: Buffer layer, 5: Body layer, 6: Emitter layer, 7: Barrier layer, 10: Emitter electrode, 11: Collector, 12: Gate electrode, 13: Emitter electrode in trench, 20: Trench, 21: Insulating film, 22: Interlayer insulating film, 100: IGBT region, 100C: Center of IGBT region, 200: Diode region, 300: Low lifetime region.

Claims

1. A semiconductor device comprising a reverse-biased IGBT having an IGBT and a diode formed on the same semiconductor substrate, characterized in that the semiconductor device comprises: The semiconductor substrate of the first conductivity type, a first electrode in contact with the surface of the semiconductor substrate, a second electrode in contact with the back side of the semiconductor substrate, a plurality of trenches formed on the surface side of the semiconductor substrate, an insulating film formed in the trenches, and a third electrode covered by the insulating film. The IGBT comprises: a first semiconductor layer of a second conductivity type, which is connected to the second electrode in the IGBT region where the IGBT is formed; a second semiconductor layer of a first conductivity type, which is connected to the second electrode in the diode region where the diode is formed; a third semiconductor layer of a first conductivity type, which is connected to the upper surfaces of the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer of a second conductivity type, which is connected to the first electrode and the insulating film in the trench; and a fifth semiconductor layer of a first conductivity type, which is connected to the first electrode and the insulating film in the trench in the IGBT region and is surrounded by the fourth semiconductor layer. The semiconductor substrate of the IGBT cell near the center of the IGBT region has a low lifetime region.

2. The semiconductor device according to claim 1, characterized in that, The impurity concentration of the first semiconductor layer near the center of the IGBT region is lower than the impurity concentration of the first semiconductor layer in the portion outside the center of the IGBT region.

3. The semiconductor device according to claim 1, characterized in that, The fifth semiconductor layer is formed in IGBT cells located outside the center of the IGBT region, while the fifth semiconductor layer is not formed in IGBT cells located near the center of the IGBT region.

4. The semiconductor device according to claim 3, characterized in that, The impurity concentration of the first semiconductor layer near the center of the IGBT region is lower than the impurity concentration of the first semiconductor layer in the portion outside the center of the IGBT region.

5. The semiconductor device according to claim 1, characterized in that, The number of IGBT cells near the center of the IGBT region is less than the number of IGBT cells outside the center of the IGBT region.

6. The semiconductor device according to claim 5, characterized in that, The impurity concentration of the first semiconductor layer near the center of the IGBT region is lower than the impurity concentration of the first semiconductor layer in the portion outside the center of the IGBT region.

7. A semiconductor device comprising a reverse-conducting IGBT having an IGBT and a diode formed on the same semiconductor substrate, characterized in that the semiconductor device comprises: The semiconductor substrate of the first conductivity type, a first electrode in contact with the surface of the semiconductor substrate, a second electrode in contact with the back side of the semiconductor substrate, a plurality of trenches formed on the surface side of the semiconductor substrate, an insulating film formed in the trenches, and a third electrode covered by the insulating film. The IGBT comprises: a first semiconductor layer of a second conductivity type, which is connected to the second electrode in the IGBT region where the IGBT is formed; a second semiconductor layer of a first conductivity type, which is connected to the second electrode in the diode region where the diode is formed; a third semiconductor layer of a first conductivity type, which is connected to the upper surfaces of the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer of a second conductivity type, which is connected to the first electrode and the insulating film in the trench; and a fifth semiconductor layer of a first conductivity type, which is connected to the first electrode and the insulating film in the trench in the IGBT region and is surrounded by the fourth semiconductor layer. The fifth semiconductor layer is formed in IGBT cells located outside the center of the IGBT region, while the fifth semiconductor layer is not formed in IGBT cells located near the center of the IGBT region.

8. The semiconductor device according to claim 7, characterized in that, The impurity concentration of the first semiconductor layer near the center of the IGBT region is lower than the impurity concentration of the first semiconductor layer in the portion outside the center of the IGBT region.

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