Semiconductor device

Abstract

The semiconductor device includes: a chip having a main surface; a gate electrode formed on the main surface; an interlayer film covering the gate electrode; an opening which is formed in the interlayer film so as to be separated from the gate electrode in a lateral direction along the main surface, and which exposes a part of the chip as a contact part; and a surface electrode formed on the interlayer film and mechanically and electrically connected to the contact portion within the opening, the contact portion including a mesa contact portion protruding from the main surface and having a mesa side portion and a mesa upper portion, the surface electrode covering the mesa side portion and the mesa upper portion.

Description

[0001] This application corresponds to Japanese Patent Application No. 2023-051501 filed with the Japan Patent Office on March 28, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device. Background Technology

[0003] Patent document 1 discloses a SiC semiconductor device, including: a p-type main region, which in n - Multiple n-type source regions are formed on the surface of the p-type SiC semiconductor layer, each constituting a unit cell; an n-type source region is formed inside the p-type main region; a gate electrode is positioned opposite the p-type main region across a gate insulating film; n + Type drain region and p + A type collector region is formed adjacent to the back side of the SiC semiconductor layer; and n - Type-drift region, located between the p-type main body region and the front n + Between the drain regions of the p type. + The collector region is formed as a region comprising at least two unit cells that covers the surface of the SiC semiconductor layer along the X-axis.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2015-207588 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] One embodiment of this disclosure provides a semiconductor device capable of reducing the contact resistance on the side of the gate electrode.

[0009] Solution for solving the problem

[0010] One embodiment of this disclosure provides a semiconductor device including: a chip having a main surface; a gate electrode formed on the main surface; an interlayer film covering the gate electrode; an opening formed separately from the gate electrode in the interlayer film in a transverse direction along the main surface, exposing a portion of the chip as a contact portion; and a surface electrode formed on the interlayer film, mechanically and electrically connected to the contact portion within the opening, the contact portion including a mesa contact portion protruding from the main surface and having a mesa side portion and a mesa upper portion, the surface electrode covering the mesa side portion and the mesa upper portion.

[0011] Invention Effects

[0012] According to one embodiment of the present disclosure, a semiconductor device capable of reducing the contact resistance on the side of the gate electrode can be provided. Attached Figure Description

[0013] Figure 1 This is a top view of a semiconductor device illustrating an implementation method.

[0014] Figure 2 It is along Figure 1 The cross-sectional view along line II-II shown.

[0015] Figure 3 This is a top view showing an example layout of the first main surface.

[0016] Figure 4 It is an enlarged top view showing the main part of the first main surface.

[0017] Figure 5 This is an enlarged top view showing another major part of the first main surface.

[0018] Figure 6 It is along Figure 5 The sectional view of line VI-VI shown.

[0019] Figure 7 It means Figure 6 Enlarged sectional view of the main part.

[0020] Figure 8 It is along Figure 5 The cross-sectional view of line VIII-VIII shown.

[0021] Figure 9 It means Figure 8 Enlarged sectional view of the main part.

[0022] Figure 10 It is a schematic three-dimensional diagram that details the structure of the contact part of the tabletop.

[0023] Figure 11 It is a schematic diagram representing a wafer.

[0024] Figure 12A It is a cross-sectional view showing the manufacturing process of a semiconductor device.

[0025] Figure 12B It means Figure 12A A cross-sectional view of the subsequent processes.

[0026] Figure 12C It means Figure 12B A cross-sectional view of the subsequent processes.

[0027] Figure 12D It means Figure 12C A cross-sectional view of the subsequent processes.

[0028] Figure 12E It means Figure 12D A cross-sectional view of the subsequent processes.

[0029] Figure 12F It means Figure 12E A cross-sectional view of the subsequent processes.

[0030] Figure 12G It means Figure 12F A cross-sectional view of the subsequent processes.

[0031] Figure 12H It means Figure 12G A cross-sectional view of the subsequent processes.

[0032] Figure 12I It means Figure 12H A cross-sectional view of the subsequent processes.

[0033] Figure 12J It means Figure 12I A cross-sectional view of the subsequent processes.

[0034] Figure 12K It means Figure 12J A cross-sectional view of the subsequent processes.

[0035] Figure 12L It means Figure 12K A cross-sectional view of the subsequent processes.

[0036] Figure 12M It means Figure 12L A cross-sectional view of the subsequent processes.

[0037] Figure 12N It means Figure 12M A cross-sectional view of the subsequent processes.

[0038] Figure 12O It means Figure 12N A cross-sectional view of the subsequent processes.

[0039] Figure 13 This is a cross-sectional view showing the first modified example (second contact part) of the tabletop contact area.

[0040] Figure 14 It includes Figure 13 A perspective view of the platform contact portion of the second contact portion.

[0041] Figure 15A It means and Figure 13 The diagram shows the process related to the formation of the second contact portion.

[0042] Figure 15B It means Figure 15AA cross-sectional view of the subsequent processes.

[0043] Figure 15C It means Figure 15B A cross-sectional view of the subsequent processes.

[0044] Figure 15D It means Figure 15C A cross-sectional view of the subsequent processes.

[0045] Figure 16 This is a cross-sectional view showing a second variation (third contact portion) of the tabletop contact portion.

[0046] Figure 17 It includes Figure 16 A three-dimensional view of the platform contact part of the third contact part.

[0047] Figure 18A It means and Figure 16 The diagram shows the process related to the formation of the third contact portion.

[0048] Figure 18B It means Figure 18A A cross-sectional view of the subsequent processes.

[0049] Figure 18C It means Figure 18B A cross-sectional view of the subsequent processes.

[0050] Figure 18D It means Figure 18C A cross-sectional view of the subsequent processes.

[0051] Figure 19 This is a cross-sectional view showing the fourth modified example of the tabletop contact area.

[0052] Figure 20 This is a cross-sectional view showing the fifth variation of the tabletop contact area.

[0053] Figure 21 This is a cross-sectional view showing the sixth modified example of the tabletop contact area. Detailed Implementation

[0054] The embodiments will now be described in detail with reference to the accompanying drawings. The drawings are schematic diagrams and not strictly illustrative; the positions, scales, ratios, and angles of opposing elements may not be consistent. Corresponding structures in the drawings are labeled with the same reference numerals, and repeated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the description preceding the omission or simplification will apply.

[0055] When the term "substantially" is used in this specification, it includes not only the numerical value (shape) that is equal to the numerical value (shape) of the comparison object, but also a numerical error (shape error) within ±10% of the numerical value (shape) of the comparison object. In the following description, terms such as "first," "second," and "third" are used, but these are notations assigned to the names of each structure to clarify the order of description, and are not intended to define the essence of the names of each structure.

[0056] In the following description, "p-type" or "n-type" is used to refer to the conductivity type of the semiconductor (impurity), but "p-type" can also be called the "first conductivity type" and "n-type" the "second conductivity type." Conversely, "n-type" can also be called the "first conductivity type" and "p-type" the "second conductivity type." "P-type" is the conductivity type originating from trivalent elements, and "n-type" is the conductivity type originating from pentavalent elements. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0057] Figure 1 This is a top view showing the semiconductor device 1 of the embodiment. Figure 2 It is along Figure 1 The cross-sectional view along line II-II shown. Figure 3 This is a top view showing an example layout of the first main surface 3. Figure 4 This is an enlarged top view showing the main part of the first main surface 3. Figure 5 This is an enlarged top view showing another major part of the first main surface 3.

[0058] Figure 6 It is along Figure 5 The sectional view of line VI-VI shown. Figure 7 It means Figure 6 Enlarged sectional view of the main part. Figure 8 It is along Figure 5 The cross-sectional view of line VIII-VIII shown. Figure 9 It means Figure 8 Enlarged sectional view of the main part.

[0059] Reference Figures 1-9 Semiconductor device 1 is a semiconductor switching device having an insulated-gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a vertical structure. Semiconductor device 1 is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 can also be called a "SiC chip" or a "semiconductor chip".

[0060] In this embodiment, chip 2 is composed of hexagonal SiC single crystals, forming a cuboid shape. Hexagonal SiC single crystals have various polymorphs, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. This embodiment shows an example where chip 2 is composed of 4H-SiC single crystals, but chip 2 can also be composed of other polymorphs.

[0061] Chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are quadrilaterals when viewed from the vertical direction Z (hereinafter referred to as "top view"). The vertical direction Z is also the thickness direction of chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 can also be squares or rectangles when viewed from the top.

[0062] The first main surface 3 and the second main surface 4 are preferably formed from the c-plane of a SiC single crystal. In this case, the first main surface 3 is preferably formed from the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed from the carbon surface ((000-1) surface) of the SiC single crystal.

[0063] The first side surface 5A and the second side surface 5B extend along the first main surface 3 in a first direction X and are opposite each other along the first main surface 3 in a second direction Y that intersects the first direction X. Specifically, the second direction Y is orthogonal to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and are opposite each other in the first direction X.

[0064] In the following description, one side of the first direction X refers to the third side 5C, and the other side of the first direction X refers to the fourth side 5D. Similarly, one side of the second direction Y refers to the first side 5A, and the other side of the second direction Y refers to the second side 5B. In this configuration, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X can be the a-axis direction of the SiC single crystal, and the second direction Y can be the m-axis direction of the SiC single crystal.

[0065] Chip 2 (first main surface 3 and second main surface 4) has a deviation angle that is tilted at a predetermined angle in a predetermined deviation direction relative to the c-plane of the SiC single crystal. That is, the amount of the deviation angle by which the c-axis ((0001) axis) of the SiC single crystal is tilted from the vertical axis toward the deviation direction. In addition, the amount of the deviation angle by which the c-plane of the SiC single crystal is tilted relative to the horizontal plane.

[0066] The deviation direction is preferably the a-axis direction (i.e., the second direction Y) of the SiC single crystal. The deviation angle can be greater than 0° and less than 10°. The deviation angle can have a value belonging to at least one of the following ranges: greater than 0° and less than 1°, greater than 1° and less than 2.5°, greater than 2.5° and less than 5°, greater than 5° and less than 7.5°, and greater than 7.5° and less than 10°.

[0067] The deviation angle is preferably 5° or less. Particularly preferred is a deviation angle of 2° or more but less than 4.5°. The deviation angle is typically set in the range of 4° ± 0.1°. This specification does not exclude a deviation angle of 0° (i.e., the first main surface 3 is facing the front relative to surface c).

[0068] Semiconductor device 1 includes an n-type first semiconductor region 6 formed within chip 2 in a region (surface layer) on the side of a first main surface 3. The first semiconductor region 6 may also be referred to as a "drift region," "drain drift region," or "drain region," etc. A drain potential, which is a high potential (first potential), is applied to the first semiconductor region 6. The first semiconductor region 6 is formed in a layered manner extending along the first main surface 3, exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this configuration, the first semiconductor region 6 is composed of an epitaxial layer (specifically, a SiC epitaxial layer).

[0069] The semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the side of the second main surface 4 within the chip 2. A drain potential is applied to the second semiconductor region 7. The second semiconductor region 7 may also be referred to as a "drain region" or the like. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6 and is electrically connected to the first semiconductor region 6 within the chip 2.

[0070] The second semiconductor region 7 is formed as a layer extending along the second main surface 4, exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this configuration, the second semiconductor region 7 is constituted by a semiconductor substrate (specifically a SiC substrate). That is, the chip 2 has a stacked structure including a semiconductor substrate and an epitaxial layer. The second semiconductor region 7 has a thickness greater than that of the first semiconductor region 6.

[0071] Semiconductor device 1 includes an active region 8 disposed on chip 2. The active region 8 is a region that includes a device structure (transistor structure Tr) and generates an output current (drain current). The active region 8 is disposed within chip 2 at intervals from the periphery (first to fourth sides 5A to 5D) of chip 2 when viewed from above. The active region 8 is configured to have a polygonal shape (in this case, a quadrilateral shape) with four sides parallel to the periphery of chip 2 when viewed from above. The planar area of ​​the active region 8 is preferably 50% or more and 90% or less of the planar area of ​​the first main surface 3.

[0072] Semiconductor device 1 includes an outer peripheral region 9 disposed in chip 2 outside an active region 8. Viewed from above, the outer peripheral region 9 is disposed in the area between the periphery of chip 2 and the active region 8. Viewed from above, the outer peripheral region 9 extends in a strip along the active region 8 and is configured as a polygonal ring (in this case, a quadrilateral ring) surrounding the active region 8.

[0073] The semiconductor device 1 includes a plurality of p-type main regions 20 formed in the surface portion of the first main surface 3 in the active region 8. The plurality of main regions 20 are assigned a source potential that is a low potential (second potential) different from a high potential (first potential). The plurality of main regions 20 are arranged at intervals in a first direction X, and are each formed as a strip extending in a second direction Y. That is, the plurality of main regions 20 are arranged as stripes extending along the second direction Y.

[0074] Multiple main regions 20 are formed spaced apart from the bottom of the first semiconductor region 6 toward the first main surface 3, and are opposite to the second semiconductor region 7 across a portion of the first semiconductor region 6. Preferably, the multiple main regions 20 are formed spaced apart from the middle portion of the first semiconductor region 6 toward the first main surface 3. The multiple main regions 20 are exposed from the first main surface 3.

[0075] The semiconductor device 1 includes a p-type outer body region 21 formed in the outer peripheral region 9 on the surface layer of the first main surface 3. The outer body region 21 preferably has a p-type impurity concentration approximately equal to that of the main body region 20. However, the p-type impurity concentration of the outer body region 21 can be either less than or higher than that of the main body region 20.

[0076] The outer main body region 21 is formed at intervals from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8, and extends in a strip along the active region 8. The outer main body region 21 has a portion that extends in a strip along the first direction X and a portion that extends in a strip along the second direction Y when viewed from above, thus dividing the active region 8 from multiple directions.

[0077] In this configuration, the outer main body region 21 surrounds the active region 8 when viewed from above and is divided into a polygonal ring with four sides parallel to the periphery of the first main surface 3 (in this configuration, it is a quadrilateral ring). That is, the outer main body region 21 forms the boundary between the active region 8 and the outer peripheral region 9. The outer main body region 21 may also have an edge portion that connects the portion extending along the first direction X and the portion extending along the second direction Y when viewed from above in an arc shape (preferably a quarter arc shape) (see reference). Figure 4 ).

[0078] The outer body region 21 has an inner edge portion on the side of the active region 8 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer body region 21 is connected to the plurality of body regions 20 in the portion extending along the first direction X. Thus, the outer body region 21 is fixed to the same potential as the plurality of body regions 20.

[0079] The outer main body region 21 preferably has a width greater than that of the main body region 20. The width of the main body region 20 is the width in a direction orthogonal to the extension direction (i.e., the first direction X). The width of the outer main body region 21 is the width in a direction orthogonal to the extension direction. Of course, the width of the outer main body region 21 can be approximately equal to the width of the main body region 20, or it can be less than the thickness of the main body region 20.

[0080] The ratio of the width of the outer main body region 21 to the width of the main body region 20 can be 10 or more and 50 or less. Preferably, the width ratio is 20 or more and 40 or less.

[0081] The outer body region 21 is formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and is opposite to the second semiconductor region 7 across a portion of the first semiconductor region 6. Preferably, the outer body region 21 is formed at intervals from the middle portion of the first semiconductor region 6 toward the first main surface 3. The outer body region 21 is exposed from the first main surface 3.

[0082] The outer main body region 21 preferably has a thickness (depth) that is approximately equal to that of the main body region 20. Of course, the thickness of the outer main body region 21 can be less than or greater than the thickness of the main body region 20.

[0083] The semiconductor device 1 includes a plurality of n-type surface drift regions 22 formed on the surface portion of the first main surface 3. In this configuration, each of the plurality of surface drift regions 22 is constituted by a portion of the first semiconductor region 6. Of course, the plurality of surface drift regions 22 may have an n-type impurity concentration that is higher than that of the first semiconductor region 6, or they may have an n-type impurity concentration that is lower than that of the first semiconductor region 6.

[0084] Multiple surface drift regions 22 are each divided into regions between multiple adjacent main body regions 20 in the first direction X. Specifically, the surface portion of the first main surface 3 is divided by multiple main body regions 20 and outer main body regions 21. The multiple surface drift regions 22 are arranged at intervals in the first direction X, forming stripes extending in the second direction Y. That is, the multiple surface drift regions 22 are formed as stripes extending in the second direction Y.

[0085] Semiconductor device 1 includes multiple n-type source regions 23 and 24 respectively formed on the surface portion of multiple main regions 20. The multiple source regions 23 and 24 have an n-type impurity concentration higher than that of the first semiconductor region 6. Source potentials are assigned to the multiple source regions 23 and 24.

[0086] Multiple source regions 23 and 24 on the surface of each main body region 20 include a first source region 23 located on one side of the first direction X and a second source region 24 located on the other side of the first direction X. In this configuration, in the first direction X, a first source region 23 is formed at one end of the main body region 20, and a second source region 24 is formed at the other end of the main body region 20.

[0087] The first source region 23 is formed spaced apart from one end of the main body region 20 to the other end, extending in a strip shape along the extension direction of the main body region 20. The first source region 23 is formed spaced apart from the outer main body region 21 in the second direction Y. That is, the first source region 23 is not formed in the outer main body region 21. The first source region 23 is formed spaced apart from the bottom of the main body region 20 towards the first main surface 3, and is opposed to the first semiconductor region 6 across a portion of the main body region 20.

[0088] The second source region 24 is formed spaced apart from the first source region 23 toward the other end of the main body region 20. The second source region 24 is also formed spaced apart from the other end of the main body region 20 toward one end, extending in a strip shape along the extension direction of the main body region 20. The second source region 24 is formed spaced apart from the outer main body region 21 in the second direction Y. That is, the second source region 24 is not formed in the outer main body region 21. The second source region 24 is formed spaced apart from the bottom of the main body region 20 toward the first main surface 3, and is opposed to the first semiconductor region 6 across a portion of the main body region 20.

[0089] When multiple first source regions 23 are formed in a main body region 20, the multiple first source regions 23 may also be formed at intervals along the extension direction of the main body region 20. In this case, each first source region 23 may also be formed as a strip extending in the second direction Y. Similarly, when multiple second source regions 24 are formed in a main body region 20, the multiple second source regions 24 may also be formed at intervals along the extension direction of the main body region 20. In this case, each second source region 24 may also be formed as a strip extending in the second direction Y.

[0090] Semiconductor device 1 includes multiple p-type contact regions 25 formed in the surface portion of multiple body regions 20 within an active region 8. The contact regions 25 may also be referred to as "back gate regions". A source potential is assigned to the multiple contact regions 25. The contact regions 25 have a higher p-type impurity concentration compared to the p-type impurity concentration of the body regions 20.

[0091] In this configuration, a contact region 25 is located on the surface of the corresponding main body region 20, between the first source region 23 and the second source region 24. The contact region 25 extends in a strip shape along the extension direction of the main body region 20 (source regions 23, 24). The contact region 25 is formed at a distance from the outer main body region 21 in the second direction Y. That is, the contact region 25 is not formed on the outer main body region 21. The contact region 25 is formed at a distance from the bottom of the main body region 20 toward the first main surface 3, and is opposite to the first semiconductor region 6 across a portion of the main body region 20.

[0092] When multiple contact areas 25 are formed in a single main body region 20, the multiple contact areas 25 may also be formed at intervals along the extending direction of the main body region 20. In this case, each contact area 25 may also be formed as a strip extending along the second direction Y.

[0093] Semiconductor device 1 includes a plurality of p-type channel regions 26, 27 formed on the surface portion of a first main surface 3. The plurality of channel regions 26, 27 are respectively divided on the surface portion of a plurality of main body regions 20 into regions between the ends of the plurality of main body regions 20 (a plurality of surface drift regions 22) and the peripheries of a plurality of source regions 23, 24. In this configuration, the plurality of channel regions 26, 27 are arranged at intervals in a first direction X, and are respectively formed as stripes extending in a second direction Y. That is, the plurality of channel regions 26, 27 are arranged as stripes extending along the second direction Y.

[0094] The multiple channel regions 26 and 27 include multiple first channel regions 26 and multiple second channel regions 27. The multiple first channel regions 26 are respectively divided into regions between one end of multiple main regions 20 (surface drift regions 22) and multiple first source regions 23, forming a current path extending horizontally. The multiple second channel regions 27 are respectively divided into regions between the other end of multiple main regions 20 (surface drift regions 22) and multiple second source regions 24, forming a current path extending horizontally.

[0095] The semiconductor device 1 includes a plurality of planar electrode-type gate structures 30 disposed on a first main surface 3 in an active region 8. The plurality of gate structures 30 are arranged at intervals in a first direction X, and are respectively formed as stripes extending in a second direction Y. That is, the plurality of gate structures 30 are arranged in a stripe-like pattern extending along the second direction Y. The extension direction of the plurality of gate structures 30 is consistent with the offset direction of the SiC single crystal.

[0096] Each gate structure 30 is disposed over at least one channel region 26, 27. In this configuration, each gate structure 30 is configured to traverse a surface drift region 22 and span two adjacent main regions 20, covering multiple channel regions 26, 27. Specifically, each gate structure 30 is configured to span a first source region 23 on one side of a main region 20 and a second source region 24 on the other side of a main region 20, covering the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.

[0097] The structure of a gate structure 30 is described below. The gate structure 30 has a stacked structure including an insulating film 31 and a gate electrode 32. The gate structure 30 does not have insulating sidewall structures (spacers) on the side of the gate electrode 32. The insulating film 31 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 31 has a single-layer structure made of a silicon oxide film. The insulating film 31 is particularly preferably made of a silicon oxide film composed of the oxide of the chip 2.

[0098] An insulating film 31 covers the first main surface 3 in a film-like manner and is disposed on at least one channel region 26, 27. In this manner, the insulating film 31 is disposed in a way that traverses a surface drift region 22 and spans two adjacent main body regions 20, covering multiple channel regions 26, 27.

[0099] Specifically, the insulating film 31 is configured to span a first source region 23 on one side of the main body region 20 and a second source region 24 on the other side of the main body region 20, covering the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.

[0100] The insulating film 31 partially covers the first source region 23 at intervals from the contact region 25, such that a portion of the first source region 23 and the contact region 25 are exposed from the first main surface 3. The insulating film 31 partially covers the second source region 24 at intervals from the contact region 25, such that a portion of the second source region 24 and the contact region 25 are exposed from the first main surface 3.

[0101] The thickness of the insulating film 31 can also be 10 nm or more and 150 nm or less. The thickness of the insulating film 31 can be within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less. Preferably, the thickness of the insulating film 31 is 25 nm or more and 75 nm or less.

[0102] A gate electrode 32 is disposed on an insulating film 31 and faces at least one channel region 26, 27 across the insulating film 31. A gate potential, serving as a control potential, is applied to the gate electrode 32. The gate electrode 32 controls the inversion and non-inversion of at least one channel region 26, 27 in response to the gate potential.

[0103] The gate electrode 32 comprises a conductive semiconductor polysilicon. The gate electrode 32 may also comprise either or both of p-type and n-type conductive polysilicon. The conductivity type of the gate electrode 32 is adjusted according to the gate threshold voltage to be achieved. The gate electrode 32 may also be referred to as a "polysilicon gate," "polycrystalline gate," etc.

[0104] The gate electrode 32 is formed as a strip extending in the second direction Y. That is, the extension direction of the gate electrode 32 is consistent with the deviation direction of the SiC single crystal. In this manner, the gate electrode 32 is formed in the first direction X at intervals from both ends of the insulating film 31 inward, so that both ends of the insulating film 31 are exposed. The gate electrode 32 is disposed on the insulating film 31 in such a way that it traverses a surface drift region 22 and spans two adjacent main regions 20, and is opposed to a plurality of channel regions 26, 27 through the insulating film 31.

[0105] Specifically, the gate electrode 32 is configured to span the first source region 23 on one side of the main body region 20 and the second source region 24 on the other side of the main body region 20, and is positioned opposite the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26 and the second channel region 27 through the insulating film 31.

[0106] The gate electrode 32 has an electrode surface 33, a first sidewall 34 on one side in the first direction X, and a second sidewall 35 on the other side in the first direction X. The electrode surface 33 extends along the insulating film 31 (first main surface 3). The electrode surface 33 may also extend substantially parallel to the insulating film 31 (first main surface 3).

[0107] A first sidewall 34 is formed spaced apart from one end of the insulating film 31 toward the other end in the first direction X, and extends in the vertical direction Z. A second sidewall 35 is formed spaced apart from the other end of the insulating film 31 toward one end in the first direction X, and extends in the vertical direction Z.

[0108] The first sidewall 34 and the second sidewall 35 may also extend perpendicularly to the insulating film 31. That is, the gate electrode 32 may also be formed into a quadrilateral shape (a flat rectangular shape) in cross-section. The first sidewall 34 and the second sidewall 35 may also be inclined toward the electrode surface 33. In other words, the gate electrode 32 may also be formed into a conical shape (preferably an isosceles trapezoidal shape) in cross-section.

[0109] The width of the gate structure 30 can be 1 μm or more and 10 μm or less. The width of the gate structure 30 is the width in the direction orthogonal to the extension direction (i.e., the first direction X). Preferably, the width of the gate structure 30 is 1 μm or more and 5 μm or less.

[0110] The thickness of the gate structure 30 can be 0.1 μm or more and 2.0 μm or less. Preferably, the thickness of the gate structure 30 is 0.2 μm or more and 1.0 μm or less.

[0111] Reference Figure 4 , Figure 5 as well as Figure 8 The semiconductor device 1 includes a p-type terminal region 45 formed on a first main surface 3 in an outer peripheral region 9. The terminal region 45 may also be referred to as a "well region," "terminal well region," etc., and may have a p-type impurity concentration approximately equal to that of the outer body region 21. The p-type impurity concentration of the terminal region 45 may be higher or lower than that of the outer body region 21.

[0112] Terminal region 45 is formed inwardly from the periphery of the first main surface 3 in the area between the periphery of the first main surface 3 and the outer main body region 21. Terminal region 45 extends in a strip-like shape along the outer main body region 21 when viewed from above. Terminal region 45 has a portion extending in a strip-like shape along a first direction X and a portion extending in a strip-like shape along a second direction Y when viewed from above, thus dividing the active region 8 in multiple directions.

[0113] In this configuration, the terminal region 45, when viewed from above, surrounds the outer main body region 21 and is divided into a polygonal ring with four sides parallel to the periphery of the first main surface 3 (in this configuration, a quadrilateral ring). The terminal region 45 may also have an edge portion that, when viewed from above, connects the portion extending along the first direction X and the portion extending along the second direction Y in an arc shape (preferably a quarter arc shape) (see reference). Figure 4 ).

[0114] The terminal region 45 is formed spaced apart from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6. Preferably, the terminal region 45 is formed spaced apart from the middle portion of the first semiconductor region 6 toward the first main surface 3. The terminal region 45 may also have a thickness (depth) approximately equal to the thickness (depth) of the outer body region 21. The thickness of the terminal region 45 may be greater than or less than the thickness of the outer body region 21.

[0115] The terminal region 45 has an inner edge on the side of the active region 8 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the terminal region 45 is connected to the outer edge of the outer main body region 21. Thus, the terminal region 45 is fixed to the same potential as the outer main body region 21 and is electrically connected to the plurality of main body regions 20 via the outer main body region 21. In this manner, the inner edge of the terminal region 45 is connected to the outer edge of the outer main body region 21 around its entire circumference.

[0116] The terminal region 45 (inner edge) has an overlapping region 46 that overlaps with the outer edge of the outer body region 21. The overlapping region 46 is a high-concentration region including both the outer edge of the outer body region 21 and the inner edge of the terminal region 45. That is, the overlapping region 46 includes both the p-type impurities of the outer body region 21 and the p-type impurities of the terminal region 45, and has a higher p-type impurity concentration than both the p-type impurity concentrations of the outer body region 21 and the terminal region 45.

[0117] The overlapping region 46 extends in a strip shape along the outer main body region 21 when viewed from above. The overlapping region 46, when viewed from above, has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y, dividing the active region 8 from multiple directions. In this configuration, the overlapping region 46 is divided into a polygonal ring shape (in this configuration, a quadrilateral ring shape) with four sides parallel to the periphery of the first main surface 3. The width of the overlapping region 46 is preferably greater than the width of the main body region 20. Of course, the width of the overlapping region 46 can also be less than the width of the main body region 20.

[0118] Semiconductor device 1 may also have a well region 46 with a relatively high concentration of p-type impurities instead of the overlapping region 46. In this case, the well region 46 has a higher p-type impurity concentration than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the terminal region 45. The well region 46 may also be formed in either or both of the surface portion of the outer body region 21 and the surface portion of the terminal region 45.

[0119] Semiconductor device 1 includes at least one (preferably two or more and less than 20) p-type field regions 47 formed in the outer peripheral region 9 on the surface portion of the first main surface 3. The number of field regions 47 is typically three or more and less than eight. In this configuration, semiconductor device 1 includes three field regions 47. The field regions 47 are formed in an electrically floating state to mitigate the electric field within the chip 2 at the periphery of the first main surface 3. The number, spacing, width, depth, p-type impurity concentration, etc., of the field regions 47 are arbitrary and can be varied depending on the electric field to be mitigated.

[0120] Field region 47 may also have a p-type impurity concentration that is approximately equal to that of the main region 20 (terminal region 45). The p-type impurity concentration of field region 47 may be higher or lower than that of the main region 20 (terminal region 45).

[0121] Multiple field regions 47 are spaced apart from the periphery of the first main surface 3 and formed in the region between the periphery of the first main surface 3 and the active region 8. Specifically, the multiple field regions 47 are formed in the region between the periphery of the first main surface 3 and the outer main body region 21. More specifically, the multiple field regions 47 are arranged in a spaced-apart manner from the terminal region 45 toward the periphery of the first main surface 3 in the region between the periphery of the first main surface 3 and the terminal region 45.

[0122] Multiple field regions 47 are formed in a strip shape extending along the active region 8 (terminal region 45) when viewed from above. Each of the multiple field regions 47 has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y. In this configuration, the multiple field regions 47 are formed in a polygonal ring shape (in this configuration, a quadrilateral ring shape) surrounding the active region 8 (terminal region 45) when viewed from above. The multiple field regions 47 may also have an edge portion (see reference) connecting the portions extending in the first direction X and the portions extending in the second direction Y in an arc shape (preferably a quarter arc shape). Figure 4 ).

[0123] Multiple field regions 47 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and are opposite to the second semiconductor region 7 across a portion of the first semiconductor region 6. Preferably, the multiple field regions 47 are formed at intervals from the middle portion of the first semiconductor region 6 toward the first main surface 3.

[0124] Reference Figure 8The semiconductor device 1 includes a peripheral insulating film 51 covering the first main surface 3 in the peripheral region 9. The peripheral insulating film 51 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this configuration, the peripheral insulating film 51 has a single-layer structure composed of a silicon oxide film. Particularly preferably, the peripheral insulating film 51 comprises a silicon oxide film composed of an oxide of the chip 2. The peripheral insulating film 51 is preferably composed of an insulating material of the same type as the insulating material of the insulating film 31. The peripheral insulating film 51 preferably has a thickness substantially equal to that of the insulating film 31.

[0125] The peripheral insulating film 51 covers the first main surface 3 in a film-like manner in the peripheral region 9. The peripheral insulating film 51 covers the outer main body region 21, the terminal region 45, and the multiple field regions 47. The peripheral insulating film 51 is connected to the multiple insulating films 31 on the active region 8 side. Specifically, the peripheral insulating film 51 is integrally formed with the multiple insulating films 31, forming a single insulating film with the multiple insulating films 31.

[0126] Reference Figure 4 , Figure 5 as well as Figure 8 The semiconductor device 1 includes a gate wiring 52 disposed on a first main surface 3 in an outer peripheral region 9. The semiconductor device 1 does not have insulating sidewall structures (spacers) on the sides of the gate wiring 52. The gate wiring 52 is selectively wound on the first main surface 3 and has portions extending in directions different from those of a plurality of gate electrodes 32. The gate wiring 52 is connected to the plurality of gate electrodes 32, imparting gate signals to the plurality of gate electrodes 32. The gate wiring 52 may also be referred to as a "polysilicon gate wiring," "polycrystalline gate wiring," "second gate electrode," etc.

[0127] Gate wiring 52 comprises conductive semiconductor polysilicon. Gate wiring 52 may also comprise either or both of p-type and n-type conductive polysilicon. Gate wiring 52 preferably has the same conductivity type as gate electrode 32. The conductivity type of gate wiring 52 is adjusted according to the conductivity type of gate electrode 32.

[0128] Gate wiring 52 is disposed on the outer peripheral insulating film 51 in the outer peripheral region 9. Specifically, gate wiring 52 is disposed on a portion of the outer peripheral insulating film 51 that covers the outer main body region 21, and is opposed to the outer main body region 21 through the outer peripheral insulating film 51. Gate wiring 52 is formed at intervals from the periphery of the first main surface 3 toward the active region 8, and extends in a strip shape along the active region 8. When viewed from above, gate wiring 52 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y, dividing the active region 8 from multiple directions.

[0129] In this configuration, the gate wiring 52, when viewed from above, surrounds the active region 8 and is divided into a polygonal ring with four sides parallel to the periphery of the first main surface 3 (in this configuration, a quadrilateral ring). The gate wiring 52 can also be terminal or ring-shaped. In this configuration, the gate wiring 52 extends in a strip shape (in this configuration, a ring) along the outer body region 21 when viewed from above, and is opposed to the outer body region 21 across the entire region in the stacking direction by the outer peripheral insulating film 51. The gate wiring 52 may also have an edge portion (see reference) where the portion extending along the first direction X and the portion extending along the second direction Y when viewed from above are connected in an arc shape (preferably a quarter arc shape). Figure 4 ).

[0130] The gate wiring 52 is formed to be narrower than the outer body region 21 when viewed from above, and is disposed on the outer body region 21 at intervals from the inner edge and the outer edge of the outer body region 21. That is, in this manner, a plurality of gate electrodes 32 are led out onto the outer body region 21, and the gate wiring 52 is connected to the plurality of gate electrodes 32 on the outer body region 21.

[0131] The width of the gate wiring 52 is preferably greater than the width of the gate electrode 32. The width of the gate wiring 52 is the width in a direction orthogonal to the extension direction. Of course, the width of the gate wiring 52 can also be less than the width of the gate electrode 32. The width of the gate wiring 52 can also be greater than the width of the outer body region 21. The thickness of the gate wiring 52 is preferably approximately equal to the thickness of the gate electrode 32.

[0132] The gate wiring 52 has a wiring surface 53, a first wiring sidewall 54 on the inner edge side, and a second wiring sidewall 55 on the outer edge side. The wiring surface 53 extends along the outer peripheral insulating film 51 (first main surface 3). The wiring surface 53 may also extend substantially parallel to the outer peripheral insulating film 51 (first main surface 3). The first wiring sidewall 54 extends vertically in the Z direction above the outer peripheral insulating film 51, and the second wiring sidewall 55 extends vertically in the Z direction above the outer peripheral insulating film 51.

[0133] The first wiring sidewall 54 is connected to a plurality of gate electrodes 32 (first sidewall 34 and second sidewall 35) at a portion extending along the first direction X. That is, the gate wiring 52 has a plurality of portions connected in a T-shape relative to the plurality of gate electrodes 32. Thus, the gate wiring 52 is fixed to the same potential as the plurality of gate electrodes 32.

[0134] The first wiring sidewall 54 and the second wiring sidewall 55 may also extend perpendicularly to the outer peripheral insulating film 51. That is, the gate wiring 52 may also be formed into a quadrilateral shape (a flat rectangular shape) in cross-section. The first wiring sidewall 54 and the second wiring sidewall 55 may also be inclined toward the wiring surface 53. In other words, the gate wiring 52 may also be formed into a conical shape (preferably an isosceles trapezoidal shape) in cross-section.

[0135] Semiconductor device 1 includes an insulating interlayer film 70 covering a first main surface 3. The interlayer film 70 may also be referred to as an "interlayer insulating film," "intermediate insulating film," etc. The interlayer film 70 has an insulating surface 71 extending along the first main surface 3. The interlayer film 70 covers both the active region 8 and the peripheral region 9 on the first main surface 3.

[0136] Interlayer film 70 covers multiple gate structures 30 in active region 8. For each gate structure 30, interlayer film 70 directly covers both insulating film 31 and gate electrode 32. That is, interlayer film 70 has portions that directly cover electrode surface 33, first sidewall 34 and second sidewall 35 of gate electrode 32.

[0137] Interlayer film 70 sandwiches peripheral insulating film 51 within peripheral region 9, thus covering outer main body region 21, terminal region 45, and multiple field regions 47. Interlayer film 70 directly covers both peripheral insulating film 51 and gate wiring 52. That is, interlayer film 70 has portions that directly cover wiring surface 53, first wiring sidewall 54, and second wiring sidewall 55 of gate wiring 52. In this configuration, interlayer film 70 is connected to the first to fourth side surfaces 5A to 5D. Interlayer film 70 may also be formed with gaps between the first to fourth side surfaces 5A to 5D, exposing the periphery of the first main surface 3 (first semiconductor region 6).

[0138] In this configuration, the interlayer film 70 has a laminated structure comprising a first oxide film 72 (first insulating film) and a second oxide film 73 (second insulating film) sequentially stacked from the first main surface 3. The interlayer film 70 has an insulating surface 71 formed by the second oxide film 73. The first oxide film 72 has a monolayer structure composed of a silicon oxide film without added impurities. The first oxide film 72 may also be referred to as an NSG film (Nondoped Silicate Glass film).

[0139] The first oxide film 72 covers both the active region 8 and the peripheral region 9. The first oxide film 72 covers multiple gate structures 30 in the active region 8. The first oxide film 72 covers both sides of the insulating film 31 and the gate electrode 32 with respect to each gate structure 30 in a film-like manner.

[0140] The first oxide film 72 has a first covering portion 74, a second covering portion 75, and a third covering portion 76. The first covering portion 74 extends horizontally along the insulating film 31 (first main surface 3) in a film-like manner and has a portion that contacts the first sidewall 34 (second sidewall 35) of the gate electrode 32. In this configuration, the first covering portion 74 (first oxide film 72) has a thickness less than that of the gate electrode 32 and covers the insulating film 31 at intervals from the height position of the electrode surface 33 of the gate electrode 32 toward the insulating film 31.

[0141] The second cover portion 75 extends from the first cover portion 74 toward the electrode surface 33 in the stacking direction, and directly covers the first sidewall 34 (second sidewall 35) in a film-like manner.

[0142] The third cover portion 76 extends from the second cover portion 75 toward the electrode surface 33 and extends horizontally along the electrode surface 33 in a film-like manner. The third cover portion 76 directly covers the entire area of ​​the electrode surface 33 between the first sidewall 34 and the second sidewall 35. Preferably, the portion of the third cover portion 76 covering the corner of the gate electrode 32 is formed together with the second cover portion 75 into an arc-shaped rounded corner. The rounded corner may also have a center of curvature on the gate electrode 32 side.

[0143] The first oxide film 72 sandwiches the outer peripheral insulating film 51 in the outer peripheral region 9 and covers the outer body region 21, the terminal region 45, and multiple field regions 47. The first oxide film 72 covers the gate wiring 52 in the outer peripheral region 9.

[0144] The first oxide film 72 has a first wiring cover 77, a second wiring cover 78, and a third wiring cover 79. The first wiring cover 77 extends horizontally in a film-like manner along the outer peripheral insulating film 51 (first main surface 3) and has a portion that connects to the first wiring sidewall 54 (second wiring sidewall 55) of the gate wiring 52. In this configuration, the first wiring cover 77 (first oxide film 72) has a thickness less than that of the gate wiring 52 and covers the outer peripheral insulating film 51 at intervals from the height of the wiring surface 53 of the gate wiring 52 toward the outer peripheral insulating film 51.

[0145] The second wiring cover 78 extends from the first wiring cover 77 toward the wiring surface 53 in the stacking direction and directly covers the first sidewall 34 (second sidewall 35) in a membrane-like manner.

[0146] The third wiring cover 79 extends from the second wiring cover 78 toward the wiring surface 53 and extends horizontally along the wiring surface 53 in a film-like manner. The third wiring cover 79 directly covers the entire area of ​​the wiring surface 53 between the first wiring sidewall 54 and the second wiring sidewall 55. Preferably, the portion of the third wiring cover 79 covering the corner of the gate wiring 52 is formed together with the second wiring cover 78 into an arc-shaped rounded corner. The rounded corner may also have a center of curvature on the gate wiring 52 side.

[0147] The second oxide film 73 can have a single-layer structure composed of a phosphorus-containing silicon oxide film, or a multilayer structure including a phosphorus-containing silicon oxide film. The phosphorus-containing silicon oxide film may contain boron. The phosphorus-containing silicon oxide film can also be called a PSG film (Phosphorus Silicon Glass film). A silicon oxide film containing both phosphorus and boron can also be called a BPSG film (Boron Phosphorus Silicon Glass film).

[0148] The second oxide film 73 may also have a monolayer structure consisting of a PSG film or a BPSG film stacked on the first oxide film 72. Alternatively, the second oxide film 73 may have a laminated structure comprising a PSG film stacked on the first oxide film 72 and a BPSG film stacked on top of the PSG film. In this embodiment, as an example, the second oxide film 73 has a monolayer structure consisting of a PSG film.

[0149] The second oxide film 73 covers the first oxide film 72 in a film-like manner, and together with the first oxide film 72, covers the active region 8 and the outer peripheral region 9. The second oxide film 73 sandwiches the first oxide film 72 in the active region 8 and together covers multiple gate structures 30. Specifically, the second oxide film 73 covers both the insulating film 31 and the gate electrode 32 in a film-like manner, with the first oxide film 72 in a film-like manner.

[0150] The second oxide film 73 includes a first upper cover portion 80 and a second upper cover portion 81. The first upper cover portion 80 covers the first cover portion 74 and the second cover portion 75 of the first oxide film 72. The portion of the first upper cover portion 80 above the first cover portion 74 covers an insulating film 31 across the first cover portion 74.

[0151] The first upper cover portion 80 extends in a film-like manner from the first cover portion 74 along the second cover portion 75 in the stacking direction, covering the first sidewall 34 (second sidewall 35) of the gate structure 30 through the second cover portion 75.

[0152] The second upper cover portion 81 covers the third cover portion 76 of the first oxide film 72. The second upper cover portion 81 extends horizontally along the third cover portion 76 in a film-like manner from the first upper cover portion 80, sandwiching the electrode surface 33 of the gate structure 30 covered by the third cover portion 76. The second upper cover portion 81 sandwiches the entire area of ​​the electrode surface 33 covered by the third cover portion 76 between the first sidewall 34 and the second sidewall 35. Preferably, the portion of the second upper cover portion 81 covering the corner of the gate wiring 52 is formed into an arc-shaped rounded corner together with the first upper cover portion 80. The rounded corner may also have a center of curvature on the gate wiring 52 side.

[0153] The second oxide film 73 covers the outer body region 21, the terminal region 45, and multiple field regions 47 in the outer peripheral region 9, separated by the outer peripheral insulating film 51 and the first oxide film 72. The second oxide film 73 covers the gate wiring 52 in the outer peripheral region 9, separated by the first oxide film 72.

[0154] The second oxide film 73 includes a first upper wiring cover portion 82 and a second upper wiring cover portion 83. The first upper wiring cover portion 82 covers the first wiring cover portion 77 and the second wiring cover portion 78 of the first oxide film 72. The portion of the first upper wiring cover portion 82 above the first wiring cover portion 77 covers the outer peripheral insulating film 51 across the first wiring cover portion 77.

[0155] The first upper wiring cover 82 extends in a membrane-like manner from the first wiring cover 77 along the second wiring cover 78 in the stacking direction, covering the first wiring sidewall 54 (second wiring sidewall 55) through the second wiring cover 78.

[0156] The second upper wiring cover 83 covers the third wiring cover 79 of the first oxide film 72. The second upper wiring cover 83 extends horizontally in a film-like manner from the first upper wiring cover 82 along the third wiring cover 79, covering the wiring surface 53 through the third wiring cover 79. The second upper wiring cover 83 sandwiches the third wiring cover 79 between the first wiring sidewall 54 and the second wiring sidewall 55, thus covering the entire area of ​​the wiring surface 53. Preferably, the portion of the second upper wiring cover 83 covering the corner of the gate wiring 52 is formed into an arc-shaped corner together with the first upper wiring cover 82. The arc-shaped corner may also have a center of curvature on the gate wiring 52 side.

[0157] The semiconductor device 1 includes a plurality of source openings 90 formed in an interlayer film 70 in an active region 8. The plurality of source openings 90 are formed at intervals to the sides of the plurality of gate electrodes 32, exposing a first main surface 3 (chip 2). Specifically, the plurality of source openings 90 are formed in the region between the plurality of gate electrodes 32, penetrating the insulating film 31 and the interlayer film 70.

[0158] Multiple source openings 90 penetrate both the first oxide film 72 and the second oxide film 73, and have walls defined by the first oxide film 72 and the second oxide film 73. The multiple source openings 90 have opening ends defined by the rounded corners of the interlayer film 70. The multiple source openings 90 expose corresponding multiple source regions 23, 24 and contact region 25.

[0159] In this configuration, a plurality of source openings 90 are formed at intervals in the first direction X, and are respectively formed as stripes extending in the second direction Y. That is, the plurality of source openings 90 are formed as stripes extending in the second direction Y. The plurality of source openings 90 are formed at intervals from the gate wiring 52 in the second direction Y. That is, the plurality of source openings 90 are formed in the region surrounded by the plurality of gate electrodes 32 and the gate wiring 52.

[0160] Multiple source openings 90 may also be formed in the region between two adjacent gate structures 30 along the first direction X. In this case, the multiple source openings 90 may also be arranged in a row with intervals in the second direction Y. Moreover, in this case, each source opening 90 may be formed in a quadrilateral shape (square), a rectangular shape extending along the first direction X, a rectangular shape extending along the second direction Y, a hexagonal shape, a circular shape, etc. when viewed from above.

[0161] The source opening 90 may have a width W of 0.2 μm or more and 3 μm or less. The width W of the source opening 90 is preferably 0.3 μm or more and 1 μm or less. The source opening 90 may have a depth D of 0.2 μm or more and 2 μm or less. The depth D of the source opening 90 is preferably 0.5 μm or more and 1 μm or less.

[0162] The source opening 90 preferably has an aspect ratio D / W of 0.3 or more and 3 or less. The aspect ratio D / W is defined by the ratio of the depth D of the source opening 90 to the width W of the source opening 90. The aspect ratio D / W is preferably 0.5 or more and 2 or less. Particularly preferred is an aspect ratio D / W greater than 1. According to this structure, a plurality of gate structures 30 are arranged with a narrow pitch.

[0163] The semiconductor device 1 includes at least one (in this embodiment, multiple) external openings 92 formed in an interlayer film 70 within a peripheral region 9. The multiple external openings 92 are formed in the interlayer film 70 in portions covering a terminal region 45. The multiple external openings 92 penetrate the interlayer film 70, exposing the terminal region 45. In this embodiment, the multiple external openings 92 are formed in the interlayer film 70 in portions covering an overlapping region 46 of the terminal region 45, exposing the overlapping region 46.

[0164] Multiple external openings 92 may replace the terminal region 45 (overlapping region 46) or, based thereon, expose the outer main body region 21. The multiple external openings 92 penetrate both the first oxide film 72 and the second oxide film 73, and have walls defined by both the first oxide film 72 and the second oxide film 73. The multiple external openings 92 have opening ends defined by the rounded corners of the interlayer film 70.

[0165] Multiple external openings 92 are formed at intervals along the terminal region 45 (overlapping region 46) (see reference). Figure 4 and Figure 5 The multiple external openings 92 can also be formed in a quadrilateral (square), rectangular, hexagonal, circular, or other shapes when viewed from above. The multiple external openings 92 can also be formed in a strip shape that extends along the terminal region 45 (overlapping region 46) when viewed from above. Like the source opening 90, the external openings 92 can also have an aspect ratio D / W (preferably greater than 1).

[0166] The semiconductor device 1 may also have a single external opening 92. The single external opening 92 may also be formed as a strip extending along the terminal region 45 (overlapping region 46). The single external opening 92 may also have a portion extending in a strip shape along a first direction X and a portion extending in a strip shape along a second direction Y when viewed from above.

[0167] The single outer opening 92 can also be formed as a polygonal ring with four sides parallel to the periphery of the first main surface 3, either end-shaped or ring-shaped (in this case, a quadrilateral ring). The single outer opening 92 can also have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y, which, when viewed from above, mimic the terminal region 45 (overlapping region 46), into an arc shape (preferably a quarter arc shape).

[0168] The semiconductor device 1 includes a plurality of recesses 93 formed in portions of the first main surface 3 that are exposed from a plurality of external openings 92. The semiconductor device 1 does not necessarily need to have the recesses 93. Therefore, a structure without the recesses 93 may also be used.

[0169] Multiple recesses 93 each have a planar shape that matches the planar shape of the corresponding external opening 92, and are recessed from the first main surface 3 toward the second main surface 4. The multiple recesses 93 are formed at intervals from the bottom of the terminal region 45 (overlapping region 46) toward the first main surface 3, thus exposing the terminal region 45 (overlapping region 46) respectively. In the case of a single external opening 92, a single external recess 93 is formed that matches the planar shape of the single external opening 92.

[0170] The semiconductor device 1 includes at least one (in this case, multiple) gate openings 94 formed in an interlayer film 70 in an outer peripheral region 9. The multiple gate openings 94 are formed in the interlayer film 70 in portions covering gate wiring 52. The multiple gate openings 94 penetrate the interlayer film 70, exposing the wiring surface 53 of the gate wiring 52.

[0171] Multiple gate openings 94 penetrate both the first oxide film 72 and the second oxide film 73, and have walls defined by the first oxide film 72 and the second oxide film 73. The multiple gate openings 94 have opening ends defined by the rounded corners of the interlayer film 70.

[0172] Multiple gate openings 94 are spaced apart along gate wiring 52 (see reference) Figure 4 as well as Figure 5 The multiple gate openings 94 can also be formed in a quadrilateral (square), rectangular, hexagonal, circular, or other shapes when viewed from above. The multiple gate openings 94 can also be formed as a strip extending along the gate wiring 52 when viewed from above. The gate openings 94 can have the same aspect ratio D / W (preferably greater than 1) as the source openings 90.

[0173] Semiconductor device 1 may also have a single gate opening 94. The single gate opening 94 may also be formed as a strip extending along the gate wiring 52. The single gate opening 94 may also have a portion extending in a strip shape along a first direction X and a portion extending in a strip shape along a second direction Y when viewed from above.

[0174] A single gate opening 94 can also be formed as a polygonal ring with four sides parallel to the periphery of the first main surface 3, either end-shaped or annular (in this case, a quadrilateral ring). A single gate opening 94 can also have an edge portion where, when viewed from above, the portion extending in the first direction X and the portion extending in the second direction Y, mimicking the gate wiring 52, are connected in an arc shape (preferably a quarter arc shape) (see reference). Figure 4 ).

[0175] Reference Figure 1 The semiconductor device 1 includes a source pad electrode 95 disposed on an interlayer film 70. The source pad electrode 95 is a terminal electrode on which a source potential is applied from the outside. The source pad electrode 95 may also be referred to as a "first pad electrode", "first main surface electrode", "first terminal electrode", etc.

[0176] The source pad electrode 95 is disposed on the portion of the interlayer film 70 covering the active region 8. The source pad electrode 95 covers multiple gate electrodes 32 through the interlayer film 70 and is electrically separated from the multiple gate electrodes 32 through the interlayer film 70. The source pad electrode 95 is electrically connected to multiple body regions 20, outer body region 21, multiple source regions 23, 24, contact region 25, etc., through multiple source openings 90.

[0177] In this configuration, the source pad electrode 95 has a first pad portion 96, a second pad portion 97, and a third pad portion 98. The first pad portion 96 has a relatively large planar area, forming the main body of the source pad electrode 95. In this configuration, the first pad portion 96 is formed into a polygonal shape (quadrilateral shape in this configuration) with four sides parallel to the periphery of the chip 2 when viewed from above, and is offset towards the fourth side 5D side relative to the center of the active region 8. The first pad portion 96 covers multiple gate electrodes 32 through the interlayer film 70 and is electrically connected to multiple main body regions 20 via multiple source openings 90.

[0178] The second pad portion 97 has a planar area smaller than that of the first pad portion 96, and extends in a strip shape (quadrilateral shape) from one end of the first pad portion 96 in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C side. The second pad portion 97 covers a plurality of gate electrodes 32 through the interlayer film 70, and is electrically connected to a plurality of body regions 20 via a plurality of source openings 90.

[0179] The third pad portion 98 has a planar area smaller than that of the first pad portion 96, and extends in a strip shape (quadrilateral shape) from the other end of the first pad portion 96 in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C side, and is opposite to the second pad portion 97 in the second direction Y. The third pad portion 98 covers a plurality of gate electrodes 32 through the interlayer film 70, and is electrically connected to a plurality of body regions 20 via a plurality of source openings 90.

[0180] The planar area of ​​the third pad portion 98 can also be approximately equal to the planar area of ​​the second pad portion 97. Of course, the planar area of ​​the third pad portion 98 can be larger or smaller than the planar area of ​​the second pad portion 97. Either or both of the second pad portion 97 and the third pad portion 98 can be used as a terminal portion for current monitoring.

[0181] The source pad electrode 95 does not necessarily have both a second pad portion 97 and a third pad portion 98. The source pad electrode 95 may also have only one of the second pad portion 97 and the third pad portion 98. Of course, the source pad electrode 95 may also be composed only of the first pad portion 96, without the second pad portion 97 and the third pad portion 98.

[0182] Reference Figure 6 as well as Figure 7 The source pad electrode 95 includes a first base electrode film 100 and a first main electrode film 102. The first base electrode film 100 can also be referred to as the "source base electrode film", and the first main electrode film 102 can be referred to as the "source main electrode film".

[0183] The first base electrode film 100 forms the lower layer of the source pad electrodes 95 (first pad portion 96, second pad portion 97, and third pad portion 98), and covers the active region 8 with an interlayer film 70. The first base electrode film 100 covers the region of the interlayer film 70 where multiple source openings 90 are formed as a film. That is, the first base electrode film 100 extends from above the insulating surface 71 into the multiple source openings 90.

[0184] The first base electrode film 100 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner and a portion that covers the wall surfaces of the plurality of source openings 90 in a film-like manner. The first base electrode film 100 has recesses defined in each of the plurality of source openings 90. The first base electrode film 100 may also have a portion that partially covers the gate wiring 52 through the interlayer film 70. The first base electrode film 100 may also be formed at intervals from the gate wiring 52 inward when viewed from above.

[0185] In this configuration, the first substrate electrode film 100 has a laminated structure comprising a first electrode film 103 laminated on an interlayer film 70 and a second electrode film 104 laminated on the first electrode film 103. In this configuration, the first electrode film 103 comprises a Ti film, and the second electrode film 104 comprises a TiN film.

[0186] The first substrate electrode film 100 does not necessarily need to have a laminated structure; it can also have a single-layer structure composed of either the first electrode film 103 (Ti film) or the second electrode film 104 (TiN film). The thickness of the first electrode film 103 can also be 10 nm or more and 100 nm or less. The thickness of the second electrode film 104 can also be 50 nm or more and 200 nm or less.

[0187] The first electrode film 103 covers the region of the interlayer film 70 where multiple source openings 90 are formed in a film-like manner, extending from above the insulating surface 71 into the multiple source openings 90. The first electrode film 103 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surface of the multiple source openings 90 in a film-like manner. The first electrode film 103 directly covers the insulating surface 71.

[0188] That is, the first electrode film 103 directly covers the second oxide film 73 on the insulating surface 71. The first oxide film 72 is sandwiched with an interlayer film 70 in the part covering the insulating surface 71 and is opposite to the plurality of gate electrodes 32.

[0189] The first electrode film 103 covers the rounded corner of the interlayer film 70 (second oxide film 73) in a film-like manner and extends into the source opening 90. That is, the first electrode film 103 has a portion that extends in an arc shape at the rounded corner. As a result, the film-forming properties of the first electrode film 103 are improved relative to the interlayer film 70 (the wall surface of the source opening 90).

[0190] The first electrode film 103 extends along the wall of the source opening 90, covering the insulating film 31, the first oxide film 72, and the second oxide film 73. The first electrode film 103 is opposed to the first sidewall 34 (second sidewall 35) of the gate electrode 32 through the interlayer film 70.

[0191] The first electrode film 103 covers the bottom of each source opening 90 in a film-like manner on the first main surface 3 and is electrically connected to the first main surface 3. Specifically, the first electrode film 103 has a portion that covers the bottom of each source opening 90 in a film-like manner and is electrically connected to a plurality of source regions 23, 24 and a contact region 25.

[0192] The second electrode film 104 covers the region in the interlayer film 70 where a plurality of source openings 90 are formed on the first electrode film 103 in a film-like manner. The second electrode film 104 has a portion that sandwiches the first electrode film 103 to cover the interlayer film 70 in a film-like manner, and a portion that sandwiches the wall surface of the first electrode film 103 to cover the plurality of source openings 90 in a film-like manner.

[0193] The second electrode film 104 sandwiches the first electrode film 103 and the interlayer film 70 in the portion covering the insulating surface 71 and is opposed to the plurality of gate electrodes 32.

[0194] The second electrode film 104, mimicking the first electrode film 103, covers the rounded corners of the interlayer film 70 (second oxide film 73) in a film-like manner and extends into the source opening 90. That is, the second electrode film 104 has a portion that extends in an arc shape at the rounded corners of the interlayer film 70. This improves the film-forming properties of the second electrode film 104 relative to the interlayer film 70 (the wall surface of the source opening 90).

[0195] The second electrode film 104 extends along the wall of the source opening 90 and covers the insulating film 31, the first oxide film 72, and the second oxide film 73 through the first electrode film 103. The second electrode film 104 is opposite to the first sidewall 34 (second sidewall 35) of the gate electrode 32 through the first electrode film 103 and the interlayer film 70.

[0196] The second electrode film 104 has a portion that sandwiches the first electrode film 103 and covers the bottom of each source opening 90 in a film-like manner, and is electrically connected to a plurality of source regions 23, 24 and contact region 25 via the first electrode film 103.

[0197] The first main electrode film 102 forms the upper portion of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98) and covers the first base electrode film 100 in a film-like manner. The first main electrode film 102 includes a conductive material that is different from the conductive material of the first base electrode film 100.

[0198] The first main electrode film 102 may also include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may also include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 102 has a thickness greater than the thickness (total thickness) of the first substrate electrode film 100.

[0199] The thickness of the first main electrode film 102 may also be 0.5 μm or more and 5 μm or less. The thickness of the first main electrode film 102 may also have a value belonging to at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0200] The first main electrode film 102 is mechanically and electrically connected to the first base electrode film 100 at the portion covering the insulating surface 71. Thus, the first main electrode film 102 is positioned opposite to the plurality of gate electrodes 32 through the first base electrode film 100 and the interlayer film 70.

[0201] Semiconductor device 1 includes a source finger electrode 110 extending from a source pad electrode 95 to an outer peripheral region 9. The source finger electrode 110 transfers the source potential imparted to the source pad electrode 95 to the outer peripheral region 9. In this manner, the source finger electrode 110 is wound from a portion of the source pad electrode 95 (first pad portion 96) on the fourth side 5D side to a portion of the interlayer film 70 covering the outer peripheral region 9.

[0202] The source finger electrode 110 is led out onto the terminal region 45 and electrically connected to the terminal region 45 via a plurality of external openings 92. Specifically, the source finger electrode 110 is electrically connected to the overlapping region 46 of the terminal region 45 via a plurality of external openings 92.

[0203] The source finger electrode 110 extends in a strip shape along the terminal region 45 (overlapping region 46). When viewed from above, the source finger electrode 110 has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y. In this configuration, the source finger electrode 110 is formed as a polygonal ring (in this configuration, a quadrilateral ring) with four sides parallel to the periphery of the first main surface 3, surrounding the source pad electrode 95. The source finger electrode 110 may also have an edge portion (see reference) where the portion extending in the first direction X and the portion extending in the second direction Y when viewed from above are connected in an arc shape (preferably a quarter arc shape). Figure 4 ).

[0204] The source finger electrode 110, like the source pad electrode 95, includes a first base electrode film 100 and a first main electrode film 102. The first base electrode film 100 forms the lower layer of the source finger electrode 110 and covers the outer peripheral region 9 with an interlayer film 70.

[0205] The first base electrode film 100 covers the region of the interlayer film 70 where multiple external openings 92 are formed in a film-like manner. That is, the first base electrode film 100 extends from above the insulating surface 71 into the multiple external openings 92. The first base electrode film 100 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner and a portion that covers the wall surfaces of the multiple external openings 92 in a film-like manner. The first base electrode film 100 divides recesses into the multiple external openings 92.

[0206] The first base electrode film 100, like the source pad electrode 95, has a stacked structure including a first electrode film 103 and a second electrode film 104. The first electrode film 103 covers the region of the interlayer film 70 where multiple external openings 92 are formed in a film-like manner, extending from above the insulating surface 71 into the multiple external openings 92. That is, the first electrode film 103 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surface of the multiple external openings 92 in a film-like manner.

[0207] The first electrode film 103 covers the rounded corner of the interlayer film 70 (second oxide film 73) in a film-like manner and extends into the outer opening 92. That is, the first electrode film 103 has a portion extending in an arc shape at the rounded corner. As a result, the film-forming properties of the first electrode film 103 are improved relative to the interlayer film 70 (the wall surface of the outer opening 92). The first electrode film 103 extends along the wall surface of the outer opening 92, covering the outer peripheral insulating film 51, the first oxide film 72, and the second oxide film 73.

[0208] The first electrode film 103 covers the first main surface 3 in a film-like manner at the bottom of each external opening 92 and is electrically connected to the first main surface 3 (chip 2). Specifically, the first electrode film 103 has a portion at the bottom of each external opening 92 that covers the external recess 93 in a film-like manner, and is electrically connected to the terminal region 45 (overlapping region 46) within the external recess 93.

[0209] The first electrode film 103 may also be spaced apart from the height position of the first main surface 3 toward the bottom side of the outer recess 93 to cover the outer recess 93 in a film-like manner. The first electrode film 103 may have a portion located at the bottom side of the outer recess 93 relative to the height position of the first main surface 3, and a portion located on the side of the outer peripheral insulating film 51 relative to the height position of the first main surface 3.

[0210] The second electrode film 104 covers the region of the interlayer film 70 in which a plurality of external openings 92 are formed on the first electrode film 103 in a film-like form. That is, the second electrode film 104 has a portion that sandwiches the first electrode film 103 and covers the insulating surface 71 of the interlayer film 70 in a film-like form, and a portion that sandwiches the first electrode film 103 and covers the wall surface of the plurality of external openings 92 in a film-like form.

[0211] The second electrode film 104, mimicking the first electrode film 103, covers the rounded corners of the interlayer film 70 (second oxide film 73) in a film-like manner and extends into the outer opening 92. That is, the second electrode film 104 has a portion extending in an arc shape at the rounded corners of the interlayer film 70 (second oxide film 73). This improves the film-forming properties of the second electrode film 104 relative to the interlayer film 70 (the wall surface of the outer opening 92). The second electrode film 104 extends along the wall surface of the outer opening 92, covering the outer peripheral insulating film 51, the first oxide film 72, and the second oxide film 73 through the first electrode film 103.

[0212] The second electrode film 104 has a portion at the bottom of each external opening 92 that covers the outer recess 93 in a film-like manner through the first electrode film 103, and is electrically connected to the terminal region 45 (overlapping region 46) via the first electrode film 103. When the first electrode film 103 is located on the bottom side of the outer recess 93 relative to the first main surface 3, the second electrode film 104 may also have a portion located inside the outer recess 93. When the first electrode film 103 has a portion located above the first main surface 3, the entire second electrode film 104 is located above the outer recess 93.

[0213] The first main electrode film 102 forms the upper part of the source finger electrode 110 and covers the first base electrode film 100 in a film-like manner. The first main electrode film 102 is mechanically and electrically connected to the first base electrode film 100 in the portion covering the insulating surface 71. That is, the first main electrode film 102 is electrically connected to the terminal region 45 (overlapping region 46) via the first base electrode film 100.

[0214] Semiconductor device 1 includes gate fingers 115 selectively wound on an interlayer film 70. Gate fingers 115 deliver gate potential to gate wiring 52. Gate fingers 115 are wound over a portion of the interlayer film 70 covering the gate wiring 52 (i.e., over the outer peripheral region 9) and electrically connected to the gate wiring 52 via a plurality of gate openings 94.

[0215] The gate finger electrode 115 is disposed spaced apart from the source pad electrode 95 and the source finger electrode 110 in the region between the source pad electrode 95 and the source finger electrode 110. The gate finger electrode 115 is disposed on the gate wiring 52 and extends in a strip shape along the gate wiring 52. When viewed from above, the gate finger electrode 115 has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y.

[0216] In this configuration, the gate finger electrode 115 is formed as an ended strip with four sides parallel to the periphery of the first main surface 3, surrounding the source pad electrode 95. The gate finger electrode 115 may also have an edge portion (see reference) where the portion extending in the first direction X and the portion extending in the second direction Y, when viewed from above, are connected in an arc shape (preferably a quarter arc shape). Figure 4 The gate finger electrode 115 has a pair of open terminals on the fourth side surface 5D side through which the source finger electrode 110 passes.

[0217] Reference Figure 9 The gate finger electrode 115 includes a second base electrode film 120 and a second main electrode film 122. The second base electrode film 120 may also be referred to as the "gate base electrode film" and the second main electrode film 122 as the "gate main electrode film".

[0218] The second base electrode film 120 forms the lower layer of the gate finger electrode 115 and covers the interlayer film 70 in the outer peripheral region 9. The second base electrode film 120 covers the region in the interlayer film 70 where a plurality of gate openings 94 are formed as a film. That is, the second base electrode film 120 extends from above the insulating surface 71 into the plurality of gate openings 94. The second base electrode film 120 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the plurality of gate openings 94 in a film-like manner. The second base electrode film 120 divides a plurality of recesses in the plurality of gate openings 94.

[0219] The second substrate electrode film 120 has a laminated structure including a first electrode film 123 laminated on the interlayer film 70 and a second electrode film 124 laminated on the first electrode film 123. Preferably, the first electrode film 123 comprises the same conductive material as the first electrode film 103 on the source side, and the second electrode film 124 comprises the same conductive material as the second electrode film 104 on the source side. In this embodiment, the first electrode film 123 comprises a Ti film, and the second electrode film 124 comprises a TiN film.

[0220] The second substrate electrode film 120 does not necessarily need to have a laminated structure; it can also have a single-layer structure composed of either the first electrode film 123 (Ti film) or the second electrode film 124 (TiN film). The first electrode film 123 can also have a thickness approximately equal to the thickness of the first electrode film 103 on the source side. The second electrode film 124 can also have a thickness approximately equal to the thickness of the second electrode film 104 on the source side.

[0221] The first electrode film 123 covers the region in the interlayer film 70 where a plurality of gate openings 94 are formed in a film-like manner, and extends into the plurality of gate openings 94 from above the insulating surface 71. That is, the first electrode film 123 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surface of the plurality of gate openings 94 in a film-like manner.

[0222] The first electrode film 123 covers the rounded corner of the interlayer film 70 (second oxide film 73) in a film-like manner and extends into the gate opening 94. That is, the first electrode film 123 has a portion extending in an arc shape at the rounded corner. As a result, the film-forming properties of the first electrode film 123 are improved relative to the interlayer film 70 (the wall surface of the gate opening 94). The first electrode film 123 extends along the wall surface of the gate opening 94, covering the outer peripheral insulating film 51, the first oxide film 72, and the second oxide film 73.

[0223] The first electrode film 123 covers the gate wiring 52 in a film-like manner at the bottom of each gate opening 94 and is electrically connected to the gate wiring 52.

[0224] The second electrode film 124 covers the region in the interlayer film 70 where a plurality of gate openings 94 are formed on the first electrode film 123 in a film-like manner. That is, the second electrode film 124 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner with the first electrode film 123 sandwiched in it, and a portion that covers the wall surface of the first electrode film 123 in a film-like manner with the plurality of gate openings 94 sandwiched in it.

[0225] The second electrode film 124, mimicking the first electrode film 123, covers the rounded corners of the interlayer film 70 (second oxide film 73) in a film-like manner and extends into the gate opening 94. That is, the second electrode film 124 has a portion extending in an arc shape at the rounded corners of the interlayer film 70 (second oxide film 73). This improves the film-forming properties of the second electrode film 124 relative to the interlayer film 70 (the wall surface of the gate opening 94). The second electrode film 124 extends along the wall surface of the gate opening 94, covering the outer peripheral insulating film 51, the first oxide film 72, and the second oxide film 73 through the first electrode film 123.

[0226] The second electrode film 124 has a portion at the bottom of each gate opening 94 where the first electrode film 123 is sandwiched to cover the gate wiring 52 in a film-like manner, and is electrically connected to the gate wiring 52 via the first electrode film 123.

[0227] The second main electrode film 122 forms the upper portion of the gate finger electrode 115, covering the second base electrode film 120 in a film-like manner. The second main electrode film 122 includes a conductive material different from the conductive material of the second base electrode film 120.

[0228] The second main electrode film 122 may also include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may also include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. Preferably, the second main electrode film 122 includes the same conductive material as the conductive material of the first main electrode film 102. The second main electrode film 122 may also have a thickness approximately equal to that of the first main electrode film 102.

[0229] The second main electrode film 122 is mechanically and electrically connected to the second base electrode film 120 in the portion covering the insulating surface 71.

[0230] Semiconductor device 1 includes a gate pad electrode 130 disposed on an interlayer film 70. The gate pad electrode 130 is a terminal electrode to which a gate potential is applied from the outside. The gate pad electrode 130 may also be referred to as a "second pad electrode," "second main surface electrode," "second terminal electrode," etc. The gate pad electrode 130 is disposed in the region between the source pad electrode 95 and the source finger electrode 110, spaced apart from the source pad electrode 95 and the source finger electrode 110.

[0231] In this configuration, the gate pad electrode 130 is positioned relative to the first pad portion 96 on the third side surface 5C and is held by the second pad portion 97 and the third pad portion 98. That is, the gate pad electrode 130 is opposite to the first pad portion 96 in the first direction X, and opposite to the second pad portion 97 and the third pad portion 98 in the second direction Y.

[0232] The gate pad electrode 130, when viewed from above, is formed as a polygon with four sides parallel to the periphery of the chip 2 (in this case, a quadrilateral shape). The gate pad electrode 130 has an area smaller than the planar area of ​​the source pad electrode 95 (first pad portion 96). The gate pad electrode 130 may also have a planar area smaller than the planar area of ​​the second pad portion 97 (third pad portion 98).

[0233] The gate pad electrode 130 is disposed over the portion covering the active region 8 and the outer peripheral region 9 and is connected to the gate finger electrode 115. The gate pad electrode 130 may cover multiple gate electrodes 32 through the interlayer film 70, or it may cover the gate wiring 52 through the interlayer film 70.

[0234] The gate pad electrode 130, like the gate finger electrode 115, includes a second base electrode film 120 and a second main electrode film 122. The second base electrode film 120 forms the lower layer of the gate pad electrode 130, covering the interlayer film 70 in a film-like manner. Like the gate finger electrode 115, the second base electrode film 120 has a laminated structure including a first electrode film 123 and a second electrode film 124. The first electrode film 123 covers the interlayer film 70 in a film-like manner, and the second electrode film 124 covers the first electrode film 123 in a film-like manner. The second main electrode film 122 forms the upper layer of the gate pad electrode 130, covering the second base electrode film 120 in a film-like manner.

[0235] The gate potential applied to the gate pad electrode 130 is applied to the gate wiring 52 via the gate finger electrode 115. The gate potential is transmitted to the plurality of gate electrodes 32 via the wiring path (current path) along the gate wiring 52. As a result, the plurality of gate electrodes 32 are turned on, controlling the on and off states of the plurality of channel regions 26, 27.

[0236] Semiconductor device 1 includes a drain pad electrode 140 covering a second main surface 4. The drain pad electrode 140 is a terminal electrode to which a drain potential is applied from the outside. The drain pad electrode 140 may also be referred to as a "third pad electrode," "third main surface electrode," "third terminal electrode," etc. The drain pad electrode 140 is electrically connected to a second semiconductor region 7. The drain pad electrode 140 may also cover the entire area of ​​the second main surface 4 in a manner connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain pad electrode 140 may also partially cover the second main surface 4 in a manner that exposes the periphery of the second main surface 4.

[0237] The breakdown voltage that can be applied between the source pad electrode 95 and the drain pad electrode 140 (between the first main surface 3 and the second main surface 4) can be 500V or more and 3000V or less. The breakdown voltage can have a value belonging to at least one of the following ranges: 500V or more and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or less, and 2500V or more and 3000V or less.

[0238] Next, refer to Figure 6 , Figure 7 as well as Figure 10 The contact structures for source regions 23 and 24 are described in detail. Figure 10 This is a schematic perspective view that details the structure of the tabletop contact part 41.

[0239] In semiconductor device 1, a portion of chip 2 is exposed as a contact portion 40 from a source opening 90 between adjacent gate structures 30. A source pad electrode 95 is mechanically and electrically connected to the contact portion 40 within the source opening 90.

[0240] Reference Figure 7 and Figure 10 In this configuration, the contact portion 40 includes a tabletop contact portion 41 and a flat contact portion 42.

[0241] Mesa contact portions 41 are formed separately from the two side walls of the source opening 90 and extend inward. The mesa contact portions 41 extend in a stripe shape along the stripe direction of the gate structure 30. In this manner, one mesa contact portion 41 is formed in each source opening 90 that extends in a stripe shape, and as a whole, a plurality of mesa contact portions 41 are arranged in a stripe shape.

[0242] Each tabletop contact portion 41 protrudes from the first main surface 3 and has an upper tabletop portion 43 and a tabletop side portion 44.

[0243] The upper part 43 of the tabletop can also extend approximately parallel to the insulating film 31 (first main surface 3). The upper part 43 of the tabletop can also be referred to as the upper wall of the tabletop.

[0244] The platform side 44 may also include a first platform side 44A facing the first sidewall 34 and a second platform side 44B facing the second sidewall 35. Both the first platform side 44A and the second platform side 44B are formed spaced apart from the sidewall of the interlaminar membrane 70 in the first direction X and extend in the vertical direction Z. The first platform side 44A and the second platform side 44B may also extend perpendicularly to the first main surface 3. That is, the platform contact portion 41 may also be formed in a quadrilateral shape (a flat rectangular shape) in cross-section.

[0245] Although the illustration is omitted, the first tabletop side portion 44A and the second tabletop side portion 44B may also be inclined toward the upper part 43 of the tabletop. That is, the tabletop contact portion 41 may also be formed into a conical shape (preferably an isosceles trapezoidal shape) in cross-section. The first tabletop side portion 44A and the second tabletop side portion 44B may also be referred to as the first tabletop sidewall and the second tabletop sidewall, respectively.

[0246] The flat contact portion 42 is a region formed by a portion of the first main surface 3 between the mesa contact portion 41 and the sidewall of the source opening 90. In this manner, a pair of flat contact portions 42 sandwiching the strip-shaped mesa contact portion 41 are arranged side by side with the mesa contact portion 41 to form a stripe pattern.

[0247] The width W1 of the mesa contact portion 41 may also be wider than the width W2 of each flat contact portion 42. The width W1 of the mesa contact portion 41 may also be wider than the sum of the widths W2 of the pair of flat contact portions 42. The width W1 of the mesa contact portion 41 may also be wider than half the width W of the source opening 90.

[0248] In this configuration, the mesa contact portion 41 is formed by the main body region 20, the contact region 25, and the source regions 23 and 24. The mesa contact portion 41 includes these three impurity regions by dividing the main body region 20, the contact region 25, and the source regions 23 and 24 into a predetermined pattern during cross-sectional observation.

[0249] At least one of the contact region 25 and the source regions 23 and 24 is exposed from the upper part 43 and the side part 44 of the mesa contact portion 41 and connected to the source pad electrode 95.

[0250] In this configuration, the tabletop contact portion 41 includes an impurity region in the first contact portion 36 configuration. (See reference...) Figure 10 In the first contact portion 36, the tabletop contact portion 41 includes: a main body protrusion 37, formed by a portion of the main body region 20, facing the upper part of the tabletop 43 through the side of the source regions 23 and 24; a contact region 25, connected to the main body protrusion 37 at the upper part of the tabletop 43; and source regions 23 and 24, formed around the main body protrusion 37 and exposed from the side of the tabletop 44.

[0251] The main body protrusion 37 has boundary surfaces 38 with the source regions 23 and 24 at intervals spaced inward from the first mesa side 44A and the second mesa side 44B, respectively. Thus, the main body protrusion 37 extends in a strip-like shape along the strip-shaped mesa contact portion 41. The upper end of the main body protrusion 37 (the boundary with the contact region 25) may be less than half the height of the mesa contact portion 41. Of course, the upper end of the main body protrusion 37 may also be more than half the height of the mesa contact portion 41.

[0252] The contact area 25 is continuously formed along the length of the tabletop contact portion 41 on the upper part 43 of the tabletop, and is exposed from the upper part 43 of the tabletop and a pair of tabletop sides 44A and 43B. Therefore, the contact area 25 is entirely exposed from the upper surface of the tabletop contact portion 41.

[0253] The first source region 23 and the second source region 24 span between the mesa contact portion 41 and the gate electrode 32, and have ends on the inner side of the mesa contact portion 41 in the width direction. Each source region 23, 24 integrally includes: a source flat portion 28, which protrudes from the flat contact portion 42 and extends into the interior of the mesa contact portion 41; and a source vertical portion 29, which stands upright from the source flat portion 28 along the mesa side portion 44 and protrudes from the mesa side portion 44. Thus, the source regions 23 and 24 are formed in a generally L-shape when viewed in cross section. The source vertical portions 29 of the first source region 23 and the second source region 24 are spaced apart and facing each other in the first direction X inside the mesa contact portion 41, with a main body protrusion 37 formed between them.

[0254] In this configuration, the first source region 23 and the second source region 24 are integrally exposed from the underside of the mesa contact portion 41 and the flat contact portion 42 along the stripe direction of the mesa contact portion 41.

[0255] Reference Figure 7 The source pad electrode 95 enters the contact portion 40 and covers the upper part 43 and the side part 44 of the mesa. The source pad electrode 95 is mechanically and electrically connected to the contact area 25 on the upper part 43 and the upper side of the mesa 44, and mechanically and electrically connected to the source areas 23 and 24 on the lower side of the mesa 44 and the flat contact portion 42. In this configuration, the first base electrode film 100 is embedded in the gap 39 between the mesa contact portion 41 and the interlayer film 70, and the first main electrode film 102 is embedded in the area of ​​the source opening 90 above the mesa contact portion 41.

[0256] For example, to meet the requirements of device miniaturization, multiple gate structures 30 are sometimes arranged with a narrow pitch. Because the distance between adjacent gate structures 30 is narrowed, the width W of the source opening 90 used for the source contact becomes very small. This reduction in the width W of the source opening 90 decreases the contact area between the source pad electrode 95 and the source regions 23, 24 and the contact region 25. If the contact area is reduced, the contact resistance increases.

[0257] Therefore, according to the semiconductor device 1, since a mesa contact portion 41 is formed in the contact portion 40, the source pad electrode 95 can make contact with both the upper mesa 43 and the mesa side portion 44. Thus, compared to the case where the contact portion 40 is formed only by a flat surface, the contact resistance with respect to the source regions 23, 24 and the contact region 25 can be reduced. Therefore, the requirement for narrower pitch in the gate structure 30 can be met, and the contact resistance can also be reduced.

[0258] Figure 11 This is a schematic diagram showing the wafer 150 used in the manufacture of semiconductor device 1. (Refer to...) Figure 11 Wafer 150 is the substrate of chip 2, including SiC single crystal. Wafer 150 is formed into a flat disk shape. Of course, wafer 150 can also be formed into a flat cuboid shape. Wafer 150 has a first wafer main surface 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.

[0259] The first wafer principal surface 151 corresponds to the first principal surface 3 of the chip 2, and the second wafer principal surface 152 corresponds to the second principal surface 4 of the chip 2. Both the first wafer principal surface 151 and the second wafer principal surface 152 are formed from the c-plane of a SiC single crystal. The first wafer principal surface 151 is formed from the silicon plane of a SiC single crystal, and the second wafer principal surface 152 is formed from the carbon plane of a SiC single crystal. The wafer 150 (the first wafer principal surface 151 and the second wafer principal surface 152) has the aforementioned offset direction and offset angle.

[0260] The wafer 150 has a mark 154 on its side surface 153 indicating the crystal orientation of the SiC single crystal. The mark 154 may also include either or both of an orientation plane and an orientation notch. The orientation plane is formed by a cut portion that appears as a straight line when viewed from above. The orientation notch is formed by a cut portion that is cut into a concave shape (e.g., a pointed shape) towards the center of the first wafer main surface 151 when viewed from above.

[0261] Marker 154 may also include either or both of a first orientation plane extending along the m-axis and a second orientation plane extending along the a-axis. Marker 154 may also include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0262] The wafer 150 includes a first semiconductor region 6 in the region (surface layer) on the side of the first wafer main surface 151. The first semiconductor region 6 is formed as a layer extending along the first wafer main surface 151. In this configuration, the first semiconductor region 6 is composed of an epitaxial layer (specifically a SiC epitaxial layer).

[0263] The wafer 150 includes a second semiconductor region 7 in the region (surface portion) on the second main surface 152. The second semiconductor region 7 is formed as a layer extending along the second main surface 4 and is electrically connected to the first semiconductor region 6. In this configuration, the second semiconductor region 7 is constituted by a wafer body (specifically, a SiC wafer). That is, in this configuration, the wafer 150 is constituted by an epitaxial wafer (so-called epitaxial wafer) having a stacked structure including a wafer body and an epitaxial layer.

[0264] For example, on wafer 150, multiple device regions 155 and multiple cut-off lines 156 are defined by alignment marks, etc. Each device region 155 is a region corresponding to semiconductor device 1. The multiple device regions 155 are each set as quadrilateral shapes when viewed from above.

[0265] In this configuration, multiple device regions 155 are arranged in a matrix shape along the first direction X and the second direction Y when viewed from above. The multiple device regions 155 are spaced apart from the periphery of the first wafer main surface 151 when viewed from above. Multiple predetermined cutting lines 156 are arranged in a grid shape extending along the first direction X and the second direction Y to divide the multiple device regions 155.

[0266] Figures 12A to 12O This is a cross-sectional view showing a method for manufacturing semiconductor device 1. Figures 12A to 12O The image shows a cross-section of a portion of the active region 8 within a device region 155.

[0267] Reference Figure 12A First, prepare the aforementioned wafer 150. Next, refer to... Figure 12B Multiple host regions 20 are formed by selectively introducing p-type impurities into the surface layer of the first wafer host surface 151 via ion implantation through a mask (not shown). Additionally, multiple host regions 21 are formed by selectively introducing p-type impurities into the surface layer of the first wafer host surface 151 via ion implantation through a mask (not shown). Furthermore, multiple source regions 23 and 24 are formed by selectively introducing n-type impurities into the surface layer of the first wafer host surface 151 via ion implantation through a mask (not shown).

[0268] Next, refer to Figure 12C p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 to form contact region 25.

[0269] Next, refer to Figure 12D A mask 167 with a predetermined layout is formed on the first wafer main surface 151 (contact region 25). The mask 167 may also be an organic mask (e.g., a resist mask). The mask 167 has multiple openings 166 that cover the area where multiple mesa contacts 41 are to be formed and expose other areas.

[0270] Next, refer to Figure 12E Unwanted portions of wafer 150 are removed in the thickness direction. In this process, wafer 150 is removed by etching via mask 167. The etching method can be wet etching and / or dry etching, but dry etching is preferred. Thus, the portion of wafer 150 protected by mask 167 remains as mesa contact portion 41, while other areas are formed as flat contact portion 42.

[0271] Next, refer to Figure 12F A base insulating film 160 is formed covering the main surface 151 of the first wafer. The base insulating film 160 is the base of the insulating film 31 and the outer peripheral insulating film 51. The base insulating film 160 can also be formed by CVD (Chemical Vapor Deposition) or oxidation treatment (e.g., thermal oxidation treatment).

[0272] Next, refer to Figure 12G A base electrode 161 is formed on the base insulating film 160. The base electrode 161 is the base of the gate electrode 32 and the gate wiring 52. The base electrode 161 comprises conductive polysilicon. The base electrode 161 can also be formed by CVD. The base electrode 161 has a base electrode surface 162 extending along the base insulating film 160.

[0273] Next, refer to Figure 12H A mask 168 with a predetermined layout is formed on the base electrode 161 (base electrode surface 162). The mask 168 may also be an organic mask (e.g., a resist mask). The mask 168 has a plurality of openings 169 that expose areas other than a plurality of mask portions covering the areas where the plurality of gate electrodes 32 are to be formed.

[0274] Next, refer to Figure 12I Unwanted portions of the base electrode 161 are removed in the thickness direction. The base electrode 161 is removed in this process by etching via a mask 168. The etching method can be wet etching and / or dry etching. This forms a plurality of gate electrodes 32 and gate wiring 52. After the formation of the gate electrodes 32 and gate wiring 52, the mask 168 is removed.

[0275] Next, refer to Figure 12J An interlayer film 70 is formed on the main surface 151 of the first wafer. In this process, an interlayer film 70 having a portion directly covering the gate electrode 32 is formed. In addition, an interlayer film 70 having a portion directly covering the gate wiring 52 is formed.

[0276] In this manner, the interlayer film 70 has a laminated structure including a first oxide film 72 and a second oxide film 73 (see reference). Figure 7 The first oxide film 72 comprises a silicon oxide film without added impurities. The second oxide film 73 comprises a silicon oxide film containing phosphorus. The first oxide film 72 can also be formed by CVD. The second oxide film 73 can also be formed by CVD. After the formation of the second oxide film 73, a reflow process (heat treatment process) is performed on the interlayer film 70.

[0277] As a result, the corners and surface roughness of the interlayer membrane 70 are smoothed.

[0278] Next, refer to Figure 12K A mask 174 with a predetermined layout is disposed on the interlayer film 70. The mask 174 exposes the areas where a plurality of source openings 90, a plurality of external openings 92 and a plurality of gate openings 94 should be formed, and covers the areas outside them.

[0279] Next, refer to Figure 12L Unwanted portions of the interlayer film 70 and the base insulating film 160 are removed by etching via mask 174. In this process, unwanted portions of the second oxide film 73, the first oxide film 72, and the base insulating film 160 are removed sequentially. The etching method can be wet etching and / or dry etching. Anisotropic dry etching (e.g., RIE (Reactive Ion Etching)) is preferred.

[0280] Thus, multiple source openings 90, multiple external openings 92, and multiple gate openings 94 are formed on the interlayer film 70. Additionally, an insulating film 31 and a peripheral insulating film 51 are formed. The mask 174 is then removed.

[0281] Next, refer to Figure 12M Through reflow treatment, the upper corner of the interlayer membrane 70 is shaped into an arc shape. The reflow conditions are as follows: Figure 12L The condition that the upper corner of the etched, pointed interlayer film 70 becomes rounded is acceptable, without particular restrictions. For example, it can be appropriately determined based on the film thickness, film quality, and opening width of the source opening 90.

[0282] Next, refer to Figure 12N A first substrate electrode film 100 and a second substrate electrode film 120 are formed on the interlayer film 70. The first substrate electrode film 100 and the second substrate electrode film 120 can be formed by sputtering or vapor deposition.

[0283] Next, refer to Figure 12O A first main electrode film 102 and a second main electrode film 122 are formed on the first base electrode film 100 and the second base electrode film 120, respectively. The first main electrode film 102 and the second main electrode film 122 may also include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may also include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 102 and the second main electrode film 122 may also be formed by sputtering or vapor deposition.

[0284] Then, a drain pad electrode 140 is formed on the main surface 152 of the second wafer. The drain pad electrode 140 can be formed by sputtering or vapor deposition. Then, the wafer 150 is cut using a dicing line 156 to cut out a plurality of semiconductor devices 1. Through the above processes, the semiconductor devices 1 are manufactured.

[0285] The following shows a modified example of the tabletop contact portion 41. Figure 13 This is a cross-sectional view showing a first modified example (second contact portion 50) of the tabletop contact portion 41. Figure 14 It includes Figure 13 A perspective view of the platform contact portion 41 of the second contact portion 50.

[0286] In this configuration, the tabletop contact portion 41 includes an impurity area not only as the first contact portion 36, but also as the second contact portion 50. (See reference...) Figure 14 The first contact portion 36 and the second contact portion 50 are formed in a segmented manner along the stripe direction of the mesa contact portion 41 (the stripe direction of the gate structure 30). For example, in Figure 14 In the middle, the second contact portion 50 is formed as a strip on the table surface contact portion 41, and the first contact portion 36 and the second contact portion 50 are formed continuously.

[0287] exist Figure 14 In this configuration, one strip-shaped second contact portion 50 and one strip-shaped first contact portion 36 are each formed. The second contact portion 50 is located in front of the paper surface, but the first contact portion 36 may also be located in front of the paper surface. In addition, multiple second contact portions 50 and multiple first contact portions 36 may be arranged alternately along the stripe direction of the table surface contact portion 41.

[0288] Reference Figure 14 In the second contact portion 50, the platform contact portion 41 is formed entirely by source regions 23 and 24 from the upper platform 43 to the thickness direction, with source regions 23 and 24 exposed from both the upper platform 43 and the platform side portion 44. The first source region 23 and the second source region 24 are integrated inside the platform contact portion 41 and are formed as a single source region 56 in the entire platform contact portion 41 of the second contact portion 50.

[0289] The source region 56 is continuously formed in the second contact portion 50 along the length direction of the mesa contact portion 41 on the upper mesa 43 and the mesa side portion 44, and is exposed from the upper mesa 43 and the pair of mesa side portions 44A and 43B. Therefore, the source region 56 is completely exposed from the surface of the mesa contact portion 41.

[0290] According to this structure, the source pad electrode 95 can be made into overall contact with the upper part 43 and the side part 44 of the mesa contact portion 41 at the second contact portion 50. As a result, the contact area relative to the source regions 23 and 24 can be reduced, and the contact resistance can be reduced.

[0291] Figures 15A to 15D It means and Figure 13 The diagram shows the process related to the formation of the second contact portion 50. The second contact portion 50 can be formed in parallel with the aforementioned first contact portion 36.

[0292] To form the second contact portion 50, for example, after preparing the wafer 150, refer to... Figure 15A Multiple host regions 20 are formed by selectively introducing p-type impurities into the surface layer of the first wafer host surface 151 via ion implantation through a mask (not shown). Additionally, multiple host regions 21 are formed by selectively introducing p-type impurities into the surface layer of the first wafer host surface 151 via ion implantation through a mask (not shown). Furthermore, multiple source regions 56 are formed by selectively introducing n-type impurities into the surface layer of the first wafer host surface 151 via ion implantation through a mask (not shown).

[0293] Next, refer to Figure 15B When the aforementioned contact area 25 is formed (refer to...) Figure 12C The area where the second contact portion 50 should be formed is covered and protected by the mask 165. This prevents p-type impurities from being introduced into the second contact portion 50.

[0294] Next, refer to Figure 15C A mask 167 with a predetermined layout is formed on the first wafer main surface 151 (contact region 25 and source region 56). The mask 167 may also be an organic mask (e.g., a resist mask). The mask 167 has multiple openings 166 that cover the area where multiple mesa contacts 41 are to be formed and expose other areas.

[0295] Next, refer to Figure 15D Unwanted portions of wafer 150 are removed in the thickness direction. In this process, wafer 150 is removed by etching via mask 167. The etching method can be wet etching and / or dry etching, but dry etching is preferred. Thus, portions of wafer 150 protected by mask 167 remain as mesa contact portions 41 (first contact portion 36 and second contact portion 50), while other areas are formed as flat contact portions 42.

[0296] Figure 16 This is a cross-sectional view showing a second modified example (third contact portion 84) of the tabletop contact portion 41. Figure 17 It includes Figure 16A perspective view of the third contact portion 84 and the platform contact portion 41.

[0297] In this configuration, the tabletop contact portion 41 includes an impurity area not only as a second contact portion 50, but also as a third contact portion 84. (See reference...) Figure 17 The second contact portion 50 and the third contact portion 84 are formed in a mutually segmented manner along the stripe direction of the mesa contact portion 41 (the stripe direction of the gate structure 30). For example, in Figure 17 In the middle, the third contact portion 84 is formed as a strip on the table surface contact portion 41, and the second contact portion 50 and the third contact portion 84 are formed continuously.

[0298] exist Figure 17 In this configuration, one strip-shaped third contact portion 84 and one strip-shaped second contact portion 50 are each formed. The third contact portion 84 is located in front of the paper surface, but the second contact portion 50 may also be located in front of the paper surface. Alternatively, multiple third contact portions 84 and multiple second contact portions 50 may be arranged alternately along the stripe direction of the table surface contact portion 41.

[0299] Reference Figure 17 In the third contact portion 84, the platform contact portion 41 is formed by the contact area 25 extending from the upper platform 43 and throughout the thickness direction. The contact area 25 is exposed from both the upper platform 43 and the platform side portion 44. The contact area 25 penetrates the first source region 23 and the second source region 24, and is connected to the main body region 20 at the lower part of the platform contact portion 41.

[0300] The contact area 25 integrally includes a base 85 formed inside the mesa contact portion 41 and an extension 86 extending from the base 85 to the flat contact portion 42. The base 85 extends from the upper mesa 43 to the base of the mesa contact portion 41 in the depth direction and extends from the first mesa side portion 44A to the second mesa side portion 44B in the lateral direction. In this configuration, the base 85 is formed to a depth greater than the source regions 23 and 24. Thus, the contact area 25 (base 85) is exposed in three directions from the upper mesa 43 and the pair of mesa sides 44A and 43B. Therefore, the contact area 25 is entirely exposed from the surface of the mesa contact portion 41.

[0301] The lead-out portion 86 of the contact region 25 extends laterally from the base 85 to both sides, and has a boundary surface 87 with the source regions 23 and 24 in the flat contact portion 42. The lead-out portion 86 is formed in a strip shape along the stripe direction of the mesa contact portion 41. In this configuration, strip-shaped lead-out portions 86 are formed on both sides of the mesa contact portion 41, and the mesa contact portion 41 is sandwiched by a pair of lead-out portions 86. Thus, in each flat contact portion 42, the strip-shaped contact region 25 (lead-out portion 86) and the source regions 23 and 24 are arranged along the stripe direction of the mesa contact portion 41.

[0302] According to this structure, the source pad electrode 95 can be made into overall contact with the upper part 43 and the side part 44 of the mesa contact portion 41 at the third contact portion 84. As a result, the contact area relative to the contact region 25 can be reduced, thereby reducing the contact resistance.

[0303] Figures 18A to 18D It means and Figure 16 The diagram shows the process related to the formation of the third contact portion 84. The third contact portion 84 can be formed in parallel with the aforementioned second contact portion 50.

[0304] To form the third contact 84, for example, after preparing wafer 150, refer to Figure 18A Multiple host regions 20 are formed by selectively introducing p-type impurities into the surface layer of the first wafer host surface 151 via ion implantation through a mask (not shown). Additionally, multiple host regions 21 are formed by selectively introducing p-type impurities into the surface layer of the first wafer host surface 151 via ion implantation through a mask (not shown). Furthermore, multiple source regions 56 are formed by selectively introducing n-type impurities into the surface layer of the first wafer host surface 151 via ion implantation through a mask (not shown).

[0305] Next, refer to Figure 18B A mask 180 with a predetermined layout is formed on the first wafer main surface 151. The mask 180 may also be an organic mask (e.g., a photoresist mask). The mask 180 has openings 181 in the areas where multiple contact regions 25 are to be formed, covering other areas. For example, the entire area where the second contact portion 50 is to be formed is covered by the mask 180. Then, p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 via ion implantation through the mask 180 to form the contact regions 25.

[0306] Next, refer to Figure 18C A mask 167 with a predetermined layout is formed on the first wafer main surface 151 (contact region 25 and source region 56). The mask 167 may also be an organic mask (e.g., a resist mask). The mask 167 has multiple openings 166 that cover the area where multiple mesa contacts 41 are to be formed and expose other areas.

[0307] Next, refer to Figure 18D Unwanted portions of wafer 150 are removed in the thickness direction. In this process, wafer 150 is removed by etching via mask 167. The etching method can be wet etching and / or dry etching, but dry etching is preferred. As a result, portions of wafer 150 protected by mask 167 remain as mesa contact portions 41 (second contact portion 50 and third contact portion 84), while other areas are formed as flat contact portions 42.

[0308] Figures 19-21 These are cross-sectional views showing the fourth to sixth variations of the tabletop contact portion 41. (Refer to...) Figures 19-21 In the contact portion 40, the plurality of mesa contact portions 41 may also be arranged in a dotted pattern at intervals along the stripe direction of the gate structure 30. A second flat contact portion 48 may also be formed between adjacent plurality of mesa contact portions 41.

[0309] In this configuration, the second flat contact portion 48 spans between a pair of strip-shaped flat contact portions 42 sandwiching the platform contact portion 41. The source regions 23 and 24 are exposed from the second flat contact portion 48, forming a single source region 56. Thus, in... Figures 19-21 In the middle, when viewed from above, the ladder-shaped source region 56 is exposed.

[0310] The dotted tabletop contact portions 41 can be any one of the aforementioned first contact portion 36, second contact portion 50, and third contact portion 84, or they can be combined with each other.

[0311] For example, in Figure 19 In this case, all the tabletop contact portions 41 are formed by the first contact portion 36. For example, Figure 20 It is a combination of the platform contact portion 41 formed by the second contact portion 50 and the platform contact portion 41 formed by the first contact portion 36. For example, Figure 21 It is a combination of the tabletop contact portion 41 formed by the third contact portion 84 and the tabletop contact portion 41 formed by the second contact portion 50.

[0312] The embodiments of the present disclosure have been described above, but the semiconductor device 1 of the present disclosure can also be implemented in other ways.

[0313] The aforementioned embodiments (including variations) can also be implemented in other ways. For example, in the various embodiments described, a structure in which the relationship between the a-axis direction and the m-axis direction is interchanged can also be used. The specific structure in this case is obtained by interchangeping the "a-axis direction (deviation direction)" and the "m-axis direction (direction orthogonal to the deviation direction)" in the foregoing description and drawings.

[0314] In the various embodiments described, a structure may also be adopted in which the conductivity type of the "n-type" semiconductor region is reversed to "p-type" and the conductivity type of the "p-type" semiconductor region is reversed to "n-type". The specific structure in this case is obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the foregoing description and drawings.

[0315] In the various embodiments described, a chip 2 comprising a SiC single crystal (first semiconductor region 6 and second semiconductor region 7) is used. However, the chip 2 (first semiconductor region 6 and second semiconductor region 7) may also comprise a single crystal of a wide bandgap semiconductor other than SiC. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. Examples of single crystals that are wide bandgap semiconductors include gallium nitride, diamond, and gallium oxide. Of course, the chip 2 (first semiconductor region 6 and second semiconductor region 7) may also comprise single-crystal silicon.

[0316] In the various embodiments described, an n-type second semiconductor region 7 is shown. However, a p-type second semiconductor region 7 may be used instead of an n-type second semiconductor region 7. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of a MISFET structure. In this case, as described above, the "source" of the MISFET structure is replaced by the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced by the "collector" of the IGBT structure. The p-type second semiconductor region 7 may also include an impurity region containing p-type impurities that is implanted into the surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0317] Hereinafter, examples of features extracted from this specification and accompanying drawings are shown. Hereinafter, alphanumeric characters, etc., denote corresponding constituent elements in the foregoing embodiments, but do not imply that the scope of each item (clause) is limited to the embodiments. The term "semiconductor device" in the following item can be replaced as needed with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc.

[0318] [Appendix 1-1] A semiconductor device 1 includes:

[0319] Chip 2 has a main surface 3;

[0320] Gate electrode 32 is formed on the main surface 3;

[0321] Interlayer film 70, which covers the gate electrode 32;

[0322] An opening 90, formed separately from the gate electrode 32 in the interlayer film 70 along the transverse direction of the main surface 3, exposes a portion of the chip 2 as a contact portion 40; and

[0323] A surface electrode 95, formed on the interlayer film 70, is mechanically and electrically connected to the contact portion 40 within the opening 90.

[0324] The contact portion 40 includes a tabletop contact portion 41 that protrudes from the main surface 3 and has a tabletop side portion 44 and a tabletop upper portion 43.

[0325] The surface electrode 95 covers the side portion 44 of the platform and the upper portion 43 of the platform.

[0326] According to this structure, the surface electrode 95 can make contact with both the mesa side 44 and the upper mesa 43. As a result, compared with the case where the contact portion 40 is formed only by a flat surface, the contact resistance of the contact portion 40 can be reduced.

[0327] [Appendix 1-2] According to the semiconductor device 1 described in Appendix 1-1,

[0328] It also includes a plurality of gate electrodes 32 arranged at intervals on the main surface 3.

[0329] The opening 90 is divided into regions between the plurality of gate electrodes 32.

[0330] The contact portion 40 includes: a tabletop contact portion 41, which is formed inwardly from both side walls of the opening 90; and a flat contact portion 42, which is formed by a portion of the main surface 3 between the tabletop contact portion 41 and the side walls of the opening 90.

[0331] [Appendix 1-3] In the semiconductor device 1 according to Appendix 1-2, wherein,

[0332] The plurality of gate electrodes 32 are formed in a stripe shape.

[0333] The mesa contact portion 41 is formed in a stripe shape along the stripe direction of the gate electrode 32.

[0334] The pair of flat contact portions 42 sandwiching the tabletop contact portion 41 are arranged side by side with the tabletop contact portion 41 in a striped pattern.

[0335] [Appendix 1-4] The semiconductor device 1 according to Appendix 1-2 or Appendix 1-3 further includes:

[0336] A semiconductor region 6 of the first conductivity type is formed on the surface portion of the main surface 3;

[0337] The main body region 20 of the second conductivity type is formed on the surface layer of the semiconductor region 6;

[0338] Impurity regions 23 and 24 of the first conductivity type are formed on the surface of the main body region 20;

[0339] Channels 26 and 27 are formed in the surface portion of the main body region 20 in the region between the semiconductor region 6 and the impurity regions 23 and 24; and

[0340] An insulating film 31, which covers the channels 26 and 27 on the main surface 3, is sandwiched between the gate electrode 32 and the channels 26 and 27.

[0341] The impurity regions 23 and 24 are exposed at least from the platform side 44 and the flat contact portion 42, and are connected to the surface electrode 95.

[0342] [Appendix 1-5] In the semiconductor device 1 according to Appendix 1-4, wherein,

[0343] The tabletop contact portion 41 includes a first contact portion 40, which includes: a main body protrusion 37 formed from a portion of the main body region 20, facing the upper part of the tabletop 43 through the side of the impurity regions 23, 24; a second conductive main body contact region 25 connected to the main body protrusion 37 on the upper part of the tabletop 43; and the impurity regions 23, 24 formed around the main body protrusion 37 and exposed from the side of the tabletop 44.

[0344] [Appendix 1-6] In the semiconductor device 1 according to Appendix 1-5, wherein,

[0345] The tabletop contact portion 41 further includes a second contact portion 50, which is formed entirely by the impurity regions 23 and 24 from the upper part of the tabletop 43 and throughout the thickness direction. The impurity regions 23 and 24 are exposed from both the upper part of the tabletop 43 and the side part of the tabletop 44.

[0346] [Appendix 1-7] In the semiconductor device 1 according to Appendix 1-6, wherein,

[0347] The first contact portion 40 and the second contact portion 50 are formed in a mutually segmented manner along the stripe direction of the gate electrode 32.

[0348] [Appendix 1-8] In the semiconductor device 1 according to Appendix 1-4, wherein,

[0349] The tabletop contact portion 41 includes:

[0350] The second contact portion 50, which is formed entirely by the impurity regions 23 and 24 along the thickness direction from the upper part 43 of the platform, is exposed from both the upper part 43 and the side part 44 of the platform; and

[0351] The third contact portion 84 is formed integrally from the upper part 43 of the table surface in the thickness direction, and is connected to the main body region 20 at the lower part of the table surface contact portion 41. It is formed by the second conductive type main body contact region 25 exposed from both the upper part 43 of the table surface and the side part 44 of the table surface.

[0352] [Notes 1-9] In the semiconductor device 1 according to Notes 1-8, wherein,

[0353] The second contact portion 50 and the third contact portion 84 are formed in a segmented manner along the stripe direction of the tabletop contact portion 41.

[0354] [Appendix 1-10] In the semiconductor device 1 according to Appendix 1-2, wherein,

[0355] The plurality of gate electrodes 32 are formed in a stripe shape.

[0356] The plurality of mesa contacts 41 are arranged at intervals along the stripe direction of the gate electrode 32.

[0357] The pair of flat contact portions 42 sandwiching the tabletop contact portion 41 are arranged side by side with the tabletop contact portion 41 in a striped pattern.

[0358] The contact portion 40 further includes a second flat contact portion 48 formed between adjacent plurality of platform contact portions 41.

[0359] [Appendix 1-11] The semiconductor device 1 according to Appendix 1-10 further includes:

[0360] A semiconductor region 6 of the first conductivity type is formed on the surface portion of the main surface 3;

[0361] The main body region 20 of the second conductivity type is formed on the surface layer of the semiconductor region 6;

[0362] Impurity regions 23 and 24 of the first conductivity type are formed on the surface of the main body region 20;

[0363] Channels 26 and 27 are formed in the surface portion of the main body region 20 in the region between the semiconductor region 6 and the impurity regions 23 and 24; and

[0364] An insulating film 31, which covers the channels 26 and 27 on the main surface 3, is sandwiched between the gate electrode 32 and the channels 26 and 27.

[0365] The impurity regions 23 and 24 are exposed at least from the platform side 44, the flat contact portion 42 and the second flat contact portion 48, and are connected to the surface electrode 95.

[0366] [Appendix 1-12] In the semiconductor device 1 according to Appendix 1-11, wherein,

[0367] The tabletop contact portion 41 includes a first contact portion 40, which includes: a main body protrusion 37 formed from a portion of the main body region 20, facing the upper part of the tabletop 43 through the side of the impurity regions 23, 24; a second conductive main body contact region 25 connected to the main body protrusion 37 on the upper part of the tabletop 43; and the impurity regions 23, 24 formed around the main body protrusion 37 and exposed from the side of the tabletop 44.

[0368] [Appendix 1-13] In the semiconductor device 1 according to Appendix 1-12, wherein,

[0369] The tabletop contact portion 41 further includes a second contact portion 50, which is formed entirely by the impurity regions 23 and 24 from the upper part of the tabletop 43 and throughout the thickness direction. The impurity regions 23 and 24 are exposed from both the upper part of the tabletop 43 and the side part of the tabletop 44.

[0370] [Appendix 1-14] In the semiconductor device 1 according to Appendix 1-13, wherein,

[0371] The first contact portion 40 and the second contact portion 50 are formed separately from each other along the stripe direction of the gate electrode 32.

[0372] [Appendix 1-15] In the semiconductor device 1 according to any one of Appendix 1-11, wherein,

[0373] The tabletop contact portion 41 includes:

[0374] The second contact portion 50, which is formed entirely by the impurity regions 23 and 24 along the thickness direction from the upper part 43 of the platform, is exposed from both the upper part 43 and the side part 44 of the platform; and

[0375] The third contact portion 84 is formed integrally from the upper part 43 of the table surface in the thickness direction, and is connected to the main body region 20 at the lower part of the table surface contact portion 41. It is formed by the second conductive type main body contact region 25 exposed from both the upper part 43 of the table surface and the side part 44 of the table surface.

[0376] [Appendix 1-16] According to the semiconductor device 1 described in Appendix 1-15, wherein,

[0377] The second contact portion 50 and the third contact portion 84 are formed separately from each other along the stripe direction of the gate electrode 32.

[0378] [Appendix 1-17] The semiconductor device 1 according to any one of Appendices 1-1 to 1-16, wherein,

[0379] The chip 2 is a SiC chip 2.

[0380] Symbol Explanation

[0381] 1—Semiconductor device; 2—Chip; 3—First main surface; 4—Second main surface; 5A—First side surface; 5B—Second side surface; 5C—Third side surface; 5D—Fourth side surface; 6—First semiconductor region; 7—Second semiconductor region; 8—Active region; 9—Outer peripheral region; 20—Main body region; 21—Outer main body region; 22—Surface drift region; 23—First source region; 24—Second source region; 25—Contact region; 26—First channel region; 27—Second channel region; 28—Source planar portion; 29—Source vertical portion; 30—Gate structure; 31—Insulating film; 32—Gate electrode; 33—Electrode surface; 34—First sidewall; 35—Second sidewall; 36—First contact portion 37—Main body protrusion, 38—Boundary surface, 39—Gap, 40—Contact portion, 41—Mesa contact portion, 42—Flat contact portion, 43—Upper mesa, 43B—Mesa side portion, 44—Mesa side portion, 44A—First mesa side portion, 44B—Second mesa side portion, 45—Termination region, 46—Overlap region, 47—Field region, 48—Second flat contact portion, 50—Second contact portion, 51—Outer peripheral insulating film, 52—Gate wiring, 53—Wiring surface, 54—First wiring sidewall, 55—Second wiring sidewall, 56—Source region, 70—Interlayer film, 71—Insulating surface, 72—First oxide film, 73—Second oxide film, 74—First cover portion, 75—Second cover portion, 7 6—Third cover portion, 77—First wiring cover portion, 78—Second wiring cover portion, 79—Third wiring cover portion, 80—First upper cover portion, 81—Second upper cover portion, 82—First upper wiring cover portion, 83—Second upper wiring cover portion, 84—Third contact portion, 85—Base base, 86—Lead-out portion, 87—Boundary surface, 90—Source opening, 92—Outer opening, 93—Outer recess, 94—Gate opening, 95—Source pad electrode, 96—First pad portion, 97—Second pad portion, 98—Third pad portion, 100—First substrate electrode film, 102—First main electrode film, 103—First electrode film, 104—Second electrode film, 110—Source finger electrode, 115—Gate 120—Second base electrode film, 122—Second main electrode film, 123—First electrode film, 124—Second electrode film, 130—Gate pad electrode, 140—Drain pad electrode, 150—Wafer, 151—First wafer main surface, 152—Second wafer main surface, 153—Wafer side surface, 154—Mark, 155—Device area, 156—Pre-cut line, 160—Base insulating film, 161—Base electrode, 162—Base electrode surface, 165—Mask, 166—Opening, 167—Mask, 168—Mask, 169—Opening, 174—Mask, 180—Mask, 181—Opening, X—First direction, Y—Second direction, Z—Vertical direction.

Claims

1. A semiconductor device, characterized in that, include: A chip has a main surface; A gate electrode is formed on the main surface; An interlayer film covering the gate electrode; An opening, which is formed separately from the gate electrode in the interlayer film in the transverse direction along the main surface, exposes a portion of the chip as a contact portion; as well as A surface electrode, formed on the interlayer film, is mechanically and electrically connected to the contact portion within the opening. The contact portion includes a tabletop contact portion, which protrudes from the main surface and has a tabletop side portion and a tabletop upper portion. The surface electrode covers the side portion of the platform and the upper portion of the platform.

2. The semiconductor device according to claim 1, characterized in that, It also includes a plurality of gate electrodes arranged at intervals on the main surface. The opening is divided into regions between the plurality of gate electrodes. The contact portion includes: the tabletop contact portion, which is formed separately from the two side walls of the opening toward the inward side; and the flat contact portion, which is formed by a portion of the main surface between the tabletop contact portion and the side walls of the opening.

3. The semiconductor device according to claim 2, characterized in that, The plurality of gate electrodes are formed in a stripe pattern. The mesa contact portion is formed in a stripe shape along the stripe direction of the gate electrode. The pair of flat contact portions sandwiching the tabletop contact portion are arranged side by side with the tabletop contact portion to form a stripe pattern.

4. The semiconductor device according to claim 2 or 3, characterized in that, Also includes: A semiconductor region of a first conductivity type is formed on the surface portion of the main surface; The main region of the second conductivity type is formed on the surface layer of the semiconductor region; A first conductivity type of impurity region is formed in the surface portion of the main body region; A channel, which is formed in the surface portion of the main region in the region between the semiconductor region and the impurity region; and An insulating film, which covers the channel on the main surface and is sandwiched between the gate electrode and the channel, The impurity region is exposed at least from the side of the platform and the flat contact portion, and is connected to the surface electrode.

5. The semiconductor device according to claim 4, characterized in that, The tabletop contact portion includes a first contact portion comprising: a main body protrusion formed from a portion of the main body region, extending toward the upper surface of the tabletop through the impurity region; a second conductive main body contact region connected to the main body protrusion on the upper surface of the tabletop; and the impurity region formed around the main body protrusion and exposed from the side of the tabletop.

6. The semiconductor device according to claim 5, characterized in that, The tabletop contact portion further includes a second contact portion, which is formed by the impurity region extending from the upper part of the tabletop throughout the thickness direction, and the impurity region is exposed from both the upper part of the tabletop and the side of the tabletop.

7. The semiconductor device according to claim 6, characterized in that, The first contact portion and the second contact portion are formed in a segmented manner along the stripe direction of the gate electrode.

8. The semiconductor device according to claim 4, characterized in that, The tabletop contact portion includes: The second contact portion, which extends from the upper part of the platform and is entirely formed by the impurity region along its thickness direction, is exposed from both the upper part of the platform and the side portion of the platform; and The third contact portion is formed integrally from the upper part of the table surface throughout the thickness direction, and is connected to the main body region at the lower part of the table surface contact portion. It is formed by the second conductive type main body contact region exposed from both the upper part of the table surface and the side part of the table surface.

9. The semiconductor device according to claim 8, characterized in that, The second contact portion and the third contact portion are formed in a segmented manner along the stripe direction of the table surface contact portion.

10. The semiconductor device according to claim 2, characterized in that, The plurality of gate electrodes are formed in a stripe pattern. The plurality of mesa contacts are arranged at intervals along the stripe direction of the gate electrode. The pair of flat contact portions sandwiching the tabletop contact portion are arranged side-by-side with the tabletop contact portion in a striped pattern. The contact portion further includes a second flat contact portion formed between adjacent plurality of platform contact portions.

11. The semiconductor device according to claim 10, characterized in that, Also includes: A semiconductor region of a first conductivity type is formed on the surface portion of the main surface; The main region of the second conductivity type is formed on the surface layer of the semiconductor region; A first conductivity type of impurity region is formed in the surface portion of the main body region; A channel is formed in the surface portion of the main region in the region between the semiconductor region and the impurity region; as well as An insulating film, which covers the channel on the main surface and is sandwiched between the gate electrode and the channel, The impurity region is exposed at least from the platform side, the flat contact portion, and the second flat contact portion, and is connected to the surface electrode.

12. The semiconductor device according to claim 11, characterized in that, The tabletop contact portion includes a first contact portion comprising: a main body protrusion formed from a portion of the main body region, extending toward the upper surface of the tabletop through the impurity region; a second conductive main body contact region connected to the main body protrusion on the upper surface of the tabletop; and the impurity region formed around the main body protrusion and exposed from the side of the tabletop.

13. The semiconductor device according to claim 12, characterized in that, The tabletop contact portion further includes a second contact portion, which is formed by the impurity region extending from the upper part of the tabletop throughout the thickness direction, and the impurity region is exposed from both the upper part of the tabletop and the side of the tabletop.

14. The semiconductor device according to claim 13, characterized in that, The first contact portion and the second contact portion are formed separately from each other along the stripe direction of the gate electrode.

15. The semiconductor device according to claim 11, characterized in that, The tabletop contact portion includes: The second contact portion, which extends from the upper part of the platform and is entirely formed by the impurity region along its thickness direction, is exposed from both the upper part of the platform and the side portion of the platform; and The third contact portion is formed integrally from the upper part of the table surface throughout the thickness direction, and is connected to the main body region at the lower part of the table surface contact portion. It is formed by the second conductive type main body contact region exposed from both the upper part of the table surface and the side part of the table surface.

16. The semiconductor device according to claim 15, characterized in that, The second contact portion and the third contact portion are formed separately from each other along the stripe direction of the gate electrode.

17. The semiconductor device according to any one of claims 1 to 16, characterized in that, The chip is a SiC chip.

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