Semiconductor device

Abstract

The semiconductor device includes a drift region of a first conductivity type formed inside a chip, and a plurality of FLRs formed on a surface layer portion of a first main surface so as to surround an active region in an outer peripheral region, each FLR having FLR curved portions having a curved shape in a plan view at four corners. Each FLR has a linear portion having a linear shape in plan view between four corners, and each FLR curve portion has a double diffusion structure including a first diffusion region on the inner side and a second diffusion region on the outer side having a lower impurity concentration of a second conductivity type than the first diffusion region.

Description

[0001] This application claims priority to Japan Patent Application No. 2023-056392, filed on March 30, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices. Background Technology

[0003] Patent Document 1 discloses a semiconductor device comprising an active region and an edge terminal region surrounding the active region. An IGBT and a bus diode are formed in the active region. Multiple guard rings (field limiting rings (FLRs)) and field plate electrodes (FLR electrodes) are formed in the edge terminal region, each disposed on and electrically connected to the corresponding guard ring.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2022-882 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] The purpose of this disclosure is to provide a semiconductor device capable of increasing the insulation breakdown voltage at the corner of the curved portion of the FLR in the peripheral region.

[0009] Solution for solving the problem

[0010] One embodiment of the present invention provides a semiconductor device comprising: a chip having a first main surface of quadrilateral shape in plan view and a second main surface opposite thereto; an active region disposed on the first main surface and having a component structure thereon; an outer peripheral region, which is a region outside the active region, disposed on the outer periphery of the first main surface and having four corners; a drift region of a first conductivity type formed inside the chip; and a plurality of field limiting rings (hereinafter referred to as "FLRs") of a second conductivity type formed on the surface portion of the first main surface in the outer peripheral region in a manner surrounding the active region, each FLR having a curved portion of curvature shape in plan view at each of the four corners, and a straight portion of curvature shape in plan view between the four corners, each curved portion of FLR having a double diffusion structure including an inner first diffusion region and an outer second diffusion region of a second conductivity type having a lower impurity concentration than the first diffusion region.

[0011] This structure can improve the insulation breakdown voltage at the corners of the curved portion of the FLR in the outer peripheral region.

[0012] The above-described or other objects, features, and effects become clear from the embodiments described with reference to the accompanying drawings. Attached Figure Description

[0013] Figure 1 This is a top view showing one embodiment of a semiconductor device.

[0014] Figure 2 This is a top view showing the layout of the first main surface.

[0015] Figure 3 It is an enlarged top view showing the active region and the outer perimeter region.

[0016] Figure 4 It is along Figure 3 The cross-sectional view of line IV-IV shown.

[0017] Figure 5 It is along Figure 3 The cross-sectional view of the VV line shown.

[0018] Figure 6 It is along Figure 3 The sectional view along line VI-VI is shown.

[0019] Figure 7 It is an enlarged top view representing the active region and the boundary region.

[0020] Figure 8 It is along Figure 7 The cross-sectional view of line VIII-VIII shown.

[0021] Figure 9 It is along Figure 7 The cross-sectional view of the IX-IX line shown.

[0022] Figure 10A It is along Figure 1 The cross-sectional view of line XA-XA shown.

[0023] Figure 10B It is along Figure 1 The cross-sectional view of the XB-XB line shown.

[0024] Figure 10C This is a cross-sectional view showing a modified example of the FLR curve portion, and is related to... Figure 10B The sectional view corresponding to the sectional view.

[0025] Figure 11 This is a magnified top view showing the pad area.

[0026] Figure 12 It means Figure 11 An enlarged top view of the gate resistor structure shown.

[0027] Figure 13 It means Figure 12 An enlarged top view of the interior of the gate resistor structure shown.

[0028] Figure 14 It means Figure 12 An enlarged top view of one end of the gate resistor structure shown.

[0029] Figure 15 It means Figure 12 An enlarged top view of the other end of the gate resistor structure shown.

[0030] Figure 16 It is along Figure 13 The cross-sectional view of the XVI-XVI line shown.

[0031] Figure 17 It is along Figure 13 A cross-sectional view of line XVII-XVII shown.

[0032] Figure 18 It is along Figure 13 The cross-sectional view of line XVIII-XVIII shown.

[0033] Figure 19 It is along Figure 13 The cross-sectional view of the XIX-XIX line shown.

[0034] Figure 20 It is along Figure 14 The sectional view shown is along line XX-XX.

[0035] Figure 21 It is along Figure 15 The cross-sectional view of the XXI-XXI line shown.

[0036] Figure 22 It is along Figure 12 The sectional view of line XXII-XXII shown.

[0037] Figure 23 It is a top view showing the layout of the resistive film, gate electrode film, and gate wiring film.

[0038] Figure 24 It is a circuit diagram that shows the gate resistor structure, gate terminal electrode, and gate wiring electrode.

[0039] Figure 25 It is a schematic top view used to illustrate a modified example of the FLR, FLR electrode, and FLR connection electrode, and is a schematic top view that mainly shows the structure of the second corner of the outer peripheral region.

[0040] Figure 26 It is along Figure 25The diagram shows a cross-sectional view of the XXVI-XXVI line.

[0041] Figure 27 It is used for explanation Figure 25 A top view illustrating a variation of the FLR curve portion.

[0042] Figure 28 It is a schematic top view used to illustrate other variations of the FLR, FLR electrode, and FLR connecting electrode, and is a schematic top view that mainly shows the structure of the second corner of the outer peripheral region.

[0043] Figure 29 It is used for explanation Figure 28 A top view illustrating a variation of the FLR curve portion.

[0044] Figure 30A This is a schematic top view showing the structure of the first corner in another variation of the FLR, FLR electrode, and FLR connecting electrode.

[0045] Figure 30B It means and Figure 30A A schematic top view of the structure of the second corner in the same variant example.

[0046] Figure 30C It means and Figure 30A A schematic top view of the structure of the third corner in the same variant example.

[0047] Figure 30D It means and Figure 30A A schematic top view of the structure of the fourth corner in the same variant example.

[0048] Figure 31 It is along Figure 30B A graphical sectional view of the XXXI-XXXI line shown.

[0049] Figure 32 It is used for explanation Figure 30B A top view illustrating a variation of the FLR curve portion. Detailed Implementation

[0050] The embodiments will now be described in detail with reference to the accompanying drawings. The drawings are schematic diagrams and not strictly illustrative; scales and other dimensions may vary. Furthermore, corresponding structures in the drawings will be labeled with the same reference numerals, and repeated descriptions will be omitted or simplified. For structures whose descriptions have been omitted or simplified, the description preceding the omission or simplification will apply.

[0051] When the description of a comparison target uses the phrase "substantially equal," this phrase includes not only the numerical value (shape) that is equal to the numerical value (shape) of the comparison target, but also a numerical error (shape error) within a range of ±10% based on the numerical value (shape) of the comparison target. In the implementation, terms such as "first," "second," and "third" are used, but these are notations assigned to the names of each structure to clarify the order of description, and are not assigned with the intention of defining the meaning of each structure's name.

[0052] Figure 1 This is a top view showing the semiconductor device 1A according to the first embodiment. Figure 2 This is a top view showing the layout of the first main surface 3. Figure 3 This is an enlarged top view showing the active region 6 and the outer peripheral region 9. Figure 4 It is along Figure 3 The cross-sectional view of line IV-IV shown. Figure 5 It is along Figure 3 The cross-sectional view of the VV line shown.

[0053] Figure 6 It is along Figure 3 The sectional view along line VI-VI is shown. Figure 7 This is an enlarged top view showing the active region 6 and the boundary region 8. Figure 8 It is along Figure 7 The cross-sectional view of line VIII-VIII shown. Figure 9 It is along Figure 7 The cross-sectional view of the IX-IX line shown. Figure 10A It is along Figure 1 The cross-sectional view of line XA-XA shown. Figure 10B It is along Figure 1 The cross-sectional view of the XB-XB line shown.

[0054] Semiconductor device 1A is an IGBT semiconductor device equipped with an IGBT (Insulated Gate Bipolar Transistor). (Refer to...) Figures 1 to 10B The semiconductor device 1A includes a chip 2 with a hexahedral shape (specifically a cuboid shape). The chip 2 may also be referred to as a "semiconductor chip". In this embodiment, the chip 2 has a single-layer structure made of a monocrystalline silicon substrate (semiconductor substrate).

[0055] Chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are quadrilaterals when viewed from above (hereinafter referred to as "top view") from their normal direction Z. The normal direction Z is also the thickness direction of chip 2. The first main surface 3 has a quadrilateral shape when viewed from above.

[0056] The first side surface 5A and the second side surface 5B extend along the first main surface 3 in a first direction X and are opposite each other along the first main surface 3 in a second direction Y that intersects the first direction X. Specifically, the second direction Y is orthogonal to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and are opposite each other in the first direction X.

[0057] Semiconductor device 1A includes a plurality of active regions 6 spaced apart on a first main surface 3. The plurality of active regions 6 includes a first active region 6A and a second active region 6B. The first active region 6A is located on the side of a first side surface 5A relative to a straight line that crosses the center of the first main surface 3 in a first direction X. The second active region 6B is located on the side of a second side surface 5B relative to a straight line that crosses the center of the first main surface 3 in the first direction X. In this embodiment, each active region 6 is formed as a polygon with four sides parallel to the periphery of the chip 2 when viewed from above. The planar shape of each active region 6 is arbitrary.

[0058] A device structure is formed in the active region 6. In this embodiment, the device structure includes an IGBT structure Tr (transistor structure). The device structure may also include transistors other than IGBTs. As shown in Japanese Patent Application Publication No. 2022-882, the device structure may also include an IGBT structure and a freewheeling diode (FWD) structure connected in reverse parallel with the IGBT structure.

[0059] Semiconductor device 1A includes an active region 7 disposed in a first main surface 3 outside a plurality of active regions 6. The active region 7 includes a boundary region 8 and an outer peripheral region 9. The boundary region 8 is disposed in a strip shape extending along a first direction X in the region between the first active region 6A and the second active region 6B. In this embodiment, the boundary region 8 is located on a straight line that crosses the center of the first main surface 3 in the first direction X.

[0060] Boundary region 8 includes a pad region 10 with a relatively large width in the second direction Y, and a channel region 11 with a width smaller than that of the pad region 10 in the second direction Y. The pad region 10 may also be referred to as the "first boundary region" or "wide region". The channel region 11 may also be referred to as the "second boundary region", "line region" or "narrow region".

[0061] The pad region 10 is located on one side (the third side surface 5C side) in the first direction X. In this embodiment, the pad region 10, viewed from above, is situated on a straight line running through the center of the first main surface 3 in the first direction X, and is quadrilateral near the center of the third side surface 5C. The channel region 11 is located on the other side (the fourth side surface 5D side) in the first direction X, opposite to the pad region 10. In this embodiment, the channel region 11 extends in a strip shape from the pad region 10 toward the fourth side surface 5D, and is situated on a straight line running through the center of the first main surface 3 in the first direction X.

[0062] The outer peripheral region 9 is disposed on the periphery of the chip 2 in such a way that it surrounds multiple active regions 6. The outer peripheral region 9 is configured as a ring (in this embodiment, a four-sided ring) extending along the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). The outer peripheral region 9 is connected to the pad region 10 on one side of the first main surface 3 (third side surface 5C side) and to the channel region 11 on the other side of the first main surface 3 (fourth side surface 5D side).

[0063] The outer peripheral region 9 has four corners 201, 202, 203, and 204. Corner 201 is the corner sandwiched between the first side surface 5A and the third side surface 5C when viewed from above (hereinafter referred to as "first corner 201"). Corner 202 is the corner sandwiched between the first side surface 5A and the fourth side surface 5D when viewed from above (hereinafter referred to as "second corner 202").

[0064] Corner 203 is the corner that is sandwiched between the fourth side 5D and the second side 5B when viewed from above (hereinafter referred to as "third corner 203"). Corner 204 is the corner that is sandwiched between the second side 5B and the third side 5C when viewed from above (hereinafter referred to as "fourth corner 204").

[0065] Semiconductor device 1A includes an n-type (first conductivity type) drift region 12 formed inside a chip 2. The drift region 12 is formed over the entire area inside the chip 2. In this embodiment, the chip 2 is constructed of an n-type semiconductor substrate (n-type semiconductor chip), and the drift region 12 is formed using the n-type chip 2.

[0066] Semiconductor device 1A includes an n-type buffer region 13 formed on the surface portion of a second main surface 4. In this embodiment, the buffer region 13 is formed as a layer extending along the second main surface 4 over the entire area of ​​the second main surface 4. The buffer region 13 has a higher n-type impurity concentration compared to the drift region 12. The presence or absence of the buffer region 13 is arbitrary, and it is also possible to use a configuration without the buffer region 13.

[0067] Semiconductor device 1A includes a p-type (second conductivity type) collector region 14 formed on the surface portion of a second main surface 4. The collector region 14 is formed on the surface portion of the buffer region 13 on the side of the second main surface 4. In this embodiment, the collector region 14 is formed as a layer extending along the second main surface 4 over the entire area of ​​the second main surface 4. The collector region 14 is exposed from a portion of the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0068] Semiconductor device 1A includes multiple trench separation structures 15 formed on a first main surface 3 in a manner that divides multiple active regions 6. A gate potential is applied to the multiple trench separation structures 15. The trench separation structures 15 may also be referred to as "trench gate separation structures" or "trench gate connection structures". The multiple trench separation structures 15 include a first trench separation structure 15A on the side of the first active region 6A and a second trench separation structure 15B on the side of the second active region 6B.

[0069] The first trench separation structure 15A surrounds the first active region 6A and defines the first active region 6A from the boundary region 8 and the outer peripheral region 9. In this embodiment, the first trench separation structure 15A is formed as a polygonal ring with four sides parallel to the periphery of the chip 2 when viewed from above. The first trench separation structure 15A has a portion that is curved in a manner that defines the pad region 10 and the channel region 11 of the boundary region 8 when viewed from above.

[0070] The second trench separation structure 15B surrounds the second active region 6B, defining the second active region 6B from the boundary region 8 and the outer peripheral region 9. In this embodiment, the second trench separation structure 15B is formed as a polygonal ring with four sides parallel to the periphery of the chip 2 when viewed from above. The second trench separation structure 15B has a portion that is curved in a manner that divides the pad region 10 and the channel region 11 of the boundary region 8 when viewed from above.

[0071] The trench separation structure 15 preferably has a width smaller than the width of the channel region 11. The width of the trench separation structure 15 is the width in a direction orthogonal to the direction in which it extends. The width of the trench separation structure 15 can be 0.1 μm or more and 2.5 μm or less. The width of the trench separation structure 15 is preferably 0.3 μm or more and 1 μm or less. The width of the trench separation structure 15 is preferably 0.4 μm or more and 0.7 μm or less. The trench separation structure 15 can have a depth of 1 μm or more and 20 μm or less. The depth of the trench separation structure 15 is preferably 4 μm or more and 10 μm or less.

[0072] The following describes the structure of a trench separation structure 15. The trench separation structure 15 includes a separation trench 16, a separation insulating film 17, and a separation embedded electrode 18. The separation trench 16 is formed on the first main surface 3, dividing the wall surface of the trench separation structure 15. The separation insulating film 17 covers the wall surface of the separation trench 16 in a film-like manner. The separation insulating film 17 may also include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.

[0073] The separation insulating film 17 preferably has a single-layer structure consisting of a single insulating film. Particularly preferably, the separation insulating film 17 comprises a silicon oxide film consisting of the oxide of the chip 2. The separation buried electrode 18 is buried in the separation trench 16 across the separation insulating film 17. The separation buried electrode 18 may comprise conductive polysilicon. A gate potential is applied to the separation buried electrode 18.

[0074] Semiconductor device 1A includes IGBT structures Tr (transistor structures) formed in each active region 6. The IGBT structures Tr are not formed in the non-active regions 7. The structure on the second active region 6B side (the structure of the IGBT structure Tr) is substantially the same as the structure on the first active region 6A side (the structure of the IGBT structure Tr), therefore, the structure on the first active region 6A side will be described below. In this embodiment, the structure on the second active region 6B side is symmetrical to the structure on the first active region 6A side across the boundary region 8. The description of the structure on the second active region 6B side will be omitted in connection with the description of the structure on the first active region 6A side.

[0075] In this embodiment, the n-type impurity concentration in the drift region 12 varies in a manner that gradually decreases from the surface on the first main surface 3 side of the drift region 12 to the surface on the second main surface 4 side. The n-type impurity concentration in the drift region 12 is preferably, for example, 1.0 × 10⁻⁶. 13 cm -3 Above and 1.0×10 15 cm -3 the following.

[0076] Semiconductor device 1A includes a p-type channel region 20 formed in the surface portion of the first main surface 3 within the first active region 6A. The channel region 20 may also be referred to as a "body region" or "substrate region." The channel region 20 is formed in the surface portion on the side of the first main surface 3 of the drift region 12. The channel region 20 extends in layers along the first main surface 3 and connects to the inner peripheral wall of the trench separation structure 15. The channel region 20 is formed shallower than the trench separation structure 15 and has a bottom located closer to the first main surface 3 than the bottom wall of the trench separation structure 15. The bottom of the channel region 20 is preferably located closer to the first main surface 3 than the middle of the depth range of the trench separation structure 15. The thickness of the channel region 20 can be approximately 1 μm.

[0077] Semiconductor device 1A includes a plurality of first trench structures 21 formed on a first main surface 3 in a first active region 6A. A gate potential is applied to the plurality of first trench structures 21. The first trench structures 21 may also be referred to as "trench gate structures". The plurality of first trench structures 21 penetrate the channel region 20 in a manner reaching the drift region 12. When viewed from above, the plurality of first trench structures 21 are arranged at intervals in a first direction X, and are respectively formed as stripes extending in a second direction Y. That is, the plurality of first trench structures 21 are arranged as stripes extending in the second direction Y.

[0078] Each first trench structure 21 has one end on the boundary region 8 and another end on the outer peripheral region 9 in the length direction (second direction Y). One end and the other end of the plurality of first trench structures 21 are mechanically and electrically connected to the trench separation structure 15. That is, the plurality of first trench structures 21 together with the trench separation structure 15 form a ladder-shaped trench structure. The connection between the first trench structure 21 and the trench separation structure 15 can be regarded as part of the trench separation structure 15 and / or part of the first trench structure 21.

[0079] The spacing between the plurality of first trench structures 21 is preferably less than the width of the channel region 11. The width of the first trench structure 21 is preferably less than the width of the channel region 11. The width of the first trench structure 21 is the width in a direction orthogonal to the direction in which the first trench structure 21 extends. The width of the first trench structure 21 can be 0.1 μm or more and 2.5 μm or less. The width of the first trench structure 21 is preferably 0.3 μm or more and 1 μm or less.

[0080] The width of the first trench structure 21 is particularly preferably 0.4 μm or more and 0.7 μm or less. The width of the first trench structure 21 is preferably approximately equal to the width of the trench separation structure 15. The first trench structure 21 may also have a depth of 1 μm or more and 20 μm or less. The depth of the first trench structure 21 is preferably 4 μm or more and 10 μm or less. The depth of the first trench structure 21 is preferably approximately equal to the depth of the trench separation structure 15.

[0081] The structure of a first trench structure 21 is described below. The first trench structure 21 includes a first trench 22, a first insulating film 23, and a first embedded electrode 24. The first trench 22 is formed on the first main surface 3, dividing the wall surface of the first trench structure 21. In this embodiment, the two ends of the first trench 22 communicate with the separation trench 16 in the second direction Y. Specifically, the sidewall of the first trench 22 communicates with the sidewall of the separation trench 16, and the bottom wall of the first trench 22 communicates with the bottom wall of the separation trench 16.

[0082] The first insulating film 23 covers the wall of the first trench 22 in a film-like manner. The first insulating film 23 may also include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. The first insulating film 23 preferably has a single-layer structure composed of a single insulating film.

[0083] The first insulating film 23 preferably comprises a silicon oxide film made of the oxide of the chip 2. In this embodiment, the first insulating film 23 is made of the same insulating film as the separation insulating film 17. The first insulating film 23 is connected to the separation insulating film 17 at the connection between the separation trench 16 and the first trench 22.

[0084] The first embedded electrode 24 is embedded in the first trench 22 through the first insulating film 23. The first embedded electrode 24 may also comprise conductive polysilicon. A gate potential is applied to the first embedded electrode 24. The first embedded electrode 24 is mechanically and electrically connected to the separated embedded electrode 18 at the connection between the separating trench 16 and the first trench 22.

[0085] Semiconductor device 1A includes a plurality of second trench structures 25 formed in the region between a plurality of adjacent first trench structures 21 on the first main surface 3 of a first active region 6A. The second trench structures 25 may also be referred to as "emitter trench structures". Each second trench structure 25 is formed at intervals from the plurality of first trench structures 21 in a first direction X when viewed from above, forming a quadrilateral ring extending in a second direction Y.

[0086] The width of the second trench structure 25 is preferably smaller than the width of the channel region 11. The width of the second trench structure 25 is the width in a direction orthogonal to the direction in which the second trench structure 25 extends. The width of the second trench structure 25 can be 0.1 μm or more and 2.5 μm or less. Preferably, the width of the second trench structure 25 is 0.3 μm or more and 1 μm or less.

[0087] The width of the second trench structure 25 is particularly preferably 0.4 μm or more and 0.7 μm or less. The width of the second trench structure 25 is preferably approximately equal to the width of the first trench structure 21. The second trench structure 25 may have a depth of 1 μm or more and 20 μm or less. The depth of the second trench structure 25 is preferably 4 μm or more and 10 μm or less. The depth of the second trench structure 25 is preferably approximately equal to the depth of the first trench structure 21.

[0088] The following describes the structure of a second trench structure 25. The second trench structure 25 includes a second trench 26, a second insulating film 27, and a second embedded electrode 28. The second trench 26 is formed on the first main surface 3, dividing the wall surface of the second trench structure 25.

[0089] The second insulating film 27 covers the walls of the second trench 26 in a film-like manner. The second insulating film 27 may also include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. The second insulating film 27 preferably has a single-layer structure composed of a single insulating film. The second insulating film 27 particularly preferably includes a silicon oxide film composed of the oxide of the chip 2. In this embodiment, the second insulating film 27 is composed of the same insulating film as the first insulating film 23.

[0090] The second embedded electrode 28 is embedded in the second trench 26 through the second insulating film 27. The second embedded electrode 28 may also comprise conductive polysilicon. An emitter potential is applied to the second embedded electrode 28.

[0091] Semiconductor device 1A includes a plurality of n-type emitter regions 29 formed in the surface portion of channel region 20 within a first active region 6A. Each of the plurality of emitter regions 29 has a higher n-type impurity concentration than the drift region 12. The plurality of emitter regions 29 are formed on both sides of a plurality of first trench structures 21. The n-type impurity concentration of the emitter regions 29 is preferably, for example, 1.0 × 10⁻⁶. 19 cm -3 Above and 1.0×10 21 cm -3 the following.

[0092] The plurality of emitter regions 29 are formed as strips extending along the plurality of first trench structures 21 when viewed from above. Alternatively, the plurality of emitter regions 29 may be formed spaced apart along the plurality of first trench structures 21 when viewed from above. In this embodiment, the plurality of emitter regions 29 are formed in the region between the first trench structure 21 and the second trench structure 25 in a manner connected to both the first trench structure 21 and the second trench structure 25. Preferably, the emitter regions 29 are not formed in the region between the trench separation structure 15 and the outermost second trench structure 25.

[0093] The semiconductor device 1A includes a plurality of contact holes 30 formed on a first main surface 3 such that an emitter region 29 is exposed in a first active region 6A. The plurality of contact holes 30 are formed at intervals on both sides of a plurality of first trench structures 21. The plurality of contact holes 30 may also be formed as a pointed shape in which the opening width narrows from the opening toward the bottom wall.

[0094] The plurality of contact holes 30 extend through the emitter region 29 to reach the channel region 20. The plurality of contact holes 30 may also be separated from the bottom of the emitter region 29 toward the first main surface 3 without reaching the channel region 20. In top view, the plurality of contact holes 30 are respectively formed as strips extending along the plurality of first trench structures 21. In the length direction (second direction Y), the plurality of contact holes 30 are preferably shorter than the plurality of first trench structures 21. The plurality of contact holes 30 are particularly preferably shorter than the plurality of second trench structures 25.

[0095] Semiconductor device 1A includes a plurality of p-type channel contact regions 31 formed on the surface of a channel region 20 in a first active region 6A in a region different from a plurality of emitter regions 29. The plurality of channel contact regions 31 have a higher p-type impurity concentration than the channel region 20. The plurality of channel contact regions 31 are each formed as a strip extending along a corresponding contact hole 30 when viewed from above. The bottom of each of the plurality of channel contact regions 31 is formed in the region between the bottom wall of the corresponding contact hole 30 and the bottom of the channel region 20.

[0096] The concentration of p-type impurities in channel region 20 is preferably, for example, 1.0 × 10⁻⁶. 16 cm -3 Above and 1.0×10 18 cm -3 The p-type impurity concentration in the channel contact region 31 is preferably, for example, 1.0 × 10⁻⁶. 18 cm -3 Above and 1.0×10 20 cm -3 the following.

[0097] Semiconductor device 1A includes a plurality of p-type floating regions 32 formed in the surface portion of the first main surface 3 of the first active region 6A, in a region surrounded by a plurality of second trench structures 25. The plurality of floating regions 32 are formed in an electrically floating state. Of course, an emitter potential may also be assigned to the plurality of floating regions 32. Preferably, the plurality of floating regions 32 have a higher p-type impurity concentration than the channel region 20.

[0098] Each floating region 32 extends in layers along the first main surface 3 and connects to the inner peripheral wall of each second trench structure 25. Preferably, each floating region 32 is formed deeper than the middle portion of the depth range of the second trench structure 25. In this embodiment, each floating region 32 is formed deeper than the second trench structure 25 and has a portion covering the bottom wall of the second trench structure 25.

[0099] Thus, the first active region 6A, as an IGBT structure Tr, includes a channel region 20, multiple first trench structures 21, multiple second trench structures 25, multiple emitter regions 29, multiple contact holes 30, multiple channel contact regions 31, and multiple floating regions 32. Similarly, the second active region 6B, like the first active region 6A, also serves as an IGBT structure Tr and includes a channel region 20, multiple first trench structures 21, multiple second trench structures 25, multiple emitter regions 29, multiple contact holes 30, multiple channel contact regions 31, and multiple floating regions 32.

[0100] Semiconductor device 1A includes a p-type boundary well region 40 formed in the surface portion of a first main surface 3 within a boundary region 8. In this embodiment, the boundary well region 40 has a higher p-type impurity concentration than the channel region 20. Of course, the boundary well region 40 may also have a lower p-type impurity concentration than the channel region 20.

[0101] The boundary well region 40, when viewed from above, is formed as a strip extending along the boundary region 8 in the first direction X. That is, the boundary well region 40 is formed as a layer extending along the first main surface 3 in the region sandwiched between the first trench separation structure 15A and the second trench separation structure 15B, and is exposed from the first main surface 3. The boundary well region 40 is formed in the region sandwiched between the plurality of first trench structures 21 on the side of the first active region 6A and the plurality of first trench structures 21 on the side of the second active region 6B.

[0102] The boundary well region 40 includes a first boundary well region 40A formed in the pad region 10 and a second boundary well region 40B formed in the channel region 11. The first boundary well region 40A has a relatively large region width in the second direction Y. The first boundary well region 40A is polygonal (quadrilateral in this embodiment) when viewed from above. The first boundary well region 40A is preferably formed over the entire area of ​​the pad region 10.

[0103] The second boundary well region 40B has a smaller region width in the second direction Y than the first boundary well region 40A, and extends in a strip shape from the first boundary well region 40A toward the channel region 11. In this embodiment, the second boundary well region 40B is located on a straight line that crosses the center of the first main surface 3 in the first direction X. The second boundary well region 40B extends in a strip shape relative to the region on one side (third side 5C side) and the other side (fourth side 5D side) of the straight line that crosses the center of the first main surface 3 in the second direction Y.

[0104] The boundary well region 40 is preferably formed deeper than the channel region 20. The boundary well region 40 is particularly preferably formed deeper than the plurality of trench separation structures 15 (the plurality of first trench structures 21). In this embodiment, the boundary well region 40 has a width in the second direction Y that is greater than the width of the boundary region 8, extending from the boundary region 8 into the plurality of active regions 6.

[0105] The boundary well region 40 is connected to a plurality of trench separation structures 15 adjacent in the second direction Y. The boundary well region 40 has a portion that covers the bottom wall of the plurality of trench separation structures 15. The boundary well region 40 also has a portion that traverses the plurality of trench separation structures 15 and covers the bottom wall of a plurality of first trench structures 21.

[0106] The boundary well region 40 covers the sidewalls of the trench separation structure 15 and the sidewalls of the multiple trench structures within the multiple active regions 6, and is connected to each channel region 20 on the surface of the first main surface 3. The depth of the boundary well region 40 can be more than 1 μm and less than 20 μm. Preferably, the depth of the boundary well region 40 is more than 5 μm and less than 10 μm.

[0107] Semiconductor device 1A includes a p-type peripheral well region 41 formed in the outer peripheral region 9 on the surface portion of the first main surface 3. In this embodiment, the peripheral well region 41 has a higher p-type impurity concentration than the channel region 20. Of course, the peripheral well region 41 may also have a lower p-type impurity concentration than the channel region 20. Preferably, the p-type impurity concentration of the peripheral well region 41 is approximately equal to the p-type impurity concentration of the boundary well region 40.

[0108] The peripheral well region 41 is formed in a layered shape extending along the first main surface 3 and exposed from the first main surface 3. The peripheral well region 41 is formed at intervals from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) inward. When viewed from above, the peripheral well region 41 is formed in a strip shape extending along the plurality of active regions 6. In this embodiment, the peripheral well region 41 is formed in a ring shape that surrounds the plurality of active regions 6 when viewed from above (in this embodiment, it is a four-sided ring).

[0109] The peripheral well region 41 is preferably formed to be deeper than the channel region 20. Particularly preferably, the peripheral well region 41 is formed to be deeper than the plurality of trench separation structures 15 (the plurality of first trench structures 21). The peripheral well region 41 preferably has a depth approximately equal to that of the boundary well region 40.

[0110] The peripheral well region 41 is connected to a plurality of trench separation structures 15. The peripheral well region 41 has a portion that covers the bottom wall of the plurality of trench separation structures 15. The peripheral well region 41 is led out from the peripheral region 9 into a plurality of active regions 6. The peripheral well region 41 has a portion that traverses the plurality of trench separation structures 15 and covers the bottom wall of a plurality of first trench structures 21.

[0111] The peripheral well region 41 covers the sidewalls of the trench separation structure 15 and the sidewalls of the multiple first trench structures 21 within each active region 6, and connects to the multiple channel regions 20 on the surface of the first main surface 3. The peripheral well region 41 connects to the boundary well region 40 at the junction of the boundary region 8 and the peripheral region 9. That is, the peripheral well region 41 and the boundary well region 40 together divide the multiple active regions 6.

[0112] Reference Figure 2 , Figure 10A and Figure 10B The semiconductor device 1A includes a plurality of p-type field limiting rings (FLRs) 42 formed in the outer peripheral region 9 on the surface portion of the first main surface 3. Hereinafter, the field limiting rings are referred to as FLRs 42. FLRs 42 are provided to mitigate the concentration of electric field at the outer end of the PN junction of the semiconductor device 1A. FLRs 42 can also be referred to as "protective rings".

[0113] The number of FLR42s is arbitrary, and can be more than 2 and less than 20 (typically more than 3 and less than 10). In this embodiment, four FLR42s are provided. The multiple FLR42s are configured to be in an electro-floating state.

[0114] Multiple FLRs 42 are formed spaced apart from the periphery of chip 2 and the outer peripheral well region 41 in the region between the periphery of chip 2 and the outer peripheral well region 41. The multiple FLRs 42 are formed as a strip extending along the outer peripheral well region 41 when viewed from above. In this embodiment, the multiple FLRs 42 are formed as a ring (quadrilateral ring) surrounding the outer peripheral well region 41 when viewed from above. Each of the multiple FLRs 42 has a width smaller than the width of the outer peripheral well region 41.

[0115] The multiple FLR42s are preferably formed deeper than the channel region 20. The multiple FLR42s may also be formed at a depth approximately equal to that of the peripheral well region 41. The multiple FLR42s may also be formed shallower than the peripheral well region 41. The multiple FLR2s may also be formed at a certain depth.

[0116] Each FLR 42 has an FLR curved portion 42A with a circular arc shape when viewed from top view at each of its four corners 201 to 204. In each corner 201 to 204, the inner edge 42Aa and outer edge 42Ab of all the FLR curved portions 42A may also have the same center of curvature. Each FLR 42 has a straight FLR portion 42B with a straight line shape when viewed from top view between its four corners 201 to 204.

[0117] Each FLR curve portion 42A has a dual diffusion structure including an inner first diffusion region 301 and an outer second diffusion region 302 with a lower p-type impurity concentration than the first diffusion region 301.

[0118] The inner edge 42Aa of each FLR curve portion 42A is the inner edge of the first diffusion region 301 of that FLR curve portion 42A. The outer edge 42Ab of each FLR curve portion 42A is the outer edge of the second diffusion region 302 of that FLR curve portion 42A. A boundary line (hereinafter referred to as "diffusion region boundary line BL") is formed at the midpoint of the width between the inner edge 42Aa and the outer edge 42Ab of the FLR curve portion 42A. The diffusion region boundary line BL constitutes the outer edge of the first diffusion region 301 and the inner edge of the second diffusion region 302.

[0119] Each FLR linear portion 42B has a single diffusion structure consisting only of diffusion regions having the same second conductivity type impurity concentration as the first diffusion region 301.

[0120] In this embodiment, the spacing between the plurality of FLR straight segments 42B is constant between the four corners 201 to 204, and the widths of the plurality of FLR straight segments 42B are the same. Similarly, the spacing between the plurality of FLR curved segments 42A is constant between the four corners 201 to 204, and the widths of the plurality of FLR curved segments 42A are the same. Furthermore, the first diffusion regions 301 of the plurality of FLR curved segments 42A have the same width as each other, and the second diffusion regions 302 of the plurality of FLR curved segments 42A have the same width as each other. Additionally, the width of the first diffusion region 301 of each FLR curved segment 42A is the same as the width of each FLR straight segment 42B.

[0121] In this embodiment, in each corner 201-204, the inner edge 42Aa and outer edge 42Ab of all FLR curve portions 42A have the same center of curvature. Furthermore, in each corner 201-204, the centers of curvature of the inner edge 42Aa and outer edge BL of the first diffusion region 301 and the inner edge BL and outer edge 42Ab of the second diffusion region 302 in each FLR curve portion 42A are located on the line that divides the apex of the corner into half, i.e., the dividing line.

[0122] Furthermore, the spacing between the multiple straight FLR portions 42B between the four corners 201-204 may not be constant. Also, the width of the multiple straight FLR portions 42B between the four corners 201-204 may be different. Furthermore, the spacing between the multiple curved FLR portions 42A between the four corners 201-204 may not be constant. Furthermore, the width of the multiple curved FLR portions 42A between the four corners 201-204 may be different. Furthermore, the width of the first diffusion regions 301 of the multiple curved FLR portions 42A may also be different from each other. Furthermore, the width of the second diffusion regions 302 of the multiple curved FLR portions 42A may also be different from each other.

[0123] Furthermore, in each corner 201-204, the inner edge 42Aa and outer edge 42Ab of all FLR curve portions 42A may not have the same center of curvature. Additionally, in each corner 201-204, the centers of curvature of the inner edge 42Aa and outer edge BL of the first diffusion region 301 and the inner edge BL and outer edge 42Ab of the second diffusion region 302 in each FLR curve portion 42A may not exist at the position on the line dividing the apex of the corner into half, i.e., the dividing line.

[0124] In this embodiment, in each corner portion 201-204, the width of the second diffusion region 302 within each FLR curve portion 42A is narrower than the width of the first diffusion region 301. Alternatively, the width of the second diffusion region 302 within each FLR curve portion 42A may be wider than the width of the first diffusion region 301. Alternatively, the width of the second diffusion region 302 within each FLR curve portion 42A may be the same as the width of the first diffusion region 301.

[0125] In this embodiment, in each corner portion 201-204, the depth of the second diffusion region 302 within each FLR curve portion 42A is the same as the depth of the first diffusion region 301. Alternatively, the depth of the second diffusion region 302 within each FLR curve portion 42A may differ from the depth of the first diffusion region 301. For example, as... Figure 10C As shown, the depth of the second diffusion region 302 within each FLR curve portion 42A can also be deeper than the depth of the first diffusion region 301.

[0126] In this embodiment, the FLR 42 is formed as a straight line when viewed from above in the region between corners 201 and 204, while it is formed as a curve when viewed from above in the same region. Therefore, in the outer peripheral region 9, the corners 201 to 204 where the FLR curve portion 42A is present are more prone to electric field concentration compared to the region between corners where the straight FLR portion 42B is present. Consequently, the insulation breakdown voltage (BV) at the corners 201 to 204 of the outer peripheral region 9 is lower than that in the region between corners of the outer peripheral region 9.

[0127] In this embodiment, the multiple FLR curve portions 42A of each corner 201-204 have a double diffusion structure including an inner first diffusion region 301 and an outer second diffusion region 302 with a lower p-type impurity concentration than the first diffusion region 301. This allows for a smooth equipotential surface at each corner 201-204, thereby mitigating electric field concentration at each corner 201-204. Consequently, the insulation breakdown voltage of the corners 201-204 can be increased.

[0128] Semiconductor device 1A includes a channel barrier region 43 formed at intervals on the surface portion of a first main surface 3 in an outer peripheral region 9, extending from a plurality of FLRs 42 toward the periphery of chip 2. The channel barrier region 43 has a higher n-type impurity concentration than the drift region 12. Such a channel barrier region 43 can be formed simultaneously with the emitter region 29, for example, in the process of forming the emitter region 29.

[0129] When viewed from above, the channel blocking region 43 is formed as a strip extending along the periphery of the chip 2. In this embodiment, the channel blocking region 43 is formed as a ring (quadrilateral ring) surrounding the plurality of FLRs 42 when viewed from above. The channel blocking region 43 may also be exposed from the first to fourth side surfaces 5A to 5D. The channel blocking region 43 is formed in an electrically floating state.

[0130] Semiconductor device 1A includes a main surface insulating film 45 that selectively covers a first main surface 3. The main surface insulating film 45 selectively covers the first main surface 3 in an active region 6, a boundary region 8, and a peripheral region 9. The main surface insulating film 45 may also include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.

[0131] The main insulating film 45 preferably has a single-layer structure composed of a single insulating film. The main insulating film 45 particularly preferably comprises a silicon oxide film composed of the oxide of the chip 2. In this embodiment, the main insulating film 45 is composed of the same insulating film as the first insulating film 23 (separation insulating film 17). The main insulating film 45 covers the first main surface 3 in such a way that the trench separation structure 15, the first trench structure 21, and the second trench structure 25 are exposed.

[0132] Specifically, the main insulating film 45 is connected to the separation insulating film 17, the first insulating film 23, and the second insulating film 27, exposing the separation buried electrode 18, the first buried electrode 24, and the second buried electrode 28. The main insulating film 45 selectively covers the boundary well region 40, the peripheral well region 41, the FLR 42, and the channel blocking region 43 in the boundary region 8 and the outer peripheral region 9.

[0133] Reference Figure 3 as well as Figure 5 The semiconductor device 1A includes a plurality of emitter electrode films 47 disposed on a first main surface 3 such that they cover a plurality of second trench structures 25 in an active region 6. Specifically, the plurality of emitter electrode films 47 are disposed on a main surface insulating film 45. The plurality of emitter electrode films 47 may also comprise conductive polycrystalline silicon.

[0134] Multiple emitter electrode films 47 respectively cover both ends of multiple second trench structures 25 in the second direction Y. In this embodiment, the multiple emitter electrode films 47 are formed as strips extending in the second direction Y in the region between the corresponding second trench structure 25 and the trench separation structure 15. The multiple emitter electrode films 47 are formed at intervals from the trench separation structure 15 toward the second trench structure 25. The multiple emitter electrode films 47 are opposed to the channel region 20 through the main surface insulating film 45.

[0135] Multiple emitter electrode films 47 are integrally formed with the second embedded electrodes 28 of the multiple second trench structures 25. That is, the multiple emitter electrode films 47 are each formed by a portion of the second embedded electrode 28 extending out in a film shape on the first main surface 3 (main surface insulating film 45). Of course, the multiple emitter electrode films 47 can also be formed separately from the second embedded electrodes 28.

[0136] Figure 11 This is an enlarged top view of pad area 10. Figure 12 It means Figure 11 An enlarged top view of the gate resistor structure 50 shown. Figure 13 It means Figure 12 An enlarged top view of the interior of the gate resistor structure 50 shown. Figure 14 It means Figure 12 An enlarged top view of one end of the gate resistor structure 50 shown. Figure 15 It means Figure 12 An enlarged top view of the other end of the gate resistor structure 50 shown.

[0137] Figure 16 It is along Figure 13 The cross-sectional view of the XVI-XVI line shown. Figure 17 It is along Figure 13A cross-sectional view of line XVII-XVII shown. Figure 18 It is along Figure 13 The cross-sectional view of line XVIII-XVIII shown. Figure 19 It is along Figure 13 The cross-sectional view of the XIX-XIX line shown. Figure 20 It is along Figure 14 The sectional view shown is along line XX-XX.

[0138] Figure 21 It is along Figure 15 The cross-sectional view of the XXI-XXI line shown. Figure 22 It is along Figure 12 The sectional view of line XXII-XXII shown. Figure 23 This is a top view showing the layout of the resistive film 60, the gate electrode film 64, and the gate wiring film 65. Figure 24 This is a circuit diagram showing the gate resistor structure 50, the gate terminal electrode 90, and the gate wiring electrode 93.

[0139] Reference Figures 11-24 Semiconductor device 1A includes a gate resistor structure 50 formed in pad region 10. The gate resistor structure 50 constitutes a gate resistor RG relative to the gate of the IGBT (the first trench structure 21 of the IGBT structure Tr). The gate resistor structure 50 includes a plurality of trench resistor structures 51 formed in the pad region 10 on the first main surface 3. A gate potential is assigned to the plurality of trench resistor structures 51, but the plurality of trench resistor structures 51 do not contribute to channel control.

[0140] In this embodiment, a plurality of gate resistor structures 50 constitute a first trench group 52 and a second trench group 53. The first trench group 52 includes a plurality of first trench resistor structures 51A that form part of the plurality of trench resistor structures 51, and is disposed on one side (first side 5A side) in the second direction Y. The number of first trench resistor structures 51A is arbitrary and is adjusted based on the resistance value to be achieved.

[0141] For example, the first trench group 52 may also include two or more but less than 100 first trench resistor structures 51A. The number of first trench resistor structures 51A is preferably 50 or less. The number of first trench resistor structures 51A may also be 25 or less. The number of first trench resistor structures 51A is preferably 5 or more. Of course, the gate resistor structure 50 may also include a single first trench resistor structure 51A instead of the first trench group 52.

[0142] In this embodiment, the first trench group 52 is disposed on one side (first side surface 5A) of the second direction Y, relative to a straight line that crosses the center of the first main surface 3 in the first direction X. The first trench group 52 is preferably arranged in the pad region 10 such that it is biased towards the active region 6 (channel region 11 side) than the outer peripheral region 9. In this embodiment, the first trench group 52 is arranged at intervals from the center of the pad region 10 towards the active region 6 (channel region 11 side). These structures are effective in suppressing electric field concentration relative to the plurality of first trench resistor structures 51A.

[0143] Multiple first trench resistor structures 51A are formed on the first main surface 3 at intervals from multiple trench separation structures 15 (multiple first trench structures 21). When viewed from above, the multiple first trench resistor structures 51A are arranged at intervals in the first direction X, and are respectively formed as strips extending in the second direction Y. That is, the multiple first trench resistor structures 51A are arranged in a stripe-like pattern extending in the second direction Y. Each multiple first trench resistor structure 51A has one end on one side of the second direction Y (the first side surface 5A side) and another end on the other side of the second direction Y (the second side surface 5B side).

[0144] Multiple first trench resistor structures 51A are formed spaced apart from the bottom of the boundary well region 40 (first boundary well region 40A) toward the first main surface 3, located within the boundary well region 40 (first boundary well region 40A), and are opposed to the drift region 12 across a portion of the boundary well region 40. That is, the multiple first trench resistor structures 51A do not penetrate the boundary well region 40 (first boundary well region 40A).

[0145] The spacing between the plurality of first trench resistor structures 51A is preferably less than the width of the channel region 11. The spacing between the plurality of first trench resistor structures 51A is preferably approximately equal to the spacing between the first trench structure 21 and the second trench structure 25. The spacing between the plurality of first trench resistor structures 51A may also be smaller than the spacing between the first trench structure 21 and the second trench structure 25. The spacing between the plurality of first trench resistor structures 51A may also be larger than the spacing between the first trench structure 21 and the second trench structure 25.

[0146] The width of the first trench resistor structure 51A is preferably smaller than the width of the channel region 11. The width of the first trench resistor structure 51A is the width in a direction orthogonal to the direction in which the first trench resistor structure 51A extends. The width of the first trench resistor structure 51A may also be 0.1 μm or more and 2.5 μm or less. The width of the first trench resistor structure 51A is preferably 0.3 μm or more and 1 μm or less.

[0147] The width of the first trench resistor structure 51A is particularly preferably 0.4 μm or more and 0.7 μm or less. The width of the first trench resistor structure 51A is preferably approximately equal to the width of the first trench structure 21. The first trench resistor structure 51A may also have a depth of 1 μm or more and 20 μm or less. The depth of the first trench resistor structure 51A is preferably 4 μm or more and 10 μm or less. The depth of the first trench resistor structure 51A is preferably approximately equal to the depth of the first trench structure 21.

[0148] The second trench group 53 includes a plurality of second trench resistor structures 51B that form part of a plurality of trench resistor structures 51, and are spaced apart from the first trench group 52 toward the other side (second side surface 5B side) in the second direction Y. The number of second trench resistor structures 51B is arbitrary and is adjusted based on the resistance value to be achieved. For example, in order to achieve a resistance value that is approximately equal to the resistance value on the first trench group 52 side, the second trench group 53 may also include the same number of second trench resistor structures 51B as the number of first trench resistor structures 51A.

[0149] For example, when achieving a resistance value different from that on the first trench group 52 side, the second trench group 53 may also include a different number of second trench resistor structures 51B than the number of first trench resistor structures 51A. For example, when the resistance value on the second trench group 53 side is larger than the resistance value on the first trench group 52 side, the number of second trench resistor structures 51B may be less than the number of first trench resistor structures 51A. For example, when the resistance value on the second trench group 53 side is smaller than the resistance value on the first trench group 52 side, the number of second trench resistor structures 51B may be more than the number of first trench resistor structures 51A.

[0150] For example, the second trench group 53 may also include two or more but less than 100 second trench resistor structures 51B. The number of second trench resistor structures 51B is preferably 50 or less. The number of second trench resistor structures 51B may also be 25 or less. The number of second trench resistor structures 51B is preferably 5 or more. Of course, the semiconductor device 1A may also include a single second trench resistor structure 51B instead of the second trench group 53.

[0151] In this embodiment, the second trench group 53 is disposed on the other side (second side surface 5B) of the second direction Y, relative to a straight line that crosses the center of the first main surface 3 in the first direction X. The second trench group 53 is opposite to the first trench group 52 in the second direction Y. The second trench group 53 is preferably arranged in the pad region 10 in a manner that it is biased towards the active region 6 (channel region 11 side) than the outer peripheral region 9. In this embodiment, the second trench group 53 is arranged at intervals from the center of the pad region 10 toward the active region 6 (channel region 11 side). These structures are effective in suppressing electric field concentration relative to the plurality of second trench resistor structures 52B.

[0152] Multiple second trench resistor structures 51B are formed on the first main surface 3 at intervals from multiple trench separation structures 15 (multiple first trench structures 21). When viewed from above, the multiple second trench resistor structures 51B are arranged at intervals in the first direction X, and are respectively formed as strips extending in the second direction Y.

[0153] That is, the plurality of second trench resistor structures 51B are arranged in a stripe-like pattern extending in the second direction Y. The plurality of second trench resistor structures 51B are respectively positioned in a one-to-one correspondence with the plurality of first trench resistor structures 51A in the second direction Y. That is, the plurality of second trench resistor structures 51B and the plurality of first trench resistor structures 51A are respectively configured in the same straight line. The plurality of second trench resistor structures 51B have one end on one side of the second direction Y (the first side 5A side) and another end on the other side of the second direction Y (the second side 5B side).

[0154] Multiple second trench resistor structures 51B are formed spaced apart from the bottom of the boundary well region 40 (first boundary well region 40A) toward the first main surface 3, located within the boundary well region 40 (first boundary well region 40A), and are opposed to the drift region 12 across a portion of the boundary well region 40. That is, the multiple second trench resistor structures 51B do not penetrate the boundary well region 40 (first boundary well region 40A).

[0155] The spacing between the plurality of second trench resistor structures 51B is preferably less than the width of the channel region 11. The spacing between the plurality of second trench resistor structures 51B is preferably approximately equal to the spacing between adjacent first trench structures 21 and second trench structures 25. The spacing between the plurality of second trench resistor structures 51B may also be smaller than the spacing between the first trench structures 21 and second trench structures 25. Alternatively, the spacing between the plurality of second trench resistor structures 51B may be larger than the spacing between the first trench structures 21 and second trench structures 25.

[0156] The spacing between the plurality of second trench resistor structures 51B can also be smaller than the spacing between the plurality of first trench resistor structures 51A. The spacing between the plurality of second trench resistor structures 51B can also be larger than the spacing between the plurality of first trench resistor structures 51A. Preferably, the spacing between the plurality of second trench resistor structures 51B is approximately equal to the spacing between the plurality of first trench resistor structures 51A.

[0157] The width of the second trench resistor structure 51B is preferably smaller than the width of the channel region 11. The width of the second trench resistor structure 51B is the width in a direction orthogonal to the direction in which it extends. The width of the second trench resistor structure 51B can also be 0.1 μm or more and 2.5 μm or less. The width of the second trench resistor structure 51B is preferably 0.3 μm or more and 1 μm or less. The width of the second trench resistor structure 51B is particularly preferably 0.4 μm or more and 0.7 μm or less. The width of the second trench resistor structure 51B is preferably approximately equal to the width of the first trench resistor structure 51A.

[0158] In this embodiment, the second trench resistor structure 51B has a length in the second direction Y that is approximately equal to the length of the first trench resistor structure 51A. Of course, the second trench resistor structure 51B may also be longer than the first trench resistor structure 51A in the second direction Y. Alternatively, the second trench resistor structure 51B may be shorter than the first trench resistor structure 51A in the second direction Y. The lengths of the first trench resistor structure 51A and the second trench resistor structure 51B are adjusted according to the desired resistance value.

[0159] The second trench resistor structure 51B may also have a depth of 1 μm or more and 20 μm or less. The depth of the second trench resistor structure 51B is preferably 4 μm or more and 10 μm or less. The depth of the second trench resistor structure 51B is preferably approximately equal to the depth of the first trench resistor structure 51A (first trench structure 21).

[0160] The following describes the structure of a trench resistor structure 51 (a first trench resistor structure 51A and a second trench resistor structure 51B). The trench resistor structure 51 includes a resistor trench 54, a resistor insulating film 55, and a resistor embedded electrode 56. The resistor trench 54 is formed on the first main surface 3, dividing the wall of the trench resistor structure 51.

[0161] A resistive insulating film 55 covers the walls of the resistive trench 54 in a film-like form. The resistive insulating film 55 is connected to the main surface insulating film 45 on the first main surface 3. The resistive insulating film 55 may also include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. The resistive insulating film 55 preferably has a single-layer structure composed of a single insulating film. The resistive insulating film 55 particularly preferably includes a silicon oxide film composed of the oxide of the chip 2.

[0162] The buried resistor electrode 56 is embedded in the resistor trench 54 through a resistive insulating film 55. The buried resistor electrode 56 may comprise conductive polysilicon. A gate potential is applied to the buried resistor electrode 56.

[0163] In this embodiment, the gate resistor structure 50 includes a spacing region 57 that is divided in the pad region 10 between the first trench group 52 and the second trench group 53. The spacing region 57 between the other ends of the plurality of first trench resistor structures 51A and one end of the plurality of second trench resistor structures 51B is formed by a flat portion of the first main surface 3.

[0164] In this embodiment, the partition region 57 is divided into a quadrilateral shape when viewed from above. The partition region 57 exposes the boundary trap region 40 from the first main surface 3. In this embodiment, the partition region 57 is formed on a straight line that runs through the center of the first main surface 3 in the first direction X when viewed from above, and is opposite to the channel region 11 in the first direction X.

[0165] The spacing region 57 has a spacing width along the second direction Y. The spacing width is larger than the width of the first trench resistor structure 51A (second trench resistor structure 51B) in the first direction X. The spacing width is larger than the spacing between two adjacent first trench resistor structures 51A (second trench resistor structures 51B) in the first direction X. The spacing width is preferably larger than the width of the first trench group 52 (second trench group 53) in the first direction X. The spacing width may also be smaller than the width of the first trench group 52 (second trench group 53) in the first direction X.

[0166] The spacing width is preferably smaller than the length of the second direction Y of the first trench group 52 (second trench group 53). The spacing width can also be approximately equal to the width of the second direction Y of the channel region 11. The spacing width can also be greater than the width of the second direction Y of the channel region 11. The spacing width can also be less than the width of the second direction Y of the channel region 11.

[0167] The gate resistor structure 50 includes a resistive film 60 disposed on the first main surface 3 in such a way as to cover a plurality of trench resistor structures 51 in the pad region 10. Specifically, the resistive film 60 is disposed on the main surface insulating film 45. The resistive film 60 includes at least one of a conductive polycrystalline silicon film and an alloy film.

[0168] The alloy film may comprise an alloy crystal composed of metallic and non-metallic elements. The alloy film may include at least one of CrSi, CrSiN, CrSiO, TaN, and TiN films. In this embodiment, the resistive film 60 comprises conductive polycrystalline silicon.

[0169] The thickness of the resistive film 60 is appropriately adjusted according to the desired resistance value. The thickness of the resistive film 60 is preferably less than the depth of the first trench resistor structure 51A (second trench resistor structure 51B). Particularly preferably, the thickness of the resistive film 60 is less than the depth of the first trench resistor structure 51A (second trench resistor structure 51B).

[0170] The thickness of the resistive film 60 is preferably 0.5 times or more the width of the first trench resistor structure 51A (second trench resistor structure 51B). The thickness of the resistive film 60 can be 0.05 μm or more and 2.5 μm or less. The thickness of the resistive film 60 is preferably 0.5 μm or more and 1.5 μm or less. When the resistive film 60 is made of an alloy film, the thickness of the resistive film 60 can be 0.1 nm or more and 100 nm or less.

[0171] The resistive film 60 is formed as a strip extending along the second direction Y, having a first end 60A on one side of the second direction Y (first side surface 5A side) and a second end 60B on the other side of the second direction Y (second side surface 5B side). The resistive film 60 has a width in the first direction X that is larger than the width of the first trench group 52 (second trench group 53) in the first direction X. The width of the resistive film 60 can be smaller than the spacing width. Of course, the width of the resistive film 60 can also be greater than the spacing width. Preferably, the resistive film 60 has a uniform width in the first direction X.

[0172] The resistive film 60 has a portion located on one side (first side surface 5A side) and a portion located on the other side (second side surface 5B side) relative to a straight line that crosses the center of the first main surface 3 in the first direction X. The resistive film 60 is opposite to the first active region 6A, the second active region 6B, and the channel region 11 in the first direction X. That is, the resistive film 60 is opposite to a plurality of trench separation structures 15, a plurality of first trench structures 21, and a plurality of second trench structures 25 in the first direction X.

[0173] The resistive film 60 has a first covering portion 61 covering the interval region 57, a second covering portion 62 covering the first trench group 52, and a third covering portion 63 covering the second trench group 53. The first covering portion 61 is the portion covering the first main surface 3 in the region outside the first trench group 52 (a plurality of first trench resistor structures 51A) and the second trench group 53 (a plurality of second trench resistor structures 51B). The first covering portion 61 is located in the middle portion between the first end portion 60A and the second end portion 60B, and is opposite the boundary well region 40 in the thickness direction through the main surface insulating film 45.

[0174] The second cover portion 62 forms the first end portion 60A of the resistive film 60, covering all the first trench resistor structures 51A. The second cover portion 62 forms the first end portion 60A on the outer side (peripheral side of the pad region 10) of one end of the plurality of first trench resistor structures 51A. That is, the first end portion 60A is opposite to the first cover portion 61 across the first trench group 52 when viewed from above. The second cover portion 62 is connected to the resistor buried electrodes 56 of the plurality of first trench resistor structures 51A, and is opposite to the boundary well region 40 across the main surface insulating film 45 in the thickness direction.

[0175] The third cover portion 63 forms the second end portion 60B of the resistive film 60, covering all the second trench resistor structures 51B. The third cover portion 63 forms the second end portion 60B on the outer side (peripheral side of the pad region 10) of the other end of the plurality of second trench resistor structures 51B. That is, the second end portion 60B is opposite to the first cover portion 61 in plan view, separated by the second trench group 53. The third cover portion 63 is connected to the resistor buried electrodes 56 of the plurality of second trench resistor structures 51B, and is opposite to the boundary well region 40 in the thickness direction, separated by the main surface insulating film 45.

[0176] The resistive film 60 is integrally formed in the second cover portion 62 with the embedded resistive electrodes 56 of the plurality of first trench resistive structures 51A, and integrally formed in the third cover portion 63 with the embedded resistive electrodes 56 of the plurality of second trench resistive structures 51B. That is, the resistive film 60 is constituted by a portion of the embedded resistive electrodes 56 extending in a film shape from the first main surface 3 (main surface insulating film 45). Of course, the resistive film 60 can also be formed separately from the embedded resistive electrodes 56.

[0177] Semiconductor device 1A includes a gate electrode film 64 disposed adjacent to a resistive film 60 on a first main surface 3. Specifically, the gate electrode film 64 is disposed on a main surface insulating film 45. The gate electrode film 64 includes at least one of a conductive polycrystalline silicon film and an alloy film. The alloy film may include an alloy crystal composed of metallic and non-metallic elements.

[0178] The alloy film may include at least one selected from CrSi film, CrSiN film, CrSiO film, TaN film, and TiN film. The gate electrode film 64 is preferably formed of the same resistive material as the resistive film 60. In this embodiment, the gate electrode film 64 comprises conductive polycrystalline silicon. The gate electrode film 64 preferably has a thickness substantially equal to that of the resistive film 60.

[0179] The gate electrode film 64 is disposed on the main surface insulating film 45 at intervals from the resistive film 60 on the inner side (third side 5C side) of the pad region 10, and is physically separated from the resistive film 60. The gate electrode film 64 is formed at intervals from multiple trench separation structures 15 toward the inner side of the pad region 10 when viewed from above.

[0180] The gate electrode film 64 is positioned opposite the boundary well region 40 (first boundary well region 40A) across the main surface insulating film 45. The gate electrode film 64 is polygonal in top view (quadrilateral in this embodiment). In this embodiment, the gate electrode film 64 is formed as a rectangle extending along the resistive film 60 in the second direction Y.

[0181] Reference Figure 11 , Figure 12 as well as Figure 24 Semiconductor device 1A includes a gate wiring film 65 disposed adjacent to the resistive film 60 on a first main surface 3, facing the gate electrode film 64 across the resistive film 60. Specifically, the gate wiring film 65 is disposed on the main surface insulating film 45. The gate wiring film 65 includes at least one of a conductive polycrystalline silicon film and an alloy film. The alloy film may include an alloy crystal composed of metallic and non-metallic elements.

[0182] The alloy film may include at least one selected from CrSi film, CrSiN film, CrSiO film, TaN film, and TiN film. The gate wiring film 65 is preferably formed of the same resistive material as the resistive film 60. In this embodiment, the gate wiring film 65 comprises conductive polycrystalline silicon. The gate wiring film 65 preferably has a thickness substantially equal to that of the resistive film 60.

[0183] The gate wiring film 65 is disposed on the main surface insulating film 45 with a gap between it and the gate electrode film 64, and is physically separated from the gate electrode film 64. The gate wiring film 65 has a first connection portion connected to a first end 60A of the resistive film 60, and a second connection portion connected to a second end 60B of the resistive film 60.

[0184] That is, the gate wiring film 65 is electrically connected to a plurality of trench resistor structures 51 via the resistor film 60. Specifically, the gate wiring film 65 is electrically connected to a plurality of first trench resistor structures 51A between the first cover portion 61 and the second cover portion 62 of the resistor film 60, and is electrically connected to a plurality of second trench resistor structures 51B between the first cover portion 61 and the third cover portion 63 of the resistor film 60.

[0185] In this embodiment, the gate wiring film 65 includes a first lower wiring portion 66, a second lower wiring portion 67, and a third lower wiring portion 68. The first lower wiring portion 66 is wound around the pad region 10. Specifically, the first lower wiring portion 66 surrounds the resistive film 60 and the gate electrode film 64 in the pad region 10 from multiple directions (three directions in this embodiment).

[0186] The first lower wiring portion 66 includes a first lower wiring portion 69 and a plurality of second lower wiring portions 70A, 70B. The first lower wiring portion 69 is disposed on the channel region 11 side of the pad region 10 opposite to the resistive film 60. The first lower wiring portion 69 is disposed adjacent to the resistive film 60 on the first main surface 3 such that it is opposite to the gate electrode film 64 through the resistive film 60 when viewed from above. The first lower wiring portion 69 is opposite to the boundary well region 40 (first boundary well region 40A) in the thickness direction through the main surface insulating film 45.

[0187] The first lower line portion 69 is formed as a strip extending along the resistive film 60 in the second direction Y. The first lower line portion 69 has a length in the second direction Y that is greater than the length of the resistive film 60 and the length of the gate electrode film 64. The first lower line portion 69 has one end on one side of the second direction Y (the first side surface 5A side) and another end on the other side of the second direction Y (the second side surface 5B side).

[0188] The plurality of second lower trace portions 70A and 70B include a second lower trace portion 70A on one side and a second lower trace portion 70B on the other side. The second lower trace portion 70A is disposed on one side (first side 5A side) of the pad region 10 relative to the resistive film 60 and the gate electrode film 64 in the second direction Y. The second lower trace portion 70B is disposed on the other side (second side 5B side) of the pad region 10 relative to the resistive film 60 and the gate electrode film 64 in the second direction Y.

[0189] The second lower trace portion 70A is formed as a strip extending along the first direction X, having one end connected to one end of the first lower trace portion 69, and another end located on the peripheral side (third side surface 5C side) of the chip 2. The second lower trace portion 70A is further connected to the first end portion 60A of the resistive film 60, and is formed at intervals from the gate electrode film 64. That is, the second lower trace portion 70A constitutes a first connection portion relative to the first end portion 60A. The second lower trace portion 70A is opposed to the boundary well region 40 (first boundary well region 40A) in the thickness direction through the main surface insulating film 45.

[0190] The second lower line portion 70B is formed as a strip extending in the first direction X, having one end connected to the other end of the first lower line portion 69, and another end located on the peripheral side (third side surface 5C side) of the chip 2. The other side of the second lower line portion 70B is further connected to the second end 60B of the resistive film 60, and is formed at intervals from the gate electrode film 64.

[0191] That is, the second lower line portion 70B constitutes a second connection portion relative to the first end portion 60A. The second lower line portion 70B on the other side is opposite to the second lower line portion 70A on one side through the gate electrode film 64. The second lower line portion 70B on the other side is opposite to the boundary well region 40 (first boundary well region 40A) in the thickness direction through the main surface insulating film 45.

[0192] The second lower wiring portion 67 is routed to the channel region 11. Specifically, the second lower wiring portion 67 extends from the first lower wiring portion 66 to the channel region 11. More specifically, the second lower wiring portion 67 extends from the interior (central portion in this embodiment) of the first lower wiring portion 69 to the channel region 11, forming a strip extending along the first direction X.

[0193] In this embodiment, the second lower wiring portion 67 traverses the center of the chip 2. The second lower wiring portion 67 extends in a strip shape relative to a straight line that traverses the center of the first main surface 3 in the second direction Y, located in a region on one side (third side surface 5C side) and another side (fourth side surface 5D side) in the first direction X. The second lower wiring portion 67 has one end connected to the first lower wiring portion 69 (first lower wiring portion 66) on one side of the first direction X, and another end on the other side of the first direction X.

[0194] The second lower wiring section 67 is positioned opposite the boundary well region 40 (second boundary well region 40B) in the thickness direction, separated by the main surface insulating film 45. The second lower wiring section 67 has a width greater than the width of the channel region 11 in the second direction Y, and extends from the channel region 11 to a plurality of active regions 6. The second lower wiring section 67 covers a plurality of trench separation structures 15 in the plurality of active regions 6.

[0195] Furthermore, the second lower wiring portion 67 covers the ends of the plurality of first trench structures 21 in the plurality of active regions 6. Thus, the second lower wiring portion 67 is electrically connected to the plurality of separate buried electrodes 18 and the plurality of first buried electrodes 24, and transmits gate potential to the plurality of separate buried electrodes 18 and the plurality of first buried electrodes 24.

[0196] In this embodiment, the second lower wiring portion 67 is integrally formed with the plurality of separate embedded electrodes 18 and the plurality of first embedded electrodes 24. That is, the second lower wiring portion 67 is composed of portions of the plurality of separate embedded electrodes 18 and portions of the plurality of first embedded electrodes 24 that are led out in a film shape on the first main surface 3 (main surface insulating film 45). Of course, the second lower wiring portion 67 may also be formed separately from the plurality of separate embedded electrodes 18 and the plurality of first embedded electrodes 24.

[0197] The third lower wiring portion 68 is led to the outer peripheral region 9. Specifically, the third lower wiring portion 68 extends from the first lower wiring portion 66 to the outer peripheral region 9. More specifically, the third lower wiring portion 68 is formed as a strip that extends from the other ends of the plurality of second lower wiring portions 70A, 70B to one side (first side 5A side) and the other side (second side 5B side) of the outer peripheral region 9 and along the outer peripheral region 9.

[0198] The third lower wiring portion 68, together with the second lower wiring portion 67, encloses a plurality of active regions 6. Specifically, the third lower wiring portion 68 extends along the periphery (first side surfaces 5A to 5D) of the chip 2 in a manner that surrounds the plurality of active regions 6 when viewed from above, and is connected to the other end of the second lower wiring portion 67. Thus, the third lower wiring portion 68, together with the second lower wiring portion 67, surrounds the plurality of active regions 6.

[0199] The third lower wiring section 68 is positioned opposite the interior of the outer peripheral well region 41 across the main surface insulating film 45. Specifically, when viewed from above, the third lower wiring section 68 is positioned opposite the interior of the outer peripheral well region 41 at intervals from the inner and outer edges of the outer peripheral well region 41 inward.

[0200] Reference Figure 3 The third lower wiring portion 68 has multiple leads 68a extending from the outer peripheral region 9 to multiple active regions 6 in the portion extending along the first side surface 5A. The multiple leads 68a cover the first trench separation structure 15A on the first active region 6A side and cover the second trench separation structure 15B on the second active region 6B side.

[0201] That is, multiple lead-out portions 68a cover the ends of multiple first trench structures 21. As a result, the third lower wiring portion 68 is electrically connected to multiple separate buried electrodes 18 and multiple first buried electrodes 24 in the first active region 6A, and transmits gate potential to the multiple separate buried electrodes 18 and multiple first buried electrodes 24.

[0202] Of course, on the first active region 6A side, a single lead-out portion 68a extending in a strip along the first trench separation structure 15A may also be formed. Additionally, on the second active region 6B side, a single lead-out portion 68a extending in a strip along the second trench separation structure 15B may also be formed.

[0203] In this embodiment, the third lower wiring portion 68 is integrally formed with the plurality of separate embedded electrodes 18 and the plurality of first embedded electrodes 24. That is, the third lower wiring portion 68 is composed of a portion of the plurality of separate embedded electrodes 18 and a portion of the plurality of first embedded electrodes 24 that are led out in a film shape on the first main surface 3 (main surface insulating film 45). Of course, the third lower wiring portion 68 may also be formed separately from the plurality of separate embedded electrodes 18 and the plurality of first embedded electrodes 24.

[0204] Reference Figures 11-15 The semiconductor device 1A includes a first slit 71 defined in the region between the resistive film 60 and the gate electrode film 64. The first slit 71 is formed as a strip extending along the second direction Y when viewed from above, dividing the first to third covering portions 61 to 63 of the resistive film 60.

[0205] The first slit 71 exposes the main insulating film 45. In top view, the first slit 71 is formed at a position further outward than the plurality of trench resistor structures 51, and is opposite to the boundary well region 40 (first boundary well region 40A) in the thickness direction. That is, the first slit 71 is not opposite to the trench resistor structure 51 in the thickness direction.

[0206] The first slit 71 has a first length in the second direction Y. The first slit 71 is formed to be narrower than the width of the gate electrode film 64 in the first direction X. The first slit 71 is preferably formed to be narrower than the width of the resistive film 60 in the first direction X. The first slit 71 is preferably formed to be narrower than the width of the first trench group 52 in the first direction X. The first slit 71 is preferably formed to be wider than the trench resistor structure 51 in the first direction X.

[0207] The width of the first slit 71 can be 0.1 μm or more and 10 μm or less. Specifically, the width of the first slit 71 can be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. Preferably, the width of the first slit 71 is 3 μm or more and 7 μm or less.

[0208] Reference Figures 11-15 The semiconductor device 1A includes a second slit 72 defined in the region between the resistive film 60 and the gate wiring film 65. Specifically, the second slit 72 is defined in the region between the resistive film 60 and the first lower wiring portion 69. The second slit 72 is opposite to the first slit 71 across the resistive film 60.

[0209] The second slit 72, when viewed from above, is formed as a strip extending along the second direction Y, dividing the first to third covering portions 61 to 63 of the resistive film 60. That is, the second slit 72 extends parallel to the first slit 71, dividing the resistive film 60 together with the first slit 71. The second slit 72 exposes the main surface insulating film 45.

[0210] The second slit 72, when viewed from above, is formed on the outer side of the plurality of trench resistor structures 51, and is opposite to the boundary well region 40 (first boundary well region 40A) in the thickness direction. That is, the second slit 72 is not opposite to the trench resistor structure 51 in the thickness direction. When viewed from above, the second slit 72 is opposite to the first slit 71 through the plurality of first trench resistor structures 51A and the plurality of second trench resistor structures 51B.

[0211] The second slit 72 has a second length in the second direction Y. This second length may also differ from the first length of the first slit 71. From the viewpoint of properly connecting the resistive film 60 and the gate wiring film 65, the second length is preferably less than or equal to the first length. In this embodiment, the second length is less than the first length. Of course, the second length may also be approximately equal to the first length. Alternatively, the second length may be greater than the first length.

[0212] The second slit 72 is formed to be narrower than the width of the gate electrode film 64 in the first direction X. The second slit 72 is preferably formed to be narrower than the width of the first lower line portion 69 in the first direction X. The second slit 72 is particularly preferably formed to be narrower than the resistive film 60 in the first direction X. The second slit 72 is preferably formed to be narrower than the width of the first trench group 52 in the first direction X. The second slit 72 is preferably formed to be wider than the width of the trench resistor structure 51.

[0213] The width of the second slit 72 can be 0.1 μm or more and 10 μm or less. Specifically, the width of the second slit 72 can be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. Preferably, the width of the second slit 72 is 3 μm or more and 7 μm or less. The width of the second slit 72 can also be greater than or equal to the width of the first slit 71. The width of the second slit 72 can also be less than or equal to the width of the first slit 71. Alternatively, the width of the second slit 72 can be approximately equal to the width of the first slit 71.

[0214] Reference Figures 11-15 The semiconductor device 1A includes a plurality of third slits 73 defined in the region between the gate electrode film 64 and the gate wiring film 65. Specifically, the plurality of third slits 73 are respectively defined in the region between the gate electrode film 64 and the plurality of second lower wiring portions 70A, 70B.

[0215] Multiple third slits 73 are each formed as a strip extending in the first direction X when viewed from above, exposing the main surface insulating film 45. The multiple third slits 73 are connected to the first slit 71 and are positioned opposite each other in the second direction Y, separated by the gate electrode film 64. That is, the multiple third slits 73 and the first slit 71 together divide the gate electrode film 64. Furthermore, the multiple third slits 73 and the first slit 71 together physically and electrically separate the gate electrode film 64 from the gate wiring film 65.

[0216] The third slit 73 is formed to be narrower than the width of the gate electrode film 64. The third slit 73 is preferably formed to be narrower than the width of the second lower line portions 70A and 70B. The third slit 73 is particularly preferably formed to be narrower than the width of the resistive film 60. The third slit 73 is preferably formed to be narrower than the width of the first trench group 52 (second trench group 53). The third slit 73 is preferably formed to be wider than the width of the trench resistor structure 51.

[0217] The width of the third slit 73 can be 0.1 μm or more and 10 μm or less. Specifically, the width of the third slit 73 can be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. Preferably, the width of the third slit 73 is 3 μm or more and 7 μm or less. The width of the third slit 73 can also be greater than or equal to the width of the first slit 71. The width of the third slit 73 can also be less than the width of the first slit 71. Alternatively, the width of the third slit 73 can be approximately equal to the width of the first slit 71.

[0218] Semiconductor device 1A includes an interlayer insulating film 74 covering a main surface insulating film 45. The interlayer insulating film 74 is thicker than the main surface insulating film 45. The interlayer insulating film 74 may also have a single-layer structure composed of a single insulating film, or a stacked structure comprising multiple insulating films. The interlayer insulating film 74 may also include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.

[0219] The interlayer insulating film 74 may also have a stacked structure comprising multiple silicon oxide films. In this case, the interlayer insulating film 74 may also include at least one of NSG (Non-doped Silicate Glass), PSG (Phosphor Silicate Glass), and BPSG (Boron Phosphor Silicate Glass) films, which are examples of silicon oxide films. The stacking order of the NSG, PSG, and BPSG films is arbitrary.

[0220] Interlayer insulating film 74 covers main surface insulating film 45 in active region 6, boundary region 8 and peripheral region 9. Interlayer insulating film 74 covers multiple trench separation structures 15, multiple first trench structures 21 and multiple second trench structures 25 in active region 6.

[0221] Interlayer insulating film 74 covers multiple trench resistor structures 51 (buried resistor electrodes 56), resistor film 60, gate electrode film 64, and gate wiring film 65 in pad region 10. Interlayer insulating film 74 sandwiches main surface insulating film 45 in pad region 10, covering boundary well region 40 (first boundary well region 40A). Interlayer insulating film 74 selectively covers peripheral well region 41, FLR 42, and channel blocking region 43 in peripheral region 9, separated by main surface insulating film 45. The laminate of main surface insulating film 45 and interlayer insulating film 74 is an example of an "insulating film" in this disclosure.

[0222] An interlayer insulating film 74 extends from above the resistive film 60 and the gate electrode film 64 into the first slit 71, and has a portion within the first slit 71 covering the main surface insulating film 45. That is, the interlayer insulating film 74, in the first slit 71, is positioned in the thickness direction opposite to the boundary well region 40 (first boundary well region 40A) across the main surface insulating film 45. The interlayer insulating film 74 electrically insulates the resistive film 60 and the gate electrode film 64 within the first slit 71.

[0223] The interlayer insulating film 74 extends into the second slit 72 from above the resistive film 60 and the gate wiring film 65 (first lower line portion 69), and covers the main surface insulating film 45 within the second slit 72. That is, the interlayer insulating film 74 is positioned in the second slit 72, across the main surface insulating film 45, opposite the boundary well region 40 (first boundary well region 40A) in the thickness direction. The interlayer insulating film 74 electrically insulates the resistive film 60 and the gate wiring film 65 (first lower line portion 69) within the second slit 72.

[0224] The interlayer insulating film 74 has portions extending from the gate electrode film 64 and the gate wiring film 65 (second lower line portions 70A, 70B) into a plurality of third slits 73, and covering the main surface insulating film 45 within the plurality of third slits 73. That is, the interlayer insulating film 74 is positioned opposite the boundary well region 40 (first boundary well region 40A) in the thickness direction within the plurality of third slits 73, separated by the main surface insulating film 45.

[0225] Interlayer insulating film 74 electrically insulates the gate electrode film 64 and the gate wiring film 65 within a plurality of third slits 73. Interlayer insulating film 74 has an insulating main surface 75 extending along the first main surface 3 (main surface insulating film 45). The insulating main surface 75 has a first recess 76, a second recess 77, and a plurality of third recesses 78 (see reference 10) in the pad region 10. Figures 16-22A first recess 76 is formed in the portion covering the first slit 71. The first recess 76 is recessed toward the first slit 71 and, when viewed from above, is formed as a strip extending along the first slit 71 in the second direction Y.

[0226] A second recess 77 is formed in the portion covering the second slit 72. The second recess 77 is recessed toward the second slit 72 and, when viewed from above, is formed as a strip extending along the second slit 72 in the second direction Y. A plurality of third recesses 78 are respectively formed in the portions covering the plurality of third slits 73. The plurality of third recesses 78 are respectively recessed toward the corresponding third slit 73 and, when viewed from above, are formed as strips extending along the corresponding third slit 73 in the first direction X.

[0227] Reference Figures 11-22 The semiconductor device 1A includes at least one (multiple in this embodiment) first resistive connection electrode 81 embedded in the interlayer insulating film 74 in a manner electrically connected to the resistive film 60. The first resistive connection electrode 81 may also be referred to as a "first resistive via electrode". The first resistive connection electrode 81 may also include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polycrystalline silicon film. In this embodiment, the first resistive connection electrode 81 has a stacked structure including a Ti film and a W film.

[0228] In this embodiment, a plurality of first resistive connection electrodes 81 are connected to the first covering portion 61 of the resistive film 60. That is, the plurality of first resistive connection electrodes 81 are connected to the portion of the resistive film 60 that covers the area outside the plurality of trench resistive structures 51. Specifically, the plurality of first resistive connection electrodes 81 are connected to the portion of the resistive film 60 that covers the spacing region 57 between the first trench group 52 (the plurality of first trench resistive structures 51A) and the second trench group 53 (the plurality of second trench resistive structures 51B).

[0229] Multiple first resistive connection electrodes 81 are formed, when viewed from above, in a region spaced apart from the multiple trench resistor structures 51 in the second direction Y, and are not opposed to the multiple trench resistor structures 51 in the first direction X. In this embodiment, the multiple first resistive connection electrodes 81 are each formed as a strip extending along the first direction X when viewed from above, and are arranged at intervals in the second direction Y. That is, the multiple first resistive connection electrodes 81 are arranged in a stripe-like pattern extending in the first direction X when viewed from above.

[0230] The plurality of first resistive connection electrodes 81 extend in a direction that intersects (or is orthogonal in this embodiment) the extending direction of the resistive film 60 (the plurality of trench resistive structures 51). That is, the plurality of first resistive connection electrodes 81 intersect (or is orthogonal) the current direction of the resistive film 60. As a result, current can be appropriately diffused from the plurality of first resistive connection electrodes 81 to the resistive film 60. In other words, current narrowing caused by the arrangement of the plurality of first resistive connection electrodes 81 is suppressed, and undesirable changes (increases) in resistance value caused by this current narrowing are suppressed.

[0231] Multiple first resistive connection electrodes 81 are positioned opposite the flat portion of the first main surface 3 only through the resistive film 60, and opposite the trench resistive structure 51 without being separated from it by the resistive film 60. Multiple first resistive connection electrodes 81 are positioned opposite the boundary well region 40 (first boundary well region 40A) through the resistive film 60 and the main surface insulating film 45. Multiple first resistive connection electrodes 81 are formed in a region that, when viewed from above, is spaced apart from the first slit 71 and the second slit 72 and sandwiched between them.

[0232] That is, the plurality of first resistive connection electrodes 81 are formed to be narrower than the width of the resistive film 60 in the first direction X. When viewed from above, the plurality of first resistive connection electrodes 81 are opposite to one or more first trench resistor structures 51A on one side (first side 5A side) in the second direction Y, and opposite to one or more second trench resistor structures 51B on the other side (second side 5B side) in the second direction Y.

[0233] The plurality of first resistive connection electrodes 81 only need to be opposed to at least two of the plurality of first trench resistor structures 51A in the second direction Y; they do not need to be opposed to all of the first trench resistor structures 51A. In this embodiment, the plurality of first resistive connection electrodes 81 are opposed to a portion of the plurality of first trench resistor structures 51A in the second direction Y. Of course, the plurality of first resistive connection electrodes 81 may also be opposed to all of the first trench resistor structures 51A in the second direction Y.

[0234] Similarly, the plurality of first resistor connection electrodes 81 only need to be opposed to at least two of the plurality of second trench resistor structures 51B in the second direction Y, and do not need to be opposed to all of the first trench resistor structures 51A. In this embodiment, the plurality of first resistor connection electrodes 81 are opposed to a portion of the plurality of second trench resistor structures 51B in the second direction Y. Of course, the plurality of first resistor connection electrodes 81 may also be opposed to all of the second trench resistor structures 51B in the second direction Y.

[0235] Multiple first resistive connection electrodes 81 have a first connection area S1 relative to the resistive film 60. The first connection area S1 is defined by the total planar area of ​​the multiple first resistive connection electrodes 81. In the case where a single first resistive connection electrode 81 is formed, the first connection area S1 is defined by the planar area of ​​the single first resistive connection electrode 81. The first connection area S1 is adjusted according to the first current I1 flowing through the first resistive connection electrode 81 (see reference). Figure 12 ).

[0236] Reference Figures 11-22 The semiconductor device 1A includes at least one (in this embodiment, multiple) second resistive connection electrode 82 embedded in the interlayer insulating film 74 in such a manner that it is electrically connected to the resistive film 60 at a different location than the first resistive connection electrode 81. The second resistive connection electrode 82 may also be referred to as a "second resistive via electrode".

[0237] The second resistive connection electrode 82 may also include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polycrystalline silicon film. In this embodiment, the second resistive connection electrode 82 has a stacked structure including a Ti film and a W film.

[0238] In this embodiment, a plurality of second resistive connection electrodes 82 are connected to the second cover portion 62 of the resistive film 60. That is, the plurality of second resistive connection electrodes 82 are embedded in the portion of the resistive film 60 that covers the first trench group 52 (the plurality of first trench resistor structures 51A).

[0239] A plurality of second resistive connection electrodes 82 form a first gate resistor R1 between a plurality of first resistive connection electrodes 81. The first gate resistor R1 is constituted by a portion of the resistive film 60 and the region located between the plurality of first resistive connection electrodes 81 and the plurality of second resistive connection electrodes 82 in the plurality of first trench resistor structures 51A. The resistance value of the first gate resistor R1 is adjusted by the distance between the plurality of first resistive connection electrodes 81 and the plurality of second resistive connection electrodes 82.

[0240] A plurality of second resistive connection electrodes 82 are formed, when viewed from above, in a region opposite to a plurality of first trench resistor structures 51A in the first direction X. In this embodiment, the plurality of second resistive connection electrodes 82 extend in a direction different from that of the first resistive connection electrodes 81 when viewed from above. Specifically, the plurality of second resistive connection electrodes 82 are each formed as strips extending in the second direction Y when viewed from above, and are arranged at intervals in the first direction X. That is, the plurality of second resistive connection electrodes 82 are arranged as stripes extending in the second direction Y when viewed from above.

[0241] Multiple second resistor connection electrodes 82 are respectively disposed in the region between multiple first trench resistor structures 51A that are spaced apart from each other when viewed from above. That is, the multiple second resistor connection electrodes 82 are arranged alternately with the multiple first trench resistor structures 51A in the first direction X.

[0242] In this embodiment, the plurality of second resistor connection electrodes 82 are positioned opposite only to the flat portion of the first main surface 3, separated by the resistor film 60, and are not positioned opposite to the trench resistor structure 51 separated by the resistor film 60. The plurality of second resistor connection electrodes 82 are positioned opposite to the boundary well region 40 (first boundary well region 40A) separated by the resistor film 60 and the main surface insulating film 45.

[0243] The plurality of second resistor connection electrodes 82 need only be disposed in a portion of the region between the plurality of first trench resistor structures 51A, and do not necessarily need to be disposed in the entire region between the plurality of first trench resistor structures 51A. The plurality of second resistor connection electrodes 82 need only be disposed in at least one region on the active region 6 side of the region between the plurality of first trench resistor structures 51A, and may not be disposed in at least one region on the gate electrode film 64 side.

[0244] Preferably, at least one of the plurality of second resistive connection electrodes 82 is opposite to the plurality of first resistive connection electrodes 81 in the second direction Y when viewed from above. In this case, preferably at least one of the plurality of second resistive connection electrodes 82 located on the gate electrode film 64 side is opposite to the plurality of first resistive connection electrodes 81 in the second direction Y.

[0245] At least one of the plurality of second resistive connection electrodes 82 located on the active region 6 side may not be opposed to the plurality of first resistive connection electrodes 81 in the second direction Y. Of course, all the second resistive connection electrodes 82 may also be configured to be opposed to the plurality of first resistive connection electrodes 81 in the second direction Y.

[0246] The plurality of second resistor connection electrodes 82 have a length in the second direction Y that is less than the length of the plurality of first trench resistor structures 51A. The plurality of second resistor connection electrodes 82 are preferably disposed in the region on the other end side of the plurality of first trench resistor structures 51A relative to the middle portion of the plurality of first trench resistor structures 51A in the length direction.

[0247] The length of the plurality of second resistor connecting electrodes 82 is preferably more than 1 / 100 and less than 1 / 2 of the length of the plurality of first trench resistor structures 51A. The length of the plurality of second resistor connecting electrodes 82 can be more than 1 / 20 and less than 1 / 4 of the length of the plurality of first trench resistor structures 51A.

[0248] The plurality of second resistive connection electrodes 82 have a second connection area S2 relative to the resistive film 60. The second connection area S2 is defined by the total planar area of ​​the plurality of second resistive connection electrodes 82. In the case where a single second resistive connection electrode 82 is formed, the second connection area S2 is defined by the planar area of ​​the single second resistive connection electrode 82.

[0249] The second connection area S2 can also be approximately equal to the first connection area S1. The second connection area S2 can also be larger than the first connection area S1. The second connection area S2 can also be smaller than the first connection area S1. The second connection area S2 is adjusted according to the current ratio I2 / I1 (shunt ratio) of the second current I2 flowing through the second resistive connection electrode 82 relative to the first current I1 flowing through the first resistive connection electrode 81 (refer to...). Figure 12 ).

[0250] In this case, the area ratio S2 / S1 of the second connection area S2 relative to the first connection area S1 is preferably set to a value greater than or equal to the current ratio I2 / I1. For example, when the current ratio I2 / I1 is 1, the area ratio S2 / S1 is preferably set to 1 or more. For example, when the current ratio I2 / I1 is 1 / 2, the area ratio S2 / S1 is preferably set to 1 / 2 or more.

[0251] When the current ratio I2 / I1 is 1 / 4, the area ratio S2 / S1 is preferably set to 1 / 4 or more. In this embodiment, the current ratio I2 / I1 is approximately 1 / 2, and the second connection area S2 is at least 1 / 2 times the first connection area S1. Preferably, the second connection area S2 is less than or twice the first connection area S1.

[0252] Reference Figures 11-22 The semiconductor device 1A includes at least one (in this embodiment, multiple) third resistive connection electrode 83 embedded in the interlayer insulating film 74 in such a way that it is electrically connected to the resistive film 60 at a different location than the first resistive connection electrode 81 and the second resistive connection electrode 82. The third resistive connection electrode 83 may also be referred to as a "third resistive via electrode".

[0253] The third resistive connection electrode 83 may also include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polycrystalline silicon film. In this embodiment, the third resistive connection electrode 83 has a stacked structure including a Ti film and a W film.

[0254] In this embodiment, a plurality of third resistive connection electrodes 83 are connected to the third covering portion 63 of the resistive film 60. That is, the plurality of third resistive connection electrodes 83 are embedded in the portion of the resistive film 60 that covers the second trench group 53 (the plurality of second trench resistive structures 51B).

[0255] A plurality of third resistive connection electrodes 83 form a second gate resistor R2 between a plurality of first resistive connection electrodes 81. The second gate resistor R2 is composed of a portion of the resistive film 60 and the region located between the plurality of first resistive connection electrodes 81 and the plurality of third resistive connection electrodes 83 in a plurality of second trench resistor structures 51B.

[0256] The resistance value of the second gate resistor R2 is adjusted by the distance between the plurality of first resistor connection electrodes 81 and the plurality of third resistor connection electrodes 83. In this embodiment, the resistance value of the second gate resistor R2 is approximately equal to the resistance value of the first gate resistor R1. Furthermore, the distance between the plurality of first resistor connection electrodes 81 and the plurality of third resistor connection electrodes 83 is approximately equal to the distance between the plurality of first resistor connection electrodes 81 and the plurality of second resistor connection electrodes 82.

[0257] Of course, the resistance value of the second gate resistor R2 can also be different from the resistance value of the first gate resistor R1. In this case, the distance between the plurality of first resistor connection electrodes 81 and the plurality of third resistor connection electrodes 83 can be different from the distance between the plurality of first resistor connection electrodes 81 and the plurality of second resistor connection electrodes 82.

[0258] For example, the resistance value of the second gate resistor R2 can also be less than the resistance value of the first gate resistor R1. In this case, the distance between the plurality of first resistor connection electrodes 81 and the plurality of third resistor connection electrodes 83 can also be set to be less than the distance between the plurality of first resistor connection electrodes 81 and the plurality of second resistor connection electrodes 82.

[0259] For example, the resistance value of the second gate resistor R2 can also be greater than the resistance value of the first gate resistor R1. In this case, the distance between the plurality of first resistor connection electrodes 81 and the plurality of third resistor connection electrodes 83 can be set to be greater than the distance between the plurality of first resistor connection electrodes 81 and the plurality of second resistor connection electrodes 82.

[0260] Multiple third resistive connection electrodes 83 are formed in a region that, when viewed from above, faces multiple second trench resistor structures 51B in the first direction X. In this embodiment, the multiple third resistive connection electrodes 83 extend in a direction different from the first resistive connection electrodes 81 when viewed from above. Specifically, the multiple third resistive connection electrodes 83 are each formed as a strip extending in the second direction Y when viewed from above, and are arranged at intervals in the first direction X. That is, the multiple third resistive connection electrodes 83 are arranged as stripes extending in the second direction Y when viewed from above.

[0261] Multiple third resistor connection electrodes 83 are respectively disposed in the region between multiple second trench resistor structures 51B that are spaced apart from each other but adjacent to each other when viewed from above. That is, the multiple third resistor connection electrodes 83 are arranged alternately with the multiple second trench resistor structures 51B in the first direction X.

[0262] In this embodiment, the plurality of third resistor connection electrodes 83 are positioned opposite only to the flat portion of the first main surface 3, separated by the resistor film 60, and are not positioned opposite to the trench resistor structure 51 separated by the resistor film 60. The plurality of third resistor connection electrodes 83 are positioned opposite to the boundary well region 40 (first boundary well region 40A) separated by the resistor film 60 and the main surface insulating film 45.

[0263] The plurality of third resistor connection electrodes 83 need only be disposed in a portion of the region between the plurality of second trench resistor structures 51B, and do not necessarily need to be disposed in the entire region between the plurality of second trench resistor structures 51B. The plurality of third resistor connection electrodes 83 need only be disposed in at least one region on the active region 6 side of the region between the plurality of second trench resistor structures 51B, and may not be disposed in at least one region on the gate electrode film 64 side.

[0264] Preferably, at least one of the plurality of third resistive connection electrodes 83 is opposite to the plurality of first resistive connection electrodes 81 in the second direction Y when viewed from above. In this case, preferably at least one of the plurality of third resistive connection electrodes 83 located on the gate electrode film 64 side is opposite to the plurality of first resistive connection electrodes 81 in the second direction Y.

[0265] At least one of the plurality of third resistor connection electrodes 83 located on the active region 6 side may not be opposed to the plurality of first resistor connection electrodes 81 in the second direction Y. Of course, all the third resistor connection electrodes 83 may also be configured to be opposed to the plurality of first resistor connection electrodes 81 in the second direction Y.

[0266] Preferably, at least one of the plurality of third resistive connection electrodes 83 is opposed to the plurality of second resistive connection electrodes 82 in the second direction Y when viewed from above. In this embodiment, the number of the plurality of third resistive connection electrodes 83 is set to be equal to the number of the plurality of second resistive connection electrodes 82, and all the third resistive connection electrodes 83 are opposed to all the second resistive connection electrodes 82 in a one-to-one correspondence in the second direction Y. Of course, the number of third resistive connection electrodes 83 can be more or less than the number of second resistive connection electrodes 82.

[0267] The plurality of third resistor connection electrodes 83 have a length in the second direction Y that is less than the length of the plurality of second trench resistor structures 51B. The plurality of third resistor connection electrodes 83 are preferably disposed in the region on the other end side of the plurality of second trench resistor structures 51B relative to the middle portion of the long side direction.

[0268] The length of the plurality of third resistor connecting electrodes 83 is preferably more than 1 / 100 and less than 1 / 2 of the length of the plurality of second trench resistor structures 51B. The length of the plurality of third resistor connecting electrodes 83 can be more than 1 / 20 and less than 1 / 4 of the length of the plurality of second trench resistor structures 51B. The length of the third resistor connecting electrodes 83 can also be approximately equal to the length of the second trench resistor structure 51B. The length of the third resistor connecting electrodes 83 can also be greater than the length of the second trench resistor structure 51B. The length of the third resistor connecting electrodes 83 can also be smaller than the length of the second trench resistor structure 51B.

[0269] Multiple third resistive connection electrodes 83 have a third connection area S3 relative to the resistive film 60. The third connection area S3 is defined by the total planar area of ​​the multiple third resistive connection electrodes 83. In the case where a single third resistive connection electrode 83 is formed, the third connection area S3 is defined by the planar area of ​​the single third resistive connection electrode 83. The third connection area S3 is adjusted according to the current ratio I3 / I1 (shunt ratio) of the third current I3 flowing through the third resistive connection electrode 83 relative to the first current I1 flowing through the first resistive connection electrode 81 (see reference). Figure 12 ).

[0270] In this case, the value of the current ratio I3 / I1 of the third connection area S3 relative to the first connection area S1 is preferably set to a value greater than or equal to the value of the current ratio I3 / I1. For example, if the current ratio I3 / I1 is 1, the current ratio I3 / I1 is preferably set to 1 or more. For example, if the current ratio I3 / I1 is 1 / 2, the current ratio I3 / I1 is preferably set to 1 / 2 or more.

[0271] When the current ratio I3 / I1 is 1 / 4, the current ratio I3 / I1 is preferably set to 1 / 4 or more. In this embodiment, the third current I3 is approximately equal to the second current I2, and the current ratio I3 / I1 is approximately 1 / 2. Therefore, the third connection area S3 is set to be at least 1 / 2 times the first connection area S1. The third connection area S3 is preferably less than 2 times the first connection area S1. Of course, the third current I3 can be greater than or less than the second current I2.

[0272] Reference Figures 3 to 10AThe semiconductor device 1A includes a plurality of gate connection electrodes 84 embedded in an interlayer insulating film 74 in a manner electrically connected to a gate wiring film 65 in an active region 7. The gate connection electrodes 84 may also be referred to as "gate via electrodes". The plurality of gate connection electrodes 84 may also include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polycrystalline silicon film. In this embodiment, the plurality of gate connection electrodes 84 have a stacked structure including Ti films and W films.

[0273] The plurality of gate connection electrodes 84 includes at least one (in this embodiment, multiple) first gate connection electrode 84A and at least one (in this embodiment, multiple) second gate connection electrode 84B. The plurality of first gate connection electrodes 84A are embedded in the interlayer insulating film 74 in the channel region 11, covering the portion of the second lower wiring portion 67, and are electrically connected to the second lower wiring portion 67 (see reference 1). Figures 7-9 In this embodiment, a plurality of first gate connection electrodes 84A are formed at intervals in the second direction Y, forming a strip extending in the first direction X.

[0274] Multiple second gate connection electrodes 84B are embedded in the outer peripheral region 9 within the interlayer insulating film 74, covering the portion of the third lower wiring portion 68, and are electrically connected to the third lower wiring portion 68 (see reference). Figures 3-6 In this embodiment, a plurality of second gate connection electrodes 84B are formed at intervals from the inner edge to the outer edge of the third lower wiring portion 68, forming a strip extending along the third lower wiring portion 68.

[0275] Reference Figure 3 and Figure 4 Semiconductor device 1A includes a plurality of first emitter connection electrodes 85, which penetrate the main surface insulating film 45 and are embedded in the interlayer insulating film 74 in a manner that electrically connects the active region 6 to the plurality of emitter regions 29. The first emitter connection electrodes 85 may also be referred to as "first emitter via electrodes".

[0276] The plurality of first emitter connection electrodes 85 may also include at least one of Ti film, TiN film, W film, Al film, Cu film, Al alloy film, Cu alloy film, and conductive polycrystalline silicon film. In this embodiment, the plurality of first emitter connection electrodes 85 have a stacked structure including Ti film and W film.

[0277] Multiple first emitter connection electrodes 85 are embedded in multiple contact holes 30, penetrating the interlayer insulating film 74 and the main surface insulating film 45. In top view, the multiple first emitter connection electrodes 85 are formed as strips extending along multiple first trench structures 21 in the second direction Y. That is, in this embodiment, the multiple first emitter connection electrodes 85 extend in the same direction as the extension directions of the multiple second resistive connection electrodes 82 and the multiple third resistive connection electrodes 83. The multiple first emitter connection electrodes 85 are electrically connected to the emitter region 29 and the channel contact region 31 within their respective contact holes 30.

[0278] Reference Figure 3 and Figure 5 The semiconductor device 1A includes a plurality of second emitter connection electrodes 86, which penetrate the main surface insulating film 45 and are embedded in the interlayer insulating film 74 in a manner that electrically connects to the plurality of emitter electrode films 47 in the active region 6. The second emitter connection electrodes 86 may also be referred to as "second emitter via electrodes".

[0279] The plurality of second emitter connection electrodes 86 may also include at least one of Ti film, TiN film, W film, Al film, Cu film, Al alloy film, Cu alloy film, and conductive polycrystalline silicon film. In this embodiment, the plurality of second emitter connection electrodes 86 have a stacked structure including Ti film and W film. The plurality of second emitter connection electrodes 86 are electrically connected to the second buried electrode 28 via a plurality of emitter electrode films 47.

[0280] Reference Figures 3-6 The semiconductor device 1A includes at least one (in this embodiment, multiple) first well connection electrode 87 that penetrates the main surface insulating film 45 and is embedded in the interlayer insulating film 74 in a manner electrically connected to the inner edge of the outer peripheral well region 41. The first well connection electrode 87 may also be referred to as a "first well via electrode".

[0281] The plurality of first well connecting electrodes 87 may also include at least one of Ti film, TiN film, W film, Al film, Cu film, Al alloy film, Cu alloy film, and conductive polycrystalline silicon film. In this embodiment, the plurality of first well connecting electrodes 87 have a stacked structure including Ti film and W film.

[0282] In this embodiment, a plurality of first well connection electrodes 87 are arranged at intervals from the inner edge to the outer edge of the peripheral well region 41. The plurality of first well connection electrodes 87 are disposed at the middle of the width direction of the peripheral well region 41 on the inner edge side of the peripheral well region 41 and are electrically connected to the region on the inner edge side of the peripheral well region 41. Specifically, the plurality of first well connection electrodes 87 are disposed in the region between the inner edge of the peripheral well region 41 and the third lower wiring portion 68 of the gate wiring film 65. The plurality of first well connection electrodes 87 extend in a strip shape along the inner edge of the peripheral well region 41.

[0283] The plurality of first well connecting electrodes 87 each have a plurality of segmented portions 87a in the portion extending along the first direction X (see reference). Figure 3 Multiple segmented portions 87a are spaced apart from multiple leads 68a of the gate wiring film 65 (third lower wiring portion 68) and respectively disposed in the region between the multiple leads 68a. In the case where a single lead 68a extending in a strip is formed along the trench separation structure 15, the multiple segmented portions 87a are omitted.

[0284] Reference Figures 3-6 The semiconductor device 1A includes at least one (in this embodiment, multiple) second well connection electrode 88 that penetrates the main surface insulating film 45 and is embedded in the interlayer insulating film 74 in a manner electrically connected to the outer edge of the peripheral well region 41. The second well connection electrode 88 may also be referred to as a "second well via electrode".

[0285] The plurality of second well connecting electrodes 88 may also include at least one of Ti film, TiN film, W film, Al film, Cu film, Al alloy film, Cu alloy film, and conductive polycrystalline silicon film. In this embodiment, the plurality of second well connecting electrodes 88 have a stacked structure including Ti film and W film.

[0286] A plurality of second well connection electrodes 88 are arranged at intervals from the inner edge to the outer edge of the peripheral well region 41. The plurality of second well connection electrodes 88 are disposed at the outer edge of the peripheral well region 41 relative to the middle portion of the peripheral well region 41 in the width direction, and are electrically connected to the region on the outer edge of the peripheral well region 41. Specifically, the plurality of second well connection electrodes 88 are disposed in the region between the outer edge of the peripheral well region 41 and the third lower wiring portion 68 of the gate wiring film 65. The plurality of second well connection electrodes 88 extend in a strip shape along the outer edge of the peripheral well region 41.

[0287] Reference Figure 10A as well as Figure 10BThe semiconductor device 1A includes a plurality of FLR connection electrodes 89 embedded in the interlayer insulating film 74 through the main surface insulating film 45 in a manner electrically connected to the corresponding FLR 42. In this manner, one FLR connection electrode 89 is connected to one FLR 42. Of course, multiple FLR connection electrodes 89 can also be connected to one FLR 42. The FLR connection electrode 89 can also be referred to as an "FLR via electrode".

[0288] The plurality of FLR connection electrodes 89 may also include at least one selected from Ti film, TiN film, W film, Al film, Cu film, Al alloy film, Cu alloy film, and conductive polycrystalline silicon film. In this embodiment, the plurality of FLR connection electrodes 89 have a stacked structure comprising Ti film and W film.

[0289] Multiple FLR connection electrodes 89 are formed as strips extending along their respective FLR 42. Alternatively, multiple FLR connection electrodes 89 are formed as rings (quadrilateral rings) extending along their respective FLR 42. In this configuration, the multiple FLR connection electrodes 89 are electrically floating.

[0290] Reference Figure 1 as well as Figures 11-22 The semiconductor device 1A includes a gate terminal electrode 90 disposed on a first main surface 3 in a pad region 10 (non-active region 7) in a manner electrically connected to a gate resistor structure 50. Specifically, the gate terminal electrode 90 is disposed on an interlayer insulating film 74. The gate terminal electrode 90 may also be referred to as a "gate pad" or "gate pad electrode".

[0291] The gate terminal electrode 90 is preferably made of a different conductive material than the resistive film 60. The gate terminal electrode 90 is preferably made of a different conductive material than the gate electrode film 64. The gate terminal electrode 90 has a lower resistance value than the trench resistor structure 51 and the resistive film 60, and is electrically connected to the trench resistor structure 51 via the resistive film 60. The gate terminal electrode 90 has a lower resistance value than the gate electrode film 64.

[0292] In this embodiment, the gate terminal electrode 90 is made of a metal film. The gate terminal electrode 90 may also be referred to as a "gate metal terminal". The gate terminal electrode 90 may also include at least one of Ti film, TiN film, W film, Al film, Cu film, Al alloy film, Cu alloy film, and conductive polycrystalline silicon film.

[0293] The gate terminal electrode 90 may also include at least one of a pure Cu film (Cu film with a purity of 99% or higher), a pure Al film (Al film with a purity of 99% or higher), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the gate terminal electrode 90 has a stacked structure including a Ti film and an Al alloy film (AlCu alloy film in this embodiment) sequentially stacked from the chip 2 side.

[0294] The gate terminal electrode 90 preferably has a thickness greater than that of the resistive film 60 (the thickness of the gate electrode film 64). The thickness of the gate terminal electrode 90 can be 1 μm or more and 10 μm or less. The gate terminal electrode 90 preferably has a planar area of ​​1% or more and 30% or less of the planar area of ​​the first main surface 3. The planar area of ​​the gate terminal electrode 90 is particularly preferably 25% or less of the planar area of ​​the first main surface 3. The planar area of ​​the gate terminal electrode 90 can be 10% or less of the planar area of ​​the first main surface 3.

[0295] The gate terminal electrode 90 is disposed on the interlayer insulating film 74 in the pad region 10 in such a way that it covers the resistive film 60 and the gate electrode film 64. The gate terminal electrode 90 covers a plurality of first resistive connection electrodes 81 in the portion covering the resistive film 60 and is electrically connected to the plurality of first resistive connection electrodes 81. That is, the gate terminal electrode 90 is electrically connected to the resistive film 60 (first coverage portion 61) via the plurality of first resistive connection electrodes 81.

[0296] Reference Figures 11-22 (in particular Figures 11-13 The gate terminal electrode 90 includes a first electrode portion 91 and a second electrode portion 92. The first electrode portion 91 has a relatively wide electrode width in the second direction Y. The first electrode portion 91 is the portion that forms the terminal body of the gate terminal electrode 90, and is located in the region outside the first resistive connection electrode 81 when viewed from above. The first electrode portion 91 may also be referred to as the "terminal body portion".

[0297] For example, a bonding wire is connected to the first electrode portion 91. Therefore, the first electrode portion 91 is formed to be wider than the bonding width of the bonding wire. When viewed from above, the first electrode portion 91 is formed as a polygon (in this embodiment, a quadrilateral shape) with four sides parallel to the periphery of the chip 2 (the periphery of the pad region 10). The first electrode portion 91 is disposed in the region opposite to the gate electrode film 64 across the interlayer insulating film 74.

[0298] The first electrode portion 91 preferably covers more than 50% of the gate electrode film 64 when viewed from above. Particularly preferably, the first electrode portion 91 covers more than 90% of the gate electrode film 64 when viewed from above. In this embodiment, the first electrode portion 91 has an electrode width wider than the gate electrode film 64, covering the entire area of ​​the gate electrode film 64.

[0299] The flatness of the first electrode portion 91 is improved by the gate electrode film 64. The first electrode portion 91 can also be electrically insulated from the gate electrode film 64 by the interlayer insulating film 74. The first electrode portion 91 can also be electrically connected to the gate electrode film 64 via one or more gate connection electrodes 84 embedded in the interlayer insulating film 74.

[0300] The first electrode portion 91 covers the first slit 71 through the interlayer insulating film 74 and backfills the first recess 76 of the interlayer insulating film 74 (insulating main surface 75). In the case where a gate terminal electrode 90 (first electrode portion 91) is formed that partially exposes the first recess 76, electrode residue generated during the formation process of the gate terminal electrode 90 may remain in the first recess 76.

[0301] In the presence of electrode residue, the gate terminal electrode 90 (first electrode portion 91) may be electrically connected to other electrodes via the electrode residue. Therefore, the gate terminal electrode 90 (first electrode portion 91) preferably covers the entire area of ​​the first slit 71 through the interlayer insulating film 74.

[0302] That is, the gate terminal electrode 90 (first electrode portion 91) preferably fills the entire area of ​​the first recess 76 of the interlayer insulating film 74 (insulating main surface 75). This structure provides a layout that avoids the problem of electrode residue in the first recess 76. This disclosure does not exclude a manner that includes partially exposing the gate terminal electrode 90 (first electrode portion 91) of the first recess 76.

[0303] When viewed from above, the first electrode portion 91 extends across the first slit 71 from above the gate electrode film 64 and onto the resistive film 60. In this embodiment, the first electrode portion 91 covers the edge portion of the resistive film 60 across the interlayer insulating film 74. Specifically, the first electrode portion 91 covers the edge portion of the resistive film 60 at intervals on the gate electrode film 64 side, with respect to a straight line that traverses the center portion of the resistive film 60 in the second direction Y.

[0304] The first electrode portion 91 may also cover one or more trench resistor structures 51 through the resistor film 60 in the portion covering the resistor film 60. The first electrode portion 91 may also cover one or more first trench resistor structures 51A through the resistor film 60. The first electrode portion 91 may also cover one or more second trench resistor structures 51B through the resistor film 60. In this embodiment, the first electrode portion 91 covers one first trench resistor structure 51A and one second trench resistor structure 51B through the resistor film 60.

[0305] The first electrode portion 91 sandwiches the interlayer insulating film 74, covers a plurality of third slits 73, and backfills a plurality of third recesses 78 of the interlayer insulating film 74 (insulating main surface 75). In the case where a gate terminal electrode 90 (first electrode portion 91) is formed that partially exposes the plurality of third recesses 78, electrode residue generated during the formation process of the gate terminal electrode 90 may remain in the plurality of third recesses 78.

[0306] In the presence of electrode residue, the gate terminal electrode 90 (first electrode portion 91) may be electrically connected to other electrodes via the electrode residue. Therefore, the gate terminal electrode 90 (first electrode portion 91) preferably covers the entire area of ​​the plurality of third recesses 78 through the interlayer insulating film 74.

[0307] That is, the gate terminal electrode 90 (first electrode portion 91) preferably fills the entire area of ​​the third recess 78 of the interlayer insulating film 74 (insulating main surface 75). According to this structure, a layout that avoids the problem of electrode residue in the plurality of third recesses 78 is provided. This disclosure does not preclude a configuration that includes the gate terminal electrode 90 (first electrode portion 91) partially exposing the plurality of third recesses 78.

[0308] When viewed from above, the first electrode portion 91 extends across the gate electrode film 64 through multiple third slits 73 and onto multiple second lower lines 70A, 70B. In this embodiment, the first electrode portion 91 covers the edges of the multiple second lower lines 70A, 70B through the interlayer insulating film 74.

[0309] The second electrode portion 92 has a smaller electrode width than the first electrode portion 91 in the second direction Y, and is composed of a lead-out portion extending in the first direction X such that it protrudes from the first electrode portion 91 to a plurality of first resistor connection electrodes 81. The second electrode portion 92 may also be referred to as a "terminal lead-out portion". For example, no bonding wire is connected to the second electrode portion 92. Therefore, the second electrode portion 92 is formed to be narrower than the bonding width of the bonding wire.

[0310] The protruding direction of the second electrode portion 92 is the same as the extending direction of the plurality of first resistive connection electrodes 81. In this embodiment, the second electrode portion 92 extends from the central portion of the first electrode portion 91 and covers all the first resistive connection electrodes 81.

[0311] The second electrode portion 92 is formed at intervals from the first slit 71 to the second slit 72 when viewed from above, and does not intersect with the first slit 71. Furthermore, the second electrode portion 92 is formed at intervals from the second slit 72 to the first slit 71 when viewed from above, and does not intersect with the second slit 72. That is, the second electrode portion 92 has a width smaller than the width of the resistive film 60 in the first direction X, and is disposed only in the region directly above the resistive film 60.

[0312] The second electrode portion 92 is positioned opposite the spacer region 57, separated by the main surface insulating film 45, the resistive film 60, and the interlayer insulating film 74. That is, the second electrode portion 92 is positioned opposite the flat portion of the first main surface 3 in the thickness direction. In addition, the second electrode portion 92 is positioned opposite the boundary well region 40 (first boundary well region 40A) in the thickness direction.

[0313] The second electrode portion 92 has a width in the first direction X that is larger than the width of the trench resistor structure 51 in the first direction X. The second electrode portion 92 has a width in the second direction Y that is smaller than the length of the trench resistor structure 51 in the second direction Y. Preferably, the second electrode portion 92 has a width in the second direction Y that is smaller than the spacing width of the spacing region 57.

[0314] In this embodiment, the second electrode portion 92 is formed at intervals from the other end (first trench group 52) of the plurality of first trench resistor structures 51A toward the spacing region 57. Additionally, in this embodiment, the second electrode portion 92 is formed at intervals from one end (second trench group 53) of the plurality of second trench resistor structures 51B toward the spacing region 57. That is, the second electrode portion 92 is only opposed to the spacing region 57 in the thickness direction, and not opposed to the plurality of trench resistor structures 51 in the thickness direction.

[0315] Of course, the second electrode portion 92 may also be opposed to the other end (first trench group 52) of the plurality of first trench resistor structures 51A in the thickness direction. Alternatively, the second electrode portion 92 may be opposed to one end (second trench group 53) of the plurality of second trench resistor structures 51B in the thickness direction. Given the flatness of the second electrode portion 92, it is preferable that the second electrode portion 92 is formed in a region outside the plurality of trench resistor structures 51 at intervals when viewed from above.

[0316] Reference Figures 11-23 The semiconductor device 1A includes a gate wiring electrode 93 disposed on a first main surface 3 in a pad region 10 (non-active region 7) in a manner electrically connected to a gate resistor structure 50. Specifically, the gate wiring electrode 93 is disposed on an interlayer insulating film 74. The gate wiring electrode 93 may also be referred to as a "gate finger" or "gate finger electrode".

[0317] The gate wiring electrode 93 is preferably made of a different conductive material than the resistive film 60. The gate wiring electrode 93 is preferably made of a different conductive material than the gate wiring film 65. The gate wiring electrode 93 has a lower resistance value than the trench resistor structure 51 and the resistive film 60, and is electrically connected to the gate terminal electrode 90 via the trench resistor structure 51 and the resistive film 60. The gate wiring electrode 93 has a lower resistance value than the gate wiring film 65.

[0318] In this embodiment, the gate wiring electrode 93 is made of a metal film. The gate wiring electrode 93 may also be referred to as a "gate metal wiring". The gate wiring electrode 93 may also include at least one of Ti film, TiN film, W film, Al film, Cu film, Al alloy film, Cu alloy film, and conductive polycrystalline silicon film.

[0319] The gate wiring electrode 93 may also include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the gate wiring film 65 has a stacked structure comprising a Ti film and an Al alloy film (AlCu alloy film in this embodiment) sequentially stacked from the chip 2 side. That is, the gate wiring film 65 has the same electrode structure as the gate terminal electrode 90.

[0320] The gate wiring electrode 93 preferably has a thickness greater than that of the resistive film 60 (the thickness of the gate wiring film 65). The thickness of the gate wiring electrode 93 can be more than 1 μm and less than 10 μm. The thickness of the gate wiring electrode 93 is preferably approximately equal to the thickness of the gate terminal electrode 90.

[0321] The gate wiring electrode 93 is wound in the region between the active region 6 and the non-active region 7, and is electrically connected to the first trench structure 21 (trench separation structure 15) in the active region 6, and electrically connected to the resistive film 60 in the non-active region 7. Specifically, the gate wiring electrode 93 is electrically connected to the first end 60A and the second end 60B of the resistive film 60 via the gate wiring film 65.

[0322] That is, the gate wiring electrode 93 forms a parallel resistor circuit PR (also referred to) between itself and the gate terminal electrode 90, including a first gate resistor R1 and a second gate resistor R2. Figure 24 The parallel resistor circuit PR forms the gate resistor RG between the gate terminal electrode 90 and the gate wiring electrode 93. The parallel resistor circuit PR also exists between the gate electrode film 64 and the gate wiring film 65. The resistance value of the gate resistor RG (parallel resistor circuit PR) is calculated by the combined resistance of the first gate resistor R1 and the second gate resistor R2 (=(R1+R2) / R1·R2).

[0323] In this embodiment, the gate wiring electrode 93 includes a first upper wiring portion 94, a second upper wiring portion 95, and a third upper wiring portion 96. The first upper wiring portion 94 is disposed on the pad region 10 in such a way that it surrounds the gate terminal electrode 90 from multiple directions (three directions in this embodiment), and is disposed on the first lower wiring portion 66 of the gate wiring film 65 through an interlayer insulating film 74.

[0324] The first upper wiring portion 94 includes a first upper wiring portion 97 and a plurality of second upper wiring portions 98A, 98B. The first upper wiring portion 97 is formed as a strip extending in the second direction Y, sandwiching an interlayer insulating film 74 in the pad region 10 and disposed in the area of ​​the gate wiring film 65 covering the first lower wiring portion 69.

[0325] The first upper thread portion 97 has one end on one side of the second direction Y (the first side surface 5A side) and the other end on the other side of the second direction Y (the second side surface 5B side). The first upper thread portion 97 covers the second slit 72 through the interlayer insulating film 74 and backfills the second recess 77 of the interlayer insulating film 74 (insulating main surface 75).

[0326] In the case of forming a gate terminal electrode 90 (first electrode portion 91 and / or second electrode portion 92) that intersects with the second recess 77, and a gate wiring electrode 93 (first upper line portion 97) that partially exposes the second recess 77, electrode residue generated during the formation process of the gate terminal electrode 90 may remain in multiple second recesses 77.

[0327] In the presence of electrode residue, the gate wiring electrode 93 (first upper line portion 97) may be electrically connected to the gate terminal electrode 90 via the electrode residue. In this case, the gate wiring electrode 93 (first upper line portion 97) and the gate terminal electrode 90 (first electrode portion 91) together form a short-circuit circuit that does not pass through the gate resistor structure 50. Therefore, the gate wiring electrode 93 (first upper line portion 97) preferably covers the entire area of ​​the second slit 72 through the interlayer insulating film 74.

[0328] That is, the gate wiring electrode 93 (first upper line portion 97) preferably fills the entire area of ​​the second recess 77 of the interlayer insulating film 74 (insulating main surface 75). According to this structure, a layout that avoids the problem of electrode residue in the second recess 77 is provided. This disclosure does not exclude a configuration including gate terminal electrodes 90 (first electrode portion 91 and / or second electrode portion 92) intersecting the second recess 77, and gate wiring electrodes 93 (first upper line portion 97) that partially expose the second recess 77.

[0329] The first upper line portion 97, when viewed from above, extends across the second slit 72 from above the gate wiring film 65 (first lower line portion 69) to the resistive film 60. The first upper line portion 97 covers the edge portion of the resistive film 60 through the interlayer insulating film 74. The first upper line portion 97 may also further extend across a straight line that crosses the center portion of the resistive film 60 in the second direction Y, covering the portion of the resistive film 60 located on the gate electrode film 64 side relative to the straight line.

[0330] The first upper line portion 97 is formed at intervals from the first electrode portion 91 and the second electrode portion 92 of the gate terminal electrode 90 in the first direction X. In this embodiment, the first upper line portion 97 has a recess 97a that is recessed along the second electrode portion 92 of the gate terminal electrode 90 in the first direction X.

[0331] The first upper part 97 includes a first connection region 101 and a second connection region 102. The first connection region 101 is located on one side (the first side surface 5A side) of the recess 97a in the second direction Y, and is opposite to the second electrode part 92 in the second direction Y. The first connection region 101 covers the second cover portion 62 of the resistive film 60 through the interlayer insulating film 74. That is, the first connection region 101 covers the first trench group 52 (a plurality of first trench resistor structures 51A) through the interlayer insulating film 74 and the second cover portion 62 of the resistive film 60.

[0332] The first connection region 101 also covers a plurality of second resistive connection electrodes 82 and is electrically connected to the plurality of second resistive connection electrodes 82. Thus, the first connection region 101 is electrically connected to the second cover portion 62 of the resistive film 60 and the first trench group 52 (a plurality of first trench resistive structures 51A) via the plurality of second resistive connection electrodes 82.

[0333] The first connection region 101 only needs to cover one or more first trench resistor structures 51A adjacent to one or more second resistor connection electrodes 82, and does not need to cover all the first trench resistor structures 51A. Of course, the first connection region 101 can also cover all the first trench resistor structures 51A.

[0334] The second connection region 102 is located on the other side of the recess 97a in the second direction Y (the side of the second side 5B), and is opposite to the second electrode portion 92 in the second direction Y. The second connection region 102 covers the third covering portion 63 of the resistive film 60 through the interlayer insulating film 74. That is, the second connection region 102 covers the second trench group 53 (a plurality of second trench resistor structures 51B) through the interlayer insulating film 74 and the third covering portion 63 of the resistive film 60.

[0335] The second connection region 102 also covers a plurality of third resistive connection electrodes 83 and is electrically connected to the plurality of third resistive connection electrodes 83. Thus, the second connection region 102 is electrically connected to the third cover portion 63 and the second trench group 53 (a plurality of second trench resistive structures 51B) of the resistive film 60 via the plurality of third resistive connection electrodes 83.

[0336] The second connection region 102 only needs to cover one or more second trench resistor structures 51B adjacent to one or more third resistor connection electrodes 83, and does not need to cover all the second trench resistor structures 51B. Of course, the second connection region 102 can also cover all the second trench resistor structures 51B.

[0337] The area of ​​the gate wiring electrode 93 (first upper line portion 97) opposite the resistive film 60 is preferably larger than the area of ​​the gate terminal electrode 90 (first electrode portion 91 and second electrode portion 92) opposite the resistive film 60. Of course, the area of ​​the gate wiring electrode 93 opposite the resistive film 60 may also be smaller than the area of ​​the gate terminal electrode 90 opposite the resistive film 60.

[0338] When a gate terminal electrode 90 (first electrode portion 91) that partially exposes the first recess 76 and a first upper line portion 97 that intersects with the first recess 76 are formed, electrode residue generated during the formation process of the gate terminal electrode 90 may remain in multiple first recesses 76.

[0339] In the presence of electrode residue, the gate wiring electrode 93 (first upper line portion 97) may be electrically connected to the gate terminal electrode 90 (first electrode portion 91) via the electrode residue. In this case, the gate wiring electrode 93 (first upper line portion 97) and the gate terminal electrode 90 (first electrode portion 91) together form a short-circuit circuit that does not pass through the gate resistor structure 50.

[0340] Therefore, it is preferable that the first upper line portion 97 is formed at intervals from the first recess 76 (first slit 71) to the second recess 77 (second slit 72) when viewed from above, and does not intersect with the first recess 76 (first slit 71). In this embodiment, the gate terminal electrode 90 (first electrode portion 91) covers the entire area of ​​the first recess 76.

[0341] That is, the region of the first upper line portion 97 above the resistive film 60 is opposite to the first electrode portion 91 and the second electrode portion 92 of the gate terminal electrode 90 in the first direction X. According to this structure, a layout that avoids the problem of electrode residue in the first recess 76 is provided. This disclosure does not exclude a configuration including the gate terminal electrode 90 (first electrode portion 91) that partially exposes the first recess 76, and the first upper line portion 97 that intersects the first recess 76.

[0342] The first current I1 applied to the gate terminal electrode 90 (second electrode portion 92) is transmitted to the first cover portion 61 of the resistive film 60 via a plurality of first resistor connection electrodes 81. The first current I1 transmitted to the first cover portion 61 is split into a second current I2 on the side of the second cover portion 62 (first trench group 52) of the resistive film 60 and a third current I3 on ​​the side of the third cover portion 63 (second trench group 53) of the resistive film 60.

[0343] The second current I2 is transmitted to the first connection region 101 of the first upper line portion 97 through multiple second resistor connection electrodes 82, and the third current I3 is transmitted to the second connection region 102 of the first upper line portion 97 through multiple third resistor connection electrodes 83. Thus, the gate wiring electrode 93 (first upper line portion 97) forms a parallel resistor circuit PR (also referred to) between itself and the gate terminal electrode 90 (second electrode portion 92), including a first gate resistor R1 and a second gate resistor R2. Figure 24 ).

[0344] The plurality of second upper lines 98A, 98B include a second upper line 98A on one side and a second upper line 98B on the other side. The second upper line 98A is disposed in the pad region 10 on one side (first side 5A side) of the second direction Y, relative to the gate terminal electrode 90. The second upper line 98B is disposed in the pad region 10 on the other side (second side 5B side) of the second direction Y, relative to the gate terminal electrode 90.

[0345] The second upper line portion 98A is formed as a strip extending along the first direction X, having one end connected to one end of the first upper line portion 97, and another end located on the peripheral side (third side surface 5C side) of the chip 2. The second upper line portion 98A covers the second lower line portion 70A of the gate wiring film 65 through the interlayer insulating film 74. The second upper line portion 98A is formed at intervals from the first electrode portion 91 of the gate terminal electrode 90 toward the second direction Y.

[0346] The second upper line portion 98B is formed as a strip extending in the first direction X, having one end connected to the other end of the first upper line portion 97, and another end located on the peripheral side (third side surface 5C side) of the chip 2. The second upper line portion 98B covers the second lower line portion 70B of the gate wiring film 65 through the interlayer insulating film 74. The second upper line portion 98B is formed at intervals from the first electrode portion 91 of the gate terminal electrode 90 toward the other side in the second direction Y, and is opposite to the second upper line portion 98A through the first electrode portion 91.

[0347] When a gate terminal electrode 90 (first electrode portion 91) is formed that partially exposes the first recess 76, and second upper wiring portions 98A and 98B intersecting the first recess 76, electrode residue generated during the formation process of the gate terminal electrode 90 may remain in the first recess 76. In the presence of electrode residue, the gate wiring electrodes 93 (second upper wiring portions 98A and 98B) may be electrically connected to the gate terminal electrode 90 (first electrode portion 91) via the electrode residue.

[0348] In this case, the gate wiring electrodes 93 (second upper line portions 98A, 98B) together with the gate terminal electrode 90 (first electrode portion 91) form a short-circuit circuit that does not pass through the gate resistor structure 50. Therefore, the second upper line portions 98A, 98B are preferably arranged at intervals from the first recess 76 and do not have a portion covering the first recess 76 (the portion intersecting with the first recess 76).

[0349] According to this structure, a layout is provided that avoids the problem of electrode residue in the first recess 76. This disclosure does not exclude the inclusion of a gate terminal electrode 90 (first electrode portion 91) partially exposing the first recess 76, and second upper line portions 98A, 98B intersecting the first recess 76. Furthermore, in the case where gate terminal electrodes 90 (first electrode portions 91) partially expose multiple third recesses 78, and second upper line portions 98A, 98B intersecting the multiple third recesses 78 are formed, electrode residue generated during the formation process of the gate terminal electrode 90 may remain in the multiple third recesses 78. In these cases, the gate wiring electrodes 93 (second upper line portions 98A, 98B) together with the gate terminal electrodes 90 (first electrode portion 91) constitute a short-circuit circuit that does not pass through the gate resistor structure 50.

[0350] Therefore, it is preferable that the second upper line portions 98A and 98B are arranged spaced apart from the plurality of third recesses 78, and do not have portions covering the plurality of third recesses 78 (the portions intersecting with the plurality of third recesses 78). According to this structure, a layout that avoids the problem of electrode residue in the plurality of third recesses 78 is provided. In this embodiment, the gate terminal electrode 90 (first electrode portion 91) covers the entire area of ​​the plurality of third recesses 78.

[0351] That is, the regions of the second upper line portions 98A and 98B above the second lower line portions 70A and 70B are opposite to the first electrode portion 91 of the gate terminal electrode 90 in the second direction Y. This disclosure does not exclude the inclusion of the gate terminal electrode 90 (first electrode portion 91) that partially exposes the plurality of third recesses 78, and the second upper line portions 98A and 98B that intersect with the plurality of third recesses 78.

[0352] Preferably, the second upper wire portions 98A and 98B, when viewed from above, cover the interior of the second lower wire portions 70A and 70B at intervals from their periphery. That is, preferably, the second upper wire portions 98A and 98B, with the interlayer insulating film 74 sandwiched between them, are only opposite to the second lower wire portions 70A and 70B, and are opposite to the main surface insulating film 45 without the interlayer insulating film 74 sandwiched between them.

[0353] The second upper wiring portion 95 extends from the first upper wiring portion 94 to the channel region 11 and covers the second lower wiring portion 67 of the gate wiring film 65 through the interlayer insulating film 74. Specifically, the second upper wiring portion 95 extends from the interior (central portion in this embodiment) of the first upper wiring portion 97 and is formed as a strip extending along the first direction X.

[0354] In this embodiment, the second upper wiring portion 95 traverses the center of the chip 2. The second upper wiring portion 95 extends in a strip-like manner relative to a straight line traversing the center of the first main surface 3 in the second direction Y, located in a region on one side (third side surface 5C side) and another side (fourth side surface 5D side) in the first direction X. The second upper wiring portion 95 has one end connected to the first upper wiring portion 94 on one side of the first direction X and another end on the other side of the first direction X. In this embodiment, the other end of the second upper wiring portion 95 is an open end.

[0355] The second upper wiring portion 95 covers a plurality of first gate connection electrodes 84A and is electrically connected to the second lower wiring portion 67 via the plurality of first gate connection electrodes 84A. The second upper wiring portion 95 has a width in the second direction Y that is smaller than the width of the channel region 11, and is formed at intervals from the plurality of active regions 6 toward the inward of the channel region 11. That is, the second upper wiring portion 95 is formed at intervals from the plurality of trench separation structures 15 (the plurality of first trench structures 21) when viewed from above.

[0356] The third upper wiring portion 96 extends from the first upper wiring portion 94 toward the outer peripheral region 9 and covers the third lower wiring portion 68 of the gate wiring film 65 through the interlayer insulating film 74. Specifically, the third upper wiring portion 96 extends from the other ends of the plurality of second upper wiring portions 98A, 98B toward one side (first side 5A side) and the other side (second side 5B side) of the outer peripheral region 9, forming a strip extending along the outer peripheral region 9.

[0357] The third upper wiring portion 96, together with the second upper wiring portion 95, encloses a plurality of active regions 6. Specifically, the third upper wiring portion 96, when viewed from above, extends along the periphery (first sides 5A-5D) of the chip 2 in a manner that surrounds the plurality of active regions 6. Thus, the third upper wiring portion 96, together with the second upper wiring portion 95, surrounds the plurality of active regions 6. In this embodiment, the third upper wiring portion 96 and the second upper wiring portion 95 are formed at intervals. The third upper wiring portion 96 may also be connected to the second upper wiring portion 95.

[0358] The third upper wiring portion 96 covers a plurality of second gate connection electrodes 84B and is electrically connected to the third lower wiring portion 68 via the plurality of second gate connection electrodes 84B. The third upper wiring portion 96 preferably has a width smaller than the width of the third lower wiring portion 68 when viewed from above. Preferably, the third upper wiring portion 96 covers the interior of the third lower wiring portion 68 at intervals from the periphery of the third lower wiring portion 68 when viewed from above.

[0359] Reference Figures 1 to 11 The semiconductor device 1A includes an emitter sub-electrode 103 disposed on a first main surface 3, spaced apart from the gate terminal electrode 90 and the gate wiring electrode 93, in the active region 6. Specifically, the emitter sub-electrode 103 is disposed on an interlayer insulating film 74. The emitter sub-electrode 103 may also be referred to as an "emitter pad" or "emitter pad electrode." The emitter sub-electrode 103 is preferably made of a conductive material different from that of the resistive film 60. The emitter sub-electrode 103 is preferably made of a conductive material different from that of the emitter electrode film 47.

[0360] The emitter sub-electrode 103 has a lower resistance value than the trench resistor structure 51 and the resistive film 60. In this embodiment, the emitter sub-electrode 103 is made of a metal film. The emitter sub-electrode 103 may also be referred to as an "emitter metal terminal". The emitter sub-electrode 103 may also include at least one of the following: Ti film, TiN film, W film, Al film, Cu film, Al alloy film, Cu alloy film, and conductive polycrystalline silicon film.

[0361] The emitter electrode 103 may also include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the emitter electrode 103 has a stacked structure comprising a Ti film and an Al alloy film (in this embodiment, an AlCu alloy film) sequentially stacked from the chip 2 side. That is, the emitter electrode 103 has the same electrode structure as the gate terminal electrode 90.

[0362] The emitter sub-electrode 103 preferably has a thickness greater than that of the resistive film 60 (the thickness of the gate electrode film 64). The thickness of the emitter sub-electrode 103 can be more than 1 μm and less than 10 μm. The thickness of the emitter sub-electrode 103 is preferably approximately equal to the thickness of the gate terminal electrode 90.

[0363] The emitter sub-electrode 103 has a planar area larger than that of the gate terminal electrode 90. The planar area of ​​the emitter sub-electrode 103 is preferably 50% or more and 90% or less of the planar area of ​​the first main surface 3. Particularly preferably, the planar area of ​​the emitter sub-electrode 103 is 70% or more of the planar area of ​​the first main surface 3.

[0364] In this embodiment, the emitter sub-electrode 103 includes a first emitter sub-electrode 103A and a second emitter sub-electrode 103B. The first emitter sub-electrode 103A is disposed in the region between the second upper wiring portion 95 and the third upper wiring portion 96, above the portion of the interlayer insulating film 74 that covers the first active region 6A. The first emitter sub-electrode 103A extends from the first active region 6A to the outer peripheral region 9 when viewed from above.

[0365] The first emitter sub-electrode 103A covers a plurality of first emitter connection electrodes 85 and a plurality of second emitter connection electrodes 86 in the first active region 6A, and covers a plurality of first well connection electrodes 87 in the outer peripheral region 9. The first emitter sub-electrode 103A is electrically connected to a plurality of second trench structures 25, a plurality of emitter regions 29 and a plurality of channel contact regions 31 via the plurality of first emitter connection electrodes 85 and the plurality of second emitter connection electrodes 86. The first emitter sub-electrode 103A is electrically connected to the inner edge of the outer peripheral well region 41 via the plurality of first well connection electrodes 87.

[0366] The second emitting electrode 103B is disposed in the region between the second upper wiring portion 95 and the third upper wiring portion 96, above the portion of the interlayer insulating film 74 that covers the second active region 6B. When viewed from above, the second emitting electrode 103B extends from the second active region 6B to the outer peripheral region 9.

[0367] The second emitter sub-electrode 103B covers a plurality of first emitter connection electrodes 85 and a plurality of second emitter connection electrodes 86 in the second active region 6B, and covers a plurality of first well connection electrodes 87 in the outer peripheral region 9. The second emitter sub-electrode 103B is electrically connected to a plurality of second trench structures 25, a plurality of emitter regions 29, and a plurality of channel contact regions 31 via the plurality of first emitter connection electrodes 85 and the plurality of second emitter connection electrodes 86. The second emitter sub-electrode 103B is electrically connected to the inner edge of the outer peripheral well region 41 via the plurality of first well connection electrodes 87.

[0368] Semiconductor device 1A includes an emitter wiring electrode 104 extending from the emitter sub-electrode 103 to the outside of the gate wiring electrode 93 on the interlayer insulating film 74. The emitter wiring electrode 104 may also be referred to as an "emitter finger" or "emitter finger electrode". The emitter wiring electrode 104 is preferably made of a different conductive material than the resistive film 60. The emitter wiring electrode 104 is preferably made of a different conductive material than the emitter electrode film 47.

[0369] The emitter wiring electrode 104 has a lower resistance value than the trench resistor structure 51 and the resistive film 60. In this embodiment, the emitter wiring electrode 104 is made of a metal film. The emitter wiring electrode 104 may also be referred to as an "emitter metal wiring". The emitter wiring electrode 104 may also include at least one of Ti film, TiN film, W film, Al film, Cu film, Al alloy film, Cu alloy film, and conductive polycrystalline silicon film.

[0370] The emitter wiring electrode 104 may also include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the emitter wiring electrode 104 has a stacked structure comprising a Ti film and an Al alloy film (in this embodiment, an AlCu alloy film) sequentially stacked from the chip 2 side. That is, the emitter wiring electrode 104 has the same electrode structure as the emitter terminal electrode 103.

[0371] The emitter wiring electrode 104 preferably has a thickness greater than that of the resistive film 60 (the thickness of the gate electrode film 64). The thickness of the emitter wiring electrode 104 may also be 1 μm or more and 10 μm or less. The thickness of the emitter wiring electrode 104 is preferably approximately equal to the thickness of the gate terminal electrode 90 (emitter terminal electrode 103).

[0372] The emitter wiring electrode 104 is connected to both the first emitter sub-electrode 103A and the second emitter sub-electrode 103B, and is led out from the first emitter sub-electrode 103A and the second emitter sub-electrode 103B to a region that is outside the gate wiring electrode 93 (third upper wiring portion 96).

[0373] The emitter wiring electrode 104 is formed as a strip extending along the periphery of the chip 2, surrounding the gate terminal electrode 90, the gate wiring electrode 93, the first emitter sub-electrode 103A, and the second emitter sub-electrode 103B. In this embodiment, the emitter wiring electrode 104 is formed as a ring (specifically a four-sided ring) extending along the periphery of the chip 2 (the first to fourth side surfaces 5A to 5D), together surrounding the gate terminal electrode 90, the gate wiring electrode 93, the first emitter sub-electrode 103A, and the second emitter sub-electrode 103B.

[0374] Emitter wiring electrode 104 is wound around a portion of the interlayer insulating film 74 covering the outer edge of the peripheral well region 41. Emitter wiring electrode 104 covers a plurality of second well connection electrodes 88 and is electrically connected to the outer edge of the peripheral well region 41 via the plurality of second well connection electrodes 88.

[0375] Reference Figure 1 , Figure 2 , Figure 10Aas well as Figure 10B The semiconductor device 1A includes a plurality of FLR electrodes 105 disposed on an interlayer insulating film 74 in an outer peripheral region 9. The plurality of FLR electrodes 105 may also include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polycrystalline silicon film.

[0376] The plurality of FLR electrodes 105 may also include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the plurality of FLR electrodes 105 have a laminated structure comprising a barrier metal film and a main metal film stacked sequentially from the chip 2 side. The barrier metal film is, for example, composed of a laminated film comprising a Ti film and a TiN film stacked sequentially from the chip 2 side. The main metal film is, for example, composed of an Al alloy film (in this embodiment, an AlCu alloy film).

[0377] Multiple FLR electrodes 105 are each formed as a strip extending along the corresponding FLR 42. In this embodiment, the multiple FLR electrodes 105 are each formed as a ring (quadrilateral ring) extending along the corresponding FLR 42. In this embodiment, the multiple FLR electrodes 105 are formed in an electrically floating state.

[0378] Each FLR electrode 105 has an electrode curve portion 105A with a circular arc shape when viewed from above at each of the four corners 201 to 204. In each of the corners 201 to 204, the inner edge 105Aa and outer edge 105Ab of all electrode curve portions 105A may also have the same center of curvature. Each electrode curve portion 105A has a straight electrode portion 105B with a straight shape when viewed from above between the four corners 201 to 204.

[0379] In this embodiment, in each corner 201-204, the inner edge 105Aa and outer edge 105Ab of all electrode curve portions 105A have the same center of curvature. Furthermore, in each corner 201-204, the center of curvature of the inner edge 105Aa and outer edge 105Ab of each electrode curve portion 105A is located on the dividing line that bisects the apex of the corner. For example, the dividing line that bisects the apex of the second corner 202 is used, for example, in the description of the modified examples described later. Figure 25 L0 is used to represent it.

[0380] Furthermore, in each corner section 201-204, the inner edge 105Aa and outer edge 105Ab of all electrode curve portions 105A may not have the same center of curvature. Additionally, in each corner section 201-204, the center of curvature of the inner edge 105Aa and outer edge 105Ab of each electrode curve portion 105A may not be located on the line dividing the apex of that corner section into half, i.e., on the dividing line.

[0381] Multiple FLR electrodes 105 are positioned opposite corresponding FLR 42s. Each FLR electrode 105 also covers the corresponding multiple FLR connection electrodes 89. Each FLR electrode 105 is electrically connected to its corresponding FLR 42 via the corresponding multiple FLR connection electrodes 89. The FLR connection electrodes 89 may also be integrally formed with the corresponding FLR electrode 105. The multiple FLR electrodes 105 are configured to be electrically floating.

[0382] Reference Figure 1 , Figure 10A as well as Figure 10B The semiconductor device 1A includes a channel blocking electrode 106 disposed on an interlayer insulating film 74 in the outer peripheral region 9. The channel blocking electrode 106 is an "EQR (EQui-potential ring) electrode". The channel blocking electrode 106 may also include at least one selected from Ti film, TiRiN film, W film, Al film, Cu film, Al alloy film, Cu alloy film, and conductive polycrystalline silicon film.

[0383] The channel barrier electrode 106 may include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the channel barrier electrode 106 has a laminated structure comprising a barrier metal film and a main metal film sequentially stacked from the chip 2 side. The barrier metal film is, for example, composed of a laminated film comprising a Ti film and a TiN film sequentially stacked from the chip 2 side. The main metal film is, for example, composed of an Al alloy film (in this embodiment, an AlCu alloy film).

[0384] The channel blocking electrode 106 is formed as a strip extending along the periphery of the chip 2. In this embodiment, the channel blocking electrode 106 is formed as a ring (quadrilateral ring) extending along the periphery of the chip 2. The channel blocking electrode 106 enters the removal portion 46 of the interlayer insulating film 74 from above the interlayer insulating film 74 and is electrically connected to the channel blocking region 43. The channel blocking electrode 106 is formed in an electrically floating state. The channel blocking region 43 may also be formed at intervals from the periphery of the chip 2 inward, such that the periphery of the first main surface 3 (channel blocking region 43) is exposed.

[0385] Semiconductor device 1A includes a collector electrode 107 covering a second main surface 4. The collector electrode 107 is electrically connected to a collector region 14 exposed from the second main surface 4. The collector electrode 107 forms an ohmic contact with the collector region 14. The collector electrode 107 may also cover the entire area of ​​the second main surface 4 in a manner connected to the periphery (first to fourth sides 5A to 5D) of the chip 2.

[0386] Semiconductor device 1A includes a chip 2, a trench resistor structure 51, a resistive film 60, a gate terminal electrode 90, and a gate wiring electrode 93. The chip 2 has a first main surface 3. The trench resistor structure 51 is formed on the first main surface 3. The resistive film 60 is electrically connected to the trench resistor structure 51 on the first main surface 3.

[0387] The gate terminal electrode 90 has a lower resistance value than the resistive film 60 and is electrically connected to the trench resistor structure 51 on the first main surface 3 via the resistive film 60. The gate wiring electrode 93 has a lower resistance value than the resistive film 60 and is electrically connected to the gate terminal electrode 90 on the first main surface 3 via the trench resistor structure 51 and the resistive film 60.

[0388] According to this structure, a gate resistor RG, including a trench resistor structure 51 and a resistive film 60, can be sandwiched between the gate terminal electrode 90 and the gate wiring electrode 93. In particular, according to this structure, since the trench resistor structure 51 is assembled into the chip 2 in the region between the gate terminal electrode 90 and the gate wiring electrode 93, the increase in the proprietary area of ​​the gate resistor RG relative to the first main surface 3 can be suppressed. Therefore, in the structure with the gate resistor RG, a semiconductor device 1A with a novel layout that facilitates miniaturization can be provided.

[0389] Semiconductor device 1A preferably includes a gate electrode film 64 and a gate wiring film 65. The gate electrode film 64 is disposed adjacent to the resistive film 60 on the first main surface 3. The gate wiring film 65 is disposed adjacent to the resistive film 60 on the first main surface 3, facing the gate electrode film 64 with the resistive film 60 separated from it.

[0390] In this structure, the gate terminal electrode 90 preferably covers the gate electrode film 64. Additionally, the gate wiring electrode 93 preferably covers the gate wiring film 65. According to this structure, a semiconductor device 1A with a novel layout that facilitates miniaturization can be provided, comprising the resistive film 60, the gate electrode film 64, and the gate wiring film 65 on the first main surface 3.

[0391] The resistive film 60 preferably has a first end 60A on one side and a second end 60B on the other side. In this case, the gate wiring film 65 preferably has a first connection portion connected to the first end 60A of the resistive film 60 and a second connection portion connected to the second end 60B of the resistive film 60. In this case, the gate wiring electrode 93 is preferably electrically connected to the resistive film 60 via the gate wiring film 65.

[0392] According to this structure, the gate wiring electrode 93 can be electrically connected to the resistive film 60 via the gate wiring film 65, thus eliminating the need for direct connection between the gate wiring electrode 93 and the resistive film 60. This simplifies the design rules for the gate wiring electrode 93 and increases the design freedom of the gate wiring electrode 93.

[0393] Semiconductor device 1A preferably includes a first slit 71 dividing the resistive film 60 and the gate electrode film 64, and a second slit 72 dividing the resistive film 60 and the gate wiring film 65. According to this structure, the resistive film 60 can be appropriately separated (divided) from the gate electrode film 64 and the gate wiring film 65 through the first slit 71 and the second slit 72. Therefore, the accuracy of the resistance value of the resistive film 60 can be improved.

[0394] The gate terminal electrode 90 preferably crosses the first slit 71 and covers the resistive film 60 and the gate electrode film 64 when viewed from above. The gate wiring film 65 preferably crosses the second slit 72 and covers the resistive film 60 and the gate electrode film 64 when viewed from above. The first slit 71 is preferably formed to be narrower than the resistive film 60. The second slit 72 is preferably formed to be narrower than the width of the resistive film 60.

[0395] Preferably, the trench resistor structure 51 extends in a strip shape along the second direction Y (one direction) when viewed from above. In this case, the resistive film 60 preferably extends in a strip shape along the second direction Y (one direction) when viewed from above. Additionally, the first slit 71 preferably extends in a strip shape along the second direction Y (one direction) when viewed from above. Furthermore, the second slit 72 preferably extends in a strip shape along the second direction Y (one direction) when viewed from above. Alternatively, the first slit 71 may have a first length in the second direction Y (one direction), and the second slit 72 may have a second length in the second direction Y (one direction) that is smaller than the first length.

[0396] Semiconductor device 1A preferably includes a third slit 73 dividing the gate electrode film 64 and the gate wiring film 65. According to this structure, the gate wiring film 65 can be appropriately separated (divided) from the gate electrode film 64 through the third slit 73. This prevents the gate wiring film 65 and the gate electrode film 64 from forming a short-circuit circuit that does not pass through the resistive film 60. The gate terminal electrode 90 preferably traverses the third slit 73 when viewed from above, covering both the gate electrode film 64 and the gate wiring film 65.

[0397] Preferably, multiple trench resistor structures 51 are formed at intervals on the first main surface 3. In this case, the resistive film 60 preferably covers the multiple trench resistor structures 51. According to this structure, the resistance value of the gate resistor RG can be adjusted using the multiple trench resistor structures 51.

[0398] The resistive film 60 preferably has a first covering portion 61 covering the first main surface 3 outside the trench resistive structure 51 and a second covering portion 62 covering the trench resistive structure 51. In this case, the gate terminal electrode 90 is preferably electrically connected to the resistive film 60 in the portion covering the first covering portion 61. Additionally, the gate wiring electrode 93 is preferably electrically connected to the resistive film 60 in the portion covering the second covering portion 62. According to this structure, a portion of the resistive film 60 and a portion of the trench resistive structure 51 can be appropriately located in the region between the gate terminal electrode 90 and the gate wiring electrode 93.

[0399] Semiconductor device 1A preferably includes an interlayer insulating film 74, a first resistive connection electrode 81, and a second resistive connection electrode 82. The interlayer insulating film 74 covers the resistive film 60. The first resistive connection electrode 81 is embedded in the interlayer insulating film 74 in a manner that is electrically connected to the resistive film 60. The second resistive connection electrode 82 is embedded in the interlayer insulating film 74 in a manner that is electrically connected to the resistive film 60 at a different location than the first resistive connection electrode 81.

[0400] In this structure, the gate terminal electrode 90 is preferably disposed on the interlayer insulating film 74 in a manner electrically connected to the resistive film 60 via the first resistive connection electrode 81. Furthermore, the gate wiring electrode 93 is preferably disposed on the interlayer insulating film 74 in a manner electrically connected to the resistive film 60 via the second resistive connection electrode 82. According to this structure, a gate resistor RG can be formed in the region between the first resistive connection electrode 81 and the second resistive connection electrode 82. The resistance value of the gate resistor RG can be adjusted by adjusting the distance between the first resistive connection electrode 81 and the second resistive connection electrode 82.

[0401] The second resistive connection electrode 82 may also extend in a different direction than the first resistive connection electrode 81. For example, the first resistive connection electrode 81 may extend in a first direction X (one direction) when viewed from above, and the second resistive connection electrode 82 may extend in a second direction Y (intersecting direction) that intersects the first direction X (one direction) when viewed from above.

[0402] Preferably, a plurality of first resistive connection electrodes 81 are embedded in the interlayer insulating film 74. Preferably, a plurality of second resistive connection electrodes 82 are embedded in the interlayer insulating film 74. The second connection area S2 of the second resistive connection electrode 82 relative to the resistive film 60 may be smaller than the first connection area S1 of the first resistive connection electrode 81 relative to the resistive film 60.

[0403] The gate terminal electrode 90 preferably has a first electrode portion 91 located outside the first resistive connection electrode 81 when viewed from above, and a second electrode portion 92 that protrudes from the first electrode portion 91 toward the first resistive connection electrode 81 in a narrower manner than the first electrode portion 91. In this case, the first electrode portion 91 is preferably formed as a terminal body portion of the gate terminal electrode 90. In addition, the second electrode portion 92 is preferably formed as a terminal lead-out portion extending from the terminal body portion.

[0404] Based on these structures, it is possible to ensure that the region where the gate potential is imparted by the first electrode portion 91 is also ensured, as is the region where the second electrode portion 92 is electrically connected to the resistive film 60. For example, when a conductive bonding material such as a bonding wire is bonded to the gate terminal electrode 90, this conductive bonding material can be bonded to the first electrode portion 91. This suppresses stress caused by the conductive bonding material in the resistive film 60 and the trench resistance structure 51. Therefore, it is possible to suppress the degradation of the electrical characteristics of the gate resistance RG.

[0405] Semiconductor device 1A preferably includes a p-type boundary well region 40 formed on the surface portion of the first main surface 3. According to this structure, the breakdown voltage can be increased through the boundary well region 40. In this case, trench resistor structures 51 are preferably formed at intervals from the bottom of the boundary well region 40 toward the first main surface 3. According to this structure, electric field concentration relative to the bottom wall of the trench resistor structure 51 can be suppressed through the boundary well region 40. Therefore, the breakdown voltage can be appropriately increased.

[0406] Semiconductor device 1A preferably includes an active region 6 disposed on a first main surface 3, an active region 7 disposed on the first main surface 3 outside the active region 6, and a first trench structure 21 (trench gate structure) formed in the active region 6. In this case, a trench resistor structure 51 is preferably formed in the active region 7. In addition, a resistive film 60 preferably covers the trench resistor structure 51 in the active region 7.

[0407] Furthermore, the gate terminal electrode 90 is preferably electrically connected to the resistive film 60 in the non-active region 7. Additionally, the gate wiring electrode 93 is preferably electrically connected to the first trench structure 21 in the active region 6 and to the resistive film 60 in the non-active region 7. Based on these structures, a gate resistor RG is formed in the non-active region 7, thereby suppressing shrinkage of the active region 6.

[0408] Figure 25 This is a schematic top view used to illustrate a modified example of FLR42, FLR electrode 105 and FLR connecting electrode 89, and is a schematic top view mainly showing the structure of the second corner 202 of the outer peripheral region 9. Figure 26 It is along Figure 25 The diagram shows a cross-sectional view of the XXVI-XXVI line.

[0409] exist Figure 25 For ease of explanation, structures other than FLR42 and FLR electrode 105 (such as peripheral well region 41, channel blocking region 43, and channel blocking electrode 106) are omitted. However, for clarity, Figure 26 The channel blocking electrode 106 is shown.

[0410] Multiple FLRs 42 are formed in a ring shape (quadrilateral ring shape) in the outer peripheral region 9, surrounding the active region 6. Each FLR 42 has an arc-shaped FLR curve portion 42A at each of the four corners 201-204, with an inner edge 42Aa and an outer edge 42Ab. Each FLR 42 has a straight FLR portion 42B between the four corners 201-204, which is straight in shape when viewed from above.

[0411] Each FLR curve portion 42A has a dual diffusion structure comprising an inner first diffusion region 301 and an outer second diffusion region 302 with a lower p-type impurity concentration than the first diffusion region 301. Each FLR straight section 42B has a single diffusion structure consisting only of diffusion regions having the same p-type impurity concentration as the first diffusion region 301. Detailed structures of the multiple FLRs 42 are described later.

[0412] Multiple FLR electrodes 105 are formed as strips extending along their respective FLR 42. Multiple FLR electrodes 105 are formed as rings (quadrilateral rings) extending along their respective FLR 42. Multiple FLR electrodes 105 are formed in an electrically floating state.

[0413] Multiple FLR electrodes 105 are positioned opposite the corresponding FLR 42 through a laminated film consisting of a main insulating film 45 and an interlayer insulating film 74. In this modified example, the multiple FLR electrodes 105 cover the corresponding FLR 42.

[0414] Each FLR electrode 105 has an electrode curve portion 105A at each of its four corners 201-204, the inner and outer edges of which are arc-shaped when viewed from above. Each FLR electrode 105 also has a straight electrode portion 105B between the four corners 201-204, the shape of which is straight when viewed from above.

[0415] In each corner portion 201 to 204, each electrode curve portion 105A has its own center of curvature and its own inner edge 105Aa and outer edge 105Ab with different curvatures. In addition, between two adjacent electrode curve portions 105A, the curvatures of the inner edge 105Aa and the outer edge 105Ab are in opposite order.

[0416] Reference Figure 25 as well as Figure 26The structure of the FLR electrode 105 at the second corner 202 will be described.

[0417] In the second corner 202, the center of curvature of the inner edge 105Aa and the center of curvature of the outer edge 105Ab of each electrode curve portion 105A are located at different positions on the dividing line L0, which divides the apex of the second corner 202 into half, and the radius of curvature of the inner edge 105Aa and the outer edge 105Ab are different. Moreover, between two adjacent electrode curve portions 105A, the magnitudes of the curvatures of the inner edge 105Aa and the outer edge 105Ab are opposite to each other.

[0418] exist Figure 25 In the example, the center of curvature of the inner edge 105Aa of the innermost electrode curve portion 105A is Q1, and the center of curvature of the outer edge 105Ab of the same electrode curve portion 105A is Q2. The radius of curvature of the inner edge 105Aa is r1, and the radius of curvature of the outer edge 105Ab is r2 (r2 > r1). Therefore, the curvature of the inner edge 105Aa is greater than the curvature of the outer edge 105Ab.

[0419] The center of curvature of the inner edge 105Aa of the second electrode curve portion 105A from the inside is Q2, and the center of curvature of the outer edge 105Ab of the same electrode curve portion 105A is Q1. The radius of curvature of the inner edge 105Aa is larger than that of the outer edge 105Ab. Therefore, the curvature of the inner edge 105Aa is smaller than that of the outer edge 105Ab.

[0420] The center of curvature of the inner edge 105Aa of the third electrode curve portion 105A from the inside is Q1, and the center of curvature of the outer edge 105Ab of the same electrode curve portion 105A is Q2. The radius of curvature of the inner edge 105Aa is smaller than that of the outer edge 105Ab. Therefore, the curvature of the inner edge 105Aa is greater than that of the outer edge 105Ab.

[0421] The center of curvature of the inner edge 105Aa of the outermost electrode curve portion 105A is Q2, and the center of curvature of the outer edge 105Ab of the same electrode curve portion 105A is Q1. The radius of curvature of the inner edge 105Aa is larger than that of the outer edge 105Ab. Therefore, the curvature of the inner edge 105Aa is smaller than that of the outer edge 105Ab.

[0422] Each electrode curve portion 105A has a wide region and a narrow region between its inner edge 105Aa and outer edge 105Ab. Moreover, a portion of the wide region in each electrode curve portion 105A is physically and electrically connected to the corresponding FLR 42 via an FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.

[0423] Specifically, in the innermost electrode curve portion 105A and the third electrode curve portion 105A from the innermost side, the width is narrowest at the center of the length, and the width increases towards both ends from the center of the length. Therefore, these electrode curve portions 105A have wide portions 211 at both ends.

[0424] On the other hand, among the second electrode curve portion 105A from the inside and the outermost electrode curve portion 105A, the width is widest at the center of its length, and the width narrows towards both ends from the center of its length. Therefore, these electrode curve portions 105A have a wide portion 211 at the center of their length.

[0425] In the second corner 202, relative to the straight line connecting the curvature center Q1 and the vertex of the second corner 202, the counterclockwise angle centered on the curvature center Q1 is set as negative, and the clockwise angle centered on the curvature center Q1 is set as positive.

[0426] In this modified example, at the second corner 202, on a straight line L1 with a rotation angle of -45 degrees relative to the straight line connecting the curvature center Q1 and the vertex of the second corner 202, one end of the inner edge 105Aa and the outer edge 105Ab of each electrode curve portion 105A is disposed.

[0427] In addition, in this modified example, on the second corner 202, on a straight line L2 with an angle of +45 degrees relative to the straight line connecting the curvature center Q1 and the vertex of the second corner 202, the other end of the inner edge 105Aa and the outer edge 105Ab of each electrode curve portion 105A are arranged.

[0428] exist Figure 25 In the example, the widths of the innermost electrode curve portion 105A and the two ends of the third electrode curve portion 105A from the inside are greater than the widths of the two ends of the second electrode curve portion 105A from the inside and the outermost electrode curve portion 105A, respectively.

[0429] The width of the straight portion 105B of the electrode connected to both ends of each electrode curve portion 105A is equal to the width of both ends of the electrode curve portion 105A.

[0430] The structure of FLR42 will be described in detail below.

[0431] At each corner 201-204, each FLR curve portion 42A has its own center of curvature and its own inner edge 42Aa and outer edge 42Ab, which have different centers of curvature. Furthermore, between two adjacent FLR curve portions 42A, the curvature of the inner edge 42Aa and the outer edge 42Ab are in opposite order.

[0432] Reference Figure 25 as well as Figure 26 The structure of FLR42 in the second corner 202 will be explained.

[0433] In the second corner 202, the center of curvature of the inner edge 42Aa and the center of curvature of the outer edge 42Ab of each FLR curve portion 42A are located at different positions on the dividing line L0, which divides the apex of the second corner 202 into half, and the radius of curvature of the inner edge 42Aa and the outer edge 42Ab are different. Moreover, between two adjacent FLR curve portions 42A, the magnitudes of the curvatures of the inner edge 42Aa and the outer edge 42Ab are opposite to each other.

[0434] exist Figure 25 In the example, the center of curvature of the innermost FLR curve portion 42Aa is Q1, and the center of curvature of the outermost edge 42Ab is Q2. The radius of curvature of the inner edge 42Aa is smaller than that of the outer edge 42Ab. Therefore, the curvature of the inner edge 42Aa is greater than that of the outer edge 42Ab.

[0435] The center of curvature of the inner edge 42Aa of the second FLR curve portion 42A from the inside is Q2, and the center of curvature of the outer edge 42Ab is Q1. The radius of curvature of the inner edge 42Aa is larger than that of the outer edge 42Ab. Therefore, the curvature of the inner edge 42Aa is smaller than that of the outer edge 42Ab.

[0436] The center of curvature of the inner edge 42Aa of the third FLR curve segment 42A from the inside is Q1, and the center of curvature of the outer edge 42Ab is Q2. The radius of curvature of the inner edge 42Aa is smaller than that of the outer edge 42Ab. Therefore, the curvature of the inner edge 42Aa is greater than that of the outer edge 42Ab.

[0437] The center of curvature of the inner edge 42Aa of the outermost FLR curve portion 42A is Q2, and the center of curvature of the outer edge 42Ab is Q1. The radius of curvature of the inner edge 42Aa is larger than that of the outer edge 42Ab. Therefore, the curvature of the inner edge 42Aa is smaller than that of the outer edge 42Ab.

[0438] In this modified example, the center of curvature of the inner edge 42Aa of each FLR curve portion 42A coincides with the center of curvature of the inner edge 105Aa of the corresponding electrode curve portion 105A. Similarly, the center of curvature of the outer edge 42Ab of each FLR curve portion 42A coincides with the center of curvature of the outer edge 105Ab of the corresponding electrode curve portion 105A.

[0439] Furthermore, when viewed from above, the inner edge 42Aa of each FLR curve portion 42A is recessed towards the inside of the corresponding electrode curve portion 105A, and the outer edge 42Ab of each FLR curve portion 42A is recessed towards the inside of the corresponding electrode curve portion 105A, compared to the outer edge 105Ab of the corresponding electrode curve portion 105A. Therefore, the width of each FLR curve portion 42A at each length direction position is narrower than the width of the corresponding electrode curve portion 105A at the corresponding length direction position.

[0440] Furthermore, the inner edge 42Aa of each FLR curve portion 42A may extend outward from the inner edge 105Aa of the corresponding electrode curve portion 105A. Additionally, the outer edge 42Ab of each FLR curve portion 42A may extend outward from the outer edge 105Ab of the corresponding electrode curve portion 105A.

[0441] Alternatively, either the inner edge 42Aa or the outer edge 42Ab of each FLR curve portion 42A may extend to a position outside the corresponding side edge 105Aa or 105Ab of the corresponding electrode curve portion 105A. Alternatively, both the inner edge 42Aa and the outer edge 42Ab of each FLR curve portion 42A may extend to a position outside the corresponding side edge 105Aa or 105Ab of the corresponding electrode curve portion 105A.

[0442] In the innermost FLR curve portion 42A and the third FLR curve portion 42A from the innermost side, the width is narrowest at the center of the length, and the width increases towards both ends from the center of the length. Therefore, these FLR curve portions 42A have wide portions 221 at both ends.

[0443] On the other hand, in the second FLR curve portion 42A from the inside and the outermost FLR curve portion 42A, the width is widest at the center of the length, and the width narrows towards both ends from the center of the length. Therefore, these FLR curve portions 42A have a wide portion 221 at the center of the length.

[0444] In this modified example, at the second corner 202, one end of the inner edge 42Aa and the outer edge 42Ab of each FLR curve portion 42A is positioned on the straight line L1.

[0445] In addition, in this embodiment, at the second corner 202, the other ends of the inner edge 42Aa and the outer edge 42Ab of each FLR curve portion 42A are arranged on the straight line L2.

[0446] exist Figure 25 In the example, the widths of the innermost FLR curve portion 42A and the two ends of the third FLR curve portion 42A from the inside are greater than the widths of the two ends of the second FLR curve portion 42A from the inside and the outermost FLR curve portion 42A, respectively.

[0447] The width of the straight FLR portion 42B connected to both ends of each FLR curved portion 42A is equal to the width of both ends of the FLR curved portion 42A.

[0448] In this modified example, the diffusion region boundary line BL in each FLR curve portion 42A has the same center of curvature as the center of curvature of the inner edge 42Aa of the FLR curve portion 42A. Alternatively, the diffusion region boundary line BL in each FLR curve portion 42A may also have the same center of curvature as the center of curvature of the outer edge 42Ab of the FLR curve portion 42A.

[0449] In this modified example, the width of the first diffusion region 301 in the first diffusion region 301 and the second diffusion region 302 in each FLR curve portion 42A is constant in the length direction. Alternatively, the width of the second diffusion region 301 in the first diffusion region 301 and the second diffusion region 302 in each FLR curve portion 42A may also be constant in the length direction.

[0450] Furthermore, in this modified example, the top view shape of the boundary line BL between the first diffusion region 301 and the second diffusion region 302 of each FLR curve portion 42A is an arc having the same center of curvature as the inner edge of the corresponding first electrode curve portion 105A.

[0451] In the innermost electrode curve portion 105A and the third electrode curve portion 105A from the innermost side, a portion of the wide portion 211 at both ends is physically and electrically connected to the wide portion 221 at both ends of the corresponding FLR curve portion 42A via an FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.

[0452] In the second electrode curve portion 105A from the inside and the outermost electrode curve portion 105A, a portion of the central length of the wide portion 211 is physically and electrically connected to the central length of the wide portion 221 of the corresponding FLR curve portion 42A via an FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.

[0453] In this modified example, the FLR connection electrode 89 is not formed on the portion of the plurality of FLR electrodes 105 other than the electrode curve portion 105A (electrode straight portion 105B). Alternatively, the FLR connection electrode 89 may be formed on the electrode straight portion 105B of the plurality of FLR electrodes 105. The FLR connection electrode 89 may also be integrally formed with the corresponding FLR electrode 105 (electrode curve portion 105A).

[0454] The plurality of FLR connection electrodes 89 are circular when viewed from above. The plurality of FLR connection electrodes 89 may also be polygonal (such as quadrilaterals) or elliptical when viewed from above. In this embodiment, the plurality of FLR connection electrodes 89 are formed in an electrically floating state.

[0455] In this modified example, the FLR42, FLR electrode 105, and FLR connection electrode 89 in the first corner 201 have a top view shape that is symmetrical with respect to the straight line extending along the second direction Y relative to the center of the first direction X through the chip 2 and the top view shape line of the second corner 202.

[0456] In this modified example, the FLR42, FLR electrode 105, and FLR connection electrode 89 in the third corner 203 have a top view shape that is symmetrical with respect to the straight line extending along the first direction X relative to the center of the second direction Y through the chip 2 and the top view shape line of the second corner 202.

[0457] In this modified example, the FLR42, FLR electrode 105, and FLR connection electrode 89 in the fourth corner 204 have a top view shape that is symmetrical with respect to the straight line extending along the second direction Y relative to the center of the first direction X through the chip 2 and the top view shape line of the third corner 203.

[0458] In addition, such as Figure 27 As shown, the shape of each FLR curve portion 42A can also be different from the corresponding electrode curve portion 105A. Figure 27 This is a schematic top view showing the structure of the FLR42, FLR electrode 108, and FLR connecting electrode 89 in the second corner 202.

[0459] exist Figure 27 In the top view, the shape of multiple electrode curve sections 105A is similar to... Figure 25 Their top-view shapes are the same. Figure 27 In this model, the inner edge 42Aa, outer edge 42Ab, and diffusion region boundary line BL of multiple FLR curve segments 42A share the same curvature center. Specifically, their curvature center is Q2.

[0460] In the three corners 201, 202, and 203 other than the second corner 202, the multiple electrode curve portions 105A and the multiple FLR curve portions 42A also have the same structure as those in the second corner 202.

[0461] exist Figure 27 In the FLR curve portion 42A, the width of the first diffusion region 301 is constant in the length direction, and the width of the second diffusion region 302 is constant in the length direction.

[0462] In addition, Figure 27 In the first electrode curve portion 105A, the innermost and the third FLR curve portion 42A from the innermost side have inner edges 42Aa and outer edges 42Ab that have the same center of curvature as the outer edge 105Ab of the corresponding first electrode curve portion 105A. On the other hand, the inner edges 42Aa and outer edges 42Ab of the second and outermost FLR curve portions 42A from the innermost side have the same center of curvature as the inner edge 105Aa of the corresponding first electrode curve portion 105A.

[0463] Additionally, the top view shape of the FLR42, FLR electrode 105, and FLR connecting electrode 89 in the second corner 202 can also be... Figure 28 The top view shape shown. Figure 28 In the middle, to and Figure 25 The corresponding part labels and Figure 25 The same symbols are used to represent them.

[0464] Figure 28 The structure of each electrode curve portion of 105A and Figure 25 The structure of the corresponding electrode curve portion 105A is roughly the same, but the positions of the two ends of each electrode curve portion 105A are different. Figure 25 The positions of the two ends of the corresponding electrode curve portion 105A are different.

[0465] exist Figure 28 In this process, the angle formed by the straight line connecting one end of the inner edge 105Aa of each electrode curve portion 105A and the center of curvature of the inner edge 105Aa with the dividing line L0, and the angle formed by the straight line connecting one end of the outer edge 105Ab of each electrode curve portion 105A and the center of curvature of the outer edge 105Ab with the dividing line L0, are set such that the width of one end of each electrode curve portion 105A is a predetermined width W1.

[0466] In addition, the angle formed by the straight line connecting the other end of the inner edge 105Aa of each electrode curve portion 105A and the center of curvature of the inner edge 105Aa and the dividing line L0, and the angle formed by the straight line connecting the other end of the outer edge 105Ab of each electrode curve portion 105A and the center of curvature of the outer edge 105Ab and the dividing line L0, are set such that the width of the other end of each electrode curve portion 105A is a predetermined width W1.

[0467] The width of the straight portion 105B of the electrode, which is connected to both ends of each electrode curve portion 105A, is also formed to a predetermined width W1.

[0468] Figure 28 The structure of each FLR curve section 42A and Figure 25 The structure of the corresponding FLR curve portion 42A is roughly the same, but the positions of the two ends of each FLR curve portion 42A are different. Figure 25 The positions of the two ends of the corresponding FLR curve portion 42A are different.

[0469] exist Figure 28 In this context, the angle formed by the straight line connecting one end of the inner edge 42Aa of each FLR curve portion 42A and the center of curvature of the inner edge 42Aa with the dividing line L0, and the angle formed by the straight line connecting one end of the outer edge 42Ab of each FLR curve portion 42A and the center of curvature of the outer edge 42Ab with the dividing line L0, are set such that the width of one end of each FLR curve portion 42A becomes a predetermined width.

[0470] Furthermore, the angle formed by the straight line connecting the other end of the inner edge 42Aa of each FLR curve portion 42A and the center of curvature of the inner edge 42Aa with the dividing line L0, and the angle formed by the straight line connecting the other end of the outer edge 42Ab of each FLR curve portion 42A and the center of curvature of the outer edge 42Ab with the dividing line L0, are set as the width of the other end of each FLR curve portion 42A as a predetermined width.

[0471] In this modified example, the width of the FLR straight section 42B connected to both ends of each FLR curve section 42A is equal to the width of the corresponding end of the first diffusion region 301 of the FLR curve section 42A.

[0472] exist Figure 28 In the structure, also with Figure 25 Similarly, the diffusion region boundary line BL of each FLR curve portion 42A has the same center of curvature as the center of curvature of the inner edge 42Aa of the FLR curve portion 42A. Alternatively, the diffusion region boundary line BL of each FLR curve portion 42A may also have the same center of curvature as the center of curvature of the outer edge 42Ab of the FLR curve portion 42A.

[0473] exist Figure 28 In the structure, for example, even if the width of the straight portion 105B of the FLR electrode 105 is narrower than the width required to connect the straight portion 105B of the electrode to the FLR 42 via the FLR connection electrode 89, it is easy to ensure the area for connecting to the FLR 42 via the FLR connection electrode 89 in the curved portion 105A of the electrode.

[0474] In other words, the width of the straight portion 105B of the FLR electrode 105 can be narrower than the width of the straight portion 105B connected to the FLR 42 via the FLR connection electrode 89. This allows for a narrower overall width of the multiple FLR electrodes 105, thus enabling chip miniaturization.

[0475] In addition, such as Figure 29 As shown, the shape of each FLR curve portion 42A can also be different from the corresponding electrode curve portion 105A. Figure 29 This is a schematic top view showing the structure of the FLR42, FLR electrode 108, and FLR connecting electrode 89 in the second corner 202.

[0476] exist Figure 29 In the top view, the shape of multiple electrode curve sections 105A is similar to... Figure 28 Their top-view shapes are the same. Figure 29 In this model, the inner edge 42Aa, outer edge 42Ab, and diffusion region boundary line BL of multiple FLR curve segments 42A share the same curvature center. Specifically, their curvature center is Q2.

[0477] exist Figure 29 In the FLR curve portion 42A, the width of the first diffusion region 301 is constant in the length direction, and the width of the second diffusion region 302 is constant in the length direction.

[0478] In addition, Figure 29 In the first electrode curve portion 105A, the innermost and the third FLR curve portion 42A from the innermost side have inner edges 42Aa and outer edges 42Ab that have the same center of curvature as the outer edge 105Ab of the corresponding first electrode curve portion 105A. On the other hand, the inner edges 42Aa and outer edges 42Ab of the second and outermost FLR curve portions 42A from the innermost side have the same center of curvature as the inner edge 105Aa of the corresponding first electrode curve portion 105A.

[0479] In the three corners 201, 202, and 203 other than the second corner 202, the multiple electrode curve portions 105A and the multiple FLR curve portions 42A also have the same structure as those in the second corner 202.

[0480] Figures 30A to 30D This is a schematic top view used to illustrate another modified example of FLR42, FLR electrode 105 and FLR connecting electrode 89, and is a schematic top view mainly showing the structure of the four corners 201 to 204 of the outer peripheral region 9. Figure 31 It is along Figure 30B A graphical sectional view of line XXXI-XXXI shown. Figures 30A to 30D For ease of explanation, structures other than FLR42 and FLR electrode 105 (such as peripheral well region 41, channel blocking region 43, and channel blocking electrode 106) are omitted. However, for clarity, Figure 31 The channel blocking electrode 106 is shown.

[0481] Reference Figures 30A to 30D as well as Figure 31 Multiple FLRs 42 are formed in a ring shape (quadrilateral ring shape) in the outer peripheral region 9 to surround the active region 6. Each FLR 42 has an arc-shaped FLR curve portion 42A at each of the four corners 201-204, with an inner edge 42Aa and an outer edge 42Ab. Each FLR 42 has a straight FLR portion 42B between the four corners 201-204, which is straight in shape when viewed from above.

[0482] Each FLR curve portion 42A has a dual diffusion structure comprising an inner first diffusion region 301 and an outer second diffusion region 302 with a lower p-type impurity concentration than the first diffusion region 301. Each FLR straight line portion 42B has a single diffusion structure consisting only of diffusion regions having the same p-type impurity concentration as the first diffusion region 301.

[0483] Multiple FLR electrodes 105 are formed as strips extending along their respective FLR 42. Multiple FLR electrodes 105 are formed as rings (quadrilateral rings) extending along their respective FLR 42. Multiple FLR electrodes 105 are formed in an electrically floating state.

[0484] Multiple FLR electrodes 105 are positioned opposite the corresponding FLR 42 through a laminated film consisting of a main insulating film 45 and an interlayer insulating film 74. In this modified example, the multiple FLR electrodes 105 cover the corresponding FLR 42.

[0485] Each FLR electrode 105 has an electrode curve portion 105A at each corner 201-204, the inner and outer edges of which are arc-shaped when viewed from above. Each FLR electrode 105 also has a straight electrode portion 105B between the four corners 201-204, the shape of which is straight when viewed from above.

[0486] In this modified example, in each corner 201 to 204, the center of curvature of the inner edge 105Aa and the outer edge 105Ab of each electrode curve portion 105A exists on the straight line L0 that divides the apex of the corner 201 to 204 into half.

[0487] In this embodiment, the multiple electrode straight portions 105B between corners 201 and 204 have the same width and the same spacing.

[0488] In this modified example, at each corner 201 to 204, the center of curvature of the inner edge 42Aa and the outer edge 42Ab of each FLR curve portion 42A exists on the straight line L0 that divides the apex of the corner 201 to 204 into half.

[0489] In this variation, the multiple FLR straight sections 42B between corners 201 and 204 have the same width and the same spacing.

[0490] In this modified example, the two side edges of the plurality of FLR straight portions 42B between corners 201 and 204 are recessed inwards from the corresponding side edges of the corresponding electrode straight portion 105B when viewed from above. Therefore, in this embodiment, the width of the FLR straight portion 42B is narrower than the width of the corresponding electrode straight portion 105B.

[0491] Hereinafter, the structure in which the inner edge 105Aa and outer edge 105Ab of the four electrode curve portions 105A in each corner portion 201 to 204 have the same curvature center and the width and spacing of these electrode curve portions 105A are the same as the width and spacing of the corresponding four electrode straight portions 105B is called the basic electrode corner structure.

[0492] In addition, the structure in which the inner edge 42Aa and outer edge 42Ab of the four FLR curve portions 42A in each corner 201, 202, 203, and 204 have the same curvature center and the width and spacing of these FLR curve portions 42A are constant is called the basic FLR corner structure.

[0493] The electrode curve portions 105A of multiple FLR electrodes 105 are physically and electrically connected to the corresponding FLR curve portions 42A of FLR 42 via FLR connection electrodes 89 that continuously penetrate the interlayer insulating film 74 and the main surface insulating film 45 at predetermined connection positions of each FLR electrode 105.

[0494] First, refer to Figure 30A The structure of the FLR electrode 105, FLR 42 and FLR connection electrode 89 at the first corner 201 will be described.

[0495] In the first corner 201, the innermost electrode curve portion 105A among the four electrode curve portions 105A has a different structure from the corresponding electrode curve portion of the basic electrode corner structure. The other three electrode curve portions 105A have the same structure as the corresponding electrode curve portion of the basic electrode corner structure.

[0496] The curvature centers of the inner edges 105Aa and outer edges 105Ab of the second, third, and outermost electrode curve portions 105A from the inside are Q1. These electrode curve portions 105A have equal widths. The width of these electrode curve portions 105A is constant and independent of their position in the longitudinal direction.

[0497] The innermost electrode curve portion 105A has a center of curvature of Q2 on its inner edge 105Aa and a center of curvature of Q1 on its outer edge 105Ab. The curvature of the inner edge 105Aa differs from that of the outer edge 105Ab. Specifically, the curvature of the inner edge 105Aa is smaller than that of the outer edge 105Ab. In other words, the radius of curvature of the inner edge 105Aa is larger than that of the outer edge 105Ab.

[0498] The width of the innermost electrode curve portion 105A varies depending on its position along its length. Specifically, the width of the innermost electrode curve portion 105A is widest at the center of its length and narrows towards both ends.

[0499] The innermost electrode curve portion 105A has a wide portion 211 that is wider than the corresponding electrode curve portions 105A of the three corner portions 202, 203, and 204 other than the first corner portion 201. The middle part of the length of the innermost electrode curve portion 105A is the wide portion 211.

[0500] In this modified example, the curvature of the inner edge 105Aa of the innermost electrode curve portion 105A is set such that the width of both ends of the electrode curve portion 105A is the same as the width of the electrode straight portion 105B.

[0501] In the first corner 201, the innermost FLR curve portion 42A among the four FLR curve portions 42A has a different structure from the corresponding FLR curve portion of the basic FLR corner structure. The other three FLR curve portions 42A have the same structure as the corresponding FLR curve portion of the basic FLR corner structure.

[0502] The curvature centers of the inner edges 42Aa and outer edges 42Ab of the second, third, and outermost FLR curve portions 42A from the inside are Q1. These FLR curve portions 42A have equal widths. The width of these FLR curve portions 42A is constant and independent of their position in the longitudinal direction.

[0503] The innermost FLR curve portion 42A has an inner edge 42Aa with a curvature center of Q2 and an outer edge 42Ab with a curvature center of Q1. The curvature of the inner edge 42Aa differs from that of the outer edge 42Ab. Specifically, the curvature of the inner edge 42Aa is smaller than that of the outer edge 42Ab. In other words, the radius of curvature of the inner edge 42Aa is larger than that of the outer edge 42Ab.

[0504] The width of the innermost FLR curve portion 42A varies depending on its position along its length. Specifically, the width of the innermost FLR curve portion 42A is widest at the center of its length and narrows towards both ends.

[0505] The innermost FLR curve portion 42A has a wide portion 221 that is wider than the corresponding FLR curve portions 42A of the three corner portions 202, 203, and 204 other than the first corner portion 201. The middle part of the length of the innermost FLR curve portion 42A is the wide portion 221.

[0506] In this modified example, the width of the first diffusion region 301 in the innermost FLR curve portion 42A and the width of the first diffusion region 301 in the second diffusion region 302 are constant in the length direction.

[0507] Furthermore, in this modified example, the top view shape of the boundary line BL between the first diffusion region 301 and the second diffusion region 302 of the innermost FLR curve portion 42A is an arc having the same center of curvature as the inner edge of the corresponding first electrode curve portion 105A.

[0508] In this modified example, at the first corner 201, the two side edges of each FLR curve portion 42A are recessed towards the inward side of the corresponding electrode curve portion 105A compared to the corresponding side edge of the corresponding electrode curve portion 105A. That is, the width of each FLR curve portion 42A at each length direction position is narrower than the width of the corresponding electrode curve portion 105A at the corresponding length direction position.

[0509] At the first corner 201, a portion of the wide portion 211 of the innermost electrode curve portion 105A is physically and electrically connected to the corresponding wide portion 221 of the FLR curve portion 42A via an FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.

[0510] Reference Figure 30B In the second corner 202, the second electrode curve portion 105A from the inside of the four electrode curve portions 105A has a different structure from the corresponding electrode curve portion of the basic electrode corner structure. The other three electrode curve portions 105A have the same structure as the corresponding electrode curve portions of the basic electrode corner structure.

[0511] The curvature centers of the innermost electrode curve portion 105A, the third electrode curve portion 105A from the innermost side, and the inner edge 105Aa and outer edge 105Ab of the outermost electrode curve portion 105A are Q3. These electrode curve portions 105A have equal widths. The widths of these electrode curve portions 105A are constant and independent of their position in the longitudinal direction.

[0512] The center of curvature of the inner edge 105Aa of the second electrode curve portion 105A from the inside is Q4, and the center of curvature of the outer edge 105Ab is Q3. The curvature of the inner edge 105Aa is different from that of the outer edge 105Ab. Specifically, the curvature of the inner edge 105Aa is smaller than that of the outer edge 105Ab. In other words, the radius of curvature of the inner edge 105Aa is larger than that of the outer edge 105Ab.

[0513] The width of the second electrode curve portion 105A from the inside varies depending on its position along its length. Specifically, the width of the second electrode curve portion 105A from the inside is widest at the center of its length and narrows towards both ends from the center.

[0514] The second electrode curve portion 105A from the inside has a wide portion 211 that is wider than the corresponding electrode curve portions 105A of the three corner portions 201, 203, and 204 other than the second corner portion 202. The middle part of the length of the second electrode curve portion 105A from the inside is the wide portion 211.

[0515] In this modified example, the curvature of the inner edge 105Aa of the second electrode curve portion 105A from the inside is set such that the width of both ends of the electrode curve portion 105A is the same as the width of the electrode straight portion 105B.

[0516] In the second corner 202, the second FLR curve portion 42A from the inside of the four FLR curve portions 42A has a different structure from the corresponding FLR curve portion of the basic FLR corner structure. The other three FLR curve portions 42A have the same structure as the corresponding FLR curve portions of the basic FLR corner structure.

[0517] The curvature center of the innermost FLR curve portion 42A, the third FLR curve portion 42A from the inside, the inner edge 42Aa of the outermost FLR curve portion 42A, and the outer edge 42Ab is Q3. These FLR curve portions 42A have equal widths. The width of these FLR curve portions 42A is constant and independent of their position in the longitudinal direction.

[0518] The center of curvature of the inner edge 42Aa of the second FLR curve portion 42A from the inside is Q4, and the center of curvature of the outer edge 42Ab is Q3. The curvature of the inner edge 42Aa is different from that of the outer edge 42Ab. Specifically, the curvature of the inner edge 42Aa is smaller than that of the outer edge 42Ab. In other words, the radius of curvature of the inner edge 42Aa is larger than that of the outer edge 42Ab.

[0519] The width of the second FLR curve portion 42A from the inside varies depending on its position along its length. Specifically, the width of the second FLR curve portion 42A from the inside is widest at the center of its length and narrows towards both ends.

[0520] The second FLR curve portion 42A from the inside has a wide portion 221 that is wider than the corresponding FLR curve portions 42A of the three corner portions 201, 203, and 204 other than the second corner portion 202. The middle part of the length of the second FLR curve portion 42A from the inside is the wide portion 221.

[0521] In this modified example, the width of the first diffusion region 301 in the second FLR curve portion 42A from the inside and the width of the first diffusion region 301 in the second diffusion region 302 are constant in the length direction.

[0522] Furthermore, in this modified example, the top view shape of the boundary line BL between the first diffusion region 301 and the second diffusion region 302 of the second FLR curve portion 42A from the inside is an arc having the same center of curvature as the inner edge of the corresponding first electrode curve portion 105A.

[0523] In this modified example, at the second corner 202, the two side edges of each FLR curve portion 42A are recessed towards the inward side of the corresponding electrode curve portion 105A compared to the corresponding side edge of the corresponding electrode curve portion 105A. That is, the width of each FLR curve portion 42A at each length direction position is narrower than the width of the corresponding electrode curve portion 105A at the corresponding length direction position.

[0524] At the second corner 202, a portion of the wide portion 211 of the second electrode curve portion 105A from the inside is physically and electrically connected to the corresponding wide portion 221 of the FLR curve portion 42A via the FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.

[0525] Reference Figure 30CIn the triangular portion 203, the third electrode curve portion 105A from the inside among the four electrode curve portions 105A has a different structure from the corresponding electrode curve portion of the basic electrode angle structure. The other three electrode curve portions 105A have the same structure as the corresponding electrode curve portions of the basic electrode angle structure.

[0526] The curvature centers of the innermost electrode curve portion 105A, the second electrode curve portion 105A from the innermost side, and the inner edge 105Aa and outer edge 105Ab of the outermost electrode curve portion 105A are Q5. These electrode curve portions 105A have equal widths. The widths of these electrode curve portions 105A are constant and independent of their position in the longitudinal direction.

[0527] The center of curvature of the inner edge 105Aa of the third electrode curve portion 105A from the inside is Q6, and the center of curvature of the outer edge 105Ab is Q5. The curvature of the inner edge 105Aa is different from that of the outer edge 105Ab. Specifically, the curvature of the inner edge 105Aa is smaller than that of the outer edge 105Ab. In other words, the radius of curvature of the inner edge 105Aa is larger than that of the outer edge 105Ab.

[0528] The width of the third electrode curve portion 105A from the inside varies depending on its position along its length. Specifically, the width of the third electrode curve portion 105A from the inside is widest at the center of its length and narrows towards both ends from the center.

[0529] The third electrode curve portion 105A from the inside has a wide portion 211 that is wider than the corresponding electrode curve portions 105A of the three corner portions 201, 202, and 204 other than the third corner portion 203. The middle part of the length of the third electrode curve portion 105A from the inside is the wide portion 211.

[0530] In this modified example, the curvature of the inner edge 105Aa of the third electrode curve portion 105A from the inside is set such that the width of both ends of the electrode curve portion 105A is the same as the width of the electrode straight portion 105B.

[0531] In the triangular section 203, the third FLR curve portion 42A from the inside among the four FLR curve portions 42A has a different structure from the corresponding FLR curve portion of the basic FLR angle structure. The other three FLR curve portions 42A have the same structure as the corresponding FLR curve portions of the basic FLR angle structure.

[0532] The curvature center of the innermost FLR curve portion 42A, the second FLR curve portion 42A from the inside, the inner edge 42Aa of the outermost FLR curve portion 42A, and the outer edge 42Ab is Q5. These FLR curve portions 42A have equal widths. The width of these FLR curve portions 42A is constant and independent of their position in the longitudinal direction.

[0533] The center of curvature of the inner edge 42Aa of the third FLR curve segment 42A from the inside is Q6, and the center of curvature of the outer edge 42Ab is Q5. The curvature of the inner edge 42Aa is different from that of the outer edge 42Ab. Specifically, the curvature of the inner edge 42Aa is smaller than that of the outer edge 42Ab. In other words, the radius of curvature of the inner edge 42Aa is larger than that of the outer edge 42Ab.

[0534] The width of the third FLR curve portion 42A from the inside varies depending on its position along its length. Specifically, the width of the third FLR curve portion 42A from the inside is widest at the center of its length and narrows towards both ends.

[0535] The third FLR curve portion 42A from the inside has a wide portion 221 that is wider than the corresponding FLR curve portions 42A of the three corner portions 201, 202, and 204 other than the third corner portion 203. The middle part of the length of the third FLR curve portion 42A from the inside is the wide portion 221.

[0536] In this modified example, the width of the first diffusion region 301 in the third FLR curve portion 42A from the inside and the width of the first diffusion region 301 in the second diffusion region 302 are constant in the length direction.

[0537] Furthermore, in this modified example, the top view shape of the boundary line BL between the first diffusion region 301 and the second diffusion region 302 of the third FLR curve portion 42A from the inside is an arc having the same center of curvature as the inner edge of the corresponding first electrode curve portion 105A.

[0538] In this modified example, in the triangular portion 203, the two side edges of each FLR curve portion 42A are recessed towards the inward side of the corresponding electrode curve portion 105A compared to the corresponding side edge of the corresponding electrode curve portion 105A. That is, the width of each FLR curve portion 42A in the length direction is narrower than the width of the corresponding electrode curve portion 105A in the length direction.

[0539] In the triangular section 203, a portion of the wide portion 211 of the third electrode curve portion 105A from the inside is physically and electrically connected to the corresponding wide portion 221 of the FLR curve portion 42A via the FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.

[0540] Reference Figure 30D In the fourth corner 204, the outermost electrode curve portion 105A of the four electrode curve portions 105A has a different structure from the corresponding electrode curve portion of the basic electrode corner structure. The other three electrode curve portions 105A have the same structure as the corresponding electrode curve portions of the basic electrode corner structure.

[0541] The center of curvature of the innermost electrode curve portion 105A, and the inner edges 105Aa and outer edges 105Ab of the second and third electrode curve portions 105A from the inside, is Q7. These electrode curve portions 105A have equal widths. The width of these electrode curve portions 105A is constant and independent of their position in the longitudinal direction.

[0542] The center of curvature of the inner edge 105Aa of the outermost electrode curve portion 105A is Q8, and the center of curvature of the outer edge 105Ab is Q7. The curvature of the inner edge 105Aa is different from that of the outer edge 105Ab. Specifically, the curvature of the inner edge 105Aa is smaller than that of the outer edge 105Ab. In other words, the radius of curvature of the inner edge 105Aa is larger than that of the outer edge 105Ab.

[0543] The width of the outermost electrode curve portion 105A varies depending on its position along its length. Specifically, the width of the outermost electrode curve portion 105A is widest at the center of its length and narrows towards both ends.

[0544] The outermost electrode curve portion 105A has a wide portion 211 that is wider than the corresponding electrode curve portions 105A of the three corner portions 201, 202, and 203 other than the fourth corner portion 204. The middle part of the length of the outermost electrode curve portion 105A is the wide portion 211.

[0545] In this modified example, the curvature of the inner edge 105Aa of the outermost electrode curve portion 105A is set such that the width of both ends of the electrode curve portion 105A is the same as the width of the electrode straight portion 105B.

[0546] In the fourth corner 204, only the outermost FLR curve portion 42A of the four FLR curve portions 42A differs in structure from the corresponding FLR curve portion of the basic FLR corner structure. The other three FLR curve portions 42A have the same structure as the corresponding FLR curve portion of the basic FLR corner structure.

[0547] The center of curvature of the innermost FLR curve portion 42A, and the inner edges 42Aa and outer edges 42Ab of the second and third FLR curve portions 42A from the inside, is Q7. These FLR curve portions 42A have equal widths. The width of these FLR curve portions 42A is constant and independent of their position in the longitudinal direction.

[0548] The center of curvature of the inner edge 42Aa of the outermost FLR curve portion 42A is Q8, and the center of curvature of the outer edge 142Ab is Q7. The curvature of the inner edge 42Aa is different from that of the outer edge 42Ab. Specifically, the curvature of the inner edge 42Aa is smaller than that of the outer edge 42Ab. In other words, the radius of curvature of the inner edge 42Aa is larger than that of the outer edge 42Ab.

[0549] The width of the outermost FLR curve portion 42A varies depending on its position along its length. Specifically, the width of the outermost FLR curve portion 42A is widest at the center of its length and narrows towards both ends.

[0550] The outermost FLR curve portion 42A has a wide portion 221 that is wider than the corresponding FLR curve portions 42A of the three corner portions 201, 202, and 203 other than the fourth corner portion 204. The middle part of the length of the outermost FLR curve portion 42A is the wide portion 221.

[0551] In this modified example, the width of the first diffusion region 301 in the outermost FLR curve portion 42A and the width of the first diffusion region 301 in the second diffusion region 302 are constant in the length direction.

[0552] Furthermore, in this modified example, the top view shape of the boundary line BL between the first diffusion region 301 and the second diffusion region 302 of the outermost FLR curve portion 42A is an arc having the same center of curvature as the inner edge of the corresponding first electrode curve portion 105A.

[0553] In this modified example, at the fourth corner 204, the two side edges of each FLR curve portion 42A are recessed towards the inward side of the corresponding electrode curve portion 105A compared to the corresponding side edge of the corresponding electrode curve portion 105A. That is, the width of each FLR curve portion 42A at each length direction position is narrower than the width of the corresponding electrode curve portion 105A at the corresponding length direction position.

[0554] At the fourth corner 204, a portion of the wide portion 211 of the outermost electrode curve portion 105A is physically and electrically connected to the corresponding wide portion 221 of the FLR curve portion 42A via the FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.

[0555] The multiple FLR connection electrodes 89 are circular when viewed from above. The multiple FLR connection electrodes 89 can also be polygonal (such as quadrilaterals) or elliptical when viewed from above. In this modified example, the multiple FLR connection electrodes 89 are formed in an electrically floating state.

[0556] The inner edge 42Aa of each FLR curve portion 42A is the inner edge of the first diffusion region 301 of that FLR curve portion 42A. The outer edge 42Ab of each FLR curve portion 42A is the outer edge of the second diffusion region 302 of that FLR curve portion 42A. A diffusion region boundary line BL is formed at the midpoint of the width between the inner edge 42Aa and the outer edge 42Ab of the FLR curve portion 42A.

[0557] In this modified example, the diffusion region boundary line BL of each FLR curve portion 42A has the same center of curvature as the center of curvature of the inner edge 42Aa of the FLR curve portion 42A. Alternatively, the diffusion region boundary line BL of each FLR curve portion 42A may also have the same center of curvature as the center of curvature of the outer edge 42Ab of the FLR curve portion 42A.

[0558] In this modified example, in the corners 201-204, the two side edges of the plurality of FLR curved portions 42A are recessed inwards from the corresponding side edges of the corresponding electrode curved portion 105A when viewed from above. Therefore, in this embodiment, the width of the FLR curved portion 42A is narrower than the width of the corresponding electrode straight portion 105B.

[0559] Furthermore, the inner edge 42Aa of each FLR curve portion 42A may extend outward from the corresponding inner edge 105Aa of the electrode curve portion 105A. Additionally, the outer edge 42Ab of each FLR curve portion 42A may extend outward from the corresponding outer edge 105Ab of the electrode curve portion 105A.

[0560] Alternatively, only the inner edge 42Aa of each FLR curve portion 42A may extend outward from the inner edge 105Aa of the corresponding electrode curve portion 105A. In this case, only the inner edge of each FLR straight portion 42B may extend outward from the inner edge of the corresponding electrode straight portion 105B.

[0561] Alternatively, only the outer edge 42Ab of each FLR curve portion 42A may extend to a position that is closer to the outer side of the corresponding electrode curve portion 105A than the outer edge 105Ab of that electrode curve portion 105A. In this case, only the outer edge of each FLR straight portion 42B may extend to a position that is closer to the outer side of the corresponding electrode straight portion 105B than the outer edge of that electrode straight portion 105B.

[0562] Alternatively, the inner edge 105Aa and outer edge 42Ab of each FLR curve portion 42A may both extend to a position outside the corresponding side edge 105Aa, 105Ab of the corresponding electrode curve portion 105A. In this case, the inner edge and outer edge of each FLR straight portion 42B may both extend to a position outside the corresponding outer edge of the corresponding electrode straight portion 105B.

[0563] In addition, Figures 30A to 30D In the process, at each corner 201-204, the curvature of the inner edge 105Aa of the electrode curve portion 105A connected to the FLR connecting electrode 89 and the FLR 42 is smaller than the curvature of its outer edge 105Ab, but the curvature of the inner edge 105Aa can also be larger than the curvature of its outer edge 105Ab. In this case, the width of the electrode curve portion 105A connected to the FLR connecting electrode 89 and the FLR 42 increases from the center of its length towards both ends.

[0564] In this case, the electrode curve portion 105A connected to the FLR 42 via the FLR connecting electrode 89 may also have wide portions 211 at both ends. In this case, at least one portion of the wide portions 211 at both ends of the electrode curve portion 10 may be connected to the FLR 42 via the FLR connecting electrode 89.

[0565] In this variation, for example, even if the width of the straight portion 105B of the FLR electrode 105 is narrower than the width required to connect the straight portion 105B of the electrode to the FLR 42 via the FLR connection electrode 89, the area for connecting to the FLR 42 via the FLR connection electrode 89 can be easily ensured in the curved portion 105A of the electrode.

[0566] In other words, the width of the straight portion 105B of the FLR electrode 105 can be narrower than the width of the straight portion 105B connected to the FLR 42 via the FLR connecting electrode 89. This allows for a narrower overall width of the multiple FLR electrodes 105, thus enabling chip miniaturization.

[0567] exist Figures 30A to 30D as well as Figure 31In the structure shown, the four pairs formed by the combination of FLR42 and its corresponding FLR electrode 105 satisfy the following first and second conditions.

[0568] The first condition is that the electrode curve portion 105A in the four corners 201 to 204 is connected to the FLR connecting electrode 89 and the FLR42 via the FLR connecting electrode, and the condition is different in each of the four corners 201 to 204.

[0569] The second condition is that, in each corner 201 to 204, an electrode curve portion 105A connected to the FLR curve portion 42A via the FLR connection electrode 89 has a wide portion 211 that is wider than the electrode curve portion 105A of the other three corners. A portion of the wide portion 211 is physically and electrically connected to the corresponding FLR 42 via the FLR connection electrode 89.

[0570] The above four pairs also satisfy the following third condition: In each corner 201 to 204, an electrode curve portion 105A connected to FLR42 via FLR connecting electrode 89 has its center of curvature and its inner edge 105Aa and outer edge 105Ab with different curvatures.

[0571] The above four pairs also satisfy the following fourth condition: the center of curvature of the inner edge 105Aa and the center of curvature of the outer edge 105Ab of an electrode curve portion 105A connected to the FLR connecting electrode 89 and the FLR42 in each corner 201 to 204 are located at different positions on the dividing line L0 that divides the apex of the corner into half, and the radius of curvature of the inner edge 105Aa is different from that of the outer edge 105Ab.

[0572] The above four pairs also satisfy the following fifth condition: at each corner 201 to 204, an FLR curve portion 42A connected to an electrode curve portion 105A via an FLR connecting electrode 89 has its curvature center and its inner edge 42Aa and outer edge 42Ab with different curvatures.

[0573] The above four pairs also satisfy the following sixth condition: at each corner 201 to 204, the center of curvature of the inner edge 42Aa and the center of curvature of the outer edge 42Ab of an FLR curve portion 42A connected to the electrode curve portion 105A via the FLR connecting electrode 89 exist at different positions on the dividing line L0 that divides the apex of the corner into half, and the radius of curvature of the inner edge 42Aa is different from the radius of curvature of the outer edge 42Ab.

[0574] Semiconductor device 1A only needs to have four pairs of electrodes consisting of FLR 42 and FLR electrode 150, satisfying the first and second conditions described above. Furthermore, these four pairs may also satisfy the third condition. Furthermore, these four pairs may also satisfy the fourth condition. Furthermore, these four pairs may also satisfy the fifth condition. Furthermore, these four pairs may also satisfy the sixth condition.

[0575] In addition, such as Figure 32 As shown, at each corner 201 to 204, the shape of the FLR curve portion 42A connected to the electrode curve portion 105A via the FLR connecting electrode 89 may also be different from that of the electrode curve portion 105A. Figure 32 This is a schematic top view showing the structure of the FLR42, FLR electrode 105, and FLR connecting electrode 89 in the second corner 202. Figure 32 In the top view, the shape of multiple electrode curve sections 105A is similar to... Figure 30B They have the same top-down shape.

[0576] Specifically, in Figure 32 In the second FLR curve portion 42A from the inside, the inner edge 42Aa, the outer edge 42Ab, and the boundary line BL of the diffusion region share the same curvature center. Specifically, in the second corner 202, their curvature center is Q3.

[0577] That is, the inner edge 42Aa, outer edge 42Ab, and diffusion region boundary line BL of the FLR curve portion 42A, which is connected to the electrode curve portion 105A via the FLR connecting electrode 89, have the same center of curvature as the center of curvature of the inner edge 105Aa of the corresponding electrode curve portion 105A. The same applies to the other corner portions 201, 203, and 204.

[0578] In addition, in each corner section 201 to 204, the inner edge 42Aa, outer edge 42Ab, and diffusion region boundary line BL of the FLR curve section 42A connected to the electrode curve section 105A via the FLR connecting electrode 89 may also have the same curvature center as the outer edge 105Ab of the corresponding electrode curve section 105A.

[0579] exist Figure 32 In the FLR curve portion 42A, which is connected to the electrode curve portion 105A via the FLR connecting electrode 89, the width of the first diffusion region 301 is constant in the length direction, and the width of the second diffusion region 302 is constant in the length direction.

[0580] In addition, Figure 32In the first electrode curve portion 105A, the inner edge 42Aa and outer edge 42Ab of the FLR curve portion 42A connected to the electrode curve portion 105A via the FLR connecting electrode 89 have the same center of curvature as the outer edge 105Ab of the corresponding first electrode curve portion 105A.

[0581] The embodiments and variations of this disclosure have been described above, but this disclosure can also be implemented in other ways. For example, in the above embodiments, an example has been shown where chip 2 is made of a single-crystal silicon substrate. However, chip 2 may also be made of a SiC (silicon carbide) single-crystal substrate.

[0582] In the described embodiment, the n-type semiconductor region may be replaced with a p-type semiconductor region, and vice versa. The specific structure in this case is obtained by simultaneously replacing "n-type" with "p-type" and "p-type" with "n-type" in the foregoing description and figures.

[0583] In the above embodiment, a p-type collector region 14 is shown. However, an n-type drain region may be used instead of a p-type collector region 14. In this case, the buffer region 13 is omitted. The n-type drain region may be formed from an n-type semiconductor substrate, and the n-type drift region 12 may be formed from an n-type epitaxial layer. Preferably, the n-type impurity concentration in the drift region 12 is less than the n-type impurity concentration in the drain region.

[0584] In this case, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure is formed instead of an IGBT. The specific structure in this case is obtained by replacing the "emitter" with the "source" and the "collector" with the "drain" as described above.

[0585] In the aforementioned embodiments, the first direction X and the second direction Y are defined by the extension directions of the first to fourth sides 5A to 5D. However, the first direction X and the second direction Y can be any direction as long as they maintain a mutually intersecting (specifically orthogonal) relationship. For example, the first direction X can be the extension direction of the third side 5C (fourth side 5D), and the second direction Y can be the extension direction of the first side 5A (second side 5B). Alternatively, the first direction X can also be a direction intersecting the first to fourth sides 5A to 5D, and the second direction Y can also be a direction intersecting the first to fourth sides 5A to 5D.

[0586] Hereinafter, examples of features extracted from this specification and accompanying drawings are shown. Hereinafter, alphanumeric characters, etc., denote corresponding constituent elements in the foregoing embodiments, but do not imply that the scope of each item (clause) is limited to the embodiments. The term "semiconductor device" as used in the following items can also be replaced with "semiconductor switching device," "IGBT semiconductor device," "RC-IGBT semiconductor device," or "MISFET semiconductor device."

[0587] [A1] A semiconductor device includes: a chip 2 having a first main surface 3, which is quadrilateral in view from top view, and a second main surface 4 on the opposite side;

[0588] An active region 6 is disposed on the first main surface 3 and has a component structure thereon;

[0589] The outer peripheral region 9 is the region other than the active region 6, and is located on the outer periphery of the first main surface 3 and has four corners 201 to 204.

[0590] A drift region of the first conductivity type is formed inside the chip 2; and

[0591] Multiple field-limiting rings of the second conductivity type (hereinafter referred to as "FLR42") are formed in the outer peripheral region 9 on the surface portion of the first main surface 3 in a manner that surrounds the active region 6.

[0592] Each FLR42 has a curved FLR portion 42A in a top view shape at its four corners 201 to 204.

[0593] Each of the aforementioned FLR42 has a linear FLR portion 42B, which is straight in shape when viewed from above, between the four corners 201 and 204.

[0594] Each of the FLR curve portions 42A has a dual diffusion structure including an inner first diffusion region 301 and an outer second diffusion region 302 of the second conductivity type with a lower impurity concentration than the first diffusion region 301.

[0595] [A2] According to the semiconductor device of [A1], each FLR linear portion 42B has a single diffusion structure consisting only of diffusion regions having an impurity concentration of the same second conductivity type as the first diffusion region 301.

[0596] [A3] In the semiconductor device according to [A1] or [A2], in each of the corner portions 201 to 204, each FLR curved portion 42A has an inner edge 42Aa and an outer edge 42Ab that are arc-shaped when viewed from above.

[0597] In each of the corner portions 201 to 204, the first diffusion region 301 and the second diffusion region 302 in each of the FLR curve portions 42A have an inner edge and an outer edge that are arc-shaped when viewed from above.

[0598] [A4] In the semiconductor device according to [A3], in each of the corner portions 201 to 204, the inner and outer edges of the first diffusion region 301 and the inner and outer edges of the second diffusion region 302 in each FLR curve portion 42A have the same center of curvature.

[0599] [A5] In the semiconductor device according to [A4], in each of the corner portions 201 to 204, the center of curvature of the inner and outer edges of the first diffusion region 301 and the inner and outer edges of the second diffusion region 302 in each FLR curve portion 42A is located on the dividing line L0, which divides the apex of the corner portion 201 to 204 into half.

[0600] [A6] In the semiconductor device according to [5], in each of the corner portions 201 to 204, the width of each FLR curve portion 42A is the same, the width of the first diffusion region 301 in each FLR curve portion 42A is constant in its length direction, and the width of the second diffusion region 302 in each FLR curve portion 42A is constant in its length direction.

[0601] [A7] The semiconductor device according to [A1] or [A2], wherein it comprises:

[0602] Insulating films 45 and 74 are formed on the first main surface 3 and cover the plurality of FLRs 42; and

[0603] Multiple FLR electrodes 105 are disposed opposite to the multiple FLRs 42, separated by insulating films 45 and 74, and are physically and electrically connected to the corresponding FLRs 42 via FLR connection electrodes 89 that penetrate the insulating films 45 and 74.

[0604] Each FLR electrode 105 has an electrode curve portion 105A at each corner 201-204, the inner and outer edges of which are arc-shaped when viewed from above.

[0605] In each of the corner portions 201 to 204, the center of curvature of the inner edge 105Aa and the outer edge 105Ab of each electrode curve portion 105A lies on the dividing line L0, which divides the apex of the corner portion 201 to 204 into half.

[0606] In at least one of the at least four corner portions 201 to 204, the plurality of electrode curve portions 105A include at least one first electrode curve portion 105A, which has its curvature center and inner edge 105Aa and outer edge 105Ab with different curvatures.

[0607] [A8] In the semiconductor device according to [A7], the first electrode curve portion 105A has a wide region and a narrow region between its inner edge 105Aa and outer edge 105Ab.

[0608] A portion of the wide region in the first electrode curve portion 105A is connected to the corresponding FLR 42 via the FLR connection electrode 89 that penetrates the insulating films 45 and 74.

[0609] [A9] In the semiconductor device according to [7], the inner edge 42Aa of the FLR curve portion 42A corresponding to the first electrode curve portion 105A has the same center of curvature as the center of curvature of the inner edge 105Aa of the first electrode curve portion 105A.

[0610] The outer edge 42Ab of the FLR curve portion 42A corresponding to the first electrode curve portion 105A has the same center of curvature as the outer edge 105Ab of the first electrode curve portion 105A.

[0611] [A10] In the semiconductor device according to [A9], the width of one of the first diffusion region 301 and the second diffusion region 302 of the FLR curve portion 42A corresponding to the first electrode curve portion 105A is constant in the length direction.

[0612] [A11] According to the semiconductor device of [A10], the top view shape of the boundary line BL of the first diffusion region 301 and the second diffusion region 302 of the FLR curve portion 42A corresponding to the first electrode curve portion 105A is an arc having the same center of curvature as the center of curvature of the inner edge 105Aa of the first electrode curve portion 105A.

[0613] [A12] In the semiconductor device according to [A7], the width of the first diffusion region 301 of the FLR curve portion 42A corresponding to the first electrode curve portion 105A is constant in the length direction.

[0614] The width of the second diffusion region 302 of the FLR curve portion 42A corresponding to the first electrode curve portion 105A is constant in the length direction.

[0615] [A13] According to the semiconductor device of [A12], the inner edge 42Aa and the outer edge 42Ab of the FLR curve portion 42A corresponding to the first electrode curve portion 105A have the same center of curvature as the center of curvature of the inner edge 105Aa of the first electrode curve portion 105A, or have the same center of curvature as the center of curvature of the outer edge of the first electrode curve portion.

[0616] [A14] According to the semiconductor device of [A13], the top view shape of the boundary line BL of the first diffusion region 301 and the second diffusion region 302 of the FLR curve portion 42A corresponding to the first electrode curve portion 105A is an arc having the same center of curvature as the inner edge 105Aa of the first electrode curve portion 105A, or an arc having the same center of curvature as the outer edge of the first electrode curve portion.

[0617] [A15] The semiconductor device according to any one of [A7] to [A14], wherein the FLR connection electrode 89 for electrically connecting the first electrode curve portion 105A to the corresponding FLR 42 is integrally formed with the first electrode curve portion 105A.

[0618] [A16] The semiconductor device according to any one of [A1] to [A15], wherein:

[0619] A channel blocking region, which is formed in the outer peripheral region 9 in a manner surrounding the plurality of FLR42s on the surface portion of the first main surface 3, and is covered by the insulating films 45 and 74; and

[0620] A channel blocking electrode 106 is formed in the outer peripheral region 9 on the insulating films 45, 74 in such a way as to cover a portion of the channel blocking region 43, and is electrically connected to the channel blocking region 43.

[0621] [A17] The semiconductor device according to any one of [A1] to [A16], wherein the element structure includes an IGBT structure.

[0622] [A18] The semiconductor device according to any one of [A1] to [A17], wherein:

[0623] The first conductivity type of drift region 12 is formed inside the chip 2;

[0624] A second conductivity type channel region 20 is formed in the active region 6 on the surface portion of the first main surface 3;

[0625] The emitter region 29 of the first conductivity type is formed on the surface of the channel region 20, and the impurity concentration of the first conductivity type is higher than that of the drift region 12; and

[0626] A trench gate structure 21 that reaches the drift region 12 in the active region 6 via the emitter region 29 and the channel region 20.

[0627] [A19] The semiconductor device according to [A18], wherein the conductivity type of the FLR42 is a second conductivity type.

[0628] The above describes the implementation methods in detail, but these are merely specific examples used to clarify the technical content. This disclosure should not be limited to these specific examples for interpretation. The scope of this disclosure is defined by the scope of the appended technical solutions.

[0629] Symbol Explanation

[0630] 1—Semiconductor device, 2—Chip, 3—First main surface, 4—Second main surface, 5A~5D—First~Fourth side surfaces, 6—Active region, 6A—First active region, 6B—Second active region, 7—Non-active region, 8—Boundary region (7), 9—Outer peripheral region (7), 10—Pad region (8), 11—Gap region (8), 12—Drift region, 13—Buffer layer, 14—Collector region, 15—Trench separation structure, 15A—First trench separation structure, 15B—Second trench separation structure, 16—Separation trench, 17—Separation insulating film, 18—Separation buried electrode, 20—Trench region, 21—First trench structure, 22—First trench, 23—First insulating film, 24—First buried electrode 25—Second trench structure, 26—Second trench, 27—Second insulating film, 28—Second buried electrode, 29—Emitter region, 30—Contact hole (first contact hole), 31—Channel contact region, 32—Floating region, 40—Boundary well region, 40A—First boundary well region, 40B—Second boundary well region, 41—Outer peripheral well region, 42—FLR, 42A—FLR curved portion, 42Aa—Inner edge, 42Ab—Outer edge, 42B—FLR straight portion, 43—Channel blocking region, 45—Main surface insulating film, 46—Removal section, 47—Emitter electrode film, 50—Gate resistor structure, 51—Trench resistor structure, 51A—First trench resistor structure, 51B—Second trench electrode structure Resistor structure, 54—Resistor trench, 55—Resistor insulating film, 56—Resistor embedded electrode, 57—Gap region, 60—Resistor film, 60A—First end of resistor film, 60B—Second end of resistor film, 61—First covering portion of resistor film, 62—Second covering portion of resistor film, 63—Third covering portion of resistor film, 64—Gate electrode film, 65—Gate wiring film, 66—First lower wiring portion, 67—Second lower wiring portion, 68—Third lower wiring portion, 68a—Lead-out portion, 69—First lower wiring portion (66), 70A, 70B—Second lower wiring portion (66), 71—First slit, 72—Second slit, 73—Third slit, 74—Interlayer insulating film, 75—Insulating main surface, 76—First recess, 7 7—Second recess, 78—Third recess, 81—First resistor connection electrode, 82—Second resistor connection electrode, 83—Third resistor connection electrode, 84—Gate connection electrode, 84A—First gate connection electrode, 84B—Second gate connection electrode, 85—First emitter connection electrode (first connection electrode), 86—Second emitter connection electrode, 87—First well connection electrode, 87a—Segment, 88—Second well connection electrode, 89—FLR connection electrode, 90—Gate terminal electrode, 91—First electrode portion, 92—Second electrode portion, 93—Gate wiring electrode, 94—First upper wiring portion, 95—Second upper wiring portion, 96—Third upper wiring portion, 97—First upper wiring portion (94), 97a—Recess.98A, 98B—Second upper line section (94), 101—First connecting area, 102—Second connecting area, 103—Emitting end sub-electrode, 103A—First transmitting end sub-electrode, 103B—Second transmitting end sub-electrode, 104—Emitting electrode wiring electrode, 105—FLR electrode, 105A—Electrode curve section, 105Aa—Inner edge, 105Ab—Outer edge, 105B—Electrode straight section, 106—Channel blocking electrode, 107—Collector electrode, 201~204—Corner section, 221, 221—Wide section, 231—Conical section, 301—First diffusion region, 302—Second diffusion region, Q1~Q8—Center of curvature, r1~r2—Radius of curvature, BL—Boundary line of diffusion region, X—First direction, Y—Second direction.

Claims

1. A semiconductor device, characterized in that, include: A chip having a first principal face that is quadrilateral in shape when viewed from above and a second principal face on the opposite side; An active region is disposed on the first main surface and has a component structure thereon; The outer peripheral region, which is the region other than the active region, is located on the outer periphery of the first main surface and has four corners; A first conductivity type drift region is formed inside the chip; as well as Multiple field-limiting rings (FLRs) of the second conductivity type are formed on the surface portion of the first main surface in the outer peripheral region in a manner that surrounds the active region. Each of the aforementioned FLRs has a curved FLR section at each of its four corners, which has a curved shape when viewed from above. Each of the aforementioned FLRs has a straight FLR section that appears as a straight line when viewed from above between its four corners. Each of the aforementioned FLR curve portions has a dual diffusion structure, which includes an inner first diffusion region and an outer second diffusion region with a lower impurity concentration of the second conductivity type than the first diffusion region.

2. The semiconductor device according to claim 1, characterized in that, Each of the FLR linear portions has a single diffusion structure consisting only of diffusion regions having an impurity concentration of the same second conductivity type as the first diffusion region.

3. The semiconductor device according to claim 1 or 2, characterized in that, In each of the aforementioned corner portions, each of the aforementioned FLR curved portions has an inner edge and an outer edge that are arc-shaped when viewed from above. In each of the corner portions, the first diffusion region and the second diffusion region in each of the FLR curve portions respectively have an inner edge and an outer edge that are arc-shaped when viewed from above.

4. The semiconductor device according to claim 3, characterized in that, In each of the corner portions, the inner and outer edges of the first diffusion region and the inner and outer edges of the second diffusion region in each of the FLR curve portions have the same center of curvature.

5. The semiconductor device according to claim 4, characterized in that, In each of the corners, the curvature centers of the inner and outer edges of the first diffusion region and the inner and outer edges of the second diffusion region in each of the FLR curve portions are located on the line that divides the apex of the corner into half, i.e., the dividing line.

6. The semiconductor device according to claim 5, characterized in that, In each of the corner portions, the width of each of the FLR curve portions is the same, the width of the first diffusion region within each of the FLR curve portions is constant in its length direction, and the width of the second diffusion region within each of the FLR curve portions is constant in its length direction.

7. The semiconductor device according to claim 1 or 2, characterized in that, include: An insulating film is formed on the first main surface and covers the plurality of said FLRs; as well as Multiple FLR electrodes are disposed opposite to multiple FLRs through the insulating film, and are physically and electrically connected to the corresponding FLRs via FLR connection electrodes that penetrate the insulating film. Each of the aforementioned FLR electrodes has an electrode curve portion at each of the aforementioned corners, the inner edge of which and the outer edge of which are arc-shaped when viewed from above. In each of the aforementioned corner portions, the center of curvature of the inner and outer edges of each of the aforementioned electrode curve portions lies at a position on the dividing line that bisects the vertex of the corner portion. In at least one of the at least four corner portions, the plurality of electrode curve portions include at least one first electrode curve portion having their curvature center and inner and outer edges with different curvatures.

8. The semiconductor device according to claim 7, characterized in that, The first electrode curve portion has a wide region and a narrow region between its inner and outer edges. A portion of the wide region in the first electrode curve is connected to the corresponding FLR via the FLR connection electrode that penetrates the insulating film.

9. The semiconductor device according to claim 8, characterized in that, The inner edge of the FLR curve portion corresponding to the first electrode curve portion has the same center of curvature as the inner edge of the first electrode curve portion. The outer edge of the FLR curve portion corresponding to the first electrode curve portion has the same center of curvature as the outer edge of the first electrode curve portion.

10. The semiconductor device according to claim 9, characterized in that, The width of one of the first diffusion region and the second diffusion region of the FLR curve portion corresponding to the first electrode curve portion is constant in the length direction.

11. The semiconductor device according to claim 10, characterized in that, The top view shape of the boundary line between the first diffusion region and the second diffusion region of the FLR curve portion corresponding to the first electrode curve portion is an arc with the same center of curvature as the inner edge of the first electrode curve portion.

12. The semiconductor device according to claim 7, characterized in that, The width of the first diffusion region in the FLR curve portion corresponding to the first electrode curve portion is constant in the length direction. The width of the second diffusion region of the FLR curve portion corresponding to the first electrode curve portion is constant in the length direction.

13. The semiconductor device according to claim 12, characterized in that, The inner edge and outer edge of the FLR curve portion corresponding to the first electrode curve portion have the same center of curvature as the inner edge of the first electrode curve portion, or have the same center of curvature as the outer edge of the first electrode curve portion.

14. The semiconductor device according to claim 13, characterized in that, The top view shape of the boundary line between the first diffusion region and the second diffusion region of the FLR curve portion corresponding to the first electrode curve portion is an arc with the same center of curvature as the inner edge of the first electrode curve portion, or an arc with the same center of curvature as the outer edge of the first electrode curve portion.

15. The semiconductor device according to any one of claims 7 to 14, characterized in that, The FLR connection electrode, used to electrically connect the first electrode curve portion to the corresponding FLR, is integrally formed with the first electrode curve portion.

16. The semiconductor device according to any one of claims 1 to 15, characterized in that, include: A channel blocking region is formed on the surface portion of the first main surface in the outer peripheral region in such a way as to surround the plurality of said FLRs, and is covered by said insulating film; as well as A channel blocking electrode is formed on the insulating film in the outer peripheral region in such a way as to cover a portion of the channel blocking region, and is electrically connected to the channel blocking region.

17. The semiconductor device according to any one of claims 1 to 16, characterized in that, The component structure includes an IGBT structure.

18. The semiconductor device according to any one of claims 1 to 17, characterized in that, include: A first conductivity type drift region is formed inside the chip; A second type of conductive channel region is formed in the surface portion of the first main surface in the active region; The emitter region of the first conductivity type is formed on the surface of the channel region, and the impurity concentration of the first conductivity type is higher than that of the drift region. as well as A trench gate structure that reaches the drift region through the emitter region and the channel region in the active region.

19. The semiconductor device according to claim 18, characterized in that, The conductivity type of the FLR is the second conductivity type.

Images