Semiconductor device manufacturing method and semiconductor testing device

Abstract

A method for manufacturing a semiconductor device includes performing a reverse bias test on a device structure, the method including: a step of applying a reverse bias voltage to the device structure; and a monitoring step of monitoring the reduction rate of the leakage current of the device structure when the reverse bias voltage is applied.

Description

Technical Field

[0001] This application claims priority to Japan Patent Application No. 2023-056214, filed on March 30, 2023, the entire contents of which are incorporated herein by reference. This disclosure relates to a method for manufacturing a semiconductor device and a semiconductor testing apparatus. Background Technology

[0002] Patent document 1 (US2018 / 0151719A1) discloses the following reverse bias test: based on the increase in leakage current, it is determined that a malfunction has occurred in the silicon carbide semiconductor device (see reference). Figure 8 A).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: U.S. Patent Application Publication No. 2018 / 0151719 Summary of the Invention

[0006] This disclosure provides a method for manufacturing a semiconductor device for detecting potential defects, as well as a semiconductor testing apparatus.

[0007] This disclosure provides a method for manufacturing a semiconductor device, including performing a reverse bias test on a device structure, wherein the method for manufacturing the semiconductor device includes the steps of: applying a reverse bias voltage to the device structure; and monitoring a rate of decrease in leakage current of the device structure when the reverse bias voltage is applied.

[0008] This disclosure provides a method for manufacturing a semiconductor device, comprising the steps of: monitoring the rate of decrease of leakage current of the device structure when a reverse bias voltage is applied to the device structure, and determining a potential defect of the device structure based on the rate of decrease of leakage current.

[0009] This disclosure provides a semiconductor testing apparatus for performing reverse bias testing on a device structure. The semiconductor testing apparatus includes: a voltage application unit that applies a test voltage to the device structure; a voltage generation unit that generates a reverse bias voltage as the test voltage and outputs it to the voltage application unit; and a control unit that monitors the rate of decrease of leakage current of the device structure when the reverse bias voltage is applied.

[0010] This disclosure provides a semiconductor testing apparatus that monitors the rate of decrease of leakage current in a device structure when a reverse bias voltage is applied to the device structure, and determines a potential defect in the device structure based on the rate of decrease of leakage current.

[0011] The above or other objects, features, and effects become clear from the description of this disclosure with reference to the accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a schematic diagram showing the wafer structure of the first example.

[0013] Figure 2 yes Figure 1 A cross-sectional view of the wafer structure shown.

[0014] Figure 3 It means Figure 1 The diagram shows a cross-sectional view of a major part of the device structure.

[0015] Figure 4 This is a schematic diagram of a semiconductor testing device in a specific manner.

[0016] Figure 5 This is a schematic diagram showing the reverse bias test of a semiconductor test apparatus.

[0017] Figure 6 It is a cross-sectional view showing the reverse bias test and the device structure.

[0018] Figure 7 This is a schematic diagram showing the gate bias test of a semiconductor test apparatus.

[0019] Figure 8 It is a cross-sectional view showing the gate bias test and device structure.

[0020] Figure 9 It is a graph representing the initial characteristics of the leakage current.

[0021] Figure 10 It is a cross-sectional view used to illustrate the normal structure of a device.

[0022] Figure 11 It is a cross-sectional view used to illustrate the construction of a device with potential defects.

[0023] Figure 12 This is a process diagram illustrating an example of a semiconductor device manufacturing method in a specific manner.

[0024] Figure 13 This is a process diagram illustrating an example of a potentially defective inspection procedure.

[0025] Figure 14 This is a process diagram illustrating other examples of manufacturing methods for semiconductor devices in a specific manner.

[0026] Figure 15 This is a cross-sectional view showing a major part of the wafer structure of the second example.

[0027] Figure 16 This is a cross-sectional view showing a major part of the wafer structure of the third example.

[0028] Figure 17 This is a cross-sectional view showing a major part of the wafer structure of the fourth example.

[0029] Figure 18 yes Figure 17 A cross-sectional view of the wafer structure shown.

[0030] Figure 19 This is a cross-sectional view showing the wafer structure of the fifth example. Detailed Implementation

[0031] The specific methods will be described in detail below with reference to the accompanying drawings. The accompanying drawings are schematic diagrams and not strictly schematic; relative positions, scales, proportions, angles, etc., may not be consistent. Corresponding structures in the accompanying drawings will be labeled with the same reference numerals, and repeated descriptions will be omitted or simplified. For structures where descriptions have been omitted or simplified, the description preceding the omission or simplification will apply.

[0032] When the term "substantially" is used in this specification, it includes, in addition to the numerical value (method) that is equal to the numerical value (method) of the comparison object, a numerical error (method error) within ±10% of the numerical value (method) of the comparison object. In the following description, terms such as "first," "second," etc., are used, but these are notations assigned to the names of the constructs to clarify the order of description, and not to limit the names of the constructs.

[0033] In the following description, "p-type" or "n-type" is used to represent the conductivity type of the semiconductor (impurity). "P-type" can be referred to as the "first conductivity type," and "n-type" as the "second conductivity type." Alternatively, "n-type" can be called the "first conductivity type," and "p-type" the "second conductivity type." "P-type" is a conductivity type derived from trivalent elements, and "n-type" is a conductivity type derived from pentavalent elements. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0034] Figure 1 This is a schematic diagram showing the wafer structure 1A of the first embodiment. Figure 2 yes Figure 1 The cross-sectional view of wafer structure 1A shown. Figure 3 It means Figure 1 This is a cross-sectional view of a major portion of the device structure 11 of the wafer structure 1A shown. The wafer structure 1A is an intermediate for the manufacture of the semiconductor device 10.

[0035] Reference Figure 1 and Figure 2 The wafer structure 1A includes a wafer 2 formed in the shape of a flat disk. The wafer 2 may also be formed in the shape of a flat cuboid. The wafer 2 includes a SiC single crystal, which is an example of a wide-bandgap semiconductor single crystal. That is, the wafer 2 is composed of a SiC wafer. A wide-bandgap semiconductor single crystal is a semiconductor single crystal with a higher bandgap than a Si single crystal.

[0036] In this embodiment, wafer 2 is composed of hexagonal SiC single crystals and is formed into a cuboid shape. Hexagonal SiC single crystals have various polymorphs, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. This embodiment represents an example where wafer 2 contains 4H-SiC single crystals, but wafer 2 can also contain other polymorphs.

[0037] Wafer 2 has: a first surface 3 on one side, a second surface 4 on the other side, and a peripheral end surface 5 connecting the first surface 3 and the second surface 4. The first surface 3 is a device surface that extends flatly in the horizontal direction. The second surface 4 is a non-device surface that extends flatly in the horizontal direction. That is, the second surface 4 extends substantially parallel to the first surface 3. The peripheral end surface 5 extends vertically between the first surface 3 and the second surface 4.

[0038] The first surface 3 and the second surface 4 are preferably formed from the c-plane of a SiC single crystal. In this case, it is preferable that the first surface 3 is formed from the silicon surface ((0001) surface) of the SiC single crystal and the second surface 4 is formed from the carbon surface ((000-1) surface) of the SiC single crystal.

[0039] Wafer 2 (first face 3 and second face 4) has an offset angle that is tilted at a specified angle in a specified offset direction relative to the c-plane of the SiC single crystal. That is, the amount of the offset angle by which the c-axis ((0001) axis) of the SiC single crystal is tilted from the vertical axis toward the offset direction. In addition, the amount of the offset angle by which the c-plane of the SiC single crystal is tilted relative to the horizontal plane.

[0040] The deviation direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The deviation angle can be greater than 0° and less than 10°. The deviation angle can have a value belonging to at least one of the following ranges: greater than 0° and less than 1°, greater than 1° and less than 2.5°, greater than 2.5° and less than 5°, greater than 5° and less than 7.5°, and greater than 7.5° and less than 10°.

[0041] The deviation angle is preferably 5° or less. Particularly preferred is a deviation angle of 2° or more but less than 4.5°. The deviation angle is typically set in the range of 4° ± 0.1°. This specification does not exclude a deviation angle of 0° (i.e., the first surface 3 is the front face relative to surface c).

[0042] The wafer 2 has a mark 5a on its peripheral end face 5 indicating the crystal orientation of the SiC single crystal. The mark 5a can indicate either the a-axis direction or the m-axis direction ([1-100] directions). In this embodiment, the mark 5a includes a notch. The notch can also be called a "positioning notch". The notch is formed by a cut that is recessed into a pointed shape along the a-axis direction or the m-axis direction toward the center of the first face 3.

[0043] Wafer 2, when viewed from above, may have a diameter of 2 inches or more and 12 inches or less (50 mm or more and 300 mm or less). The diameter of wafer 2 is defined by the length of a chord passing through the center of wafer 2 outside of mark 5a (i.e., the diameter). The diameter of wafer 2 is preferably 6 inches or more (150 mm or more). The diameter of wafer 2 is particularly preferably 8 inches or more (200 mm or more).

[0044] In this embodiment, wafer 2 has a stacked structure comprising a first semiconductor layer 6 and a second semiconductor layer 7. The first semiconductor layer 6 is the main body of the wafer, constituting the portion of the wafer 2 other than the surface portion of the first surface 3. The first semiconductor layer 6 is composed of SiC single crystal, an example of a wide-bandgap semiconductor single crystal, and has the aforementioned offset direction and offset angle. The first semiconductor layer 6 forms the second surface 4 of wafer 2 and forms part or all of the peripheral end surface 5.

[0045] The second semiconductor layer 7 is composed of a SiC epitaxial layer (SiC semiconductor layer) formed by crystallizing a SiC single crystal, which is an example of a wide-bandgap semiconductor single crystal, from the first semiconductor layer 6, and has the aforementioned deviation direction and deviation angle. That is, in this embodiment, the wafer 2 is composed of an epitaxial wafer (so-called epitaxial wafer).

[0046] The wafer structure 1A includes multiple device regions 8 and multiple dicing lines 9 formed on the wafer 2. For example, the multiple device regions 8 and multiple dicing lines 9 are divided by alignment marks formed on the first surface 3 (second semiconductor layer 7).

[0047] Multiple device regions 8 are regions corresponding to semiconductor devices 10, and are cut out as multiple semiconductor devices 10 during the dicing process. The multiple device regions 8 are arranged neatly (e.g., in a matrix) along the a-axis and m-axis directions. When viewed from above, each of the multiple device regions 8 is divided into quadrilateral shapes. Multiple predetermined cutting lines 9 extend in a grid pattern along the a-axis and m-axis directions, dividing the multiple device regions 8.

[0048] The wafer structure 1A includes multiple device structures 11 formed in multiple device regions 8 on the first surface 3. Each device structure 11 may include at least one of a switching device, a rectifier device, and a passive device. The switching device may include at least one of MISFET (Metal Insulator Semiconductor Field Effect Transistor), BJT (Bipolar Junction Transistor), IGBT (Insulated Gate Bipolar Junction Transistor), and JFET (Junction Field Effect Transistor).

[0049] The rectifier may include at least one of the following: pn junction diode, pin junction diode, Zener diode, Schottky barrier diode, and fast recovery diode. Passive components may include at least one of the following: resistor, capacitor, inductor, and fuse.

[0050] Each device configuration 11 may include a circuit network (e.g., an integrated circuit such as an LSI) composed of at least two of switching devices, rectifier devices, and passive devices. In this embodiment, each device configuration 11 includes a MISFET configuration as an example of a transistor configuration Tr. Since the configurations of multiple device regions 8 (device configurations 11) are identical, the configuration of one device region 8 (device configuration 11) will be described below.

[0051] Figure 3 It means Figure 1 A cross-sectional view of a major portion of the device configuration 11 of the wafer configuration 1A shown. (Refer to...) Figure 3 The wafer structure 1A includes an n-type first semiconductor region 12 formed inside the wafer 2 in a region (surface layer) on the second surface 4. A drain potential Vd is assigned to the first semiconductor region 12. The first semiconductor region 12 may also be referred to as the "drain region".

[0052] The first semiconductor region 12 is formed inside the first semiconductor layer 6 and extends in a layered manner along the second surface 4. In this embodiment, the first semiconductor region 12 is formed over the entire area of ​​the first semiconductor layer 6 and is exposed from the second surface 4 and the peripheral end surface 5. In this embodiment, an n-type first semiconductor layer 6 is used, and the first semiconductor region 12 is formed using the n-type first semiconductor layer 6.

[0053] The wafer structure 1A includes an n-type second semiconductor region 13 formed inside the wafer 2 in a region (surface layer) on the side of the first surface 3. The second semiconductor region 13 may also be referred to as a "drift region". The second semiconductor region 13 has a lower n-type impurity concentration than the first semiconductor region 12.

[0054] The second semiconductor region 13 is formed inside the second semiconductor layer 7 and extends in a layered manner along the first surface 3. The second semiconductor region 13 is electrically connected to the first semiconductor region 12 in the stacking direction. In this embodiment, the second semiconductor region 13 is formed over the entire area of ​​the second semiconductor layer 7 and is exposed from the first surface 3 and the peripheral end surface 5. In this embodiment, an n-type second semiconductor layer 7 is used, and the second semiconductor region 13 is formed using the n-type second semiconductor layer 7.

[0055] The wafer structure 1A includes a p-type body region 14 formed on the surface portion of the first surface 3. The body region 14 is formed on the surface portion of the second semiconductor region 13 (i.e., the second semiconductor layer 7). The body region 14 is formed at intervals from the bottom of the second semiconductor region 13 toward the first surface 3, and the body region 14 sandwiches a portion of the second semiconductor region 13 and faces the first semiconductor region 12 (i.e., the first semiconductor layer 6).

[0056] The wafer structure 1A includes an n-type source region 15 formed on the surface portion of the body region 14. The source region 15 has a higher n-type impurity concentration than the second semiconductor region 13. The source region 15 forms a channel for a MISFET structure with the second semiconductor region 13 within the body region 14.

[0057] The wafer structure 1A includes a plurality of trench electrode-type gate structures 20 formed at intervals on a first surface 3. A gate potential Vg is applied to the gate structures 20. The gate structures 20 may also be referred to as the "first structure" or the "trench gate structure". The plurality of gate structures 20 control the inversion and non-inversion of the channel.

[0058] Multiple gate structures 20 are arranged at intervals along the m-axis and extend in a strip-like manner along the a-axis. Alternatively, the multiple gate structures 20 can also be arranged at intervals along the a-axis and extend in a strip-like manner along the m-axis. The multiple gate structures 20 penetrate the body region 14 and the source region 15, and are formed at intervals from the bottom of the second semiconductor region 13 toward the first surface 3.

[0059] Each gate structure 20 includes: a gate trench 21 (first trench), a gate insulating film 22 (first insulating film), and a gate electrode 23 (first electrode). The gate trench 21 is formed on the first surface 3. The gate insulating film 22 covers the walls of the gate trench 21. The gate electrode 23 is buried in the gate trench 21 through the gate insulating film 22.

[0060] The wafer structure 1A includes a plurality of trench electrode-type source structures 25 formed on the first surface 3. A source potential Vs is assigned to the source structures 25. The source structures 25 may also be referred to as "second structures" or "trench source structures". The plurality of source structures 25 extend in a strip-like manner in the region between two adjacent gate structures 20 along the a-axis. Alternatively, the plurality of source structures 25 may extend in a strip-like manner along the m-axis, depending on the arrangement of the plurality of gate structures 20.

[0061] Multiple source structures 25 penetrate the body region 14 and the source region 15, and are formed at intervals from the bottom of the second semiconductor region 13 toward the first surface 3. The multiple source structures 25 are formed deeper than the multiple gate structures 20. The multiple source structures 25 may have a depth approximately equal to that of the gate structures 20.

[0062] Each source electrode structure 25 includes: a source trench 26 (second trench), a source insulating film 27 (second insulating film), and a source electrode 28 (second electrode). The source trench 26 is formed on the first surface 3. The source insulating film 27 covers the wall of the source trench 26. The source electrode 28 is embedded in the source trench 26, sandwiching the source insulating film 27.

[0063] The wafer structure 1A includes a plurality of p-type contact regions 30 formed within a second semiconductor region 13 along regions of a plurality of source structures 25. The plurality of contact regions 30 have a higher p-type impurity concentration than the p-type impurity concentration of the bulk region 14.

[0064] Multiple contact areas 30 are formed in a one-to-many correspondence with a corresponding source structure 25. In top view, multiple contact areas 30 are formed at intervals along the corresponding source structure 25. Each contact area 30 extends along the sidewall and bottom wall of the corresponding source structure 25 and is electrically connected to the body region 14 on the surface of the first surface 3.

[0065] The wafer structure 1A includes a plurality of p-type well regions 31 formed in a second semiconductor region 13 along a region of a plurality of source structures 25. Each well region 31 has a p-type impurity concentration that is higher than that of the body region 14 and lower than that of the contact region 30.

[0066] Multiple well regions 31 are formed in a one-to-one correspondence with a corresponding source structure 25. When viewed from above, the multiple well regions 31 are formed as a strip extending along the corresponding source structure 25. Each well region 31 is sandwiched between multiple corresponding contact regions 30 and faces the corresponding source structure 25. Each well region 31 extends along the sidewall and bottom wall of the corresponding source structure 25, and is electrically connected to the body region 14 on the surface portion of the first surface 3.

[0067] The wafer structure 1A includes an insulating interlayer film 35 covering the first surface 3. Figure 2 In the overall cross-sectional view shown on the lower side of the paper, the interlayer film 35 is omitted for convenience (the same applies below in the corresponding figures). The interlayer film 35 may comprise at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 35 is formed over approximately the entire area of ​​the first surface 3. The interlayer film 35 covers multiple gate structures 20 in each device region 8.

[0068] The wafer structure 1A includes: a gate terminal 40, a source terminal 41, and a gate wiring 42. Figure 2 In the overall cross-sectional view shown on the lower side of the paper, for convenience, the illustrations of the gate terminal 40, the source terminal 41, and the gate wiring 42 are omitted (the same applies in the corresponding figures below).

[0069] Gate terminal 40 is disposed on interlayer film 35. Gate terminal 40 is a terminal electrode to which a gate potential Vg is imparted from the outside. Gate terminal 40 may be referred to as "first terminal electrode", "first pad electrode", "gate pad electrode", etc. Gate terminal 40 is disposed in the central region near one side of device region 8. Gate terminal 40 may also be disposed at a corner of device region 8. Gate terminal 40 is formed in a quadrilateral shape.

[0070] The gate terminal 40 may have a stacked structure comprising a Ti-based metal film and an Al-based metal film. The Ti-based metal film may comprise one or both of a Ti film and a TiN film. The Al-based metal film may comprise one or both of an Al film and an Al alloy film. The Al alloy film may also comprise at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0071] The source terminal 41 is disposed on the interlayer film 35, spaced apart from the gate terminal 40. The source terminal 41 is a terminal electrode to which a source potential Vs is imparted from the outside. The source terminal 41 may be referred to as a "second terminal electrode," "second pad electrode," "source pad electrode," etc. The source terminal 41 may contain the same conductive material as the conductive material of the gate terminal 40 and have a thickness approximately equal to that of the gate terminal 40.

[0072] The source terminal 41 is formed as a polygon with a recess along the gate terminal 40. The source terminal 41 may be formed as a quadrilateral shape. The source terminal 41 is electrically connected to the body region 14, the source region 15 and the multiple source structures 25 via a plurality of through holes formed in the interlayer film 35.

[0073] The maximum rated gate voltage that can be applied between the gate terminal 40 and the source terminal 41 can be 1V or higher and 100V or lower. The maximum rated gate voltage can have a value belonging to at least one of the following ranges: 1V or higher and 10V or lower, 10V or higher and 20V or lower, 20V or higher and 30V or lower, 30V or higher and 40V or lower, 40V or higher and 50V or lower, 50V or higher and 60V or lower, 60V or higher and 70V or lower, 70V or higher and 80V or lower, 80V or higher and 90V or lower, and 90V or higher and 100V or lower.

[0074] Gate wiring 42 extends from gate terminal 40 onto interlayer film 35. Gate wiring 42 may contain the same conductive material as the conductive material of gate terminal 40 and has a thickness substantially equal to that of gate terminal 40. Gate wiring 42 extends in a strip along source terminal 41 in a manner that surrounds source terminal 41. Gate wiring 42 intersects (specifically orthogonally) the ends of the plurality of gate structures 20 and is electrically connected to the plurality of gate structures 20 via a plurality of through-holes formed in interlayer film 35.

[0075] The wafer structure 1A includes an upper insulating film 45 that selectively covers the gate terminal 40 and the source terminal 41 above the interlayer film 35, providing insulation. The upper insulating film 45 covers the entire area of ​​the gate wiring 42. The upper insulating film 45 is preferably thicker than the gate terminal 40 (source terminal 41).

[0076] The upper insulating film 45 may comprise at least one of an inorganic insulating film and an organic insulating film. The upper insulating film 45 may have a single-layer structure composed of an inorganic or organic insulating film. The upper insulating film 45 may also have a laminated structure comprising an inorganic insulating film and an organic insulating film sequentially stacked from both sides of the wafer. The inorganic insulating film may comprise at least one of a silicon nitride film, a silicon oxynitride film, and a silicon oxide film.

[0077] The organic insulating film may comprise at least one of a photosensitive resin film and a thermosetting resin film. The organic insulating film may have a single-layer structure composed of a photosensitive resin film. The organic insulating film may also have a laminated structure comprising a photosensitive resin film and a thermosetting resin film sequentially stacked from two sides of the wafer.

[0078] The photosensitive resin film can be negative or positive. The photosensitive resin film may contain at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. Thermosetting resin films may contain a matrix resin (e.g., epoxy resin) and multiple fillers.

[0079] The wafer structure 1A includes: a gate opening 46, a source opening 47, and a spacer opening 48 formed on the upper insulating film 45. Figure 2In the overall cross-sectional view shown on the lower side of the paper, for convenience, the gate opening 46, source opening 47 and spacer channel opening 48 are omitted (the same applies in the corresponding figures below).

[0080] Gate opening 46 exposes the interior of gate terminal 40. Source opening 47 exposes the interior of source terminal 41. Spacer opening 48 is formed in a grid pattern along multiple predetermined cut lines 9, exposing one or both of the first surface 3 and interlayer film 35.

[0081] The wafer structure 1A includes a drain terminal 49 formed on the second surface 4. The drain terminal 49 is a terminal electrode to which a drain potential Vd is imparted from the outside. The drain terminal 49 may be referred to as a "third terminal electrode," "third pad electrode," "drain pad electrode," etc. The drain terminal 49 is electrically connected to the first semiconductor region 12 (first semiconductor layer 6). The drain terminal 49 may contain at least one of a Ti film, a Ni film, a Pd film, an Au film, an Ag film, and an Al film.

[0082] The maximum rated drain voltage (i.e., breakdown voltage) that can be applied between the source terminal 41 and the drain terminal 49 (between the first surface 3 and the second surface 4) can be 500V or more and 3000V or less. The maximum rated drain voltage can have a value belonging to at least one of the following ranges: 500V or more and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or less, and 2500V or more and 3000V or less.

[0083] Figure 4 This is a schematic diagram of a semiconductor testing device 51 in a specific manner. Figure 5 This is a schematic diagram showing the high-temperature reverse bias test of the semiconductor test device 51. Figure 6 This is a cross-sectional view showing the high-temperature reverse bias test and device structure 11. Figure 7 This is a schematic diagram showing the high-temperature gate bias test of the semiconductor test apparatus 51. Figure 8 This is a cross-sectional view showing the high-temperature gate bias test and device configuration 11.

[0084] Reference Figures 4-8 Semiconductor test apparatus 51 is a test apparatus used to perform high-temperature reverse bias testing. High-temperature reverse bias testing can also be called "HTRB testing." High-temperature reverse bias testing involves applying a reverse bias voltage VRB to device structure 11 at a high-temperature environment to check the characteristics of the leakage current IL (see reference). Figure 5 and Figure 6High-temperature reverse bias testing can be classified as high-temperature and high-humidity reverse bias testing. In high-temperature and high-humidity reverse bias testing, a reverse bias voltage VRB is applied to device configuration 11 under high-temperature and high-humidity conditions, and the characteristics of leakage current IL are examined.

[0085] High-temperature reverse bias testing can be performed as a full inspection or a sampling inspection. In a full inspection, all electrical characteristics of multiple device configurations 11 are checked. The leakage current IL characteristics of the multiple device configurations 11 can be checked simultaneously or sequentially. In a sampling inspection, the electrical characteristics of one or more device configurations 11 selected from the multiple device configurations 11 are checked. High-temperature reverse bias testing is preferably a full inspection.

[0086] The test period for high-temperature reverse bias testing can be more than 10 hours and less than 3000 hours. The test period for high-temperature reverse bias testing can also be set to a value within at least one of the following ranges: more than 10 hours and less than 100 hours, more than 100 hours and less than 500 hours, more than 500 hours and less than 1000 hours, more than 1000 hours and less than 1500 hours, more than 1500 hours and less than 2000 hours, more than 2000 hours and less than 2500 hours, and more than 2500 hours and less than 3000 hours.

[0087] Semiconductor test apparatus 51 can be configured to perform high-temperature gate bias test in addition to high-temperature reverse bias test (see reference). Figure 7 as well as Figure 8 The high-temperature gate bias test, also known as the "HTGB test," involves applying a gate bias voltage VGS to the gate structure 20 at a high temperature and checking the characteristics of the gate leakage current IGS.

[0088] High-temperature gate bias testing can be performed as a full inspection or a sampling inspection. In a full inspection, all characteristics of multiple device configurations 11 are examined. The gate leakage current (IGS) characteristics of the multiple device configurations 11 can be examined simultaneously or sequentially. In a sampling inspection, the characteristics of one or more device configurations 11 selected from the multiple device configurations 11 are examined. High-temperature gate bias testing is preferably performed as a full inspection.

[0089] The test period for high-temperature gate bias testing can be more than 10 hours and less than 3000 hours. The test period for high-temperature gate bias testing can be set to a value within at least one of the following ranges: more than 10 hours and less than 100 hours, more than 100 hours and less than 500 hours, more than 500 hours and less than 1000 hours, more than 1000 hours and less than 1500 hours, more than 1500 hours and less than 2000 hours, more than 2000 hours and less than 2500 hours, and more than 2500 hours and less than 3000 hours.

[0090] Reference Figure 4 The semiconductor testing apparatus 51 includes a chamber 52, a heating unit 53, a voltage application unit 54, a voltage generation unit 55, and a control unit 56. The chamber 52 includes box-shaped partitions that divide the testing space, and the chamber 52 has a transfer door 52a for moving the wafer structure 1A in and out. The transfer door 52a can also be an opening and closing gate.

[0091] The heating unit 53 includes a heater disposed within the chamber 52, which raises the temperature within the chamber 52 to a predetermined test temperature. The test temperature can be above 50°C and below 350°C. The test temperature can have a value falling within at least one of the following ranges: above 50°C and below 75°C, above 75°C and below 100°C, above 100°C and below 125°C, above 125°C and below 150°C, above 150°C and below 175°C, above 175°C and below 200°C, above 200°C and below 225°C, above 225°C and below 250°C, above 250°C and below 275°C, above 275°C and below 300°C, above 300°C and below 325°C, and above 325°C and below 350°C. Preferably, the test temperature is above 100°C and below 250°C.

[0092] The voltage application unit 54 is a unit that applies a specified test voltage to the device structure 11 (wafer structure 1A). The voltage application unit 54 includes a stage unit 57 and an application terminal unit 58.

[0093] Platform unit 57 is disposed within chamber 52. Platform unit 57 includes a plate-shaped (in this embodiment, a circular plate-shaped) platform terminal 59 serving as a voltage application terminal. Platform terminal 59 may be made of metal. Platform terminal 59 has a platform surface 60 electrically connected to the second surface 4 (drain terminal 49) of wafer structure 1A.

[0094] An application terminal unit 58 is disposed within a chamber 52. The application terminal unit 58 has one or more (in this embodiment, multiple) application terminals 61 corresponding to the number of terminals of the device configuration 11. The application terminals 61 may be probes. The type and number of application terminals 61 are appropriately adjusted according to the type and number of terminal electrodes of the device configuration 11. In this embodiment, the multiple application terminals 61 include a first application terminal 61A for the gate terminal 40 and a second application terminal 61B for the source terminal 41.

[0095] The application terminal unit 58 can be configured to simultaneously inspect all of a plurality of device structures 11. In this case, a plurality of first application terminals 61A are connected to the gate terminals 40 of all device structures 11, and a plurality of second application terminals 61B are connected to the source terminals 41 of all device structures 11. Of course, the application terminal unit 58 can also be configured to inspect a plurality of device structures 11 individually and sequentially. In this case, one first application terminal 61A is connected to the gate terminal 40 of one device structure 11, and one second application terminal 61B is connected to the source terminal 41 of one device structure 11.

[0096] The voltage generation unit 55 is a unit that generates a predetermined test voltage and outputs it to the voltage application unit 54. The voltage generation unit 55 includes a power supply and is electrically connected to the platform unit 57 and the application terminal unit 58. In this configuration, the voltage generation unit 55 generates a predetermined drain potential Vd, a predetermined gate potential Vg, and a predetermined source potential Vs, which are output to the platform terminal 59, the first application terminal 61A, and the second application terminal 61B, respectively. Thus, the drain potential Vd is applied to the platform terminal 59, the gate potential Vg is applied to the first application terminal 61A, and the source potential Vs is applied to the second application terminal 61B.

[0097] Reference Figure 5 and Figure 6 A high-temperature reverse bias test is performed with the drain terminal 49 of wafer fabrication 1A electrically connected to the platform terminal 59. The voltage generation unit 55 generates a reverse bias voltage VRB for device fabrication 11 during the high-temperature reverse bias test. Specifically, the voltage generation unit 55 short-circuits the gate terminal 40 and the source terminal 41, and applies the drain bias voltage VDS, which serves as the reverse bias voltage VRB, to the drain terminal 49.

[0098] That is, the voltage generation unit 55 generates a gate potential Vg, a source potential Vs at the same potential as the gate potential Vg, and a drain potential Vd at a higher potential than the source potential Vs. The gate potential Vg and the source potential Vs can be 0V. The drain bias voltage VDS is the voltage of the drain potential Vd relative to the source potential Vs. In the high-temperature reverse bias test, due to the drain bias voltage VDS, a drain cutoff current IDS, which is the drain current IL, is generated between the source terminal 41 and the drain terminal 49.

[0099] The drain bias voltage VDS can be the maximum rated drain voltage or less than the maximum rated drain voltage. The drain voltage ratio of the drain bias voltage VDS to the maximum rated drain voltage can be 0.5 or more and 1 or less. The drain voltage ratio can have a value belonging to at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 1 or less. The drain voltage ratio is preferably 0.8 or more and 1 or less.

[0100] The drain bias voltage VDS can be above 500V and below 3000V. The drain bias voltage VDS can have a value belonging to at least one of the following ranges: above 500V and below 1000V, above 1000V and below 1500V, above 1500V and below 2000V, above 2000V and below 2500V, and above 2500V and below 3000V.

[0101] Reference Figure 7 and Figure 8 A high-temperature gate bias test is performed with the drain terminal 49 of wafer structure 1A electrically connected to the platform terminal 59. The voltage generation unit 55 generates a gate bias voltage VGS for the gate terminal 40 (first structure) during the high-temperature gate bias test. Specifically, the voltage generation unit 55 short-circuits the source terminal 41 and the drain terminal 49, applying the gate bias voltage VGS to the gate terminal 40.

[0102] That is, the voltage generation unit 55 generates a gate potential Vg, a source potential Vs that is lower than the gate potential Vg, and a drain potential Vd that is at the same potential as the source potential Vs. The source potential Vs and the drain potential Vd can be 0V. The gate bias voltage VGS is the voltage of the gate potential Vg with the source potential Vs as a reference. In the high-temperature gate bias test, due to the gate bias voltage VGS, a gate leakage current IGS is generated between the gate terminal 40 and the source terminal 41.

[0103] The gate bias voltage VGS is adjusted according to the withstand voltage (thickness) of the gate insulating film 22. The gate bias voltage VGS can be the maximum rated gate voltage or less than the maximum rated gate voltage. The gate voltage ratio of the gate bias voltage VGS to the maximum rated gate voltage can be 0.5 or more and 1 or less. The gate voltage ratio can have a value belonging to at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 1 or less. Preferably, the gate voltage ratio is 0.8 or more and 1 or less.

[0104] The gate bias voltage VGS is less than the drain bias voltage VDS. The gate bias voltage VGS can be above 1V and below 100V. The gate bias voltage VGS can have a value belonging to at least one of the following ranges: above 1V and below 10V, above 10V and below 20V, above 20V and below 30V, above 30V and below 40V, above 40V and below 50V, above 50V and below 60V, above 60V and below 70V, above 70V and below 80V, above 80V and below 90V, and above 90V and below 100V.

[0105] The control unit 56 includes a central processing unit, a main storage unit, an auxiliary storage unit, a communication unit, a display unit, an input unit, etc., and is connected to the chamber 52, the heating unit 53, the voltage application unit 54, and the voltage generation unit 55. The control unit 56 controls the chamber 52, the heating unit 53, the voltage application unit 54, and the voltage generation unit 55 with predetermined processing actions according to a predetermined processing procedure stored in the auxiliary storage unit, etc.

[0106] Control unit 56 is configured to detect potential defects in device structure 11 based on the performance of the drain current IL (drain cutoff current IDS) of device structure 11 when a reverse bias voltage VRB (drain bias voltage VDS) is applied. That is, control unit 56 performs a sorting test to investigate the presence of potential defects using a high-temperature reverse bias test. Control unit 56 may be referred to as a "measurement unit," "detection unit," etc. In this specification, "potential defect" refers to a potential initial defect that can evade long-term conventional high-temperature reverse bias testing or high-temperature gate bias testing.

[0107] Hereinafter, after describing a potential defective example of device construction 11, a structural example of control unit 56 will be described. Figure 9 This is a graph showing the initial characteristics of the leakage current IL, based on the application of the reverse bias voltage VRB. Figure 9 In the figure, the vertical axis represents the leakage current IL[A], and the horizontal axis represents the measurement period T[s] of the leakage current IL based on the start of the application of the reverse bias voltage VRB.

[0108] exist Figure 9 The diagram illustrates the first characteristic C1 and the second characteristic C2 of two device structures 11. The first characteristic C1 represents the initial characteristic of the leakage current IL of one device structure 11, and the second characteristic C2 represents the initial characteristic of the leakage current IL of the other device structure 11.

[0109] Referring to the first characteristic C1, the leakage current IL corresponding to a device configuration 11 remains approximately constant during the measurement period T. Here, an example of a device configuration 11 with a leakage current IL of approximately 1 × 10⁻⁴ A during the measurement period T is shown. In a device configuration 11, the rate of variation of the leakage current IL during the measurement period T is less than 5%.

[0110] On the other hand, referring to the second characteristic C2, the leakage current IL corresponding to the other device configuration 11 decreases significantly during the measurement period T. Specifically, the leakage current IL corresponding to the other device configuration 11 decreases starting from the start of the test (the start of the application of the reverse bias voltage VRB). In this example, the leakage current IL corresponding to the other device configuration 11 decreases sharply after the start of the test, and then decreases slowly.

[0111] Regarding the second characteristic C2, based on the initial value Iin of the leakage current IL at the start of the test, the reduction rates of the leakage current IL after 5 seconds, 10 seconds, 25 seconds, 50 seconds, and 150 seconds are ≥20%, ≥30%, ≥60%, ≥60%, and ≥70%, respectively. Here, an example of device configuration 11 with an initial leakage current IL value Iin of approximately 1 × 10⁻⁴ A is shown. The initial value Iin of the leakage current IL is varied depending on the crystal state of wafer 2, the electrical characteristics of device configuration 11, etc.

[0112] Since the leakage current IL corresponding to the second characteristic C2 shows a decreasing trend, it can be inferred that another device configuration 11 has electrical characteristics superior to those of the first device configuration 11. The researchers in this specification conducted an in-depth study on the reduction effect of this leakage current IL. As a result, it was determined that the leakage current IL corresponding to the first characteristic C1 represents the initial characteristic of the leakage current IL corresponding to a normal device configuration 11, while the leakage current IL corresponding to the second characteristic C2 represents the initial characteristic of the leakage current IL corresponding to an abnormal device configuration 11 with potential defects.

[0113] Figure 10 This is a cross-sectional view used to illustrate the normal device structure 11. Figure 11 This is a cross-sectional view used to illustrate the device construction 11 with potential defects. (Refer to...) Figure 10 In the case of normal device configuration 11 (first characteristic C1), when a reverse bias voltage VRB is applied to device configuration 11, a first drain path P1 is formed between the source terminal 41 and the drain terminal 49 via the drain current IL of the wafer 2.

[0114] It is believed that the first drain path P1 is caused by a through-spiral dislocation in the SiC single crystal. In a normal device configuration 11, since the degree of abnormality of the first drain path P1 (through-spiral dislocation) is within the design range, the leakage current IL does not show any abnormality.

[0115] In contrast, refer to Figure 11 In the potentially defective device structure 11 (second characteristic C2), in addition to the first drain path P1, there is a tendency for one or both of the second drain path P2 and the third drain path P3 to form. The second drain path P2 is caused by crystallization defects in the semiconductor single crystal, and the third drain path P3 is caused by unwanted residues generated during the manufacturing process. In the potentially defective device structure 11, a significant trend is observed in the second drain path P2 caused by crystallization defects.

[0116] In most cases, crystallization defects in semiconductor single crystals are stacking faults formed within wafer 2, extending in the lateral direction along the first face 3 (second face 4). Stacking faults in semiconductor single crystals can form in one or both of the first semiconductor layer 6 and the second semiconductor layer 7. Stacking faults in semiconductor single crystals are a challenge in the wafer 2 manufacturing process, and the second drain path P2 may already exist before the device fabrication process 11.

[0117] The second leakage path P2 may be formed or expanded due to loads (stress, etc.) during the forming process of the device structure 11. The second leakage path P2 may be formed or expanded as a result of leakage current IL flowing through the first leakage path P1, which has an abnormality. On the other hand, residues generated during the manufacturing process may be produced during the forming process of the device structure 11 and other processes, and may adhere to the first surface 3 and / or the structure on the first surface 3.

[0118] In a potentially defective device configuration 11, it is assumed that an abnormality in leakage current IL is caused by an anomaly in at least one of the first leakage path P1, the second leakage path P2, and the third leakage path P3, or a combination of at least two of them.

[0119] When an anomaly exceeding the design range exists in the first drain path P1 (through screw dislocation), a portion of the leakage current IL is consumed as heat at the anomalous portion of the first drain path P1 (through screw dislocation). When a second drain path P2 (stacked fault) exists, a portion of the leakage current IL flows into the second drain path P2 (stacked fault) and is consumed as heat. When a third drain path P3 (residue) exists, a portion of the leakage current IL flows into the third drain path P3 (residue) and is consumed as heat.

[0120] Thus, the potentially defective device configuration 11 has undesirable elements (P1 to P3) that reduce the leakage current IL. Therefore, compared to the normal device configuration 11, the leakage current IL is reduced. In the potentially defective device configuration 11, the leakage current IL decreases at a very small rate at the beginning of the test (initial characteristics). Furthermore, in the potentially defective device configuration 11, the rate of decrease of the leakage current IL becomes slow over time, and good leakage characteristics are observed.

[0121] Therefore, a device structure 11 with potential defects can evade the tests of conventional high-temperature reverse bias testing or high-temperature gate bias testing and be marketed as a semiconductor device 10. In a semiconductor device 10 with potential defects, the cumulative effect of potential defects caused by long-term use increases the risk of device failure.

[0122] Refer again Figure 4 In this embodiment, the control unit 56 includes a measurement unit 62 configured to detect potential defects in the device structure 11 based on the performance (initial characteristics) of the leakage current IL. Specifically, the measurement unit 62 is configured to detect one or both of the following in the device structure 11: crystal defects and residues, based on the performance (initial characteristics) of the leakage current IL.

[0123] The measurement unit 62 is configured to monitor the rate of decrease of the leakage current IL, which is a manifestation (initial characteristic) of the leakage current IL. Specifically, the measurement unit 62 is configured to monitor the rate of decrease of the leakage current IL of the wafer structure 1A (device structure 11) during the application of the reverse bias voltage VRB, and to detect potential defects in the device structure 11 based on the rate of decrease of the leakage current IL.

[0124] More specifically, the measurement unit 62 is configured to have a monitoring period TM, which is a measurement period T based on the start of the application of the reverse bias voltage VRB, and to monitor the rate of decrease of the leakage current IL based on the initial value Iin of the leakage current IL during the monitoring period TM (see reference). Figure 9 ).

[0125] The initial value of the leakage current IL, Iin, can be any value of the leakage current IL measured within 5 seconds from the start of the application of the reverse bias voltage VRB. Preferably, the initial value of the leakage current IL, Iin, is set to any value of the leakage current IL measured within 1 second from the start of the application of the reverse bias voltage VRB. Alternatively, the initial value of the leakage current IL, Iin, can be the value of the leakage current IL initially detected during the monitoring period TM.

[0126] The rate of decrease of leakage current IL per unit time varies depending on the potential defect type or the specifications of device construction 11. Therefore, the monitoring period TM is appropriately adjusted according to the potential defect type or the specifications of device construction 11. Alternatively, the monitoring period TM can be set based on the statistical values ​​of the reduction time of leakage current IL corresponding to multiple device constructions 11 with potential defects.

[0127] In the case of a conventional high-temperature reverse bias test procedure, the device structure 11 is subjected to a long period of load (e.g., several hours to thousands of hours), therefore, the measurement period T of the leakage current IL is set to be a long period of load (e.g., several hours to thousands of hours).

[0128] On the other hand, if device configuration 11 has a potential defect, the leakage current IL tends to decrease from the point at which the reverse bias voltage VRB is applied due to the potential defect (see reference). Figure 9 Therefore, the monitoring period TM can be set to a shorter period than the measurement period T of the conventional high-temperature reverse bias test procedure.

[0129] The monitoring period TM can be within 60 minutes from the start of the application of the reverse bias voltage VRB. The monitoring period TM can be within 60 minutes, 55 minutes, 50 minutes, 45 minutes, 40 minutes, 35 minutes, 30 minutes, 25 minutes, 20 minutes, 15 minutes, 10 minutes, 5 minutes, or 1 minute. The preferred monitoring period TM is within 30 minutes.

[0130] For example, in the case where the leakage current IL decreases within 100 seconds from the start of the application of the reverse bias voltage VRB (see reference). Figure 9 The second characteristic (C2) allows the monitoring period TM to be within 10 minutes, 5 minutes, or 1 minute. For example, in the case of the second characteristic C2, a potential defect is detected within 400 seconds.

[0131] To avoid false detections of normal leakage characteristics (first characteristic C1), the measurement unit 62 includes a determination unit 63 that determines potential defects in the device structure 11 based on the rate of decrease of the leakage current IL. The determination unit 63 may be configured by software integrated into the measurement unit 62. The determination unit 63 is configured to determine potential defects based on the rate of decrease of the leakage current IL relative to a reference value set for the leakage current IL.

[0132] Specifically, the determination unit 63 determines potential defects based on the rate of reduction of the leakage current IL during the monitoring period, using the initial value Iin of the leakage current IL as a reference. The determination unit 63 can determine that the device structure 11 has a potential defect if the rate of reduction of the leakage current IL, based on the initial value Iin of the leakage current IL, is 10% or more. The determination unit 63 can also determine a potential defect if the rate of reduction of the leakage current IL is 20% or more.

[0133] Regarding the rate of reduction of the leakage current IL based on the initial value Iin of the leakage current IL, the determination unit 63 may have a predetermined leakage threshold LTh. If the rate of reduction of the leakage current IL exceeds the leakage threshold LTh, it is determined that the device structure 11 has a potential defect. The leakage threshold LTh may also be 10% or more and 90% or less.

[0134] The leakage threshold LTh can have a value belonging to at least one of the following ranges: 10% or more and less than 15%, 15% or more and less than 20%, 20% or more and less than 25%, 25% or more and less than 30%, 30% or more and less than 35%, 35% or more and less than 40%, 40% or more and less than 45%, 45% or more and less than 50%, 50% or more and less than 55%, 55% or more and less than 60%, 60% or more and less than 65%, 65% or more and less than 70%, 70% or more and less than 75%, 75% or more and less than 80%, 80% or more and less than 85%, and 85% or more and less than 90%. The leakage threshold LTh is preferably 10% or more. The leakage threshold LTh is particularly preferably 20% or more. The leakage threshold LTh can also be less than 60%. The leakage threshold LTh can also be less than 50%.

[0135] The determination unit 63 can determine that the device structure 11 has a potential defect if the reduction rate of the leakage current IL during the monitoring period TM is greater than or equal to the leakage threshold LTh. For example, if the leakage threshold LTh is set to 20%, the device structure 11 with the second characteristic C2 is determined to have a potential defect after 5 seconds (see reference). Figure 9 For example, with the leakage threshold LTh set to 30%, device construction 11 with second characteristic C2 is determined to have a potential defect after 10 seconds (see reference). Figure 9 ).

[0136] Of course, the determination unit 63 can also determine that the device structure 11 has a potential defect if the reduction rate of the leakage current IL at the end of the monitoring period TM is greater than or equal to the leakage threshold LTh. For example, if the leakage threshold LTh is set to a value in the range of 20% or more and 70% or less, it is determined that the device structure 11 with the second characteristic C2 has a potential defect at the end of the monitoring period TM (see reference). Figure 9 ).

[0137] The control unit 56 can be configured to store the determination result of the potential defect of the device structure 11 in an auxiliary storage device or the like, and to exclude the device structure 11 with potential defects from the production line in subsequent manufacturing processes. In this case, the determination results of potential defects of one or more (preferably all) device structures 11 can be associated with the identification number of the device structure 11 and the mapping of the wafer 2 and stored in the auxiliary storage device or the like.

[0138] Figure 12 This is a process diagram illustrating an example of a manufacturing method for a semiconductor device 10 in a specific manner. Hereinafter, reference will be made as needed. Figures 1 to 11 Additionally, matters that overlap with those described in the description of the semiconductor testing apparatus 51 are appropriately omitted below.

[0139] The method for manufacturing semiconductor device 10 includes: preparing the wafer structure 1A (refer to...) Figures 1-3 The manufacturing method of semiconductor device 10 includes a process (S1) for detecting potential defects in device structure 11. This is achieved using the semiconductor testing apparatus 51 (see reference 51). Figure 4 The potential defect detection procedure (S2) is implemented by incorporating it into the routine high-temperature reverse bias test procedure. In this case, the monitoring period TM can be set to the initial value of the measurement period T of the routine high-temperature reverse bias test (i.e., at the start of the test).

[0140] The potential defect detection step (S2) can be performed separately from the regular high-temperature reverse bias test step. The potential defect detection step (S2) can also be performed before the regular high-temperature reverse bias test. Alternatively, the potential defect detection step (S2) can be performed after the regular high-temperature reverse bias test. Given the characteristic variation of the leakage current IL caused by the regular high-temperature reverse bias test, the potential defect detection step (S2) is preferably performed before the regular high-temperature reverse bias test.

[0141] The following is for reference Figure 13 The inspection process (S2) with potential defects is explained. Figure 13 This is a process diagram illustrating an example of a potentially defective inspection step (S2). (Refer to...) Figure 13 The testing process (S2) includes: transferring the wafer fabrication 1A into the semiconductor testing apparatus 51 (see reference). Figure 4 The process within (S21) is as follows: Wafer structure 1A is configured such that drain terminal 49 is positioned on platform terminal 59 in an orientation opposite to platform surface 60. Thus, drain terminal 49 is electrically connected to platform terminal 59 (see also...). Figure 5 ).

[0142] The testing process (S2) includes a process (S22) of applying a reverse bias voltage VRB to the device structure 11 after the wafer 2 loading process (S21). In the application process (S22), at a specified test temperature, the gate terminal 40 and the source terminal 41 are short-circuited, and a drain bias voltage VDS, which is the reverse bias voltage VRB, is applied to the drain terminal 49 (also referred to). Figure 5 and Figure 6 Thus, a drain cutoff current IDS, which is the drain current IL, is generated between the source terminal 41 and the drain terminal 49.

[0143] The detection step (S2) includes a step (S23) of monitoring the performance of the leakage current IL. The leakage current IL monitoring step (S23) includes a step of monitoring the rate of decrease of the leakage current IL. Specifically, the monitoring step (S23) includes a step of monitoring the rate of decrease of the leakage current IL based on the initial value Iin of the leakage current IL during a specified monitoring period TM based on the start of the application of the reverse bias voltage VRB.

[0144] The monitoring process (S23) includes a process for determining potential defects in device structure 11. In the potential defect determination process (S23), in order to avoid false detection of normal device structure 11, potential defects in device structure 11 are determined based on the reduction rate of leakage current IL. Specifically, in the determination process (S23), potential defects are determined based on the reduction rate of leakage current IL based on the initial value Iin of leakage current IL during the monitoring period TM.

[0145] The determination process (S23) may include a process of determining that the device structure 11 has a potential defect if the reduction rate of the leakage current IL based on the initial value Iin of the leakage current IL is 10% or more. The potential defect determination process (S23) may also include a process of determining that the device structure 11 has a potential defect if the reduction rate of the leakage current IL is 20% or more.

[0146] The potential defect determination process (S23) may include the following steps: regarding the rate of reduction of the leakage current IL based on the initial value Iin of the leakage current IL, having the leakage threshold LTh (e.g., more than 10% and less than 90%), and if the rate of reduction of the leakage current IL exceeds the leakage threshold LTh, determining that the device structure 11 has a potential defect.

[0147] The potential defect detection process (S2) includes a process (S24) of storing the determination results in an auxiliary storage device or the like. In the storage process (S24), the determination results of potential defects of one or more (preferably all) device structures 11 are associated with the identification number of the device structure 11 and the mapping of the wafer 2 and stored in the auxiliary storage device or the like. As a result, in subsequent processes, device structures 11 with potential defects can be excluded from the production line.

[0148] Refer again Figure 12 The manufacturing method of the semiconductor device 10 includes a high-temperature gate bias test (S3). The high-temperature gate bias test (S3) is preferably performed after the potential defect detection process (S2). However, the high-temperature gate bias test (S3) can also be performed before the potential defect detection process (S2).

[0149] In the high-temperature gate bias test (S3), at the specified test temperature, the source terminal 41 and the drain terminal 49 are short-circuited, and the gate bias voltage VGS is applied to the gate configuration 20 (also referred to). Figure 7 and Figure 8 Therefore, a gate leakage current IGS is generated between the gate terminal 40 and the source terminal 41 and monitored. After the high-temperature gate bias test (S3), the wafer structure 1A is removed from the semiconductor test apparatus 51.

[0150] The method for manufacturing semiconductor device 10 includes a step (S4) of dicing wafer structure 1A after high-temperature reverse bias test (S2) and high-temperature gate bias test (S3). In the dicing step (S4), wafer structure 1A is diced along a predetermined dicing line 9 to cut out multiple device regions 8 (device structures 11) as multiple semiconductor devices 10. Semiconductor device 10 is manufactured through the above steps.

[0151] The above describes a method for manufacturing a semiconductor device 10 that includes a reverse bias test (S2) for device structure 11. The reverse bias test (S2) includes an application step (S22) of a reverse bias voltage VRB and a monitoring step (S23) of leakage current IL. In the application step (S22), a reverse bias voltage VRB is applied to device structure 11. In the monitoring step (S23), the rate of decrease of leakage current IL of device structure 11 is monitored when the reverse bias voltage VRB is applied.

[0152] According to this manufacturing method, potentially defective device structures 11 can be detected based on the reduction rate of leakage current IL. For example, the monitoring step (S23) can include a step of determining the potential defects of device structures 11 based on the reduction rate of leakage current IL. Thus, potentially defective device structures 11 can be removed from the production line, and the circulation of potentially defective semiconductor devices 10 to the market can be suppressed.

[0153] The monitoring process (S23) preferably includes a process of determining the potential defects of the device structure 11 based on the rate of reduction of the leakage current IL, which is based on the initial value Iin of the leakage current IL. The leakage current IL of the device structure 11 with potential defects has the characteristic of decreasing from the beginning of the application of the reverse bias voltage VRB (see reference). Figure 9 The second characteristic C2). Therefore, by using the initial value Iin of the leakage current IL as a reference, false detection of normal device configuration 11 is suppressed, and device configuration 11 with potential defects is properly detected.

[0154] The monitoring process (S23) preferably includes a process of determining that the device structure 11 has a potential defect when the reduction rate of leakage current IL is 10% or more. The monitoring process (S23) preferably includes a process of determining that the device structure 11 has a potential defect when the reduction rate of leakage current IL is 20% or more. According to these manufacturing methods, false detections of normal device structures 11 can be appropriately suppressed.

[0155] The monitoring step (S23) may include a step of monitoring the rate of decrease of the leakage current IL starting from the application of the reverse bias voltage VRB. That is, the monitoring step (S23) may include a step of monitoring the initial rate of decrease of the leakage current IL. The monitoring step (S23) may also include a step of monitoring the rate of decrease of the leakage current IL during a monitoring period TM based on the application of the reverse bias voltage VRB.

[0156] The leakage current IL of the device with potentially defective construction 11 has the characteristic of decreasing from the start of the application of the reverse bias voltage VRB (see reference). Figure 9 The second characteristic C2). Therefore, by setting a monitoring period TM based on the start of the application of the reverse bias voltage VRB, it is possible to suppress false detections of normal device configuration 11 and to properly detect device configuration 11 with potential defects.

[0157] The leakage current IL of the device with potentially defective construction 11 has the characteristic of decreasing from the start of the application of the reverse bias voltage VRB (see reference). Figure 9 The second characteristic (C2) allows potential defects to be detected within a relatively short period. For example, the monitoring period TM of the monitoring process (S23) can be set to be shorter than the test time of a conventional high-temperature reverse bias test or a conventional high-temperature gate bias test. For example, the monitoring period TM can be less than 60 minutes. For example, the monitoring period TM can also be less than 30 minutes.

[0158] The reverse bias test (S2) can be a high-temperature reverse bias test (S2) in which a reverse bias voltage VRB is applied at a high temperature. The monitoring step (S23) can be performed in a relatively short period of time, and therefore can be incorporated into the regular high-temperature reverse bias test. For example, the monitoring step (S23) can be incorporated at the beginning of the regular high-temperature reverse bias test.

[0159] The reverse bias voltage VRB can be above 500V and below 3000V. The reverse bias test (S2) is preferably a wafer-level test of the device structure 11 formed on wafer 2. According to this manufacturing method, potential defects in the device structure 11 are detected at the wafer level before the dicing process (S3), therefore, a packaging process for the potentially defective semiconductor device 10 is not required after the dicing process (S3). This reduces manufacturing costs.

[0160] Wafer 2 preferably contains a SiC single crystal, which is an example of a wide-bandgap semiconductor single crystal. According to this manufacturing method, a semiconductor device 10, which is a SiC semiconductor device, is manufactured. In the case of the SiC semiconductor device, the physical properties (electrical characteristics) of the SiC single crystal are suitable for use under high-load conditions (high voltage and / or high temperature environments). For example, the SiC semiconductor device can be used as a drive source for motors in hybrid vehicles, electric vehicles, fuel cell vehicles, etc.

[0161] When using a potentially defective SiC semiconductor device under high-load conditions, the risk of device failure starting from the potentially defective site increases. Regarding this, according to the manufacturing method of the semiconductor device 10, potential defects in the device structure 11, which is the SiC semiconductor device, can be detected. Therefore, the circulation of potentially defective SiC semiconductor devices to the market can be suppressed. This, in turn, can suppress the decrease in application reliability caused by potentially defective SiC semiconductor devices.

[0162] Device structure 11 may include transistor structure Tr. According to this manufacturing method, potential defects in device structure 11 including transistor structure Tr can be detected. Transistor structure Tr may have a gate, a source, and a drain. In this case, the reverse bias voltage VRB is the drain bias voltage VDS, and the drain current IL is the drain cutoff current IDS. The manufacturing method of semiconductor device 10 may include a gate bias test (S3) of transistor structure Tr.

[0163] In another viewpoint, specifically, a semiconductor test apparatus 51 is provided for performing a reverse bias test (S2) on device fabrication 11. The semiconductor test apparatus 51 includes a voltage application unit 54, a voltage generation unit 55, and a control unit 56. The voltage application unit 54 applies a test voltage to device fabrication 11. The voltage generation unit 55 generates a reverse bias voltage VRB as the test voltage and outputs it to the voltage application unit 54. The control unit 56 monitors the rate of decrease of leakage current IL of device fabrication 11 when the reverse bias voltage VRB is applied.

[0164] According to the semiconductor testing apparatus 51, potentially defective device structures 11 can be detected based on the reduction rate of leakage current IL. For example, the control unit 56 can determine the potential defects of device structures 11 based on the reduction rate of leakage current IL. Thus, potentially defective device structures 11 can be removed from the production line, and the circulation of potentially defective semiconductor devices 10 to the market can be suppressed.

[0165] The control unit 56 preferably determines the potential defect of the device structure 11 based on the rate of reduction of the leakage current IL, which is based on the initial value Iin of the leakage current IL. According to this structure, false detection of normal device structures 11 can be suppressed, and device structures 11 with potential defects can be appropriately detected.

[0166] The control unit 56 preferably determines that the device structure 11 has a potential defect when the reduction rate of leakage current IL is 10% or more. The control unit 56 preferably determines that the device structure 11 has a potential defect when the reduction rate of leakage current IL is 20% or more. Based on these structures, false detections of normal device structure 11 can be appropriately suppressed.

[0167] The control unit 56 preferably monitors the rate of decrease of the leakage current IL during a monitoring period TM, based on the start of the application of the reverse bias voltage VRB. According to this configuration, false detections of normal device configurations 11 can be suppressed, and potentially defective device configurations 11 can be appropriately detected. For example, the monitoring period TM can be less than 60 minutes. Alternatively, the monitoring period TM can be less than 30 minutes.

[0168] The reverse bias test (S2) can also be a high-temperature reverse bias test (S2). The reverse bias voltage VRB can be above 500V and below 3000V. The reverse bias test (S2) is preferably a wafer-level test of the device structure 11 formed on wafer 2.

[0169] According to the semiconductor testing apparatus 51, potential defects in the device fabrication 11 are detected at the wafer level before the dicing process (S3). Therefore, a packaging process for the semiconductor device 10 with potential defects is not required after the dicing process (S3). This reduces manufacturing costs.

[0170] The wafer 2 preferably contains a SiC single crystal, which is an example of a wide-bandgap semiconductor single crystal. According to this semiconductor testing apparatus 51, potential defects in the device structure 11 of the SiC semiconductor device can be detected. Therefore, according to this semiconductor testing apparatus 51, the circulation of SiC semiconductor devices with potential defects to the market can be suppressed, and the decrease in application reliability caused by SiC semiconductor devices with potential defects can be suppressed. The semiconductor testing apparatus 51 may be an apparatus for performing reverse bias testing (S2) on the device structure 11 of an automotive semiconductor device 10 (SiC semiconductor device).

[0171] Device structure 11 may include transistor structure Tr. According to the semiconductor test apparatus 51, potential defects in device structure 11 including transistor structure Tr can be detected. Transistor structure Tr may have a gate, a source, and a drain. In this case, the reverse bias voltage VRB is the drain bias voltage VDS, and the drain current IL is the drain cutoff current IDS. Semiconductor test apparatus 51 may be configured to perform a gate bias test on transistor structure Tr (S3).

[0172] Figure 14 This is a process diagram illustrating another example of a method for manufacturing a semiconductor device 10. In this other example of the semiconductor device 10 manufacturing method, a potential defect detection step (S2) as a high-temperature reverse bias test is performed, while the high-temperature gate bias test (S3) is omitted. In the high-temperature gate bias test (S3), a gate bias voltage VGS, which is lower than the drain bias voltage VDS of the potential defect detection step (S2), is applied to the gate structure 20.

[0173] Therefore, the load applied to the gate structure 20 due to the gate bias voltage VGS may be smaller than the load applied to the gate structure 20 due to the drain bias voltage VDS. Therefore, in order to ensure the reliability of the gate structure 20 in the potential defect detection process (S2), other examples of semiconductor device 10 manufacturing methods can be used. Of course, the potential defect detection process (S2) can also be incorporated into a conventional high-temperature reverse bias test.

[0174] The following are examples of other ways of constructing wafer 1A. Figure 15 This is a cross-sectional view of a major portion of the device structure 11 of the wafer structure 1B in the second embodiment. (Refer to...) Figure 15 In the second example, the wafer structure 1B does not have a source structure 25 in the device structure 11.

[0175] In this configuration, the contact region 30 is formed on the surface portion of the body region 14 in the region between two adjacent gate structures 20. In this configuration, the source terminal 41 is electrically connected to the body region 14, the source region 15, and the multiple contact regions 30 via a plurality of through-holes formed in the interlayer film 35.

[0176] Figure 16 This is a cross-sectional view of a major portion of the device structure 11 of the wafer structure 1C in the third embodiment. (Refer to...) Figure 16 In the third embodiment, the wafer structure 1C has a planar electrode type gate structure 20 instead of a trench electrode type gate structure 20 in the device structure 11. The gate structure 20 can also be called a "planar gate structure". Since multiple device structures 11 have the same structure, the structure of one device structure 11 will be described below.

[0177] The wafer structure 1C includes a plurality of p-type body regions 14 formed at intervals on the surface portion of the first surface 3. The plurality of body regions 14 are formed on the surface portion of the second semiconductor region 13 (i.e., the second semiconductor layer 7). The plurality of body regions 14 are formed at intervals from the bottom of the second semiconductor region 13 toward the first surface 3, sandwiching a portion of the second semiconductor region 13 and facing the first semiconductor region 12 (i.e., the first semiconductor layer 6).

[0178] The wafer structure 1C includes multiple n-type source regions 15 formed on the surface portions of multiple body regions 14. The multiple source regions 15 are formed at intervals from each other on the surface portions of their respective body regions 14. The multiple source regions 15 respectively form a second semiconductor region 13 and a channel of a MISFET structure on the surface portions of their respective body regions 14.

[0179] The wafer structure 1C includes multiple n-type contact regions 30 formed on the surface portions of multiple body regions 14. The multiple contact regions 30 are formed in the regions between adjacent multiple source regions 15 on the surface portions of the corresponding body regions 14.

[0180] The wafer structure 1C includes a plurality of planar electrode-type gate structures 20 arranged at intervals on a first surface 3. The plurality of gate structures 20 are respectively arranged across two adjacent body regions 14, respectively covering a plurality of source regions 15 located in one and the other body regions 14.

[0181] Each gate structure 20 has a stacked structure including a gate insulating film 22 and a gate electrode 23. The gate insulating film 22 is configured to span two adjacent body regions 14, covering a plurality of source regions 15 located within one and the other body regions 14. The gate electrode 23 is configured on the gate insulating film 22, spanning two adjacent body regions 14, covering the plurality of source regions 15 located within one and the other body regions 14, sandwiching the gate insulating film 22. The gate electrode 23 sandwiches the gate insulating film 22 and faces a plurality of channels.

[0182] The wafer structure 1C is the same as the wafer structure 1A of the first embodiment, including: an interlayer film 35, a gate terminal 40, a source terminal 41, a gate wiring 42, an upper insulating film 45, and a drain terminal 49. In this embodiment, the source terminal 41 is electrically connected to a plurality of body regions 14, a plurality of source regions 15, and a plurality of contact regions 30 via a plurality of through-holes formed in the interlayer film 35.

[0183] Figure 17 This is a cross-sectional view of a major part of the device structure 11 of the wafer structure 1D of the fourth embodiment. Figure 18 yes Figure 17 The diagram shows a cross-sectional view of wafer structure 1D. Wafer structure 1A has a transistor structure Tr, which is an example of device structure 11. In contrast, wafer structure 1D of the fourth embodiment has a diode structure Di, which is an example of device structure 11. In this embodiment, the first semiconductor region 12 is formed as a "cathode region". Since multiple device structures 11 have the same structure, the structure of one device structure 11 will be described below.

[0184] The wafer structure 1D includes a p-type impurity region 70 formed on the surface portion of the first surface 3. The impurity region 70 is formed on the surface portion of the second semiconductor region 13. When viewed from above, the impurity region 70 is formed as a polygonal ring (in this embodiment, a quadrilateral ring) surrounding the interior of the device region 8. The impurity region 70 is formed at intervals from the bottom of the second semiconductor region 13 toward the first surface 3, sandwiching a portion of the second semiconductor region 13 and facing the first semiconductor region 12.

[0185] The wafer structure 1D is similar to the wafer structure 1A of the first embodiment, including an interlayer film 35 that selectively covers the first surface 3. The interlayer film 35 is formed over substantially the entire area of ​​the first surface 3 and has an opening 71 that selectively exposes the first surface 3. In this embodiment, the opening 71 has an opening wall located above the impurity region 70, exposing the second semiconductor region 13 and the inner edge of the impurity region 70. When viewed from above, the opening 71 is formed as a polygon (quadrilateral shape in this embodiment) extending along the impurity region 70, exposing the inner periphery of the impurity region 70 throughout its entire circumference.

[0186] The wafer structure 1D includes an anode terminal 72 disposed on the first surface 3. The anode terminal 72 is a terminal electrode to which an anode potential Va is applied from the outside. The anode terminal 72 may also be referred to as a "first terminal electrode", "first pad electrode", "anode pad electrode", etc. When viewed from above, the anode terminal 72 is formed as a polygon (quadrilateral shape in this embodiment) along the periphery of the device region 8.

[0187] The anode terminal 72 extends from the interlayer film 35 into the opening 71, and is electrically connected within the opening 71 to the inner edge of the second semiconductor region 13 and the impurity region 70. The anode terminal 72 and the second semiconductor region 13 form a Schottky junction. Thus, a Schottky barrier diode structure, as an example of diode structure Di, is formed in the device region 8. The Schottky barrier diode structure has an anode terminal 72 as the anode and a second semiconductor region 13 (first semiconductor region 12) as the cathode.

[0188] The wafer structure 1D is similar to the wafer structure 1A of the first embodiment, including an upper insulating film 45 covering the first surface 3. The upper insulating film 45 is formed on the interlayer film 35 and covers the first surface 3 through the interlayer film 35. The upper insulating film 45 selectively covers the anode terminal 72 on the interlayer film 35. The upper insulating film 45 is preferably thicker than the anode terminal 72.

[0189] The wafer structure 1A includes an anode opening 73 and a spacer opening 48 formed on the upper insulating film 45. The anode opening 73 exposes the interior of the anode terminal 72. The spacer opening 48 is formed in a lattice shape along a plurality of predetermined cut lines 9, exposing one or both of the first surface 3 and the interlayer film 35.

[0190] The wafer structure 1A includes a cathode terminal 74 formed on the second surface 4. The cathode terminal 74 is a terminal electrode to which a cathode potential Vc is applied from the outside. The cathode terminal 74 may also be referred to as a "second terminal electrode," "second pad electrode," "cathode pad electrode," etc. The cathode terminal 74 is electrically connected to the first semiconductor region 12 (first semiconductor layer 6). The cathode terminal 74 may also include at least one of a Ti film, a Ni film, a Pd film, an Au film, an Ag film, and an Al film.

[0191] The maximum rated reverse voltage (i.e., breakdown voltage) that can be applied between the anode terminal 72 and the cathode terminal 74 (between the first surface 3 and the second surface 4) can also be 500V or more and 3000V or less. The maximum rated drain voltage can have a value belonging to at least one of the following ranges: 500V or more and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or less, and 2500V or more and 3000V or less.

[0192] When using a 1D wafer fabrication structure, the aforementioned potential defect detection process (high-temperature reverse bias test) (S2) is performed, but the high-temperature gate bias test is not performed (S3). When using a 1D wafer fabrication structure, the semiconductor test apparatus 51 is configured to apply a reverse bias voltage VRB to the diode structure Di. Specifically, the application terminal unit 58 of the voltage application unit 54 includes an application terminal 61 for the anode terminal 72.

[0193] On the other hand, the voltage generation unit 55 generates a predetermined anode potential Va and a predetermined cathode potential Vc, which are output to the platform terminal 59 and the application terminal 61, respectively. The voltage generation unit 55 generates a reverse bias voltage VRB for the diode configuration Di during the potential defect detection process (S2).

[0194] Specifically, the voltage generation unit 55 generates an anode potential Va and a cathode potential Vc that is higher than the anode potential Va, and applies them to the platform unit 57 and the application terminal unit 58. Thus, a reverse voltage VR, serving as a reverse bias voltage VRB, is applied between the anode terminal 72 and the cathode terminal 74.

[0195] The anode potential Va can be 0V. The reverse voltage VR is the voltage of the cathode potential Vc relative to the anode potential Va. In the potential defect detection step (S2), a reverse current IR, which is the leakage current IL, is generated between the anode terminal 72 and the cathode terminal 74 due to the reverse voltage VR. In the leakage current IL monitoring step (S23), the performance (reduction rate) of the reverse current IR, which is the leakage current IL, is monitored (S23). Thus, the initial defect of the device structure 11 with diode structure Di is detected.

[0196] The reverse voltage VR can be the maximum rated reverse voltage or less than the maximum rated reverse voltage. The voltage ratio of the reverse voltage VR to the maximum rated reverse voltage can be 0.5 or more and 1 or less. The voltage ratio can have a value belonging to at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 1 or less. The voltage ratio is preferably 0.8 or more and 1 or less.

[0197] The reverse voltage VR can be above 500V and below 3000V. The reverse voltage VR can have a value belonging to at least one of the following ranges: above 500V and below 1000V, above 1000V and below 1500V, above 1500V and below 2000V, above 2000V and below 2500V, and above 2500V and below 3000V.

[0198] Figure 19 This is a cross-sectional view showing the wafer structure 1E of the fifth embodiment. (Refer to...) Figure 19 The wafer structure 1E includes a p-type first semiconductor region 12 instead of an n-type first semiconductor region 12. That is, the wafer structure 1E has an IGBT structure as an example of a transistor structure Tr.

[0199] An IGBT has a gate, an emitter, and a collector. The specific structure of the IGBT is obtained by replacing "source" with "emitter" and "drain" with "collector" in the description above. In the IGBT structure, a gate potential Vg is applied to the gate, an emitter potential Ve is applied to the emitter, and a collector potential Vc is applied to the collector. Furthermore, in the IGBT structure, the reverse bias voltage VRB becomes the collector bias voltage VCE, and the drain current IL becomes the collector cutoff current ICE.

[0200] The p-type first semiconductor region 12 can be formed by introducing p-type impurities into the surface layer of the second side 4 of the n-type wafer 2 (first semiconductor layer 6) using ion implantation. In the case of an IGBT structure, the wafer 2 may not necessarily have a second semiconductor layer 7 (second semiconductor region 13).

[0201] The methods described above can also be implemented in other ways. For example, in the methods described above, a high-temperature reverse bias process is used to perform the potential defect detection process (S2). However, the potential defect detection process (S2) does not necessarily need to be performed in a high-temperature environment; it can also be performed in a normal temperature environment (room temperature environment) or a low-temperature environment below 0°C. That is, a normal temperature reverse bias process or a low-temperature reverse bias process can also be used to perform the potential defect detection process (S2).

[0202] In the methods described above, wafer 2 containing SiC single crystal is used. However, wafer 2 may also contain wide-bandgap semiconductor single crystals other than SiC single crystals. For example, wafer 2 may also contain gallium nitride, gallium oxide, diamond, etc. Of course, wafer 2 may also contain single-crystal silicon.

[0203] Similarly, the first semiconductor layer 6 may contain wide-bandgap semiconductor single crystals other than SiC single crystals. The first semiconductor layer 6 may also contain gallium nitride, gallium oxide, diamond, etc. Of course, the first semiconductor layer 6 may also contain single-crystal silicon.

[0204] Similarly, the second semiconductor layer 7 can contain wide-bandgap semiconductor single crystals other than SiC single crystals. The second semiconductor layer 7 can also contain gallium nitride, gallium oxide, diamond, etc. Likewise, of course, the second semiconductor layer 7 can also contain single-crystal silicon.

[0205] In the aforementioned embodiments, wafer 2 has a notch, as exemplified by mark 5a. However, mark 5a may also have a planar portion consisting of a straight-line extending notch instead of a notch. The planar portion may also be referred to as a "positioning plane". The planar portion may extend along the a-axis direction or the m-axis direction.

[0206] In the above embodiments, a wafer 2 having a stacked structure including a first semiconductor layer 6 and a second semiconductor layer 7 is illustrated. However, the wafer 2 does not necessarily need to have a second semiconductor layer 7, and may also have a single-layer structure composed of the first semiconductor layer 6.

[0207] In the above embodiments, examples are shown where the transistor structure Tr and the diode structure Di are formed on different wafers 2. However, wafer structures 1A to 1E may also include both the device region 8 for the transistor structure Tr and the device region 8 for the diode structure Di on the same wafer 2.

[0208] Of course, device structure 11 may also include both transistor structure Tr and diode structure Di formed in the same device region 8 on the same wafer 2. In this case, diode structure Di may also be electrically mounted between the source terminal 41, which serves as the anode terminal 72, and the drain terminal 49, which serves as the cathode terminal 74. That is, diode structure Di may also be electrically connected to transistor structure Tr as a freewheeling diode relative to transistor structure Tr.

[0209] Of the above embodiments, a Schottky barrier diode structure is shown as an example of diode structure Di. However, diode structure Di may also include at least one of pn junction diode, pin junction diode, Zener diode, and fast recovery diode.

[0210] In these cases, the diode structure Di may include one or more p-type anode regions that form a pn junction with the surface portion of the first surface 3 and the first semiconductor region 12 and / or the second semiconductor region 13. Furthermore, the manufacturing methods of the semiconductor device 10 and the semiconductor testing apparatus 51 of each type can be applied to various devices capable of applying a reverse bias voltage VRB.

[0211] In the above-described methods, it is also possible to construct a structure in which the conductivity type of an "n-type" semiconductor region is reversed to "p-type" and the conductivity type of a "p-type" semiconductor region is reversed to "n-type". The specific structure in this case is obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" simultaneously in the description and figures.

[0212] The following are examples of features extracted from this specification and accompanying drawings. Hereinafter, the letters and numbers in parentheses indicate corresponding constituent elements in each of the described methods, but are not intended to limit the scope of each item (clause) to each method.

[0213] [A1] A method for manufacturing a semiconductor device (10) includes performing a reverse bias test (S2) on a device structure (11), wherein the method for manufacturing the semiconductor device (10) includes the following steps: a step of applying a reverse bias voltage (VRB) to the device structure (11) (S22); and a monitoring step of monitoring the rate of decrease of leakage current (IL) of the device structure (11) when the reverse bias voltage (VRB) is applied (S23).

[0214] [A2] The method of manufacturing the semiconductor device (10) according to A1, wherein the monitoring step (S23) includes the step of determining a potential defect in the device structure (11) based on the reduction rate of the leakage current (IL).

[0215] [A3] The method of manufacturing the semiconductor device (10) according to A2, wherein the monitoring step (S23) includes the step of determining the potential defect based on the reduction rate based on the initial value (Iin) of the leakage current (IL).

[0216] [A4] The method of manufacturing the semiconductor device (10) according to A2 or A3, wherein the monitoring step (S23) includes the step of determining that the device structure (11) has the potential defect when the reduction rate is 10% or more.

[0217] [A5] The method for manufacturing the semiconductor device (10) according to A4, wherein the reduction rate is 20% or more.

[0218] [A6] A method for manufacturing a semiconductor device (10) according to any one of A1 to A5, wherein the monitoring step (S23) includes the step of monitoring the rate of reduction of the leakage current (IL) during a monitoring period (TM) based on the start of the application of the reverse bias voltage (VRB).

[0219] [A7] The method of manufacturing the semiconductor device (10) according to A6, wherein the monitoring period (TM) is within 60 minutes.

[0220] [A8] The method of manufacturing the semiconductor device (10) according to A7, wherein the monitoring period (TM) is within 30 minutes.

[0221] [A9] A method for manufacturing a semiconductor device (10) according to any one of A1 to A8, wherein the reverse bias test (S2) is a high-temperature reverse bias test (S2).

[0222] [A10] A method for manufacturing a semiconductor device (10) according to any one of A1 to A9, wherein the reverse bias voltage (VRB) is 500V or more and 3000V or less.

[0223] [A11] A method for manufacturing a semiconductor device (10) according to any one of A1 to A10, wherein the reverse bias test (S2) is: a wafer-level test of the device structure (11) formed on a wafer (2).

[0224] [A12] The method of manufacturing the semiconductor device (10) according to A11, wherein the wafer (2) comprises a SiC single crystal.

[0225] [A13] A method for manufacturing a semiconductor device (10) according to any one of A1 to A12, wherein the device structure (11) comprises a transistor structure (Tr).

[0226] [A14] The method of manufacturing the semiconductor device (10) according to A13 further includes a gate bias test (S3) of the transistor structure (Tr).

[0227] [A15] In the method of manufacturing the semiconductor device (10) according to A13, the gate bias test (S3) of the transistor structure (Tr) is not performed.

[0228] [A16] A method for manufacturing a semiconductor device (10) according to any one of A13 to A15, wherein the transistor structure (Tr) has: a gate (20, 40), a source (15, 41) and a drain (12, 13, 49), the reverse bias voltage (VRB) is a drain bias voltage (VDS), and the drain current (IL) is a drain cutoff current (IDS).

[0229] [A17] A method for manufacturing a semiconductor device (10) according to any one of A13 to A15, wherein the transistor structure (Tr) has: a gate (20, 40), an emitter (15, 41) and a collector (12, 13, 49), the reverse bias voltage (VRB) is a collector bias voltage (VCE), and the leakage current (IL) is a collector cutoff current (ICE).

[0230] [A18] A method for manufacturing a semiconductor device (10) according to any one of A1 to A17, wherein the device structure (11) comprises a diode structure (Di).

[0231] [A19] According to the method of manufacturing the semiconductor device (10) described in A18, the diode structure (Di) has an anode (72) and a cathode (12, 13, 74), the reverse bias voltage (VRB) is a reverse voltage (VR), and the leakage current (IL) is a reverse current (IR).

[0232] [A20] A method for manufacturing a semiconductor device (10), wherein the method comprises the following steps: when a reverse bias voltage (VRB) is applied to a device structure (11), monitoring the rate of decrease of leakage current (IL) of the device structure (11), and determining a potential defect of the device structure (11) based on the rate of decrease of leakage current (IL)

[0233] [B1] A semiconductor test apparatus (51) performs a reverse bias test (S2) on a device structure (11), wherein the semiconductor test apparatus (51) comprises: a voltage application unit (54) that applies a test voltage to the device structure (11); a voltage generation unit (55) that generates a reverse bias voltage (VRB) as the test voltage and outputs it to the voltage application unit (54); and a control unit (56) that monitors the rate of decrease of leakage current (IL) of the device structure (11) when the reverse bias voltage (VRB) is applied.

[0234] [B2] According to the semiconductor test apparatus (51) of B1, the control unit (56) determines the potential defects of the device structure (11) based on the reduction rate of the leakage current (IL).

[0235] [B3] According to the semiconductor test apparatus (51) of B2, the control unit (56) determines the potential defect based on the reduction rate based on the initial value (Iin) of the leakage current (IL).

[0236] [B4] According to the semiconductor test apparatus (51) of BB2 or B3, wherein when the reduction rate of the leakage current (IL) is 10% or more, the control unit (56) determines that the device structure (11) has the potential defect.

[0237] [B5] The semiconductor testing apparatus (51) according to B4, wherein the reduction rate is 20% or more.

[0238] [B6] The semiconductor test apparatus (51) according to any one of B1 to B5, wherein, during a monitoring period (TM) based on the start of the application of the reverse bias voltage (VRB), the control unit (56) monitors the rate of reduction of the leakage current (IL) of the device configuration (11).

[0239] [B7] The semiconductor testing apparatus (51) according to B6, wherein the monitoring period (TM) is within 60 minutes.

[0240] [B8] The semiconductor testing apparatus (51) according to B7, wherein the monitoring period (TM) is within 30 minutes.

[0241] [B9] The semiconductor testing apparatus (51) according to any one of B1 to B8, wherein the reverse bias test (S2) is a high temperature reverse bias test (S2).

[0242] [B10] The semiconductor test apparatus (51) according to any one of B1 to B9, wherein the reverse bias voltage (VRB) is 500V or more and 3000V or less.

[0243] [B11] The semiconductor test apparatus (51) according to any one of B1 to B10, wherein the reverse bias test (S2) is: a wafer-level test of the device structure (11) formed on the wafer (2).

[0244] [B12] The semiconductor testing apparatus (51) according to B11, wherein the wafer (2) comprises a SiC single crystal.

[0245] [B13] The semiconductor testing apparatus (51) according to any one of B1 to B12, wherein the device structure (11) comprises a transistor structure (Tr).

[0246] [B14] The semiconductor test apparatus (51) according to B13, wherein the transistor structure (Tr) has: a gate (20, 40), a source (15, 41) and a drain (12, 13, 49), the reverse bias voltage (VRB) is the drain bias voltage (VDS), and the drain current (IL) is the drain bias cutoff current (IDS).

[0247] [B15] The semiconductor test apparatus (51) according to B14, wherein the transistor structure (Tr) has one or both of a trench electrode type gate structure (20) and a planar electrode type gate structure (20).

[0248] [B16] The semiconductor test apparatus (51) according to B14 or B15, wherein the transistor structure (Tr) has a trench electrode type source structure (25).

[0249] [B17] The semiconductor test apparatus (51) according to B13, wherein the transistor structure (Tr) has: a gate (20, 40), an emitter (15, 41) and a collector (12, 13, 49), the reverse bias voltage (VRB) is the collector bias voltage (VCE), and the leakage current (IL) is the collector cutoff current (ICE).

[0250] [B18] The semiconductor testing apparatus (51) according to any one of B1 to B17, wherein the device structure (11) comprises a diode structure (Di).

[0251] [B19] The semiconductor test apparatus (51) according to B18, wherein the diode configuration (Di) has an anode (72) and a cathode (12, 13, 74), the reverse bias voltage (VRB) is a reverse voltage (VR), and the leakage current (IL) is a reverse current (IR).

[0252] [B20] A semiconductor testing apparatus (51) wherein, when a reverse bias voltage (VRB) is applied to a device structure (11), the rate of decrease of the leakage current (IL) of the device structure (11) is monitored, and a potential defect of the device structure (11) is determined based on the rate of decrease of the leakage current (IL).

[0253] The manufacturing method of the semiconductor device (10) described in any one of [A1] to [A20] may be the manufacturing method implemented in the semiconductor testing apparatus (51) described in any one of [B1] to [B20]. The semiconductor testing apparatus (51) described in any one of [B1] to [B20] may be a testing apparatus that implements the manufacturing method of the semiconductor device (10) described in any one of [A1] to [A20].

[0254] The "semiconductor device" in the above-mentioned projects can be replaced as needed with "SiC semiconductor device", "wide bandgap semiconductor device", "semiconductor switching device", "MISFET device", "IGBT device", "semiconductor rectifier device", etc. Similarly, the "semiconductor testing device" in the above-mentioned projects can be replaced as needed with "SiC semiconductor testing device", "wide bandgap semiconductor testing device", "transistor testing device", "MISFET testing device", "IGBT testing device", "diode testing device", etc.

[0255] The above provides a detailed description of the specific methods, but these are merely specific examples illustrating the technical content. The various technical ideas extracted from this specification are not limited to the order of description, the order of embodiments, or the order of variations within the specification, and can be appropriately combined among them.

[0256] Symbol Explanation

[0257] 1A wafer structure

[0258] 1B wafer structure

[0259] 1C wafer structure

[0260] 1D wafer structure

[0261] 1E wafer structure

[0262] 2 wafers

[0263] 10 Semiconductor Devices

[0264] 11 Device Construction

[0265] 12 First Semiconductor Region

[0266] 13 Second Semiconductor Region

[0267] 15 Source Region

[0268] 20 Gate Structure

[0269] 25 Source Structure

[0270] 40 Gate terminal

[0271] 41 source terminal

[0272] 49 Leaking extremes

[0273] 51 Semiconductor Testing Equipment

[0274] 54 Voltage application unit

[0275] 55 Voltage Generation Unit

[0276] 56 Control Unit

[0277] 72 Anode Terminal

[0278] 74 Cathode Terminal

[0279] Transistor Construction

[0280] VRB reverse bias voltage

[0281] IL leakage current

[0282] The initial value of Iin leakage current

[0283] VDS drain bias voltage

[0284] IDS drain cutoff current

[0285] VCE collector bias voltage

[0286] ICE collector cutoff current

[0287] Di diode structure

[0288] VR reverse voltage

[0289] IR reverse current

[0290] TM monitoring period

[0291] S2 Potential Defect Detection Process

[0292] S22 Application Process

[0293] S23 Monitoring process.

Claims

1. A method for manufacturing a semiconductor device, comprising performing a reverse bias test on the device structure, wherein, The method for manufacturing the semiconductor device includes the following steps: The process of applying a reverse bias voltage to the device structure; as well as A monitoring step that monitors the rate of reduction of leakage current in the device configuration when the reverse bias voltage is applied.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, The monitoring process includes the following steps: determining potential defects in the device construction based on the reduction rate of the leakage current.

3. The method for manufacturing a semiconductor device according to claim 2, wherein, The monitoring process includes the following steps: determining the potential defect based on the reduction rate relative to the initial value of the leakage current.

4. The method for manufacturing a semiconductor device according to claim 2 or 3, wherein, The monitoring process includes the following step: determining that the device structure has the potential defect when the reduction rate is 10% or more.

5. The method for manufacturing a semiconductor device according to claim 4, wherein, The reduction rate is over 20%.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein, The monitoring process includes the following steps: monitoring the rate of reduction of the leakage current during a monitoring period based on the start of the application of the reverse bias voltage.

7. The method for manufacturing a semiconductor device according to claim 6, wherein, The monitoring period is within 60 minutes.

8. The method for manufacturing a semiconductor device according to claim 7, wherein, The monitoring period is within 30 minutes.

9. A method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein, The reverse bias test is a high-temperature reverse bias test.

10. A method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein, The reverse bias voltage is above 500V and below 3000V.

11. A method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein, The reverse bias test is a wafer-level test of the device fabrication formed on the wafer.

12. The method of manufacturing a semiconductor device according to claim 11, wherein, The wafer contains SiC single crystals.

13. The method for manufacturing a semiconductor device according to any one of claims 1 to 12, wherein, The device configuration includes a transistor configuration.

14. The method of manufacturing a semiconductor device according to claim 13, wherein, The method for manufacturing the semiconductor device also includes gate bias testing of the transistor configuration.

15. The method of manufacturing a semiconductor device according to claim 13, wherein, Gate bias testing of the transistor configuration is not performed.

16. The method for manufacturing a semiconductor device according to any one of claims 13 to 15, wherein, The transistor configuration includes a gate, a source, and a drain. The reverse bias voltage is the drain bias voltage. The leakage current is the drain cutoff current.

17. The method for manufacturing a semiconductor device according to any one of claims 13 to 15, wherein, The transistor configuration includes a gate, an emitter, and a collector. The reverse bias voltage is the collector bias voltage. The leakage current is the collector cutoff current.

18. A method for manufacturing a semiconductor device according to any one of claims 1 to 17, wherein, The device configuration includes a diode configuration.

19. The method of manufacturing a semiconductor device according to claim 18, wherein, The diode is configured to have an anode and a cathode. The reverse bias voltage is a reverse voltage. The leakage current is a reverse current.

20. A semiconductor testing apparatus for performing reverse bias testing on a device structure, wherein, The semiconductor testing apparatus includes: A voltage application unit that applies a test voltage to the device configuration; A voltage generation unit generates a reverse bias voltage as the test voltage and outputs it to the voltage application unit; as well as A control unit that monitors the rate of reduction of leakage current in the device configuration when the reverse bias voltage is applied.

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