Semiconductor device
By introducing Schottky barrier diodes and p-type shielding regions into semiconductor devices, the problems of leakage current and power loss are solved, and the withstand voltage and reliability of the devices are improved. In particular, the growth of substrate dislocations is suppressed in silicon carbide devices.
Patent Information
- Application Number
- CN202480017542.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-22
- Filing Date
- 2024-02-05
- Publication Date
- 2025-11-11
AI Technical Summary
In the prior art, semiconductor devices have large leakage current, which leads to increased power loss, and current still flows even in the off state, affecting the efficiency and reliability of the device.
A Schottky barrier diode structure is adopted. By placing first and second Schottky barrier diodes in the semiconductor device and adding a p-type shielding region below the second Schottky barrier diode, the impurity concentration and configuration of the semiconductor region are adjusted to reduce leakage current and power loss.
It effectively reduces the leakage current of Schottky barrier diodes, reduces power loss, and improves the withstand voltage and reliability of semiconductor devices, especially suppressing the growth of substrate dislocations in devices containing silicon carbide.
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Figure CN120937528A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to semiconductor devices. Background Technology
[0002] Semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) are used for applications such as power conversion. It is preferable that the leakage current of semiconductor devices be low.
[0003] Existing technical documents
[0004] Patent documents
[0005] Patent Document 1: Japanese Patent No. 6649183 Summary of the Invention
[0006] The problem that the invention aims to solve
[0007] The problem to be solved by the present invention is to provide a semiconductor device that can reduce leakage current.
[0008] Methods for solving problems
[0009] The semiconductor device of the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a gate electrode, a fourth semiconductor region of a second conductivity type, a second electrode, and a fifth semiconductor region of a second conductivity type. The first semiconductor region is disposed on the first electrode. The first semiconductor region includes a first portion and a second portion, the second portion being disposed around the first portion along a first surface perpendicular to a first direction from the first electrode toward the first portion. The second semiconductor region is disposed on the first portion. The third semiconductor region is disposed on the second semiconductor region. The gate electrode is opposite to the second semiconductor region through a gate insulating layer. The fourth semiconductor region is disposed on the second portion and is located around the second semiconductor region along the first surface. The second electrode includes a first metal portion and a second metal portion. The first metal portion is in contact with the first portion and the second semiconductor region and contains at least one first element selected from the group consisting of titanium, molybdenum, and vanadium. The second metal portion is in contact with the second portion and the fourth semiconductor region and contains the first element. The second electrode is disposed on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region. The fifth semiconductor region is disposed below the fourth semiconductor region and is located directly below the second metal portion. Attached Figure Description
[0010] Figure 1 This is a top view of a semiconductor device illustrating an implementation method.
[0011] Figure 2 yes Figure 1 A top-down enlarged view of part II.
[0012] Figure 3 yes Figure 2 Sectional view III-III.
[0013] Figure 4 yes Figure 2 Sectional view IV-IV.
[0014] Figure 5 (a) and Figure 5 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.
[0015] Figure 6 (a) and Figure 6 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.
[0016] Figure 7 (a) and Figure 7 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.
[0017] Figure 8 (a) and Figure 8 (b) is a top view showing another example of a semiconductor device according to an embodiment.
[0018] Figure 9 This is a cross-sectional view showing a portion of a semiconductor device according to a first variation of the embodiment.
[0019] Figure 10 This is a cross-sectional view showing a portion of a semiconductor device according to a first variation of the embodiment.
[0020] Figure 11 This is a cross-sectional view showing a portion of a semiconductor device in a second variation of the embodiment. Detailed Implementation
[0021] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc., may not be the same as in reality. Furthermore, even when representing the same parts, there may be cases where the dimensions and ratios are represented differently according to the drawings. In the specification and figures of this application, elements that are the same as those already described are labeled with the same reference numerals, and detailed descriptions are appropriately omitted.
[0022] In the following explanation, n + n, n - and p + p, p - These markings indicate the relative concentration of impurities in each conductivity type. That is, n + This indicates that the impurity concentration of type n is relatively higher compared to type n. - This indicates that the impurity concentration of the n-type is relatively low compared to the n-type. Additionally, p... + This indicates that the impurity concentration of p-type is relatively higher compared to p-type. - This indicates that the impurity concentration of the p-type is relatively low compared to the p-type. Regarding the embodiments described below, the p-type and n-type regions of each semiconductor region can also be reversed to implement each embodiment.
[0023] Figure 1 This is a top view of a semiconductor device illustrating an implementation method. Figure 2 yes Figure 1 A top-down enlarged view of part II. Figure 3 yes Figure 2 Sectional view III-III. Figure 4 yes Figure 2 Sectional view IV-IV.
[0024] The semiconductor device used in this implementation is a MOSFET. For example... Figures 1-4 As shown, the semiconductor device 100 of the embodiment includes n - Type 1 (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) substrate region 2 (second semiconductor region), n-type (second conductivity type) drift region 1 (first semiconductor region), n-type (second conductivity type) substrate region 2 (second ...1 (second semiconductor region), n-type (second conductivity type) substrate region 2 (second semiconductor region), n-type (second conductivity type) + p-type source region 3 (third semiconductor region), p-type semiconductor region 4 (fourth semiconductor region), p - Type shielding region 5 (fifth semiconductor region), p - 6. n-type semiconductor region with reduced surface electric field; 7. n-type semiconductor region. + Type 8 drain region, p + Type contact areas 9a, p + The electrode includes a contact area 9b, a gate electrode 10, an insulating layer 15, a drain electrode 21 (first electrode), a source electrode 22 (second electrode), and a gate pad 23. Furthermore, in... Figure 1 The insulation layer 15 is omitted. Figure 2 In the original text, part of the insulating layer 15 and the source electrode 22 are omitted.
[0025] In the description of the implementation method, an XYZ orthogonal coordinate system is used. The direction from the drain electrode 21 toward n... -The direction of a portion of the drift region 1 (first portion 1a) is defined as the Z direction (first direction). Two directions perpendicular to and orthogonal to the Z direction are defined as the X direction (second direction) and the Y direction (third direction). Furthermore, for illustration, the direction from the drain electrode 21 towards n... - The direction of the drift region 1 is called "up," and its opposite direction is called "down." These directions are based on the drain electrode 21 and n. - The relative positional relationship of the drift region 1 is independent of the direction of gravity.
[0026] like Figure 1 As shown, a source electrode 22 and a gate pad 23 are disposed on the upper surface of the semiconductor device 100. The source electrode 22 and the gate pad 23 are separated from each other.
[0027] like Figure 2 As shown, n is disposed below the source electrode 22. + p-type source region 3, p-type semiconductor region 4, p - Type 6, p reduces surface electric field region + Type contact areas 9a, p + Type contact region 9b and gate electrode 10, etc. Furthermore, in Figure 2 In the image, the source electrode 22 is shown by a dashed line.
[0028] like Figure 3 and Figure 4 As shown, a drain electrode 21 is provided on the lower surface of the semiconductor device 100. + The drain region 8 is disposed on the drain electrode 21 and is electrically connected to the drain electrode 21. - Type-Drift Region 1 is set in n + Above the drain region 8. - The n-type impurity concentration in drift region 1 is higher than that in n + The n-type impurity concentration in the drain region 8 is low.
[0029] like Figure 1 As shown by the double-dotted line, n - Type-1 drift region 1 comprises a first part 1a and a second part 1b. The first part 1a is located at n - The center of the XY plane (first plane) of the drift region 1. The second part 1b is arranged around the first part 1a along the XY plane.
[0030] like Figure 3 As shown, the p-type substrate region 2 is disposed on the first portion 1a. + Type source pole region 3 and p + The p-type contact region 9a is selectively disposed on the p-type substrate region 2. +The p-type impurity concentration in the p-type contact region 9a is higher than that in the p-type substrate region 2.
[0031] The gate electrode 10 is positioned in the Z direction opposite a portion of the p-type substrate region 2, separated by the gate insulating layer 11. The gate electrode 10 is electrically connected to the gate pad 23. The gate electrode 10 and the source electrode 22 are electrically isolated from each other by the insulating layer 15.
[0032] p-type substrate region 2, n + Type source pole region 3, p + Multiple p-type contact regions 9a and gate electrodes 10 are respectively provided in the X direction. + Type source pole region 3, each p + The contact area 9a and each gate electrode 10 extend along the Y direction.
[0033] like Figure 4 As shown, a p-type semiconductor region 4 is disposed on the second portion 1b. The p-type semiconductor region 4 is located around a plurality of p-type substrate regions 2 along the XY plane. The ends of the p-type substrate regions 2 in the Y direction can be connected to the p-type semiconductor region 4. A plurality of p-type semiconductor regions 4 are disposed in the direction from the first portion 1a toward the second portion 1b. The plurality of p-type semiconductor regions 4 are separated from each other. The spacing between the p-type semiconductor regions 4 is wider than the spacing between adjacent p-type substrate regions 2 in the X direction.
[0034] p + The p-type contact region 9b is selectively disposed on the p-type semiconductor region 4. + The p-type impurity concentration in the p-type contact region 9b is higher than that in the p-type semiconductor region 4.
[0035] p - The surface electric field reduction region 6 is disposed along the XY plane around the p-type semiconductor region 4 and is in contact with the p-type semiconductor region 4. - The p-type impurity concentration in region 6, which reduces the surface electric field, is lower than that in region 4, which is a p-type semiconductor region. This is achieved by setting the p... - The reduced surface electric field region 6 enables the depletion layer to extend further to the outer periphery of the semiconductor device 100, thereby improving the withstand voltage of the semiconductor device 100.
[0036] n-type semiconductor region 7 is set along the XY plane at p - The area surrounding region 6 that reduces the surface electric field is similar to p. - The n-type semiconductor region 7 exhibits a reduced surface electric field, resulting in separation of the n-type region 6. The n-type impurity concentration in the n-type semiconductor region 7 is higher than that in the n-type region 8. -The n-type impurity concentration is high in the n-type drift region 1. The n-type semiconductor region 7 is disposed along the outer periphery of the semiconductor device 100. By providing the n-type semiconductor region 7, it is possible to suppress the depletion layer extending to the outer periphery of the semiconductor device 100 from reaching the end face of the semiconductor device 100.
[0037] Source electrode 22 is located in p-type substrate region 2, n + p-type source region 3, p-type semiconductor region 4, p + Type contact areas 9a and p + The contact area 9b is electrically connected to these semiconductor regions.
[0038] More specifically, such as Figures 1-4 As shown, the source electrode 22 includes a first metal portion 22a and a second metal portion 22b. In Figure 1 In the diagram, the first metal portion 22a and the second metal portion 22b are shown in dashed lines. The first metal portion 22a is located above the first portion 1a and is in contact with the first portion 1a and the p-type substrate region 2. The second metal portion 22b is located above the second portion 1b and is in contact with the p-type semiconductor region 4 and the p-type substrate region 2. + The contact area 9b is connected.
[0039] Multiple first metal portions 22a are provided in the X direction, and each first metal portion 22a extends along the Y direction. Second metal portions 22b are provided around the multiple gate electrodes 10 and the multiple first metal portions 22a along the XY plane.
[0040] As a specific example, such as Figure 2 As shown, a first metal portion 22a and one or more gate electrodes 10 are alternately disposed in the X direction. A plurality of p-type substrate regions 2 include p-type substrate region 2a and p-type substrate region 2b. One end of the p-type substrate region 2a in the X direction is opposite to the gate electrode 10, and the other end of the p-type substrate region 2a is connected to the first metal portion 22a. The two ends of the p-type substrate region 2b in the X direction are respectively opposite to the two gate electrodes 10.
[0041] Schottky junctions are formed between the first portion 1a and the first metal portion 22a, and between the second portion 1b and the second metal portion 22b, respectively. That is, the semiconductor device 100 includes a Schottky barrier diode D1 composed of the first portion 1a and the first metal portion 22a, and a Schottky barrier diode D2 composed of the second portion 1b and the second metal portion 22b.
[0042] like Figure 3 and Figure 4 As shown, the source electrode 22 may further include a silicide region 22c. Furthermore, in Figure 2 In the original text, the silicide region 22c is omitted. The silicide region 22c is set at n+ Type source pole region 3 and p + Above the contact area 9a, and n + Type source pole region 3 and p + Type 9a ohmic contact.
[0043] p - The p-type shielding region 5 is positioned below the p-type semiconductor region 4, directly below the second metal portion 22b. More specifically, the plurality of p-type semiconductor regions 4 are separated from each other by a portion of the second portion 1b. The second metal portion 22b is connected to this portion of the second portion 1b. - Type 5 shielding area is located below this part of the second part 1b. - The shielding area 5 is arranged in a ring shape along the second metal part 22b.
[0044] like Figure 3 As shown, the first part 1a may include a first region r1 and a second region r2. The first region r1 is connected to the p-type substrate region 2 and the first metal portion 22a. The first region r1 may also be located directly below the gate electrode 10. The second region r2 is located between the drain electrode 21 and the first region r1 in the Z direction. The n-type impurity concentration of the first region r1 is higher than that of the second region r2.
[0045] like Figure 4 As shown, the second part 1b may include a third region r3 and a fourth region r4. The third region r3 and the p-type semiconductor region 4, p... - The shielded region 5 and the second metal part 22b are connected. The third region r3 is separated from the first region r1. The fourth region r4 is located between the drain electrode 21 and the third region r3 in the Z direction. The n-type impurity concentration in the third region r3 is higher than that in the fourth region r4.
[0046] An example of the materials used in each of the constituent elements will be provided.
[0047] n - Type drift region 1, p-type substrate region 2, n + p-type source region 3, p-type semiconductor region 4, p - Type shielding area 5, p - 6. n-type semiconductor region with reduced surface electric field; 7. n-type semiconductor region. + Type 8 drain region, p + Type contact areas 9a and p + The n-type contact region 9b contains silicon, silicon carbide, gallium nitride, or gallium arsenide as the semiconductor material. Silicon carbide is preferred as the semiconductor material. Nitrogen, arsenic, phosphorus, or antimony can be used as the n-type impurity. Aluminum or boron can be used as the p-type impurity.
[0048] The gate electrode 10 comprises a conductive material such as polysilicon. The gate insulating layer 11 and the insulating layer 15 comprise insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 21 and the gate pad 23 comprise a metallic material such as aluminum.
[0049] The first metal portion 22a and the second metal portion 22b contain at least one first element selected from the group consisting of titanium, molybdenum, and vanadium. By including the first metal portion 22a and the second metal portion 22b in the first metal portion 22a, a Schottky junction is formed between the first portion 1a and the first metal portion 22a, and between the second portion 1b and the second metal portion 22b. The silicide region 22c contains nickel silicide. The portion of the source electrode 22 other than the first metal portion 22a, the second metal portion 22b, and the silicide region 22c contains aluminum.
[0050] The operation of the semiconductor device 100 will be explained. When a positive voltage is applied to the drain electrode 21 relative to the source electrode 22, a voltage above a threshold value is applied to the gate electrode 10. This forms a channel (inversion layer) in the p-type substrate region 2, and the semiconductor device 100 becomes conductive. Electrons flow from the source electrode 22 to the drain electrode 21 through the channel. If the voltage applied to the gate electrode 10 falls below the threshold value, the channel in the p-type substrate region 2 disappears, and the semiconductor device 100 becomes cut off.
[0051] When the semiconductor device 100 is in the off state, a positive voltage is sometimes applied to the source electrode 22 relative to the drain electrode 21. At this time, current flows from the source electrode 22 to the drain electrode 21 through the Schottky barrier diodes D1 and D2.
[0052] Figure 5 (a)~ Figure 7 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.
[0053] First, prepare a collection of n - Type semiconductor layer 1x and n + A semiconductor substrate with an 8x semiconductor layer. - Type semiconductor layer 1x is set in n + Above the 8x type semiconductor layer. On the n... - The upper surface of the semiconductor layer 1x is sequentially ion-implanted with p-type impurities and n-type impurities, such as... Figure 5 As shown in (a), n-type semiconductor region 1y, n-type semiconductor region 1z and p are formed. - Type 5x semiconductor region. Alternatively, it can be applied to n... - p-type semiconductor layer 1x is formed by ion implantation of p-type impurities onto its upper surface. - After 5x of the type semiconductor region, n-type semiconductors are epitaxially grown. -Type-n semiconductor layer. This is achieved by epitaxially growing n... - The n-type semiconductor layer is selectively ion-implanted with n-type impurities to form n-type semiconductor region 1y and n-type semiconductor region 1z. The n-type semiconductor region 1y and n-type semiconductor region 1z are separated from each other. - The n-type semiconductor region 5x is located below the n-type semiconductor region 1z.
[0054] In n - A photoresist is formed on the n-type semiconductor layer 1x, the n-type semiconductor region 1y, and the n-type semiconductor region 1z. The photoresist is patterned using photolithography and reactive ion etching (RIE). Thus, as... Figure 5 As shown in (b), masks M1 to M3 are formed. Mask M1 is formed on n-type semiconductor region 1y. The position of mask M1 corresponds to the position of the gap between p-type substrate regions 2. Mask M2 is formed on n-type semiconductor region 1z. The position of mask M2 corresponds to the position of the gap between p-type semiconductor regions 4. Mask M3 is formed on n... - Above the outer periphery of the semiconductor layer 1x. For example, the width (dimension in the X direction) of mask M2 is wider than the width of mask M1.
[0055] To n - P-type impurities are ion-implanted onto the upper surfaces of the n-type semiconductor layer 1x, the n-type semiconductor region 1y, and the n-type semiconductor region 1z. For example... Figure 6 As shown in (a), p-type semiconductor regions 2x and 4x are formed in the regions not covered by masks M1 to M3.
[0056] After removing masks M1 to M3, as follows Figure 6 As shown in (b), n is formed + Type source pole region 3, p - 6. N-type semiconductor region, p-type semiconductor region, n-type semiconductor region, p ... + Type contact areas 9a, p + The contact region 9b, gate electrode 10, gate insulating layer 11, and insulating layer 15 are formed using known methods.
[0057] A first metal portion 22a is formed on the n-type semiconductor region 1y, and a second metal portion 22b is formed on the n-type semiconductor region 1z. In the p-type substrate regions 2 and 1z... + p-type source region 3, p-type semiconductor region 4, p + Type contact areas 9a and p + A silicide region 22c is formed above the contact region 9b. For example... Figure 7 As shown in (a), an aluminum layer 22d is formed on the first metal portion 22a, the second metal portion 22b and the silicide region 22c.
[0058] Grinding n + The lower surface of the 8x type semiconductor layer extends up to n. + The semiconductor layer is 8x thick, which is the specified thickness. For example... Figure 7 As shown in (b), in the ground n + A drain electrode 21 is formed on the lower surface of the semiconductor layer 8x. Through the above processes, the semiconductor device 100 of the embodiment is manufactured.
[0059] Figure 7 n shown in (b) - Type semiconductor layer 1x and Figure 3 and Figure 4 The second region r2 of the first part 1a and the fourth region r4 of the second part 1b correspond to each other. The n-type semiconductor region 1y corresponds to the first region r1 of the first part 1a. The n-type semiconductor region 1z corresponds to the third region r3 of the second part 1b. The p-type semiconductor region 2x corresponds to the p-type substrate region 2. The p-type semiconductor region 4x corresponds to the p-type semiconductor region 4. - Type semiconductor region 5x and p - Type 5 shielding area corresponds to n. + Type semiconductor layer 8x and n + Type 8 drain region corresponds to.
[0060] The advantages of the implementation method will be explained.
[0061] Semiconductor device 100 includes n - The parasitic diode formed by the n-type drift region 1 and the p-type substrate region 2, and the n-type substrate region 2 - The parasitic diodes consist of the n-type drift region 1 and the p-type semiconductor region 4. If these parasitic diodes activate, a large number of charge carriers will be injected into the n-type semiconductor region. - Type 1 drift region. Therefore, if the parasitic diode operates, reverse recovery requires a long time. In addition, since the charge Qrr during reverse recovery is large, the power loss also increases.
[0062] Regarding this issue, the semiconductor device 100 includes Schottky barrier diodes D1 and D2. The forward voltage of Schottky barrier diodes D1 and D2 is lower than the forward voltage of the parasitic diode. Therefore, when a positive voltage is applied to the source electrode 22, the Schottky barrier diodes D1 and D2 operate before the parasitic diode operates. If current flows through the Schottky barrier diodes D1 and D2, the voltage rise at the source electrode 22 is suppressed. Therefore, the parasitic diode becomes less likely to operate, thereby reducing the power loss of the semiconductor device 100.
[0063] However, when Schottky barrier diodes D1 and D2 are provided, leakage current may flow through them when the semiconductor device 100 is in the off state. If leakage current flows through the semiconductor device 100, power loss increases. Therefore, the leakage current caused by Schottky barrier diodes D1 and D2 is preferably small.
[0064] Regarding the Schottky barrier diode D1, leakage current can be significantly reduced by adjusting the size and arrangement of the p-type substrate region 2. For example, by narrowing the spacing between the p-type substrate regions 2, the contact area between the first portion 1a and the first metal portion 22a can be reduced, thereby reducing the leakage current caused by the Schottky barrier diode D1.
[0065] On the other hand, regarding the Schottky barrier diode D2, it is difficult to narrow the spacing between the p-type semiconductor regions 4. For example, the spacing between the p-type substrate regions 2 and the spacing between the p-type semiconductor regions 4 are respectively... Figure 5 The widths of mask M1 and mask M2 shown in (b) correspond. A large number of masks M1 are concentrated on the first part 1a. On the other hand, only a few masks M2 are formed on the second part 1b. Given the conditions for forming a large number of fine masks M1, it is difficult to simultaneously and precisely manufacture the few masks M2 that are far from the large number of masks M1 while suppressing deviations. That is, it is difficult to narrow the width of mask M2 while forming a large number of fine masks M1.
[0066] Furthermore, in order to suppress the operation of parasitic diodes on the outer periphery of the semiconductor device 100 where the p-type semiconductor region 4 is located, it is preferable to make the mask M2 wider, so that the contact area between the second metal portion 22b and the second portion 1b is larger. On the other hand, the larger the contact area between the second metal portion 22b and the second portion 1b, the greater the leakage current of the Schottky barrier diode D2.
[0067] As mentioned above, regarding the Schottky barrier diode D2, from the perspective of constraints on the manufacturing method and suppressing the operation of parasitic diodes, it is not easy to reduce leakage current by adjusting the size and configuration of the p-type semiconductor region 4.
[0068] The semiconductor device 100 of the embodiment includes a p disposed below the second metal portion 22b. - Type shielding area 5. By setting p - The shielding region 5 reduces the electric field strength near the Schottky barrier diode D2. Therefore, when the semiconductor device 100 is in the off state, the leakage current through the Schottky barrier diode D2 can be reduced. According to the embodiment, the leakage current caused by the Schottky barrier diode D2 can be reduced, thereby reducing the power loss of the semiconductor device 100.
[0069] p- The p-type impurity concentration in the p-type shielding region 5 is preferably lower than that in the p-type semiconductor region 4. This mitigates the p-type impurity concentration. - The electric field strength at the outer periphery of the shielded region 5 can further improve the withstand voltage of the semiconductor device 100.
[0070] p - The position of the p-type shielding region 5 in the Z direction can be appropriately changed. However, if the p-type semiconductor region 4 and p... - If the distance between the p-type shielding regions 5 is too short, the Schottky barrier diode D2's effect in suppressing the parasitic diode's operation may be weakened. If the distance between the p-type semiconductor region 4 and the p-type shielding region 5 is too short, the effect of the Schottky barrier diode D2 in suppressing the parasitic diode's operation may be weakened. - If the distance between shielding regions 5 is too long, then p - The effect of p-type shielding region 5 in reducing electric field strength is weakened. Therefore, the p-type semiconductor region 4 and p-type semiconductor region 5 are less effective in reducing electric field strength. - The distance in the Z direction between the shielding regions 5 is preferably longer than 0.2 μm and shorter than 1.0 μm.
[0071] like Figure 3 As shown, the first part 1a preferably includes a first region r1. With the first region r1 provided, the resistance in the current path surrounding the p-type substrate region 2 can be reduced when the Schottky barrier diode D1 operates. This suppresses the voltage rise in the p-type substrate region 2, thereby reducing the resistance of the current path. - The parasitic diode formed by the p-type drift region 1 and the p-type substrate region 2 is difficult to operate.
[0072] Similarly, as Figure 4 As shown, the second part 1b preferably also includes a third region r3. With the third region r3 provided, the resistance in the current path surrounding the p-type semiconductor region 4 can be reduced when the Schottky barrier diode D2 operates. This suppresses the voltage rise in the p-type semiconductor region 4, thus reducing the resistance of the current path. - The parasitic diode formed by the p-type drift region 1 and the p-type semiconductor region 4 is difficult to operate.
[0073] This embodiment is particularly suitable for so-called SiC devices in which each semiconductor region contains silicon carbide. In the case where each semiconductor region contains silicon carbide, crystal defects called basal plane dislocations exist within the silicon carbide crystal. During parasitic diode operation, these basal plane dislocations become stacked defects due to the recombination energy of injected electrons and holes, deteriorating the electrical characteristics of the semiconductor device. For example, an increase in leakage current and an increase in on-resistance may occur. According to this embodiment, the operation of parasitic diodes can be suppressed, thus suppressing the growth of silicon carbide basal plane dislocations into stacked defects. This suppresses the deterioration of the semiconductor device 100's characteristics and improves the reliability of the semiconductor device 100. Furthermore, by using silicon carbide in each semiconductor region, the breakdown voltage of the semiconductor device 100, Schottky barrier diode D1, and Schottky barrier diode D2 can be increased. The leakage current of Schottky barrier diodes D1 and D2 can also be suppressed.
[0074] Figure 8 (a) and Figure 8 (b) is a top view showing another example of a semiconductor device according to an embodiment.
[0075] like Figure 8 As shown in (a), multiple second metal portions 22b can also be arranged along the outer periphery of the p-type semiconductor region 4. The multiple second metal portions 22b are separated from each other. Figure 8 As shown in (b), a plurality of second metal portions 22b may also be provided in the direction from the first portion 1a toward the second portion 1b. Each second metal portion 22b surrounds a plurality of first metal portions 22a along the XY plane. Figure 8 (a) and Figure 8 In either of the examples shown in (b), p is provided directly below the second metal part 22b. - Type 5 shielding area.
[0076] like Figure 8 (a) and Figure 8 As shown in (b), the configuration of the second metal part 22b can be appropriately changed. More preferably, as shown in [the diagram]... Figure 1 or Figure 8 As shown in (b), the second metal portion 22b surrounds a plurality of first metal portions 22a along the XY plane. Therefore, when the Schottky barrier diode D2 operates, current can flow evenly through the outer periphery of the p-type semiconductor region 4.
[0077] (First variation)
[0078] Figure 9 and Figure 10 This is a cross-sectional view showing a portion of a semiconductor device according to a first variation of the embodiment.
[0079] In semiconductor device 100, p- The p-type shielding region 5 is separated from the p-type semiconductor region 4. In the semiconductor device 110 or 120 of the first modification, such as Figure 9 and Figure 10 As shown, p - The p-type shielding region 5 is connected to the p-type semiconductor region 4. - The p-type shielding region 5 is electrically connected to the source electrode 22 via the p-type semiconductor region 4. Therefore, p - The potential of the shielded region 5 is essentially the same as the potential of the source electrode 22.
[0080] It is possible Figure 9 As shown, in p - The inner periphery of shielding area 5, p - The shielding region 5 is connected to the p-type semiconductor region 4, or it can be like... Figure 10 As shown, in p - The outer periphery of shielding area 5, p - The p-type shielding region 5 is connected to the p-type semiconductor region 4. In either case, the third region r3 is connected to the fourth region r4.
[0081] According to the first variation, p can be avoided. - The potential of the shielded region 5 becomes floating, which can make the operation of the semiconductor device 110 or 120 more stable.
[0082] (Second variation)
[0083] Figure 11 This is a cross-sectional view showing a portion of a semiconductor device in a second variation of the embodiment.
[0084] exist Figure 11 In the semiconductor device 130 shown, the third region r3 is wider than the third region r3 of the semiconductor device 100. The third region r3 is connected to the first region r1. Additionally, in p... - The outer periphery of the shielding area 5 is provided with p - Type semiconductor region 5a. p - Type semiconductor region 5a is set along the XY plane in p - The area surrounding the shielding region 5. For example, multiple p are provided in the direction from the first part 1a toward the second part 1b. - Type semiconductor region 5a, each p - Type semiconductor region 5a surrounds p - Type 5 shielding area.
[0085] By connecting the third region r3 to the first region r1, the lateral resistance from the third region r3 towards the first region r1 can be reduced. By reducing the resistance, the voltage applied to the parasitic diode formed by the third region r3 and the p-type semiconductor region 4 is reduced. As a result, the voltage generated by the n-type semiconductor region 4 can be further suppressed. - The operation of the parasitic diode formed by the p-type drift region 1 and the p-type semiconductor region 4. Furthermore, if the p-type drift region 4 is not provided... - With the third region r3 in the state of the p-type shielded region 5, the contact area between the third region r3 and the p-type semiconductor region 4 increases, which may increase the leakage current caused by the Schottky barrier diode D2. However, in the semiconductor device 130, since p-type shielded region 5 is provided, the leakage current may increase. - The shielding region 5 is such that leakage current caused by the increased contact area between the third region r3 and the p-type semiconductor region 4 can be suppressed. That is, according to the second modification, leakage current caused by the increased contact area between the third region r3 and the p-type semiconductor region 4 can be suppressed, and the operation of the parasitic diode can be suppressed more reliably.
[0086] By setting p - Type semiconductor region 5a, capable of setting p - At the height of shielding region 5, the depletion layer extends further outwards. This allows p - The electric field strength at the outer periphery of the shielded region 5 decreases, which can improve the withstand voltage of the semiconductor device 130.
[0087] The embodiments of the present invention include the following features.
[0088] (Feature 1)
[0089] A semiconductor device comprising:
[0090] First electrode;
[0091] A first semiconductor region of a first conductivity type is disposed on the first electrode, comprising a first portion and a second portion disposed around the first portion along a first surface perpendicular to a first direction from the first electrode toward the first portion;
[0092] A second semiconductor region of a second conductivity type is disposed on the first portion;
[0093] A third semiconductor region of a first conductivity type is disposed on top of the second semiconductor region;
[0094] The gate electrode is opposite to the second semiconductor region through the gate insulating layer;
[0095] A fourth semiconductor region of a second conductivity type is disposed on the second portion and located around the second semiconductor region along the first surface;
[0096] A second electrode, disposed on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, includes a first metal portion and a second metal portion. The first metal portion is connected to the first portion and the second semiconductor region and contains at least one first element selected from the group consisting of titanium, molybdenum, and vanadium. The second metal portion is connected to the second portion and the fourth semiconductor region and contains the first element.
[0097] The fifth semiconductor region of the second conductivity type is disposed below the fourth semiconductor region and is located directly below the second metal portion.
[0098] (Feature 2)
[0099] The semiconductor device according to feature 1, wherein...
[0100] The impurity concentration of the second conductivity type in the fifth semiconductor region is lower than that in the fourth semiconductor region.
[0101] (Feature 3)
[0102] The semiconductor device according to feature 1 or 2, wherein,
[0103] The fifth semiconductor region is connected to the fourth semiconductor region.
[0104] (Feature 4)
[0105] The semiconductor device according to any one of features 1 to 3, wherein...
[0106] The second semiconductor region, the third semiconductor region, the gate electrode, and the first metal portion are respectively disposed in multiple locations above the first portion along a second direction perpendicular to the first direction.
[0107] The fourth semiconductor region is disposed around the plurality of second semiconductor regions along the first surface.
[0108] The second metal portion is disposed around the plurality of first metal portions along the first surface.
[0109] (Feature 5)
[0110] The semiconductor device according to feature 4, wherein...
[0111] The fourth semiconductor region is provided in multiple portions in the direction from the first portion toward the second portion.
[0112] The second metal portion is in contact with the plurality of fourth semiconductor regions and a portion of the second portion located between the plurality of fourth semiconductor regions.
[0113] The fifth semiconductor region is located below the portion of the second part.
[0114] (Feature 6)
[0115] The semiconductor device according to any one of features 1 to 5, wherein...
[0116] The first part includes:
[0117] The first region is in contact with the second semiconductor region and the first metal portion; and
[0118] The second region is located between the first electrode and the first region;
[0119] The impurity concentration of the first conductivity type in the first region is higher than that in the second region.
[0120] (Feature 7)
[0121] The semiconductor device according to any one of features 1 to 6, wherein,
[0122] The second part includes:
[0123] The third region is connected to the fourth semiconductor region and the second metal portion, and is located between the fifth semiconductor region and the second metal portion; and
[0124] The fourth region is located between the first electrode and the third region;
[0125] The impurity concentration of the first conductivity type in the third region is higher than that in the fourth region.
[0126] (Feature 8)
[0127] The semiconductor device according to any one of features 1 to 7, wherein...
[0128] The first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region comprise silicon carbide.
[0129] The relative levels of impurity concentrations among the semiconductor regions in the embodiments described above can be confirmed, for example, using SCM (scanning electrostatic capacitance microscopy). Furthermore, the carrier concentration in each semiconductor region can be considered equal to the concentration of impurities activated in that region. Therefore, the relative levels of carrier concentrations among the semiconductor regions can also be confirmed using SCM. Additionally, the impurity concentration in each semiconductor region can be measured, for example, using SIMS (secondary ion mass spectrometry).
[0130] The foregoing has illustrated several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents. Furthermore, the foregoing embodiments can be implemented in combination with each other.
[0131] Explanation of reference numerals in the attached figures
[0132] 1:n - Type Drift Area
[0133] 1a: Part One
[0134] 1b: Part Two
[0135] 1x:n - Type semiconductor layer
[0136] 1y, 1z: n-type semiconductor regions
[0137] 2, 2a, 2b: p-type substrate regions
[0138] 2x: p-type semiconductor region
[0139] 3:n + Type source polar region
[0140] 4: p-type semiconductor region
[0141] 4x: p-type semiconductor region
[0142] 5:p - Type shielding area
[0143] 5a:p - Type semiconductor region
[0144] 5x:p - Type semiconductor region
[0145] 6:p - Type of reduced surface electric field region
[0146] 7: n-type semiconductor region
[0147] 8:n + Type Drain Region
[0148] 8x:n + Type semiconductor layer
[0149] 9a, 9b: p + Type contact area
[0150] 10: Gate electrode
[0151] 11: Gate insulating layer
[0152] 15: Insulation layer
[0153] 21: Drain electrode
[0154] 22: Source electrode
[0155] 22a: First metal part
[0156] 22b: Second metal part
[0157] 22c: Silicide region
[0158] 22d: Aluminum layer
[0159] 23: Gate pad
[0160] 100-130: Semiconductor devices
[0161] D1, D2: Schottky barrier diodes
[0162] M1~M3: Masks
[0163] r1: First region
[0164] r2: Second region
[0165] r3: Third Region
[0166] r4: Fourth Region
Claims
1. A semiconductor device, characterized in that, have: First electrode; A first semiconductor region of a first conductivity type is disposed on the first electrode, comprising a first portion and a second portion disposed around the first portion along a first surface perpendicular to a first direction from the first electrode toward the first portion; A second semiconductor region of a second conductivity type is disposed on the first portion; A third semiconductor region of a first conductivity type is disposed on top of the second semiconductor region; The gate electrode is opposite to the second semiconductor region through the gate insulating layer; A fourth semiconductor region of a second conductivity type is disposed on the second portion and located around the second semiconductor region along the first surface; The second electrode is disposed on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, and includes a first metal portion and a second metal portion. The first metal portion is connected to the first portion and the second semiconductor region and includes at least one first element selected from the group consisting of titanium, molybdenum, and vanadium. The second metal portion is connected to the second portion and the fourth semiconductor region and includes the first element. as well as The fifth semiconductor region of the second conductivity type is disposed below the fourth semiconductor region and is located directly below the second metal portion.
2. The semiconductor device according to claim 1, characterized in that, The impurity concentration of the second conductivity type in the fifth semiconductor region is lower than that in the fourth semiconductor region.
3. The semiconductor device according to claim 1 or 2, characterized in that, The fifth semiconductor region is connected to the fourth semiconductor region.
4. The semiconductor device according to claim 1 or 2, characterized in that, The second semiconductor region, the third semiconductor region, the gate electrode, and the first metal portion are respectively disposed in multiple locations above the first portion along a second direction perpendicular to the first direction. The fourth semiconductor region is disposed around the plurality of second semiconductor regions along the first surface. The second metal portion is disposed around the plurality of first metal portions along the first surface.
5. The semiconductor device according to claim 4, characterized in that, The fourth semiconductor region is provided in multiple portions in the direction from the first portion toward the second portion. The second metal portion is in contact with the plurality of fourth semiconductor regions and a portion of the second portion located between the plurality of fourth semiconductor regions. The fifth semiconductor region is located below the portion of the second part.
6. The semiconductor device according to claim 1 or 2, characterized in that, The first part includes: The first region is in contact with the second semiconductor region and the first metal portion; and The second region is located between the first electrode and the first region; The impurity concentration of the first conductivity type in the first region is higher than that in the second region.
7. The semiconductor device according to claim 1 or 2, characterized in that, The second part includes: The third region is connected to the fourth semiconductor region and the second metal portion, and is located between the fifth semiconductor region and the second metal portion; as well as The fourth region is located between the first electrode and the third region; The impurity concentration of the first conductivity type in the third region is higher than that in the fourth region.
8. The semiconductor device according to claim 1 or 2, characterized in that, The first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region comprise silicon carbide.