Semiconductor device having low concentration of separate-type doped

Abstract

Disclosed examples include a microelectronic device (100), such as an integrated circuit, including a source region (138) and a drain region (139) extending into a semiconductor substrate (103), the semiconductor substrate (103) having a second conductivity type, the source region (138) and the drain region (139) having an opposite first conductivity type. A channel region having the second conductivity type extends between the source region (138) and the drain region (139). A gate electrode (128) over the channel region has a first portion (158) and a second portion (150). The first portion (158) has the second conductivity type and a first dopant concentration. The second portion (150) extends from the first portion toward the source region and has the second conductivity type and a second higher dopant concentration.

Description

Technical Field

[0001] This disclosure relates to the field of microelectronic devices. More specifically, but not exclusively, this disclosure relates to gated devices such as MOS transistors. Background Technology

[0002] Semiconductor components are constantly being improved to operate reliably with smaller feature sizes. Manufacturing semiconductor devices that offer increasingly higher performance while meeting reliability specifications is challenging. Summary of the Invention

[0003] This summary is provided to introduce a simplified series of disclosed concepts, which will be further described below in detail with reference to the accompanying drawings. This summary is not intended to limit the scope of the claimed subject matter.

[0004] The disclosed examples include microelectronic devices, such as integrated circuits. One such example includes a source region and a drain region extending into a semiconductor substrate having a second conductivity type, and the source and drain regions having opposite first conductivity types. A channel region having the second conductivity type extends between the source and drain regions. A gate electrode above the channel region has a first portion and a second portion. The first portion has the second conductivity type and a first dopant concentration. The second portion extends from the first portion toward the source region and has the second conductivity type and a second higher dopant concentration.

[0005] The disclosed examples further include methods for forming integrated circuits. In one example, a method includes forming a source region and a drain region having a first conductivity type, the source region and drain region extending into a semiconductor substrate having an opposite second conductivity type. A gate electrode is formed above the semiconductor substrate between the source region and the drain region, the gate electrode having a first portion and a second portion, the first portion and the second portion having the second conductivity type. The first portion is between the second portion and the drain region and has a first dopant concentration, and the second portion has a second higher dopant concentration. Attached Figure Description

[0006] Figures 1A to 1F Cross-sections of an example microelectronic device containing a transistor with a depletable resurf gate electrode at various formation stages.

[0007] Figure 2 To show Figures 1A to 1F A graph showing the gate electrode doping distribution of an example microelectronic device with a depletable resurf gate electrode.

[0008] Figures 3A to 3FThis is a cross-section of an LDMOS transistor with a depletable resurf gate electrode at various formation stages.

[0009] Figure 4 To show Figures 3A to 3F A graph showing the gate electrode doping distribution of an LDMOS transistor with a depletable resurf gate electrode.

[0010] Figure 5 A top view of an LDMOS transistor with a depletable resurf gate electrode arranged in a racetrack configuration.

[0011] Figure 6 The cross-section is shown for a DENMOS transistor with a depletable resurf gate electrode.

[0012] Figure 7 A graph comparing the electric field in the channel below the gate electrode between the source and drain regions for a reference transistor and a transistor with a depletable resurf gate electrode.

[0013] Figure 8 This is a graph of a depletable resurf gate electrode LDMOS transistor. Detailed Implementation

[0014] This disclosure is described with reference to the accompanying drawings. The drawings are not to scale and are provided for illustrative purposes only. Several aspects of this disclosure are described below with reference to exemplary applications used for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of this disclosure. This disclosure is not limited to the order of the activities or events shown, as some activities may occur in a different order and / or simultaneously with other activities or events. Furthermore, not all of the illustrated actions or events are required to implement the methods according to this disclosure.

[0015] Furthermore, although some examples illustrated herein are shown in two-dimensional views of individual zones with depth and width, it should be clearly understood that these zones are merely illustrations of a portion of a device that is actually a three-dimensional structure. Therefore, when manufactured in an actual device, these zones will have three dimensions, including length, width, and depth. Moreover, while this disclosure is illustrated by examples of active devices, it is not intended that these illustrations limit the scope or applicability of this disclosure. The active devices of this disclosure are not intended to be limited to the illustrated physical structures. These structures are included to demonstrate the utility and application of this disclosure to a variety of examples.

[0016] It should be noted that terms such as top, bottom, above, above, and below are used in this disclosure. These terms should not be construed as limiting the position or orientation of structures or elements, but are used to provide spatial relationships between structures or elements. The terms "lateral" and "laterally" refer to a direction parallel to a plane corresponding to the surface of a layer (e.g., the top surface of a semiconductor substrate). Furthermore, as used herein, the term "approximately" may refer to a variation of ±5% to ±10% of the stated value in some cases. In other cases, the term "approximately" may refer to a variation of ±10% to ±20% of the stated value.

[0017] Microelectronic devices are constantly being improved to operate reliably with higher performance and smaller feature sizes. Manufacturing such microelectronic devices that meet area scaling and reliability requirements is challenging. For example, some gated devices, such as metal-oxide-semiconductor (MOS) transistors, include features to support high-voltage operation, where voltages applied to their drain (or drain structure) are approximately 20V, 30V, 40V, or even higher. Such MOS transistors may include drain diffusion profiles (or drain junction profiles) designed to support high voltages applied to the drain, for example, having extended portions to distribute voltage drops across greater distances. Therefore, such MOS transistors can be referred to as drain-extended MOS transistors, such as drain-extended n-channel MOS (DENMOS) transistors, drain-extended p-channel MOS (DEPMOS) transistors, laterally diffused MOS (LDMOS) transistors, and groups of DENMOS and DEPMOS transistors (which may be referred to as complementary drain-extended MOS or DECMOS transistors). Other gated microelectronic devices may include gated bipolar semiconductor devices, gated unipolar semiconductor devices, insulated gate bipolar transistors (IGBTs), metal-oxide-semiconductor (MOS) triggered SCRs, MOS-controlled thyristors, and gated diodes.

[0018] Conventional field-effect transistors typically have a gate electrode above a channel region, which is doped with the same conductivity type as the channel region, which in turn has the opposite conductivity type between the source and drain regions. Therefore, when the transistor is off, the gate electrode has a majority carrier type opposite to that of the channel region. For example, a conventional n-type transistor, such as an n-channel MOSFET, has a p-type body region before channel inversion, and the gate electrode is typically heavily doped to achieve high conductivity. In the case of extended drain (ED) transistors, the operating voltage can be limited by avalanche breakdown at the drain-body junction, which typically occurs at the silicon surface. In contrast, examples of this disclosure contain an innovative identification that dops the drain end of the gate electrode (e.g., for electrons in an n-channel device) with a light doping of the majority charge carriers of the opposite doping type to that of the channel under inversion, allowing the gate electrode to be depleted by the electric field generated by the drain at high drain voltages. In this way, the gate electrode can act as a semiconductor "resurf" element, where resurf refers to reducing the surface field. The gate electrode of an exemplary device can be called a "depletable resurf gate electrode" because the carriers in the gate electrode are simultaneously depleted along with the carriers in the drain drift region of the ED device instance. Electrons and holes deplete each other due to the electric field caused by the junction reverse bias. This results in a weakening of the electric field in the gate oxide at the drain end of the gate electrode, which reduces aging in the microelectronic device by reducing failure mechanisms such as channel hot carriers (CHC) and gate oxide cracking. In this way, device reliability can be improved and / or device size can be reduced.

[0019] With the aid of further context, the gate electrode of an operating ED transistor performs the crucial function of controlling the silicon surface potential in the channel region. During gate switching, a metal boundary condition must be enforced at the bottom of the portion of the gate electrode that covers the channel in order to control the surface potential of the underlying channel silicon, thereby forcing the accumulation of carrier distribution on the silicon surface (transistor gate off state), through depletion (subthreshold), and ultimately to strong inversion (on state) as the gate electrode changes from 0V to a positive on-state voltage (NMOS transistor) or a negative on-state voltage (PMOS transistor).

[0020] To achieve this channel surface potential control, the portion of the semiconductor gate electrode located above the channel on the lower surface must have a high dopant concentration. This is because maintaining the metal boundary conditions requires the vertical electric field in the gate dielectric to be shielded by free carriers to generate a zero electric field within the conductive interior of this portion of the gate electrode. Obtaining a sufficiently high concentration of free carriers requires high majority carrier doping in the portion of the gate electrode located above the channel. In some instances, it is desirable that the dopant concentration in the channel is at least high enough to degenerate the carrier distribution, or at least 1 x 10⁻⁶.19 cm -3 .

[0021] At the drain end of the gate electrode, the drain region doping is distributed beneath the gate electrode. In the transistor gate-off state, and specifically when the drain region is held at a high reverse bias (often referred to as the blocking state), the majority carriers in this lower drain overlap portion of the gate electrode are depleted, exposing ionized majority carrier dopant. If the doping type of the gate electrode overlying the drain region is the same as that of the drain electrode, then majority carriers will be attracted to the bottom of the gate electrode, close to and containing its drain end, forming an accumulation layer that provides metallic boundary conditions. This causes a high localized high electric field in the gate dielectric near the drain end, and at the bottom corner of the gate electrode facing the drain, the electric field is amplified by the curvature of the gate electrode corner. This localization peak in the electric field can be high enough to induce transistor degradation mechanisms, such as channel hot carrier (CHC) injection or dielectric failure in the gate dielectric, which can severely limit transistor use at elevated drain blocking voltages.

[0022] According to an example of this disclosure, the drain terminal of the gate electrode is provided with a doping of a conductivity type opposite to that of the drain doping (e.g., n-type) (e.g., p-type). In this configuration, the majority carriers in the drain terminal of the gate electrode can be depleted by the electric field induced by the drain in a reverse bias state. Furthermore, in various examples, the majority carrier concentration in the drain terminal of the gate electrode can be sufficiently low to be depleted without experiencing breakdown, such as by having a concentration of less than 1 × 10⁻⁶. 13 cm -2 The resurf condition ensures the optimal dopant dosage. A significant portion of the gate (e.g., even wider than the gate electrode thickness) can be depleted during drain reverse bias, turning this portion of the gate electrode into a charged dielectric region that balances the exposed charge in the underlying silicon due to opposite doping signs. This charge balance alleviates the high surface electric field over the entire overlap region between the drain dopant distribution and the gate electrode, enabling drain-extended transistor operation at high blocking drain voltages without inducing the degradation effect of high local electric fields, especially during pulsed mode operation. This mutual depletion effect between the drain carrier distribution and the carrier distribution in the drain-facing end of the gate electrode is similar to the mutual depletion of the n-layer and p-layer in the resurf drift region; therefore, we refer to drain-extended transistors employing this gate electrode doping distribution as depletable resurf gate-drain-extended transistors.

[0023] The depletion level of the gate electrode facing the drain end should be limited so that it does not extend to source end features such as silicides on the top surface of the gate electrode, thereby avoiding breakdown effects such as avalanche. To suppress this effect, in some instances, the doping concentration of the gate electrode increases as it approaches any surface silicides or other features that could cause breakdown.

[0024] Figures 1A to 1F These figures illustrate a first type of electronic device to which the principles of this disclosure can be advantageously applied. These figures show a cross-section of an example microelectronic device 100 (e.g., a MOS transistor) comprising a depletable resurf gate electrode 128. Figure 1B (Hereinafter referred to as gate electrode 128). Without being implied, in this example, gate electrode 128 is implemented in an n-type metal-oxide-semiconductor (NMOS) transistor 101 shown in a sequential stage of the example formation method. Other embodiments of gate electrode 128 for a PMOS transistor are within the scope of this example. In the example NMOS transistor 101, the dopant of the first conductivity type is an n-type dopant, and the dopant of the second conductivity type is a p-type dopant.

[0025] Figure 1A This illustration shows a microelectronic device 100 containing an NMOS transistor 101 after the formation of a gate dielectric layer 120 and a gate polysilicon layer 122. Structures and methods within the microelectronic device 100 formed prior to the formation of the gate dielectric layer 120 may include an epitaxial layer 102 above a substrate wafer 104, the substrate wafer and the epitaxial layer together referred to as a substrate 103 having a top surface 106. For example, the substrate wafer 104 may be a substrate having a top surface 106. 17 cm -3 Up to 1×10 19 cm -3 The dopant concentration is low for p-type silicon. Alternatively, the substrate wafer 104 may be lightly doped, with an average dopant concentration of less than 1 × 10⁻⁶. 16 cm -3 As an example, the epitaxial layer 102 can be a layer with a 1×10⁻⁶ layer. 15 cm -3 Up to 1×10 16 cm -3 The dopant concentration is p-type silicon. The epitaxial layer 102 is optional, because in some instances, the NMOS transistor 101 can be formed directly in the substrate wafer 104.

[0026] The isolation layer for NMOS transistors can be formed by shallow trench isolation (STI) or local oxidation of silicon (LOCOS), either of which can be conventional or formed by any future discovered method. The example shown includes STI structure 105.

[0027] In substrate 103, a p-type well region 108 (DWELL) is also formed. The p-type well region 108 is implanted with a p-type dopant that may contain boron and / or indium. The p-type well region 108 may have a depth of 3 x 10⁻⁶ at a depth between 0.5 μm and 1.5 μm below the top surface 106. 16 cm -3 With 1x 10 19 cm -3 The peak dopant density is between [a certain value]. The p-type well region 108 (in some instances, it is combined with the epitaxial layer 102) can be referred to as the body region (e.g., p-type body region) of the NMOS transistor 101. Additionally, an n-type well region 131 is formed in the substrate 103. The n-type well region 131 is doped with an n-type dopant that may contain, for example, phosphorus or arsenic. The n-type well region 131 may have a depth between 0.5 μm and 1.5 μm below the top surface 106 at a density of 3 x 10 [units unclear]. 16 cm -3 With 1x 10 19 cm -3 The peak dopant density between.

[0028] Although not limited to the above Figure 1A The features described herein are formed in the substrate 103 of the NMOS transistor 101, but the gate dielectric layer 120 and the gate polysilicon layer 122 are formed above the top surface 106. The gate dielectric layer 120 can be formed in a high-temperature boiler operation or a rapid thermal process. Other methods for forming the gate dielectric layer 120 are within the scope of this disclosure. The gate dielectric layer 120 can be of any material and have any thickness suitable for the technical application. The gate polysilicon layer 122 is formed on the gate dielectric layer 120 by conventional methods discovered in the future. In the illustrated example, the gate polysilicon layer 122 is formed by using one or more silane-based precursor deposition processes for polycrystalline silicon (which may be referred to as polysilicon). In other examples, alternative gate processes can be used to form the gate polysilicon layer 122. The gate polysilicon layer 122 has a thickness that can range from approximately 50 nm to 300 nm. The gate polysilicon layer 122 is a semiconductor layer and can be undoped or doped after deposition. The gate polysilicon layer 122 can also be a polycrystalline SiGe layer, a polycrystalline Ge layer, a polycrystalline SiC layer, or another semiconductor that can be grown or deposited on the gate dielectric. Figure 1A In the example shown, the gate polysilicon layer 122 is undoped. Figure 3A This refers to an example of polycrystalline silicon being doped after deposition.

[0029] Figure 1BThe diagram shows a cross-section of the NMOS transistor 101 after the formation of gate resist 124 and after gate plasma etching 126. Gate plasma etching 126 removes the previously formed gate dielectric layer 120 and gate polysilicon layer 122 in areas not covered by gate resist 124. The area beneath gate resist 124 defines the gate electrode 128, which is the gate polysilicon layer 122 and gate dielectric layer 120 remaining after gate plasma etching 126. After gate plasma etching 126 is completed, gate resist 124 is removed, and the wafer surface can be cleaned using wet or dry processes.

[0030] refer to Figure 1C Sidewall spacers 130 may be formed on the vertical surface of the gate electrode 128 and may extend from the lateral edge of the gate electrode 128 by 50 nm to 200 nm. After forming the sidewall spacers 130, first source and drain resists 132 are deposited and patterned. First source / drain implantation 136 implants n-type dopant into the substrate 103 through source / drain openings 134 to implant source regions 138, drain regions 139, and portions 135 of the gate electrode. First source / drain implantation 136 may include one or more implantation steps, such that the resulting portions 135 of the source regions 138, drain regions 139, and gate electrode 128 have a 1 x 10⁻⁶ Å diameter. 19 cm -3 With 1x 10 21 cm -3 The conditions for dopant concentration peaking are determined. The doping level implanted in the gate electrode portion 135 is such that it is not depleted during the operation of the NMOS transistor 101. The source region 138 and drain region 139 contain an average dopant density at least twice the average dopant density of the epitaxial layer 102, wherein the peak dopant density is between 0.5 μm and 1.5 μm from the top surface 106. The source / drain resist extension 133 extends the resist toward the drain region 139 past the end of the gate electrode 128. The source / drain resist extension 133 prevents n-type dopant from the first source / drain implant 136 from extending below the gate electrode 128 after a subsequent thermal annealing process. After the source region 138 and drain region 139 are formed, the source and drain resist 132 is removed.

[0031] Figure 1DThis refers to the cross-section of the NMOS transistor 101 after the deposition and patterning of the second source / drain implantation resist 144 to form the opening 146 for the second source / drain implantation 148. The second source / drain implantation 148 may implant dopant into the second source / drain region of the p-channel device (not specifically shown) of the microelectronic device 100. Additionally, the second source / drain implantation 148 implants p-type dopant through the opening 146 to form a heavily p-type doped portion 150 of the gate electrode 128.

[0032] Similar to the first source / drain implantation 136, the second source / drain implantation 148 may occur in one or more steps. The second source / drain implantation 148 may implant boron (or indium)-containing material with total dose and energy such that it provides degenerate doping of a portion 150 of the gate electrode 128, for example, having a doping density greater than 1 x 10⁻⁶ near the solubility limit of the dopant atoms in the gate electrode 128. 19 cm -3 Effective average dopant density. After the second source / drain implantation 148, the second source / drain implantation resist 144 is removed.

[0033] Figure 1E The diagram shows a cross-section after the resurf resist 152 has been deposited and patterned with openings 154. Resurf implantation 156 uses ion implantation to implant p-type dopant to form a first portion 158 of the gate electrode 128. In the remainder of the discussion, gate electrode portions 158, 150, and 135 may be referred to as the first portion 158, the second portion 150, and the third portion 135, respectively. In the first portion 158 of the gate electrode 128, the p-type doping density in the resurf region is sufficiently low to allow depletion during operation of the NMOS transistor 101 and to allow it to function as a resurf region. Resurf implantation 156 may contain implanted material having a density of 1 x 10⁻⁶ p⁻¹. 12 cm -2 With 1x 10 13 cm -2 The total dose of boron or indium occurs in one or more steps. The second portion 150 of the gate electrode 128 is in the heavily n-type doped (greater than 1 x 10⁻⁶) gate electrode 128. 18 cm -3 The third part 135 provides a heavily doped p-type region (greater than 1 x 10⁻⁶) between the lightly p-type doped first part 158. 18 cm -3 The second part 150 prevents the n-type dopant of the third part 135 from reverse-doping the p-type dopant of the first part 158. After resurf implantation 156, the resurf resist 152 is removed.

[0034] Figure 1F The diagram shows a cross-section of the NMOS transistor 101 after the first layer of interconnect 168 is completed. In some instances, a silicide blocking layer 160 may be formed over a first portion 158 of the gate electrode 128, extending partially over a second portion 150 of the gate electrode 128, leaving a region of the second portion 150 uncovered by the silicide blocking layer 160. The silicide blocking layer 160 may be formed by depositing one or more sublayers of oxide, nitride, oxide oxynitride, or any combination thereof over the entire wafer and patterning them to the open regions where silicide formation is desired. In some instances, a metal silicide layer 162 may be formed on the exposed portions of the source region 138, drain region 139, and gate electrode 128. The metal silicide layer 162 provides ohmic electrical connections to the source region 138, drain region 139, and gate electrode 128 with lower resistance compared to similar microelectronic devices without the metal silicide layer 162.

[0035] A front metal dielectric (PMD) layer 164 is formed over the top surface 106 of the substrate 103. The PMD layer 164 may comprise one or more dielectric layers, such as silicon nitride, silicon oxynitride, silicon dioxide, or the like. In some instances, the PMD layer 164 includes a PMD liner and a primary dielectric layer formed on the PMD liner. The PMD layer 164 may then be planarized using a chemical mechanical polishing (CMP) process. Contacts 166 (e.g., tungsten plugs) are formed within the PMD layer 164 to provide electrical connections to the source region 138 and the drain region 139. Interconnects 168 electrically connected to the contacts 166 are formed over the PMD layer 164 using any suitable metallization scheme and provide electrical contacts between the NMOS transistor 101 and other components of the microelectronic device 100.

[0036] Figure 2 This is a schematic representation of the total dopant atom concentration (vertical axis) along the gate electrode 128 of an NMOS transistor 101. Gate electrode 128 shows the portion corresponding to the first part 158 ​​closest to the drain region 139. Figure 1F The first region has a p-type dopant density within a range that allows the first portion 158 to be depleted during operation. The second region corresponds to the second portion 150. Figure 1F The second portion 150 is also p-type doped and is aligned with the first portion 158. The second portion 150 has a p-type doping density so that it does not deplete during operation, as shown in the figure. The third region corresponds to the third portion 135 (…). Figure 1F The third portion 135 is n-type doped, with a doping density such that it will not be depleted during the operation of the NMOS transistor 101. Therefore, the third portion 135 can act as a switching element, while the second portion 150 acts as a lightly doped p-type doped first region 158 that provides a resurf region to prevent the n-type dopant of the third portion 135 from reverse doping.

[0037] Figures 3A to 3F This illustrates a second type of electronic device to which the principles of this disclosure can be advantageously applied. These figures depict a method of forming an example microelectronic device 300 comprising an LDMOS transistor 301, the LDMOS transistor including a depletable resurf gate electrode (such as...). Figure 3B (Gate electrode 328 and below shown). Figure 3A The diagram shows a cross-section of the microelectronic device 300, indicating the region for the LDMOS transistor 301, after the gate dielectric layer 320 and the gate polysilicon layer 322 have been formed. An earlier process included providing a substrate 303 comprising a semiconductor material (e.g., silicon, germanium, or the like) and having a top surface 304. The substrate 303 may comprise, for example, a portion of a bulk semiconductor wafer, a portion of a semiconductor wafer with an epitaxial layer, a portion of a silicon-on-insulator (SOI) wafer, or other structures suitable for forming the microelectronic device 300.

[0038] Substrate 303 may include an optional n-type buried layer (NBL) 306 on p-type layer 305. p-type layer 305 may be a portion of the bulk semiconductor wafer on which microelectronic device 300 is formed, and may have, for example, a 1×10⁻⁶ layer. 18 cm -3 Up to 1×10 19 cm -3 The p-type dopant concentration is between [a certain value]. Alternatively, the p-type layer 305 can be lightly doped, having a dopant concentration less than 1 × 10 [units]. 18 cm -3 The average p-type dopant concentration. For example, NBL 306 can be 2 μm to 10 μm thick and can have a concentration greater than 1 × 10⁻⁶. 19 cm -3 The concentration of n-type dopant (e.g., arsenic, antimony). Substrate 303 may include an epitaxial layer 308 comprising silicon above NBL 306. Epitaxial layer 308 may be considered part of substrate 303 and may be, for example, 2 μm to 12 μm thick. Epitaxial layer 308 may be p-type and have, for example, a 1 × 10⁻⁶ m² / h² concentration. 15 cm -3 Up to 1×10 16 cm -3 The dopant concentration, or "lightly doped," is specified. In versions where substrate 303 lacks NBL 306, epitaxial layer 308 may be directly on p-type layer 305. Alternatively, epitaxial layer 308 is optional, and LDMOS transistor 301 may be directly formed in p-type layer 305.

[0039] An STI structure 310 may be included to provide lateral isolation from other electrical devices above the substrate 303. The field release dielectric layer 312 may be formed using a LOCOS process and may have a thickness in the range of 50 nm to 500 nm. The field release dielectric layer 312 may have a tapered edge along its periphery, wherein the field release dielectric layer 312 abuts the top surface 304 of the substrate 303. The tapered edge of the field release dielectric layer 312 may be referred to as a "bird's beak" region. Although... Figures 3A to 3F The example LDMOS transistor 301 shown includes an STI structure 310 and a field-release dielectric layer 312, but either feature may be omitted in other embodiments within the scope of this disclosure. For example, the field-release dielectric layer 312 may be replaced by another STI structure. Similarly, the STI structure 310 may be replaced by another LOCOS structure, such as one similar to the field-release dielectric layer 312.

[0040] Drift region 314 is formed in substrate 303 beneath a portion of field release dielectric layer 312 and gate dielectric layer 320. One or more n-type implantations are performed to form drift region 314 (which may be referred to as n-drift region) in substrate 303. The n-type dopant defining n-drift region 314 may be implanted in one step or in multiple steps. For example, phosphorus may be 1 x 10⁻⁶. 12 cm -2 With 1x10 13 cm -2 The total dose injected between these parameters has an energy suitable for forming the n-drift region 314 with or without subsequent thermal cycling. Arsenic can also be injected in a similar dose, with a relatively lower energy than phosphorus injections.

[0041] In addition to the n-drift region 314, a DWELL region 336 is also formed. The DWELL region 336 is implanted with p-type dopants that may contain boron and / or indium, and n-type dopants such as arsenic. The DWELL region 336 may have a depth between 0.5 μm and 1.5 μm below the top surface 304 at a depth of 1 x 10⁻⁶. 17 cm -3 With 1x 10 19 cm -3 The p-type peak dopant density is between [values]. The n-type dopant density is greater than 1 x 10 [units]. 18 cm -3 Furthermore, under specific deposition conditions, the p-type / n-type junction depth is between 50 nm and 300 nm below the top surface 304. DWELL region 336 is p-type, except for the n-type region 338 located within DWELL region 336, because... Figure 3AThe final distribution of p-type and n-type dopants after the thermal annealing process preceding the processing stage is indicated. The p-type portion of DWELL region 336 (in some instances combined with epitaxial layer 308) may be referred to as the body region (e.g., p-type body region) of LDMOS transistor 301.

[0042] Continue to refer to Figure 3A The gate dielectric layer 320 can be formed by thermal oxidation of the top surface 304 using well-known methods, or by blanket deposition of a dielectric material such as silicon oxynitride (SiON) over the top surface 304. Depending on the desired device characteristics, the gate dielectric layer 320 can have a thickness ranging from about 3 nm to about 50 nm. The gate polysilicon layer 322 has been formed in the preceding process step, for example, using one or more silane-based precursor deposition processes. Alternatively, alternative gate processes can be used. In either case, previously known or future-developed processes can be used to form the gate polysilicon layer 322, which can have a thickness ranging from approximately 50 nm to 300 nm. The gate polysilicon layer 322 can be undoped or doped in situ after deposition. In this example, the gate polysilicon layer 322 is co-deposited with a p-type precursor (e.g., diborane, boron trichloride, tris(2,4-pentanediol)gallium(III)) such that the p-type dopant dose (e.g., the integral of the net p-type doping concentration through the thickness of the gate electrode) is within 1 x 10⁻⁶. 12 cm -2 With 1x 10 13 cm -2 Between. The low doping concentration in the gate polysilicon layer 322 provides a resurf region defined in a later stage of processing.

[0043] Figure 3B The image shows a cross-section after the gate resist 324 has been deposited and patterned. Gate plasma etching 326 is used to define the gate electrode 328. The gate electrode 328 may have the following characteristics: Figure 5 The raceway layout of the gate electrode 528 is shown. After the gate plasma etching 326 is completed, the gate resist 324 is removed. Figure 3B As shown, the gate electrode 328 extends over portions of the DWELL region 336, the n-type region 338, the epitaxial layer 308, and the n-drift region 314, where these regions intersect with the top surface 304. For discussion purposes, the gate electrode 328 is defined as terminating where the gate dielectric layer merges with the field release dielectric layer 312, where the polysilicon above the field release dielectric layer 312 is a polysilicon field plate 329. The end of the gate electrode 328 opposite to the polysilicon field plate 329 terminates above the DWELL region 336, for example, above the n-type region 338.

[0044] Figure 3C This illustrates an LDMOS transistor 301 after sidewall spacers 340 are formed on the vertical surfaces (e.g., sidewalls) of the gate electrode 328 and the polysilicon field plate 329. The sidewall spacers 340 can be formed by methods currently known or developed in the future, and can extend laterally from 50 nm to 200 nm away from the corresponding sidewalls of the gate electrode 328 and the polysilicon field plate 329.

[0045] Figure 3D The diagram shows a cross-section after the first source / drain resist 342 has been deposited and patterned to form openings 344 and 345 for subsequent first source / drain implantation 346. Opening 345 allows the implantation of n-type dopant from source / drain implantation 346 to form drain region 350, and opening 344 allows n-type dopant to form source region 348. The patterned source / drain resist 342 covers gate electrode 328, thereby protecting gate electrode 328 from the effects of first source / drain implantation 346. The conditions of first source / drain implantation 346 allow the resulting source region 348 and drain region 350 to have a 1 x 10⁻⁶ Ω·cm configuration. 19 cm -3 With 1x10 21 cm -3 The dopant concentration peaks between 0.05 μm and 0.03 μm from the top surface 304. The drain region 350 may have at least twice the average dopant density of the n-drift region 314. The source region 348 may have at least twice the average dopant density of the DWELL region 336. Although the source region 348 is laterally separated from the edge of the gate electrode 328, the n-type region 338 provides a continuous n-type path below the sidewall spacers 340, thereby providing electrical overlap with the gate electrode 328, allowing the source region 348 to be electrically coupled to the channel below the gate electrode 328. After the first source / drain implantation 346, the source / drain resist 342 is removed.

[0046] Figure 3E The diagram shows an LDMOS transistor 301 after a second source / drain resist 354 has been deposited and patterned to form various source / drain resist openings for a second source / drain implantation 358. The second source / drain implantation 358 implants p-type dopant into the source and drain regions of a p-channel transistor (not shown) simultaneously formed in a substrate 303. Like the first source / drain implantation 346, the second source / drain implantation 358 can occur in one or more steps using an implantation material comprising boron and / or indium, the implantation material having a total dose and energy suitable for providing degenerate doping of the source and drain regions of the p-channel transistor, for example, having a value greater than 1 x 10⁻⁶ near the solubility limit of dopant atoms in the source and drain regions. 19 cm -3Effective average dopant density.

[0047] An opening 356 in the second source / drain resist 354 exposes a portion of the top surface 304 to form a back gate region 360. The back gate region 360 forms a continuous p-type conductive path to the DWELL region 336 and to the epitaxial layer 308. The second source / drain resist 354 also includes an opening 357 positioned to selectively introduce the p-type dopant of the second source / drain implant 358 into a second portion 362 of the gate electrode 328.

[0048] Due to the second source / drain implantation 358, the second portion 362 of the gate electrode 328 is heavily p-type doped, for example, having a doping density greater than 1 x 10⁻⁶. 19 cm -3 The degenerate doping of the effective average dopant density. Due to the... Figure 3A In the in-situ doping described, the first portion 323 of the gate electrode 328 remains lightly p-type doped. In other words, the gate electrode 328 has a lightly p-type doped first portion 323 that can become depleted during operation of the LDMOS transistor 301. Therefore, this first portion 323 of the gate electrode 328 can act as a depletion resurf region. The polysilicon field plate 329 above the field release dielectric layer 312 docks with the first portion 323 of the gate electrode 328 at the intersection of the field release dielectric layer 312 and the gate dielectric layer 320, and terminates above the field release dielectric layer 312. The second portion 362 of the gate electrode 328 docks with the first portion of the gate electrode 328 near the intersection of the DWELL region 336 and the epitaxial layer 308 at the top surface 304 of the substrate 303, and terminates above the n-type region 338. The second portion 362 of the gate electrode 328 provides the switching region of the LDMOS transistor 301.

[0049] Figure 3F The diagram shows a cross-section of the LDMOS transistor 301 after the first layer of interconnect 370 is completed. A silicide blocking layer 364 has protected the first portion 323 of the gate electrode 328 from silicide formation, while silicide 366 has been formed over the source region 348, drain region 350, and back gate region 360, and partially over the second portion 362 of the gate electrode 328.

[0050] A metal front dielectric (PMD) layer 368 is formed over the top surface 304 of the substrate 303. The PMD layer 368 may include one or more dielectric layers, such as silicon nitride, silicon oxynitride, silicon dioxide, or the like. In some instances, the PMD layer 368 includes a PMD liner and a primary dielectric layer formed on the PMD liner.

[0051] Contacts 372, passing through PMD layer 368, provide electrical contacts to source region 348, drain region 350, and back gate region 360, while interconnects 370 provide electrical connections to other components of microelectronic device 300. Contacts 372 and interconnects 370 can be formed using any suitable metallization process.

[0052] Continue to refer to Figure 3F Similar to Figure 2 of Figure 4 A schematic representation of the total dopant atom concentration (vertical axis) of the LDMOS transistor 301 is shown along the axis passing through the gate electrode 328 between the source region 348 and the drain region 350. Figure 4 On the right, region 3, representing the dopant concentration, indicates the first portion 323 of the gate electrode 328 closest to the drain region 350. The first portion 323 has a p-type dopant density within a range that allows this portion of the gate electrode 328 to be depleted during operation of the LDMOS transistor 301. Figure 4 Section 2 corresponds to the second part 362 ( Figure 3F The second portion 362 is also p-type doped and is aligned with the first portion 323. The second portion 362 has a p-type doping density such that it will not be depleted during operation of the LDMOS transistor 301. Therefore, the second portion 362 can act as a switching element for the LDMOS transistor 301, while the first portion provides a resurf effect. Advantageously, the gate electrode 328 has an integrated resurf region as the first portion 323 of the gate electrode 328, which provides a depletion region so that during operation, the electric field across the gate is lower and more uniform compared to a gate electrode with a uniformly high doping level.

[0053] Figure 5 This is a top view of a microelectronic device 500 including an LDMOS transistor 501 in a racetrack configuration, such as a racetrack layout (or a generally rounded rectangular layout) that is generally larger in a first orientation than in a second orientation perpendicular to the first orientation. The racetrack configuration can also be referred to as a closed-loop configuration. The LDMOS transistor 501 includes a reference... Figures 3A to 3F Aspects of the LDMOS transistor 501 are described. The LDMOS transistor 501 includes a gate electrode 528 arranged in a racetrack configuration.

[0054] like Figure 5 As shown, the drain region 550 can be the innermost linear element of the LDMOS transistor 501, while the other elements shown form a series of concentric closed-loop elements surrounding the drain region 550. A field-release dielectric layer 512 is mated to the drain region 550. Other elements of the LDMOS transistor 501 include a field plate 529, a first portion 523 and a second portion 562 of the gate electrode 528, a sidewall 540, a source region 548, a back gate region 560, and an STI region 510.

[0055] Figure 6 This figure illustrates a third type of electronic device to which the principles of this disclosure can be advantageously applied. It is a cross-section of a microelectronic device 600 comprising a DENMOS transistor 601 having a depletable resurf gate electrode 628. The gate electrode 628 is similar to... Figures 1A to 1F The gate electrode 128 is characterized in that the gate electrode 628 has: a first portion 623 that terminates closest to the drain, the first portion 623 being lightly p-type doped and allowing depletion during operation; a second portion 662 that docks to the first portion 623, the second portion 662 being heavily p-type doped and not depleted during operation; and a third portion 650 that docks to the second portion 662, the third portion 650 being heavily n-type doped and not depleted during operation. (As in the section on...) Figures 1A to 1F and Figures 3A to 3F In the described structure, the first portion 623 of the gate electrode 628 is lightly p-type doped and acts as a resurf element. This element reduces the electric field at the drain terminal of the gate electrode 628, thereby allowing for a higher operating voltage and favorable reliability characteristics regarding CHC and gate dielectric loss compared to the DENMOS transistor 601 without a resurf element. Furthermore, at certain operating voltages, the gate electrode 628 including the first portion 623 acting as a resurf element can advantageously eliminate the need for a field-release dielectric layer due to the lower and more uniform electric field across the gate electrode 628, as shown in the example DENMOS transistor 601.

[0056] Other structural components of the DENMOS transistor 601 include a substrate 603, a top surface of the substrate 604, a p-type wafer 605, an NBL layer 606, an optional p-type buried layer 616, an epitaxial layer 608, an STI isolation layer 610, an n-type drift region 614, a p-type well 636, an implanted source region 646, a furnace-annealed source region 647, an implanted drain region 648, a furnace-annealed drain region 649, an implanted back gate region 660, a furnace-annealed back gate region 661, a silicide blocking layer 664, a silicide layer 666, a PMD layer 668, contacts 672, and interconnects 670.

[0057] Figure 7 and 8 Some beneficial results of the described principles are illustrated graphically. (Initial reference) Figure 7The graph shows a comparison of the electric field below the gate electrode of a reference LDMOS transistor (dashed line) with that of a similar depletionable resurf gate electrode LDMOS transistor (solid line) derived from TCAD modeling. The gate electrode of the reference transistor is uniformly n-type doped as is conventionally possible. The depletionable resurf gate electrode of the LDMOS transistor has a similar field to that in the first section 158 (…). Figure 1F The first portion 158 has a lightly doped p-type portion and a heavily doped p-type portion similar to portion 150 extending from the first portion 158 toward the source. The lightly doped first portion 158 serves as the resurf region of the depletable resurf gate LDMOS transistor. The magnitude of the electric field below the gate electrode between the source and drain regions is shown. The two modeled transistors are simulated operating in a pulse mode with a pulse length of less than 1 μs. As shown in the graph, the electric field below the gate electrode of the depletable resurf gate LDMOS transistor is more uniformly distributed than the electric field below the gate electrode of the reference transistor. Furthermore, the peak value of the electric field below the gate electrode is lower near the drain end of the gate electrode of the depletable resurf gate LDMOS. The lower electric field below the gate electrode near the drain of the depletable resurf gate LDMOS is advantageous because it improves reliability characteristics with respect to CHC and gate dielectric loss compared to the reference transistor.

[0058] See also Figure 8 For depletable gate LDMOS transistors, the BVDSS in pulse mode is greater than that in DC mode. The increased BVDSS of depletable gate LDMOS transistors in pulse mode can be advantageous in applications where tolerance to inductive ringing is desired.

[0059] Although various examples of this disclosure have been described above, it should be understood that they are presented by way of example only and not limitation. Thus, while the foregoing examples of using various resist layers (e.g., photoresist or photomask layers) to perform various process steps (e.g., implantation or etching steps) have been described, this disclosure is not limited thereto. For example, one or more hard masks (comprising one or more layers) may be patterned to define various regions for subsequent process steps to be applied (e.g., regions for receiving dopant atoms, regions for blocking etchant). Furthermore, in some examples, the resist layer may comprise multiple layers of resist instead of a single layer. Many changes may be made to the disclosed examples based on the disclosure herein without departing from the spirit or scope of this disclosure. Therefore, the breadth and scope of this disclosure should not be limited to any of the examples described above. In fact, the scope of this disclosure should be defined according to the appended claims and their equivalents.

Claims

1. A microelectronic device comprising: A source region and a drain region extending into a semiconductor substrate having a second conductivity type, and the source region and the drain region having an opposite first conductivity type; A channel region having the second conductivity type extends between the source region and the drain region; as well as A gate electrode is provided above the channel region and has a first portion and a second portion, the first portion having a second conductivity type and a first dopant concentration, and the second portion extending from the first portion toward the source region and having a second conductivity type and a second higher dopant concentration.

2. The microelectronic device of claim 1, further comprising a drain drift region having the first conductivity type, the drain drift region extending below the first portion from the drain region toward the source region, the drain drift region having an average dopant concentration lower than the average dopant concentration of the drain region.

3. The microelectronic device of claim 2, further comprising a field release dielectric layer above the drain drift region, the field release dielectric layer extending from a gate dielectric layer located below the first portion of the gate electrode, the field release dielectric layer having a thickness greater than the thickness of the gate dielectric layer.

4. The microelectronic device of claim 1, wherein the channel region comprises a DWELL region having the second conductivity type.

5. The microelectronic device of claim 1, wherein the second portion has a size greater than 1 x 10⁻⁶. 18 cm -3 The second dopant concentration, and the first portion having a concentration less than 1 x 10⁻⁶. 13 cm -2 The first dopant dose.

6. The microelectronic device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

7. The microelectronic device of claim 1, further comprising a silicide blocking layer above the first portion of the gate electrode.

8. The microelectronic device of claim 1, wherein a gate electrode field plate extends from the first portion of the gate electrode toward the drain region, the gate electrode field plate being above a field release dielectric layer, the gate electrode field plate having the second conductivity type and the same dopant concentration as the first portion.

9. The microelectronic device of claim 1, wherein a third portion of the gate electrode extends from the second portion toward the source region, the third portion having the first conductivity type.

10. The microelectronic device of claim 1, wherein the microelectronic device is selected from the group consisting of: metal-oxide-semiconductor transistors, laterally diffused metal-oxide-semiconductor (LDMOS) transistors, drain-extended metal-oxide-semiconductor (DENMOS) transistors, gated bipolar semiconductor devices, gated unipolar semiconductor devices, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor (MOS) triggered SCRs, MOS-controlled thyristors, and gated diodes.

11. The microelectronic device of claim 1, wherein the gate electrode comprises a semiconductor layer selected from the group consisting of polycrystalline silicon, polycrystalline SiGe, polycrystalline Ge, and polycrystalline SiC.

12. A method of forming a microelectronic device, comprising: A source region and a drain region having a first conductivity type are formed, the source region and the drain region extending into a semiconductor substrate having an opposite second conductivity type; as well as A gate electrode is formed above the semiconductor substrate between the source region and the drain region. The gate electrode has a first portion and a second portion, the first portion and the second portion having a second conductivity type, the first portion being between the second portion and the drain region and having a first dopant concentration, and the second portion having a second higher dopant concentration.

13. The method of claim 12, further comprising forming a drain drift region having the first conductivity type in the semiconductor substrate, the drain drift region extending from the drain region toward the source region, extending below the first portion and ending before the second portion, the drain drift region having an average dopant concentration lower than the average dopant concentration of the drain region.

14. The method of claim 12, further comprising forming a field release dielectric layer on the drain drift region, the field release dielectric layer extending from the gate dielectric toward the drain region and having a thickness greater than the thickness of the gate dielectric layer.

15. The method of claim 12, further comprising forming a DWELL having the second conductivity type in the semiconductor substrate and extending from the source region below the second portion toward the drain region.

16. The method of claim 12, further comprising forming a shape having a size greater than 1 x 10⁻⁶. 18 cm -3 The second portion of the second dopant concentration and having less than 1 x 10 13 cm -2 The first portion of the first dopant dose.

17. The method of claim 12, further comprising forming a silicide blocking layer over the first portion of the gate electrode, and retaining a region of the second portion uncovered by the silicide blocking layer.

18. The method of claim 12, further comprising forming a gate electrode field plate extending from the first portion of the gate electrode toward the drain region, the gate electrode field plate being above a field release dielectric layer, the gate electrode field plate having the second conductivity type and the same dopant concentration as the first portion.

19. The method of claim 12, further comprising forming a third portion of the gate electrode extending from the second portion toward the source region, the third portion having the first conductivity type and greater than 1x10 18 cm -3 The doping concentration.

20. The method of claim 12, wherein the first portion of the gate electrode is doped by in-situ doping of the polysilicon layer forming the first portion.

21. The method of claim 12, wherein the first portion of the gate electrode is doped by ion implantation.

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