Semiconductor device

Abstract

According to one embodiment, a semiconductor device includes: a first conductor exposed on a first surface of a package; first and second transistors, the drains of which are connected to the first conductor; an insulating substrate; a second conductor and a third conductor exposed from the second surface of the package and disposed on the third surface of the insulating substrate; a first wiring layer embedded in the insulating substrate and connected to the second conductor; a fourth conductor connected to the source of the first transistor and the third conductor; a fifth conductor connected to the source of the second transistor and the third conductor; a sixth conductor connected to the gate of the first transistor and the second conductor; and a seventh conductor provided on the fourth surface of the insulating substrate and connected to the gate of the second transistor and the first wiring layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device. Background Technology

[0002] Power modules are known as semiconductor devices that achieve high output. A power module is configured as a package that integrates multiple power semiconductors.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2022-165445 Patent Document 2: U.S. Patent Application Publication No. 2013 / 0258628 Summary of the Invention

[0004] The technical problem that the invention aims to solve In one embodiment of the present invention, a semiconductor device capable of suppressing oscillations within the device is provided.

[0005] Technical solutions for solving technical problems The semiconductor device according to the embodiment includes: a first conductor exposed on a first side of a package; a first transistor disposed within the package with its drain connected to the first conductor; a second transistor disposed within the package with its drain connected to the first conductor; an insulating substrate; the second conductor exposed from a second side of the package opposite to the first side and disposed on a third side of the insulating substrate; a third conductor exposed from the second side of the package and disposed separately from the second conductor on the third side of the insulating substrate; a first wiring layer embedded in the insulating substrate and connected to the second conductor; a fourth conductor disposed on a fourth side of the insulating substrate opposite to the third side and connected to the source of the first transistor and the third conductor; a fifth conductor disposed on the fourth side of the insulating substrate and connected to the source of the second transistor and the third conductor; a sixth conductor disposed on the fourth side of the insulating substrate and connected to the gate of the first transistor and the second conductor; and a seventh conductor disposed on the fourth side of the insulating substrate and connected to the gate of the second transistor and the first wiring layer. Attached Figure Description

[0006] Figure 1 This is a circuit diagram illustrating an example of the circuit configuration of the semiconductor device according to the first embodiment.

[0007] Figure 2 This is a top view of the upper surface of a semiconductor device package according to one embodiment.

[0008] Figure 3 This is a top view of the lower surface of a semiconductor device package according to one embodiment.

[0009] Figure 4 It is along Figure 2 and Figure 3 A cross-sectional view of the semiconductor device along lines A1-A2.

[0010] Figure 5 This is a top view of the packaged upper surface of a semiconductor device according to a first variation of an embodiment.

[0011] Figure 6 This is a circuit diagram illustrating the circuit configuration of a semiconductor device according to a second variation of an embodiment.

[0012] Figure 7 This is a cross-sectional view of a semiconductor device according to a third variation of an embodiment.

[0013] Figure 8 This is a cross-sectional view of a semiconductor device according to a fourth variation of an embodiment. Detailed Implementation

[0014] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having the same function and configuration will be labeled with common reference numerals. Additionally, when multiple constituent elements sharing common reference numerals are distinguished, a suffix will be added to the common reference numerals for differentiation. Furthermore, when it is not necessary to specifically distinguish multiple constituent elements, only the common reference numerals will be used for the multiple constituent elements, without any suffix. Here, the suffix is ​​not limited to subscript characters or superscript characters, but includes, for example, lowercase English letters added to the end of the reference numerals and indexes indicating arrangement, etc.

[0015] One embodiment of the semiconductor device is a power module. Semiconductor devices, for example, are suitable for power conversion devices used in railway vehicles or industrial equipment used in renewable energy power generation systems.

[0016] 1. Circuit structure of semiconductor devices First, refer to Figure 1 An example of the circuit configuration of semiconductor device 1 will be described. Figure 1 This is a circuit diagram illustrating an example of the circuit configuration of semiconductor device 1.

[0017] like Figure 1 As shown, semiconductor device 1 includes a plurality of transistors Tr connected in parallel. Figure 1 In the example shown, semiconductor device 1 includes two transistors Tr1 and Tr2 connected in parallel. Furthermore, the number of transistors Tr connected in parallel can also be three or more.

[0018] Transistors Tr1 and Tr2 are, for example, n-channel MOS (Metal Oxide Semiconductor) transistors. Furthermore, the substrate for forming transistor Tr can be a Si substrate or a SiC substrate. The following explanation focuses on the case where the substrate is SiC.

[0019] The drains of transistors Tr1 and Tr2 are connected to the drain terminal D. For example, a positive voltage is applied to the drain terminal D from the outside.

[0020] The gates of transistors Tr1 and Tr2 are connected together to the gate terminal G. A gate signal (voltage) controlling transistors Tr1 and Tr2 is applied to the gate terminal G. Parasitic inductance (also referred to as "gate inductance") is generated in the gate wiring connecting the gates of transistors Tr1 and Tr2.

[0021] The sources of transistors Tr1 and Tr2 are connected together to the source terminal S. For example, a lower voltage than the drain terminal D is applied to the source terminal S. A parasitic inductance (also referred to as "source inductance") is generated in the source wiring connecting the sources of transistors Tr1 and Tr2.

[0022] 2. Composition of semiconductor devices 2.1 Planar Configuration of Semiconductor Devices First, refer to Figure 2 and Figure 3 An example of the planar configuration of semiconductor device 1 will be described. Figure 2 This is a top view of the upper surface P1 of the package of semiconductor device 1. Figure 3 This is a top view of the lower surface P2 of the package of semiconductor device 1. In the following description, when the semiconductor device 1 is surface-mounted, for example, on a printed circuit board, the mounting surface that bonds to the printed circuit board is referred to as "lower surface P2 of the package". Furthermore, the surface of the semiconductor device 1 opposite to the lower surface P2 of the package is referred to as "upper surface P1 of the package". Figure 2 and Figure 3 In the example, the plane along the upper surface P1 and the lower surface P2 of the package is represented as the XY plane. The direction intersecting the XY plane is represented as the Z direction.

[0023] like Figure 2 and Figure 3 As shown, molding resin 10 and conductors 22, 23 and 30 are exposed on the package surface of semiconductor device 1.

[0024] The molding resin 10 seals the semiconductor device 1. The molding resin 10 stably maintains the insulation and arrangement between the semiconductor chip (not shown) and the conductors 22, 23, and 30 within the semiconductor device 1. The molding resin 10 may be, for example, epoxy resin. Alternatively, the molding resin 10 may contain fillers such as silicon oxide.

[0025] Conductors 22, 23, and 30 are made of conductive materials, such as copper (Cu). The exposed surfaces of each conductor from the molding resin 10 (hereinafter referred to as "exposed surfaces") may be covered with tin (Sn), solder, etc., or may not be covered. The exposed surfaces of conductors 22, 23, and 30 can function as heat sinks for the semiconductor device 1. Furthermore, Figure 2 and Figure 3 The diagram shows a configuration where, for example, the conductors (lead terminals) do not protrude from the molding resin 10 (i.e., the package), as in a DFN (Dual Flatpack Non-leaded) package, but it is not limited to this. The conductors may also protrude from the molding resin 10. Furthermore, the shape of the conductors is arbitrary.

[0026] Conductors 22 and 23 are exposed on the upper surface P1 of the package. For example, conductor 22 functions as the source terminal S. Conductor 23 functions as the gate terminal G. The exposed surfaces of conductors 22 and 23 are electrically connected to the printed circuit board or the like via solder.

[0027] Conductor 30 is exposed on the lower surface P2 of the package. For example, conductor 30 functions as a drain terminal D. For example, the exposed surface of conductor 30 is electrically connected to the printed circuit board or the like via solder.

[0028] 2.2 Cross-sectional configuration of semiconductor devices Next, refer to Figure 4 An example of the cross-sectional configuration of semiconductor device 1 will be described. Figure 4 It is along Figure 2 and Figure 3 A cross-sectional view of semiconductor device 1 along lines A1-A2. In the following description, the direction in which the two semiconductor chips 40 are arranged in the XY plane is defined as the X direction. The direction intersecting the X direction is defined as the Y direction.

[0029] like Figure 4 As shown, the semiconductor device 1 includes molding resin 10, wiring substrate 20, conductor 30, two semiconductor chips 40, and mounting materials 50d, 50g, and 50s.

[0030] The lower surface of the conductor 30 is exposed on the lower surface P2 of the package. The conductor 30 functions as the drain terminal D. Two semiconductor chips 40 are bonded to the upper surface of the conductor 30 via mounting material 50g. That is, the two semiconductor chips 40 are disposed within the package (molding resin 10).

[0031] Two semiconductor chips 40 are used Figure 1 The transistors Tr1 and Tr2 are described. The semiconductor chip 40 includes a SiC substrate 41, an epitaxial layer 42, a gate insulating layer 46, a gate electrode 47, a source electrode 48, and a passivation film 49.

[0032] SiC substrate 41 is n + The SiC substrate 41 functions as the drain region. The lower surface of the SiC substrate 41 is bonded to the upper surface of the conductor 30 via mounting material 50g. That is, the lower surface of the SiC substrate 41 serves as the drain electrode and is electrically connected to the conductor 30 (drain terminal D). Alternatively, a separate drain electrode can be provided in contact with the lower surface of the SiC substrate 41. Figure 4 In the example shown, two semiconductor chips 40 arranged in the X direction are bonded to the upper surface of the conductor 30 by mounting material 50g.

[0033] An epitaxial layer 42 is disposed on the upper surface of the SiC substrate 41. An n-type epitaxial layer is disposed inside the epitaxial layer 42. - Type 43 drift region, p-type body region 44 and n + The source region of type 45.

[0034] The drift region 43 is disposed on the upper surface of the SiC substrate 41, i.e. the drain region.

[0035] Two p-shaped regions 44 are provided near the surface (upper surface) of the drift region 43.

[0036] A source region 45 is disposed near the surface of the p-type body region 44. The p-type body region 44 surrounds the source region 45.

[0037] A gate insulating layer 46 is disposed on the upper surface of the epitaxial layer 42. The lower surface of the gate insulating layer 46 contacts a portion of the two source regions 45, a portion of the two p-type body regions 44, and a drift region 43 between the two p-type body regions 44. For example, a channel for a transistor Tr is formed between the two source regions 45 near the surface of the p-type body region 44 that is in contact with the gate insulating layer 46. The gate insulating layer 46 is made of an insulating material.

[0038] The gate electrode 47 is disposed on the upper surface of the gate insulating layer 46. The gate electrode 47 is made of a conductive material.

[0039] Source electrodes 48 are disposed above the two p-type body regions. More specifically, the source electrodes 48 are disposed on the upper surfaces of a portion of the source region 45 and a portion of the p-type body region 44. The source electrodes 48 are made of a conductive material. For example, a gate electrode 47 is disposed between the two source electrodes 48 in the X direction.

[0040] The passivation film 49 is disposed in a manner that surrounds the gate electrode 47 and the source electrode 48. The passivation film 49 physically and electrically separates the gate electrode 47 and the source electrode 48. The passivation film 49 is made of a resin material such as polyimide.

[0041] A wiring substrate 20 is disposed above the semiconductor chip 40. That is, the semiconductor chip 40 is disposed between the conductor 30 and the wiring substrate 20.

[0042] The gate electrode 47 is electrically connected to the wiring substrate 20 via mounting material 50g. The source electrode 48 is electrically connected to the wiring substrate 20 via mounting material 50s.

[0043] Mounting materials 50d, 50g, and 50s are made of conductive materials. Mounting materials 50d, 50g, and 50s can be made of solder, for example. Alternatively, non-melting sintered materials (such as any one of copper, silver, lead, copper-tin compounds, silver-tin compounds, or nickel-tin compounds) can be used instead of solder. In this case, pressure-sintered materials with excellent pressure resistance can be used.

[0044] Next, the internal structure of the wiring substrate 20 will be described. The wiring substrate 20 is a multilayer wiring substrate having multiple conductors (wiring layers) disposed on both sides and inside. The wiring substrate 20 includes an insulating substrate 21, conductors 22, 23, conductors 24a-24d, conductors 25a and 25b, gate wiring 26, and contact plugs 27a-27g. Conductors 22, 23, 24a-24d, 25a and 25b, gate wiring 26, and contact plugs 27a-27g are made of conductive material, such as copper.

[0045] The insulating substrate 21 is made of an insulating material. The insulating substrate 21 may be, for example, ceramic, or may contain a thermosetting resin.

[0046] Conductor 22 is disposed on the upper surface S1 of insulating substrate 21. The upper surface of conductor 22 is exposed on the upper surface P1 of the package, and functions as source wiring and source terminal S.

[0047] Conductor 23 is disposed separately from conductor 22 on the upper surface S1 of insulating substrate 21. The upper surface of conductor 23 is exposed on the upper surface P1 of the package and functions as gate terminal G.

[0048] Conductors 24a~24d, conductors 25a and 25b are disposed on the lower surface S2 of the insulating substrate 21.

[0049] Conductors 24a-24d are connected to the source electrodes 48 of the semiconductor chip 40 via mounting material 50s. For example, conductors 24a and 24b are connected to the two source electrodes 48 of the semiconductor chip 40 (transistor Tr1), respectively. Conductors 24c and 24d are connected to the two source electrodes 48 of the semiconductor chip 40 (transistor Tr2), respectively.

[0050] Conductors 25a and 25b are respectively connected to the gate electrode 47 of the semiconductor chip 40 via mounting material 50g. For example, conductor 25a is connected to the gate electrode 47 of the semiconductor chip 40 (transistor Tr1). Conductor 25b is connected to the gate electrode 47 of the semiconductor chip 40 (transistor Tr2).

[0051] Gate wiring 26 is embedded in insulating substrate 21. Gate wiring 26 is disposed in the Z direction between the upper surface S1 and the lower surface S2 of insulating substrate 21. Gate wiring 26 extends in the XY plane. Furthermore, the wiring width, wiring thickness, and wiring length (wiring layout) of gate wiring 26 can be arbitrarily set. By adjusting the wiring width, wiring thickness, and wiring length of gate wiring 26, the gate inductance of gate wiring 26 can be adjusted.

[0052] The gate wiring 26 is arranged parallel to the conductor 22 in the Z direction.

[0053] Contact plugs 27a-27g are disposed within the insulating substrate 21. Contact plugs 27a-27g extend in the Z direction. One end of contact plug 27a is connected to conductor 22, and the other end is connected to conductor 24a. One end of contact plug 27b is connected to conductor 23, and the other end is connected to conductor 25a. One end of contact plug 27c is connected to conductor 23, and the other end is connected to gate wiring 26. One end of contact plug 27d is connected to conductor 22, and the other end is connected to conductor 24b. One end of contact plug 27e is connected to conductor 22, and the other end is connected to conductor 24c. One end of contact plug 27f is connected to gate wiring 26, and the other end is connected to conductor 25b. One end of contact plug 27g is connected to conductor 22, and the other end is connected to conductor 24d.

[0054] The current flowing through the gate wiring 26 is designated as Ig, and the current flowing through the conductor 22 (i.e., the source wiring) is designated as Is. In this embodiment, the conductor 22 and the gate wiring 26 are arranged such that the currents Ig and Is are in opposite directions. That is, the gate signal flowing in the gate wiring 26 and the source signal flowing in the conductor 22 are arranged in opposite phases. As a result, the gate inductance is in opposite phase to the source inductance. Therefore, the gate inductance is canceled out by the mutual inductance of the gate inductance and the source inductance.

[0055] According to the configuration of this embodiment, a semiconductor device 1 capable of suppressing oscillations within the device can be provided.

[0056] For example, in a loop between parallel-connected transistors, if the length of the source wiring increases, the source inductance between the transistors increases, which can easily cause oscillations during switching. Increasing the gate inductance between the transistors is an effective countermeasure against oscillations. However, if the gate inductance increases, the performance of the semiconductor device deteriorates due to substrate misalignment during transistor switching, reduced switching speed, and other factors.

[0057] In contrast, according to the configuration of this embodiment, the semiconductor device 1 can use a wiring substrate 20 in the connection between the semiconductor chip 40 and the gate terminal G and the source terminal S. By using the wiring substrate 20, the current path (wiring layout) of the gate wiring and the source wiring can be optimized. That is, the gate inductance and the source inductance between the semiconductor chips 40 can be adjusted. As a result, the gate inductance can be increased. In addition, by shortening the current path of the source wiring and increasing the wiring area, the source inductance can be reduced.

[0058] Furthermore, according to the configuration of this embodiment, the semiconductor device 1 can arrange the conductor 22 (i.e., the source wiring) and the gate wiring 26 in the wiring substrate 20, such that the gate current Ig and the source current Is flow in opposite directions. This allows the gate inductance to be the opposite phase of the source inductance. Therefore, the gate inductance can be canceled out by the mutual inductance with the source inductance. Thus, the reduction in switching speed caused by the gate inductance can be suppressed.

[0059] Furthermore, according to the configuration of this embodiment, the semiconductor device 1 allows the conductors 22 and 23 disposed on the upper surface S1 of the wiring substrate 20 to be exposed from the upper surface P1 of the package. Additionally, the semiconductor device 1 allows the conductor 30 to be exposed from the lower surface P2 of the package. Thus, the semiconductor device 1 allows a conductor (metallic material) with excellent thermal conductivity to be exposed from both sides of the package. That is, the semiconductor device 1 can dissipate heat from both sides of the package. Therefore, the heat dissipation performance of the semiconductor device 1 can be improved.

[0060] 3. Variations, etc. Furthermore, various modifications can be applied beyond the embodiments described above. Three modifications will be described below. In these modifications, the focus will be on the differences from the original embodiments.

[0061] 3.1 First Variation Reference Figure 5 The first variation will be explained. Figure 5 This is a top view of the upper surface P1 of the package of semiconductor device 1.

[0062] like Figure 5 As shown, the insulating substrate 21 can also be exposed on the upper surface P1 of the package of the semiconductor device 1.

[0063] 3.2 Second variation Reference Figure 6 The second variation will be explained. Figure 6 This is a circuit diagram showing the circuit configuration of semiconductor device 1. Semiconductor device 1 can also be... Figure 6 The circuit configuration is shown.

[0064] like Figure 6 As shown, for example, semiconductor device 1 includes an upper arm portion UA ​​containing a plurality of transistors connected in parallel, and a lower arm portion LA containing a plurality of transistors connected in parallel. The upper arm portion UA ​​and the lower arm portion LA are connected in series. Each arm portion is used with... Figure 1 The circuit configuration described corresponds to this.

[0065] The upper arm portion UA ​​contains transistors Tr1 and Tr2. Transistor Tr1 and transistor Tr2 are connected in parallel.

[0066] The lower arm LA contains transistors Tr3 and Tr4. Transistor Tr3 and transistor Tr4 are connected in parallel.

[0067] Transistors Tr1, Tr2, Tr3, and Tr4 are, for example, n-channel MOS transistors.

[0068] The drains of transistors Tr1 and Tr2 are connected to the positive terminal P. A positive voltage is applied to the positive terminal P externally. The gates of transistors Tr1 and Tr2 are connected to the upper gate terminal HG via upper gate wiring. The sources of transistors Tr1 and Tr2 are connected to the upper source sensing terminal HSS via upper source sensing wiring. The upper source sensing terminal HSS is used to sense (monitor) the source voltages of transistors Tr1 and Tr2. Additionally, the sources of transistors Tr1 and Tr2 are connected to the output terminal AC and the drains of transistors Tr3 and Tr4.

[0069] The gates of transistors Tr3 and Tr4 are connected to the lower gate terminal LG via a lower gate wiring. The sources of transistors Tr3 and Tr4 are connected to the lower source sensing terminal LSS via a lower source sensing wiring. The lower source sensing terminal LSS is used for sensing (monitoring) the source voltages of transistors Tr3 and Tr4. Additionally, the sources of transistors Tr3 and Tr4 are connected to the negative terminal N. A lower voltage is applied to the negative terminal N than to the positive terminal P.

[0070] 3.3 Third variation Reference Figure 7 The third variation will be explained. Figure 7 This is a cross-sectional view of semiconductor device 1.

[0071] like Figure 7 As shown, the wiring substrate 20 may also include source wiring 28 embedded in the insulating substrate 21. For example, the source wiring 28 is disposed in the Z direction between the upper surface S1 of the insulating substrate 21 and the upper surface of the gate wiring 26. The source wiring 28 extends in the XY plane. The source wiring 28 is disposed parallel to the gate wiring 26 in the Z direction. The source wiring 28 is connected to the conductor 22 via a contact plug 27h.

[0072] 3.4 Fourth Variation Example Reference Figure 8 The fourth variation will be explained. Figure 8 This is a cross-sectional view of semiconductor device 1.

[0073] like Figure 8 As shown, a wiring substrate 60 can also be provided between the semiconductor chip 40 and the conductor 30. The wiring substrate 60 is a wiring substrate having a plurality of conductors disposed on both sides. The wiring substrate 60 includes an insulating substrate 61, conductors 62 and 63. The insulating substrate 61 is made of an insulating material. Conductors 62 and 63 are made of a conductive material, such as copper.

[0074] Conductor 62 is disposed on the upper surface of insulating substrate 61 and connected to the SiC substrate (drain region) of semiconductor chip 40. Conductor 63 is disposed on the lower surface of insulating substrate 61 and connected to conductor 30 via mounting material 50d. Conductors 62 and 63 are electrically connected via contact plugs (not shown).

[0075] In addition, the “connection” in the above embodiments also includes a state in which the two are indirectly connected by interleaving something else, such as a transistor or a resistor.

[0076] While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, characterized in that, have: The first conductor is exposed on the first side of the package; A first transistor is disposed within the package, with its drain connected to the first conductor; A second transistor is disposed within the package, with its drain connected to the first conductor; Insulating substrate; The second conductor is exposed from the second side of the package opposite to the first side and is disposed on the third side of the insulating substrate; A third conductor is exposed from the second side of the package and is disposed separately from the second conductor on the third side of the insulating substrate; The first wiring layer is embedded in the insulating substrate and connected to the second conductor. A fourth conductor is disposed on the fourth surface of the insulating substrate opposite to the third surface, and is connected to the source of the first transistor and the third conductor. A fifth conductor is disposed on the fourth surface of the insulating substrate and is connected to the source of the second transistor and the third conductor; A sixth conductor is disposed on the fourth surface of the insulating substrate and is connected to the gate of the first transistor and the second conductor; as well as A seventh conductor is disposed on the fourth surface of the insulating substrate and is connected to the gate of the second transistor and the first wiring layer.

2. The semiconductor device according to claim 1, characterized in that, The third conductor is arranged parallel to the first wiring layer.

3. The semiconductor device according to claim 1, characterized in that, The first signal applied to the third conductor is out of phase with the second signal applied to the first wiring layer.

4. The semiconductor device according to claim 1, characterized in that, The first transistor and the second transistor are disposed between the first conductor and the insulating substrate.

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