Impedance detection circuit and link contact state detection method

Abstract

The application discloses an impedance detection circuit and a link contact state detection method, and relates to the technical field of server fault diagnosis. The impedance detection circuit comprises a switching circuit, an amplification circuit, a comparison circuit and a logic operation circuit. The input end of the switching circuit is connected with a target sending line and a target receiving line of a differential transceiving channel, the output end of the switching circuit is connected with the input end of the amplification circuit, the output end of the amplification circuit is connected with the input end of the comparison circuit, and the output end of the comparison circuit is connected with the input end of the logic operation circuit. The impedance detection circuit can be used for on-line detection of the link contact state, and even a slight link contact abnormality can be detected.

Description

Technical Field

[0001] This invention relates to the field of server fault diagnosis technology, and in particular to an impedance detection circuit and a method for detecting link contact status. Background Technology

[0002] Abnormal contact in PICe (Peripheral Component Interconnect Express) links (including poor slot contact, gold finger oxidation, bending, and plating cracking) can lead to signal reflection, level jitter, and CRC (Cyclic Redundancy Check) errors. Therefore, detecting the contact status of PICe links is crucial. However, related technologies are not sensitive to minute contact anomalies and perform offline detection, failing to provide online detection and early warning. Therefore, addressing these technical shortcomings has become a pressing technical problem for those skilled in the art. Summary of the Invention

[0003] This invention provides an impedance detection circuit and a link contact status detection method to at least solve the problems in related technologies that are insensitive to minute contact anomalies and cannot achieve online detection and early warning.

[0004] This invention provides an impedance detection circuit, comprising:

[0005] The system includes a switching circuit, an amplifier circuit, a comparator circuit, and a logic operation circuit. The input terminal of the switching circuit is connected to the target transmit line and the target receive line of the differential transceiver channel. The output terminal of the switching circuit is connected to the input terminal of the amplifier circuit. The output terminal of the amplifier circuit is connected to the input terminal of the comparator circuit. The output terminal of the comparator circuit is connected to the input terminal of the logic operation circuit.

[0006] The switching circuit is used to simultaneously connect the target transmitting line and the target receiving line to the output terminal of the switching circuit when the switching circuit is enabled, so as to synchronously input the signals transmitted by the target transmitting line and the target receiving line into the amplifier circuit.

[0007] The amplifier circuit is used to amplify the signals transmitted by the target transmitting line and the target receiving line, respectively.

[0008] The comparison circuit is used to compare the signal transmitted by the target transmitting line after amplification with the signal transmitted by the target receiving line after amplification.

[0009] The logic operation circuit is used to perform logical operations on the output result of the comparison circuit and output a first level signal or a second level signal; the first level signal indicates that the impedance of the transmitting circuit where the target transmitting line is located or the receiving circuit where the target receiving line is located is abnormal, and the second level signal indicates that the impedance of the transmitting circuit and the receiving circuit are both normal.

[0010] This invention also provides a link contact status detection method applied to a host, wherein the target transmitting line and target receiving line of the differential transceiver channel between the host and the device are connected to the impedance detection circuit described above; the link contact status detection method includes:

[0011] A first control signal is output to the impedance detection circuit to enable the switching circuit in the impedance detection circuit;

[0012] A first signal sequence is sent to the device; wherein, the device simultaneously sends a second signal sequence to the host; the first signal sequence is the same as the second signal sequence;

[0013] Detect the signal output from the output terminal of the impedance detection circuit;

[0014] If the signal output by the impedance detection circuit is a first-level signal, then the differential transceiver channel link is abnormally contacted.

[0015] If the signal output by the impedance detection circuit is a second-level signal, then the differential transceiver channel link is in normal contact.

[0016] The present invention also provides a link contact status detection device, applied to a host, wherein the target transmitting line and target receiving line of the differential transceiver channel between the host and the device are connected to the impedance detection circuit described above; the link contact status detection device includes:

[0017] The output module is used to output a first control signal to the impedance detection circuit to enable the switching circuit in the impedance detection circuit.

[0018] A transmitting module is configured to transmit a first signal sequence to the device; wherein the device synchronously transmits a second signal sequence to the host; the first signal sequence is the same as the second signal sequence;

[0019] The detection module is used to detect the signal output from the output terminal of the impedance detection circuit;

[0020] The first determining module is used to determine if the signal output by the impedance detection circuit is a first level signal, then the differential transceiver channel link is abnormally contacted.

[0021] The second determining module is used to determine if the signal output by the impedance detection circuit is a second level signal, in which case the differential transceiver channel link is in normal contact.

[0022] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described link contact state detection methods.

[0023] The present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described link contact state detection methods.

[0024] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described link contact state detection methods.

[0025] The beneficial effects of the impedance detection circuit are as follows: The impedance detection circuit provided by this invention can detect the impedance of the differential loop, and thus determine the link contact status based on the impedance of the differential loop. Even minor link contact anomalies can be detected. Furthermore, the impedance detection circuit provided by this invention can detect the link contact status online. In addition, the impedance detection circuit provided by this invention can identify contact degradation trends in advance, before link faults cause PCIe devices to experience speed reduction or bandwidth reduction. Using the impedance detection circuit provided by this invention for link contact status detection can distinguish between genuine contact problems and temporary signal interference, reducing false alarms.

[0026] The beneficial effects of the link contact status detection method are as follows: The link contact status detection method provided by this invention achieves efficient detection of link contact status through a combination of software and hardware. Using an impedance detection circuit, the impedance of the differential circuit can be detected, and the link contact status can be determined based on the impedance of the differential circuit, even detecting minute link contact anomalies. Furthermore, the link contact status detection method provided by this invention can identify contact degradation trends in advance, before link faults cause PCIe devices to experience speed reduction or bandwidth reduction. The link contact status detection method provided by this invention can distinguish between genuine contact problems and temporary signal interference, reducing false alarms. Attached Figure Description

[0027] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of an impedance detection circuit provided in an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram illustrating the connection relationship between a server motherboard and a PCIe device, provided in an embodiment of the present invention.

[0030] Figure 3 A schematic diagram of a specific impedance detection circuit provided in an embodiment of the present invention;

[0031] Figure 4 A flowchart illustrating a link contact state detection method provided in an embodiment of the present invention;

[0032] Figure 5 This is a flowchart illustrating a specific link contact status detection method provided in an embodiment of the present invention. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0034] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0035] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] This invention provides an impedance detection circuit, reference Figure 1 As shown, an impedance detection circuit provided in this embodiment of the invention includes:

[0037] The circuit includes a switching circuit 10, an amplifier circuit 20, a comparator circuit 30, and a logic operation circuit 40. The input of the switching circuit 10 is connected to the target transmit line and the target receive line of the differential transceiver channel. The output of the switching circuit 10 is connected to the input of the amplifier circuit 20. The output of the amplifier circuit 20 is connected to the input of the comparator circuit 30. The output of the comparator circuit 30 is connected to the input of the logic operation circuit 40.

[0038] The switching circuit 10 is used to connect the target transmitting line and the target receiving line synchronously to the output terminal of the switching circuit when the switching circuit 10 is enabled, so that the signals transmitted by the target transmitting line and the target receiving line are synchronously input into the amplifier circuit 20.

[0039] Amplifier circuit 20 is used to amplify the signals transmitted on the target transmitting line and the target receiving line, respectively.

[0040] Comparison circuit 30 is used to compare the signal transmitted by the target transmitting line after amplification with the signal transmitted by the target receiving line after amplification.

[0041] The logic operation circuit 40 is used to perform logical operations on the output result of the comparison circuit 30 and output a first level signal or a second level signal. The first level signal indicates that the impedance of the transmitting circuit where the target transmitting line is located or the receiving circuit where the target receiving line is located is abnormal, and the second level signal indicates that the impedance of both the transmitting circuit and the receiving circuit is normal.

[0042] A differential transceiver channel is also known as a PCIe lane. One PCIe lane consists of two pairs of differential signals, totaling four signal lines. (Reference) Figure 2 As shown, the four signal lines are HSOp (positive transmit line), HSOn (negative transmit line), HSIp (positive receive line), and HSIn (negative receive line). HSOp and HSOn form a differential circuit (hereinafter referred to as the transmit circuit) for outputting data. HSIp and HSIn form another differential circuit (hereinafter referred to as the receive circuit) for inputting data. Each pair of differential signals transmits data through a potential difference, achieving full-duplex communication.

[0043] Multiple PCIe lanes can be combined into wider channels (e.g., x1, x4, x16, etc.), with bandwidth increasing linearly with the number of PCIe lanes. For example, x1: 1 PCIe lane (4 lines); x16: 16 PCIe lanes (64 lines).

[0044] Figure 2C1, C2, C3, and C4 are coupling capacitors. The ground of the PCIe device is connected to the ground of the server motherboard. In the impedance design of PCIe high-speed circuits (the impedance of the signal line relative to the copper reference ground plane of the motherboard can be roughly characterized as capacitive reactance, as if there is a virtual capacitor between each differential signal line and GND. This capacitor creates a certain resistance to the transmission of the signal line, which is the impedance. The smaller the impedance, the steeper the rise and fall edges of the signal; the larger the impedance, the flatter the rise and fall edges of the signal, which affects the size of the digital signal eye diagram), the impedance of each differential loop needs to conform to the PCIe specification definition, for example, 85 ohms. When the signal impedance design of each differential loop is highly consistent, the rise and fall edges of the high-speed signals in each differential loop will be consistent. If the overall loop impedance changes due to abnormal contact in a certain differential loop (usually the impedance decreases), then the signal of this differential loop will be steeper than the signals of other differential loops, that is, the rise and fall times of the signal will be shorter.

[0045] Based on this, embodiments of the present invention provide an impedance detection circuit that detects the impedance of two differential loops in the same PCIe Lane. If any one of the two differential loops has an impedance anomaly, it indicates an abnormal PCIe Lane link connection.

[0046] like Figure 2 As shown, the impedance detection circuit can be integrated onto the server motherboard. The impedance detection circuit mainly includes a switching circuit 10, an amplifier circuit 20, a comparator circuit 30, and a logic operation circuit 40.

[0047] The connection relationship between the switching circuit 10, the amplifier circuit 20, the comparator circuit 30, and the logic operation circuit 40 is as follows: the input terminal of the switching circuit 10 is connected to the target transmit line and the target receive line of a differential transceiver channel; the output terminal of the switching circuit 10 is connected to the input terminal of the amplifier circuit 20; the output terminal of the amplifier circuit 20 is connected to the input terminal of the comparator circuit 30; and the output terminal of the comparator circuit 30 is connected to the input terminal of the logic operation circuit 40.

[0048] The target transmitting line can be either a positive or negative transmitting line. The target receiving line can be either a positive or negative receiving line.

[0049] When the switching circuit 10 is enabled, the target transmitting line and the target receiving line are simultaneously connected to the output terminal of the switching circuit 10, so that the signals transmitted by the target transmitting line and the target receiving line are synchronously input into the amplification circuit 20. The amplification circuit 20 amplifies the signals transmitted by the target transmitting line and the target receiving line respectively. The comparator circuit 30 compares the amplified signal transmitted by the target transmitting line with the amplified signal transmitted by the target receiving line. If the difference between the amplified signal transmitted by the target transmitting line and the amplified signal transmitted by the target receiving line is less than the monitoring threshold voltage, the comparator circuit 30 outputs a low level. When there is no signal input impedance detection circuit, the comparator circuit 30 outputs a low level. If the difference between the amplified signal transmitted by the target transmitting line and the amplified signal transmitted by the target receiving line is greater than the monitoring threshold voltage, the comparator circuit 30 outputs a high level. The logic operation circuit 40 performs a logic operation on the output result of the comparator circuit 30 and outputs a first level signal or a second level signal; the first level signal indicates an impedance abnormality in the transmitting circuit or the receiving circuit where the target transmitting line is located, and the second level signal indicates that the impedances of both the transmitting circuit and the receiving circuit are normal. If the logic operation circuit 40 outputs a first-level signal, it is considered that the PCIe Lane link connection is abnormal. If the logic operation circuit 40 outputs a second-level signal, it is considered that the PCIe Lane link connection is normal.

[0050] In some embodiments, the switching circuit 10 includes:

[0051] A first single-pole double-throw (SPD) switch circuit and a second SPD switch circuit; the common terminal of the first SPD switch circuit is connected to the target transmitting line, and the normally open port of the first SPD switch circuit is connected to the amplifier circuit 20; the common terminal of the second SPD switch circuit is connected to the target receiving line, and the normally open port of the second SPD switch circuit is connected to the amplifier circuit 20; the control input terminals of the first SPD switch circuit and the second SPD switch circuit receive the same control signal; when the control signal is the first control signal, the first SPD switch circuit and the second SPD switch circuit are enabled.

[0052] Taking HSOp as the target transmit line and HSIp as the target receive line as an example, refer to... Figure 3 As shown, Figure 3 In the diagram, SPDT1 represents the first single-pole double-throw switch circuit, and SPDT2 represents the second single-pole double-throw switch circuit. Figure 3 In the middle, Z-Test represents the control signal.

[0053] The common terminal of the first single-pole double-throw (SPDT) switch circuit is connected to HSOp, and the common terminal of the second SPDT switch circuit is connected to HSIp. Control signals are input to the control input terminals of both the first and second SPDT switch circuits. When the control signal is the first control signal (high level), both the first and second SPDT switch circuits are enabled simultaneously. HSOp is connected to the normally open port of the first SPDT switch circuit, and HSIp is connected to the normally open port of the second SPDT switch circuit.

[0054] In some embodiments, the amplifier circuit 20 includes:

[0055] A first amplifier circuit and a second amplifier circuit; the first input terminal of the first amplifier circuit is connected to the normally open port of the first single-pole double-throw switch circuit, the second input terminal of the first amplifier circuit is grounded, and the output terminal of the first amplifier circuit is connected to the input terminal of the comparator circuit 30; the first input terminal of the second amplifier circuit is connected to the normally open port of the second single-pole double-throw switch circuit, the second input terminal of the second amplifier circuit is grounded, and the output terminal of the second amplifier circuit is connected to the input terminal of the comparator circuit 30.

[0056] The first amplifier circuit amplifies the signal transmitted on the target transmitting line, output from the first single-pole double-throw switch circuit. The second amplifier circuit amplifies the signal transmitted on the target receiving line, output from the second single-pole double-throw switch circuit.

[0057] For example, the target transmitting line is HSOp, and the signal transmitted by HSOp is called the HSOp signal. The target receiving line is HSIp, and the signal transmitted by HSIp is called the HSIp signal. The first amplifier circuit is used to amplify the HSOp signal. The second amplifier circuit is used to amplify the HSIp signal.

[0058] In some embodiments, the first amplifier circuit includes:

[0059] The circuit comprises a first coupling capacitor, a first resistor, a second resistor, and a first operational amplifier; the first end of the first coupling capacitor serves as the first input terminal of the first amplifier circuit, the second end of the first coupling capacitor is connected to the first end of the first resistor, the second end of the first resistor is connected to the positive input terminal of the first operational amplifier and the first end of the second resistor, the negative input terminal of the first operational amplifier serves as the second input terminal of the first amplifier circuit, the output terminal of the first operational amplifier serves as the output terminal of the first amplifier circuit, and the second end of the second resistor is connected to the output terminal of the first operational amplifier.

[0060] refer to Figure 3 As shown, Figure 3 In the diagram, C1 represents the first coupling capacitor, R1 represents the first resistor, R2 represents the second resistor, and U1 represents the first operational amplifier.

[0061] The first coupling capacitor C1 couples the signal transmitted through the target transmission line to the first amplifier circuit. The first amplifier circuit amplifies the signal transmitted through the target transmission line.

[0062] In some embodiments, the second amplifier circuit includes:

[0063] The circuit consists of a second coupling capacitor, a third resistor, a fourth resistor, and a second operational amplifier. The first end of the second coupling capacitor serves as the first input terminal of the second amplifier circuit. The second end of the second coupling capacitor is connected to the first end of the third resistor. The second end of the third resistor is connected to the positive input terminal of the second operational amplifier and the first end of the fourth resistor. The negative input terminal of the second operational amplifier serves as the second input terminal of the second amplifier circuit. The output terminal of the second operational amplifier serves as the output terminal of the second amplifier circuit. The second end of the fourth resistor is connected to the output terminal of the second operational amplifier.

[0064] refer to Figure 3 As shown, Figure 3 In the diagram, C2 represents the second coupling capacitor, R3 represents the third resistor, R4 represents the fourth resistor, and U2 represents the second operational amplifier.

[0065] The second coupling capacitor C2 couples the signal transmitted through the target receiving line to the second amplifier circuit. The second amplifier circuit amplifies the signal transmitted through the target transmitting line.

[0066] In some embodiments, the comparison circuit 30 includes:

[0067] A first comparator circuit and a second comparator circuit; the first input terminal of the first comparator circuit is connected to the output terminal of the first amplifier circuit, the second input terminal of the first comparator circuit is connected to the output terminal of the second amplifier circuit, and the output terminal of the first comparator circuit is connected to the input terminal of the logic operation circuit 40; the first input terminal of the second comparator circuit is connected to the output terminal of the second amplifier circuit, the second input terminal of the second comparator circuit is connected to the output terminal of the first amplifier circuit, and the output terminal of the second comparator circuit is connected to the input terminal of the logic operation circuit 40.

[0068] The first comparator circuit is configured to output a first level when the difference between the signal output by the first amplifier circuit and the signal output by the second amplifier circuit is greater than the monitoring threshold voltage; and to output a second level when the difference between the signal output by the first amplifier circuit and the signal output by the second amplifier circuit is less than the monitoring threshold voltage.

[0069] The second comparator circuit is used to output a first level when the difference between the signal output by the second amplifier circuit and the signal output by the first amplifier circuit is greater than the monitoring threshold voltage; and to output a second level when the difference between the signal output by the second amplifier circuit and the signal output by the first amplifier circuit is less than the monitoring threshold voltage.

[0070] The first comparator circuit compares the signals output by the first amplifier circuit and the second amplifier circuit. When the difference between the signals output by the first amplifier circuit and the second amplifier circuit is greater than the monitoring threshold voltage, it outputs a first level; when the difference between the signals output by the first amplifier circuit and the second amplifier circuit is less than the monitoring threshold voltage, it outputs a second level.

[0071] The second comparator circuit compares the signals output by the first amplifier circuit and the second amplifier circuit. When the difference between the signal output by the second amplifier circuit and the signal output by the first amplifier circuit is greater than the monitoring threshold voltage, it outputs a first level; when the difference between the signal output by the second amplifier circuit and the signal output by the first amplifier circuit is less than the monitoring threshold voltage, it outputs a second level.

[0072] The first level is high. The second level is low.

[0073] In some embodiments, the first comparison circuit includes:

[0074] The system comprises a third operational amplifier, a first bias voltage supply circuit, a third coupling capacitor, and a fourth coupling capacitor. The first terminal of the third coupling capacitor serves as the first input terminal of the first comparator circuit, and the second terminal of the third coupling capacitor is connected to the positive input terminal of the third operational amplifier. The first terminal of the fourth coupling capacitor serves as the second input terminal of the first comparator circuit, and the second terminal of the fourth coupling capacitor is connected to the negative input terminal of the third operational amplifier. The output terminal of the third operational amplifier serves as the output terminal of the first comparator circuit. The first bias voltage supply circuit is connected to both the positive and negative input terminals of the third operational amplifier.

[0075] The first bias voltage supply circuit is used to output a first voltage to the positive input terminal of the third operational amplifier and output a second voltage to the negative input terminal of the third operational amplifier; the first voltage is less than the second voltage.

[0076] refer to Figure 3 As shown, Figure 3 In the diagram, C3 represents the third coupling capacitor, C4 represents the fourth coupling capacitor, and U3 represents the third operational amplifier. For example... Figure 3 As shown, the circuit providing the first bias voltage may include resistors R7, R8, R9, and R0. Resistors R7, R8, R9, and R0 are high-resistance circuits, with resistance values ​​in the megaohm range. Resistor R7 is connected in series with resistor R8. Resistor R9 is connected in series with resistor R0. Figure 3 In the diagram, P-Ml represents the first voltage and P-Mh represents the second voltage.

[0077] The weak voltage P-Mh is slightly higher than P-Ml.

[0078] like Figure 3As shown, when the HSOp and HSIp signals are not input to the impedance detection circuit, or when the difference between the amplified HSOp and HSIp signals (amplified HSOp signal - amplified HSIp signal) is less than the detection threshold voltage (e.g., 0.1V), the output of the third operational amplifier remains low. When the difference between the amplified HSOp and HSIp signals (amplified HSOp signal - amplified HSIp signal) is greater than the detection threshold voltage (e.g., 0.1V), the output of the third operational amplifier is high.

[0079] In some embodiments, the second comparison circuit includes:

[0080] The system includes a fourth operational amplifier, a second bias voltage supply circuit, a fifth coupling capacitor, and a sixth coupling capacitor. The first terminal of the fifth coupling capacitor serves as the first input terminal of the second comparator circuit, and the second terminal of the fifth coupling capacitor is connected to the positive input terminal of the fourth operational amplifier. The first terminal of the sixth coupling capacitor serves as the second input terminal of the second comparator circuit, and the second terminal of the sixth coupling capacitor is connected to the negative input terminal of the fourth operational amplifier. The output terminal of the fourth operational amplifier serves as the output terminal of the second comparator circuit. The second bias voltage supply circuit is connected to both the positive and negative input terminals of the fourth operational amplifier.

[0081] The second bias voltage supply circuit is used to output a third voltage to the positive input terminal of the fourth operational amplifier and output a fourth voltage to the negative input terminal of the fourth operational amplifier; the third voltage is less than the fourth voltage.

[0082] refer to Figure 3 As shown, Figure 3 In the diagram, C5 represents the fifth coupling capacitor, C6 represents the sixth coupling capacitor, and U4 represents the fourth operational amplifier. For example... Figure 3 As shown, the second bias voltage providing circuit may include resistors R10, R11, R12, and R13. Resistors R10, R11, R12, and R13 are high-resistance circuits, with resistance values ​​in the megaohm range. Resistor R10 is connected in series with resistor R1. Resistor R12 is connected in series with resistor R13. Figure 3 In the diagram, N-Ml represents the third voltage and N-Mh represents the fourth voltage.

[0083] The weak voltage N-Mh is slightly higher than N-Ml.

[0084] like Figure 3As shown, when the HSOp and HSIp signals are not input to the impedance detection circuit, or when the difference between the amplified HSOp and HSIp signals (amplified HSIp signal - amplified HSOp signal) is less than the detection threshold voltage (e.g., 0.1V), the output of the fourth operational amplifier remains low. When the difference between the amplified HSOp and HSIp signals (amplified HSIp signal - amplified HSOp signal) is greater than the detection threshold voltage (e.g., 0.1V), the output of the fourth operational amplifier is high.

[0085] In some embodiments, the logic operation circuit 40 includes:

[0086] OR gate; the first input of the OR gate is connected to the output of the first comparator circuit, and the second input of the OR gate is connected to the output of the second comparator circuit.

[0087] refer to Figure 3 As shown, Figure 3 U5 represents an OR gate. When either the first or second comparator circuit outputs a high level, the OR gate's output signal Z-abnormal is high, indicating that the difference between the HSIp and HSOp signals is greater than the monitoring threshold voltage. This means that the signal changes in the two differential circuits are different, i.e., the differential circuit impedance has changed, and a link contact anomaly has occurred.

[0088] It should be noted that the prerequisite for detecting whether the impedance of the differential circuit has changed through the impedance detection circuit is that both differential circuits of the PCIe Lane are transmitting the same signal simultaneously.

[0089] In summary, the impedance detection circuit provided by this invention can detect the impedance of the differential circuit, and thus determine the link contact status based on the impedance of the differential circuit. Even minor link contact anomalies can be detected. Furthermore, the impedance detection circuit provided by this invention can identify contact degradation trends in advance, before link faults cause PCIe devices to experience speed reduction or bandwidth reduction. Using the impedance detection circuit provided by this invention for link contact status detection can distinguish between genuine contact problems and temporary signal interference, reducing false alarms.

[0090] The present invention provides a link contact status detection method. The method is described in detail below in conjunction with the execution flow of the link contact status detection method.

[0091] refer to Figure 4 As shown, an embodiment of the present invention provides a link contact status detection method including:

[0092] S101: Output the first control signal to the impedance detection circuit to enable the switching circuit in the impedance detection circuit;

[0093] S102: Send a first signal sequence to the device; wherein, the device synchronously sends a second signal sequence to the host; the first signal sequence and the second signal sequence are the same;

[0094] S103: The signal output from the impedance detection circuit output terminal;

[0095] S104: If the signal output by the impedance detection circuit is a first-level signal, then the differential transceiver channel link is abnormally connected.

[0096] S105: If the signal output by the impedance detection circuit is a second-level signal, then the differential transceiver channel link is in normal contact.

[0097] The link contact status detection method provided in this embodiment of the invention is executed by a server (HOST). An impedance detection circuit is connected to the target transmit line and target receive line of the differential transceiver channel between the host and the PCIe device. The impedance detection circuit includes a switching circuit, an amplifier circuit, a comparator circuit, and a logic operation circuit. The input of the switching circuit is connected to the target transmit line and the target receive line of the differential transceiver channel. The output of the switching circuit is connected to the input of the amplifier circuit, the output of the amplifier circuit is connected to the input of the comparator circuit, and the output of the comparator circuit is connected to the input of the logic operation circuit. The switching circuit, when enabled, connects the target transmit line to its output and the target receive line to its output. The amplifier circuit amplifies the signals transmitted on the target transmit line and the target receive line, respectively. The comparator circuit compares the amplified signal transmitted on the target transmit line with the amplified signal transmitted on the target receive line. The logic operation circuit performs logical operations on the output of the comparator circuit, outputting a first-level signal or a second-level signal. The first-level signal indicates that the impedance of both the transmit and receive circuits is normal, and the second-level signal indicates that the impedance of either the transmit or receive circuit is abnormal.

[0098] During the server BIOS boot process, after the PCIe device initialization is complete, the host outputs a first control signal to the impedance detection circuit to enable the switching circuit within it. When the switching circuit is enabled, the target transmit line is connected to the output terminal of the switching circuit, and the target receive line is also connected to the output terminal of the switching circuit. The host and the PCIe device simultaneously send the same signal sequence to each other. The signal sequence sent by the host to the PCIe device is called the first signal sequence; the signal sequence sent by the PCIe device to the host is called the second signal sequence. The host detects the signal output from the impedance detection circuit. If the signal output from the impedance detection circuit is a first-level signal, the differential transceiver channel link connection is abnormal. If the signal output from the impedance detection circuit is a second-level signal, the differential transceiver channel link connection is normal. The first-level signal is high. The second-level signal is low.

[0099] In some embodiments, the first signal sequence and the second signal sequence include a 2-bit synchronization header and 128 bits of data; the 128 bits of data are arranged with 0s and 1s alternating.

[0100] The design incorporates a PCIe device signal synchronization and mutual transmission protocol initiated by the server host. During the server BIOS boot phase, the server host initiates the protocol to ensure that the server host and PCIe devices send the specified data precisely and simultaneously (clock aligned) on all PCIe lanes: 16 consecutive 0x55s (each 0x55 is binary 01010101, totaling 128 bits), using 128b / 130b encoding for transmission.

[0101] The protocol is based on the following:

[0102] Physical layer requirements:

[0103] PCIe Gen3 and above (supports 128b / 130b encoding).

[0104] The link has completed training and entered the L0 state.

[0105] All PCIe Lane clock phase alignment (achievable via a flexible buffer).

[0106] Synchronize with the reference clock (RefClk).

[0107] Data format:

[0108] Original data: 16 0x55s (128 bits: 01010101 × 16).

[0109] 128b / 130b encoding format:

[0110] Synchronization header: 01 (indicates a data block).

[0111] A 128-bit data block: holds 16 0x55s.

[0112] Complete transmission unit: 130 bits = 2 bits of synchronization header + 128 bits of data.

[0113] The first and second signal sequences each consist of a 2-bit synchronization header and 128 bits of data, perfectly compatible with 128b / 130b encoding. The synchronization header 01 identifies the standard data block, and 16 0x55 characters fill the 128-bit data block, with no wasted padding, conforming to the PCIe Gen3+ specification.

[0114] In some embodiments, it also includes:

[0115] Before sending the first signal sequence to the device, a first ordered set is sent to the device so that the device sends a second ordered set to the host and determines the time to send the second signal sequence based on the response end time;

[0116] Record the end time of transmission;

[0117] The transmission time of the first signal sequence is determined based on the transmission end time, so that the first signal sequence can be transmitted to the device at the transmission time.

[0118] Before the host and device send a signal sequence, they send an ordered set of signals to each other. The host records the end time of transmission and determines when to send its own signal sequence based on this end time. The device records the end time of its response and determines when to send its own signal sequence based on this end time. This ensures that the host and device send signal sequences simultaneously.

[0119] In some embodiments, sending the first ordered set to the device includes:

[0120] The device sends a first ordered set to the host a preset number of times, so that the device sends a second ordered set to the host a preset number of times.

[0121] Repeatedly sending ordered sets between the host and the device can compensate for command transmission jitter and reduce errors.

[0122] The preset number of attempts can be 4.

[0123] The protocol process may include:

[0124] Phase 1: Link preparation (standard PCIe process).

[0125] Complete the PCIe link training (LTSSM state machine).

[0126] Entering L0 state ensures reference clock synchronization, phase alignment of clocks in each PCIe Lane, and stable channel availability.

[0127] Phase 2: The server host sends a synchronization command:

[0128] The server HOST uses a custom ordered set to send commands.

[0129] The command format is: SYNC_CMD = 0x55A5.

[0130] Sending method: The server host sends four identical ordered sets consecutively. The ordered set sent by the server host is called the first ordered set.

[0131] After sending four identical ordered sets, record the end time of sending, T_cmd_end (a UI counter based on RefClk).

[0132] A PCIe device detects three consecutive first ordered sets and considers them valid.

[0133] The PCIe device replies with an ordered set of acknowledgments: ACK = 0x5AA5 (a bit reversal of SYNC_CMD). The ordered set sent by the PCIe device is called the second ordered set.

[0134] The PCIe device sends four consecutive ACKs.

[0135] After sending four ACKs, the PCIe device records the response end time T_ack_end.

[0136] The server host determines the transmission time of the first signal sequence based on the transmission end time, so as to send the first signal sequence to the device at the transmission end time. The PCIe device determines the time to send the second signal sequence based on the response end time.

[0137] In some embodiments, determining the transmission time of the first signal sequence based on the transmission end time includes:

[0138] The transmission time of the first signal sequence is the sum of the transmission end time and the predefined delay parameter; the predefined delay parameter is equal to the sum of the maximum device processing delay, the time required for the first ordered set of transmissions of a preset number, and the time margin.

[0139] Predefined delay parameter T_total:

[0140] T_total = T_proc + T_ordered_set + T_offset = 2816UI.

[0141] in:

[0142] T_proc (maximum device processing latency) = 512 UI.

[0143] T_ordered_set (time required to transfer the first ordered set a preset number of times) = 4 first ordered sets × 16 bytes × 20 UI / byte = 1280 UI.

[0144] T_offset (time margin) = 1024 UI.

[0145] The server HOST was sent at Tcmd_end + 2816UI.

[0146] In some embodiments, the time at which the device sends the second signal sequence is equal to the sum of the response end time and the time margin.

[0147] The PCIe device's transmission time is Tack_end + 1024UI.

[0148] Synchronous timing calculations are performed in phase 3 of the protocol process.

[0149] Predefined delay parameter T_total:

[0150] T_total = T_proc + T_ordered_set + T_offset = 2816UI.

[0151] in:

[0152] T_proc (maximum device processing latency) = 512 UI.

[0153] T_ordered_set (time required to transfer the first ordered set a preset number of times) = 4 first ordered sets × 16 bytes × 20 UI / byte = 1280 UI.

[0154] T_offset (time margin) = 1024 UI.

[0155] Sending time calculation:

[0156] The server HOST was sent at Tcmd_end + 2816UI.

[0157] The PCIe device's transmission time is: Tack_end + 1024UI.

[0158] Time alignment verification:

[0159] (T_ack_end - T_cmd_end) + 1024UI = (T_proc + T_ordered_set) + 1024UI= 512+1280+1024 = 2816UI.

[0160] Data is sent in phase 4 of the protocol process.

[0161] Packet construction:

[0162] 128-bit data: 16 0x55s (01010101 × 16).

[0163] Synchronization header: 01.

[0164] The complete 130-bit sequence is: 01 + [128 bits alternating between 0 and 1].

[0165] Physical layer operations:

[0166] At the calculated transmission time, the server host and the PCIe device simultaneously initiate transmission.

[0167] All PCIe lanes transmit the same 130-bit signal sequence in parallel.

[0168] The transmission time is: 130 bits × 20 UI / bit = 2600 UI.

[0169] After sending is complete, the system will revert to standard transmission mode.

[0170] In the above text, UI (Unit Interval) is the basic time unit in high-speed digital communication, representing the length of a single symbol period, and its value is equal to the reciprocal of the signal transmission rate.

[0171] For example, if the PCIe Gen3 rate is 8.0 GT / s, then UI = 1 / 8e9 = 125 picoseconds (ps).

[0172] In clock offset measurement, 0.1UI represents an accuracy of 12.5ps (in the Gen3 scenario).

[0173] In some embodiments, it also includes:

[0174] If a link connection anomaly is detected, the location of the differential transceiver channel where the link contact anomaly occurred is recorded in the system log.

[0175] If a link connection anomaly is detected, the location of the differential transceiver channel where the link contact anomaly occurred is recorded in the system log so that relevant personnel can locate the differential transceiver channel where the link contact anomaly occurred.

[0176] The pseudocode for implementing BIOS can be as follows:

[0177] / / Constant definition

[0178] #define SYNC_CMD 0x55A5

[0179] #define ACK_CMD 0x5AA5

[0180] #define ORDERED_SET_SIZE 16 / / bytes

[0181] #define DATA_PATTERN 0x55

[0182] #define DATA_REPEAT 16

[0183] / / BIOS PCIe Synchronization Protocol Main Function

[0184] void pcie_sync_protocol() {

[0185] uint8_t retry_count = 0;

[0186] / / Waiting for the PCIe link to enter L0 state

[0187] while (pcie_link_status() != PCIE_LINK_STATE_L0) {

[0188] delay_us(1);

[0189] }

[0190] sync_retry:

[0191] / / Send synchronization command (4 custom ordered sets)

[0192] for (int i = 0; i < 4; i++) {

[0193] send_custom_ordered_set(SYNC_CMD);

[0194] }

[0195] uint64_t cmd_end_time = get_refclk_count();

[0196] / / Waiting for ACK response (512 UI timeout)

[0197] if (wait_for_ack(ACK_CMD, 512) != SUCCESS) {

[0198] if (++retry_count < 3) {

[0199] delay_ui(256); / / Retry after 256 UI seconds

[0200] goto sync_retry;

[0201] }

[0202] PCIE_LOG("Sync failed after 3 retries");

[0203] trigger_link_retrain();

[0204] return;

[0205] }

[0206] uint64_t ack_end_time = get_ack_receive_time();

[0207] / / Calculate the precise synchronization time

[0208] uint64_t sync_time = cmd_end_time + 2816;

[0209] uint64_t device_delay = calculate_device_delay(cmd_end_time, ack_end_time);

[0210] / / Waiting until synchronization time

[0211] while (get_refclk_count() < sync_time - device_delay) {

[0212] / / Precise wait (hardware-level counting)

[0213] }

[0214] / / Prepare a 128-bit data block (16 0x55s)

[0215] uint8_t data_block

[16] ;

[0216] for (int i = 0; i < 16; i++) {

[0217] data_block[i] = DATA_PATTERN;

[0218] }

[0219] / / All lanes simultaneously send 130 bits of data

[0220] pcie_send_130b_block(data_block);

[0221] / / Verify the data returned by the device

[0222] if (verify_received_data(DATA_PATTERN, DATA_REPEAT) != SUCCESS) {

[0223] PCIE_LOG("Data verification failed");

[0224] trigger_diagnostic_mode();

[0225] }

[0226] }

[0227] / / 130b data block send function

[0228] void pcie_send_130b_block(uint8_t data

[16] ) {

[0229] / / Configure the physical layer to send in precise time mode

[0230] pcie_phy_prepare_sync_tx();

[0231] / / Send synchronization header 01

[0232] pcie_send_sync_header(0x1); / / 0x1 represents a 0 / 1 synchronization header

[0233] / / Send 128 bits of data (16 bytes)

[0234] for (int i = 0; i < 16; i++) {

[0235] pcie_send_symbol(data[i]);

[0236] }

[0237] / / Restore standard transmission mode

[0238] pcie_phy_restore_standard_tx();

[0239] }

[0240] / / Device delay calculation function

[0241] uint64_t calculate_device_delay(uint64_t cmd_end, uint64_t ack_end) {

[0242] uint64_t measured_delay = ack_end - cmd_end;

[0243] uint64_t expected_delay = 512 + 1280; / / T_proc + T_ordered_set

[0244] / / Calculate latency differences (not exceeding ±128 UI)

[0245] if (measured_delay > expected_delay + 128) {

[0246] return 128;

[0247] } else if (measured_delay < expected_delay - 128) {

[0248] return 0;

[0249] }

[0250] return measured_delay - expected_delay;

[0251] }

[0252] The physical layer timing analysis can be found in Table 1.

[0253] Table 1 Physical Layer Timing Analysis Table

[0254]

[0255] The synchronization accuracy analysis can be found in Table 2.

[0256] Table 2 Synchronization Accuracy Analysis Table

[0257]

[0258] The protocol provided in this invention achieves precise synchronous data transmission across multiple lanes on a standard PCIe Gen3+ link, with errors controlled within ±46 UI (approximately 230ps@8GHz), meeting the signal integrity verification requirements at the BIOS stage. The protocol design balances standardization, reliability, and accuracy, and can be implemented on existing PCIe devices without hardware modifications. The UI values ​​of the residual errors shown in the table above can be used as a reference for designing monitoring threshold voltages to ensure that the phase error between the software protocol layer and the transport layer is tolerable by the detection circuit, preventing false alarms.

[0259] Referring to Table 3, a specific implementation method is described below.

[0260] Table 3 GPIO Pin List

[0261]

[0262] Impedance detection circuits are configured in units of x4 bandwidth (typically, a PCIe link anomaly causing bandwidth reduction is caused by a degradation from x16 to x8, and from x8 to x4, so the monitoring granularity of the PCIe lane is configured as x4).

[0263] Combination Figure 5 As shown, during the server BIOS startup process, after the PCIe device initialization is completed, a set of GPIO pins (P11~P18) are used to send a high level to the switching circuit in each x4 impedance detection circuit, enabling the switching circuit, which in turn enables the impedance detection circuit.

[0264] The BIOS sends a SYNC_CMD message to all PCIe devices, synchronously exchanging 16 0x55 data values ​​with the PCIe devices. Another set of GPIO pins (P21~P28) is used to synchronously read the Z-abnormal level of each x4 impedance sensing circuit.

[0265] If any Z-abnormal signal goes high, the lane location of the link abnormality is sent to the BMC.

[0266] BMC records the location of the faulty link in the server management page SEL.

[0267] Use (P11~P18) to send a low level to each x4 impedance detection circuit to turn off the impedance detection circuit.

[0268] The link contact status detection method provided in this invention performs link contact status detection at power-on, only after hardware assembly is complete. Any changes to PCIe link hardware, Slimline signal lines, Riser cards, or PCIe device cards will trigger link contact status detection at power-on, avoiding random signal interference introduced during real-time operation. This method can accurately locate the faulty lanes in PCIe device connections. It can identify faulty lanes during the power-on self-test phase, reducing server failure rates, minimizing PCIe device warranty coverage, and lowering maintenance manpower costs.

[0269] In summary, the link contact status detection method provided by this invention achieves efficient detection of link contact status through a combination of software and hardware. By employing an impedance detection circuit, the impedance of the differential circuit can be detected, and the link contact status can be determined based on the impedance of the differential circuit, even detecting minute link contact anomalies. Furthermore, the link contact status detection method provided by this invention can identify contact degradation trends in advance, before link faults cause PCIe devices to experience speed reduction or bandwidth reduction. The link contact status detection method provided by this invention can distinguish between genuine contact problems and temporary signal interference, reducing false alarms.

[0270] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0271] Embodiments of the present invention also provide a link contact status detection device, applied to a host, wherein the target transmit line and target receive line of the differential transceiver channel between the host and the device are connected to the impedance detection circuit of the above embodiment; the link contact status detection device includes:

[0272] The output module is used to output a first control signal to the impedance detection circuit to enable the switching circuit in the impedance detection circuit.

[0273] The transmitting module is used to send a first signal sequence to the device; wherein, the device synchronously sends a second signal sequence to the host; the first signal sequence and the second signal sequence are the same.

[0274] The detection module is used to detect the signal output from the impedance detection circuit.

[0275] The first determining module is used to determine if the signal output by the impedance detection circuit is a first level signal, indicating an abnormal contact in the differential transceiver channel link.

[0276] The second determining module is used to determine whether the differential transceiver channel link is in normal contact if the signal output by the impedance detection circuit is the second level signal.

[0277] Based on the above embodiments, as a specific implementation method, it further includes:

[0278] The second sending module is used to send a first ordered set to the device before sending the first signal sequence to the device, so that the device sends a second ordered set to the host and determines the time to send the second signal sequence according to the response end time;

[0279] The recording module is used to record the end time of transmission;

[0280] The third determining module is used to determine the transmission time of the first signal sequence based on the transmission end time, so as to send the first signal sequence to the device at the transmission time.

[0281] Based on the above embodiments, as a specific implementation method, the second sending module is used for:

[0282] The device sends a first ordered set to the host a preset number of times, so that the device sends a second ordered set to the host a preset number of times.

[0283] Based on the above embodiments, as a specific implementation method, the third determining module is used for:

[0284] The transmission time of the first signal sequence is the sum of the transmission end time and the predefined delay parameter; the predefined delay parameter is equal to the sum of the maximum device processing delay, the time required for the first ordered set of transmissions of a preset number, and the time margin.

[0285] Based on the above embodiments, as a specific implementation method, the time when the device sends the second signal sequence is equal to the sum of the response end time and the time margin.

[0286] Based on the above embodiments, as a specific implementation method, it further includes:

[0287] The second recording module is used to record the differential transceiver channel that experienced the link contact anomaly in the system log if a link connection anomaly is detected.

[0288] Based on the above embodiments, as a specific implementation method, the first signal sequence and the second signal sequence include a 2-bit synchronization header and 128 bits of data; the 128 bits of data are arranged with 0 and 1 alternately.

[0289] For a description of the features in the embodiment corresponding to the link contact state detection device, please refer to the relevant description of the embodiment corresponding to the link contact state detection method, which will not be repeated here.

[0290] Embodiments of the present invention also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described embodiments of the link contact state detection method.

[0291] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program configured to execute the steps in any of the above-described embodiments of the link contact state detection method when running.

[0292] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0293] Embodiments of the present invention also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described embodiments of the link contact state detection method.

[0294] Embodiments of the present invention also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described embodiments of the link contact state detection method.

[0295] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0296] The impedance detection circuit and link contact status detection method provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only intended to help understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. An impedance detection circuit, characterized in that, Used to detect the contact status of PICe links, including: The system includes a switching circuit, an amplifier circuit, a comparator circuit, and a logic operation circuit. The input terminal of the switching circuit is connected to the target transmit line and the target receive line of the differential transceiver channel. The output terminal of the switching circuit is connected to the input terminal of the amplifier circuit. The output terminal of the amplifier circuit is connected to the input terminal of the comparator circuit. The output terminal of the comparator circuit is connected to the input terminal of the logic operation circuit. The switching circuit is used to simultaneously connect the target transmitting line and the target receiving line to the output terminal of the switching circuit when the switching circuit is enabled, so as to synchronously input the signals transmitted by the target transmitting line and the target receiving line into the amplifier circuit. The amplifier circuit is used to amplify the signals transmitted by the target transmitting line and the target receiving line, respectively. The comparison circuit includes a first comparison circuit and a second comparison circuit. The first comparison circuit is configured to output a first level when the difference between the signal transmitted by the amplified target transmitting line and the signal transmitted by the amplified target receiving line is greater than a monitoring threshold voltage, and output a second level when the difference is less than the monitoring threshold voltage. The second comparison circuit is configured to output a first level when the difference between the signal transmitted by the amplified target receiving line and the signal transmitted by the amplified target transmitting line is greater than a monitoring threshold voltage, and output a second level when the difference is less than the monitoring threshold voltage. The logic operation circuit is used to perform logical operations on the output result of the comparison circuit and output a first level signal or a second level signal; the first level signal indicates that the impedance of the transmitting circuit where the target transmitting line is located or the receiving circuit where the target receiving line is located is abnormal, and the PCIe link contact is abnormal; the second level signal indicates that the impedance of both the transmitting circuit and the receiving circuit is normal, and the PCIe link contact is normal. The switching circuit includes: a first single-pole double-throw (SPD) switch circuit and a second SPD switch circuit; the common terminal of the first SPD switch circuit is connected to the target transmitting line, and the normally open port of the first SPD switch circuit is connected to the amplifier circuit; the common terminal of the second SPD switch circuit is connected to the target receiving line, and the normally open port of the second SPD switch circuit is connected to the amplifier circuit; the control input terminals of the first SPD switch circuit and the second SPD switch circuit receive the same control signal; when the control signal is a first control signal, the first SPD switch circuit and the second SPD switch circuit are enabled; The amplifier circuit includes: a first amplifier circuit and a second amplifier circuit; the first input terminal of the first amplifier circuit is connected to the normally open port of the first single-pole double-throw switch circuit, the second input terminal of the first amplifier circuit is grounded, and the output terminal of the first amplifier circuit is connected to the input terminal of the comparator circuit; the first input terminal of the second amplifier circuit is connected to the normally open port of the second single-pole double-throw switch circuit, the second input terminal of the second amplifier circuit is grounded, and the output terminal of the second amplifier circuit is connected to the input terminal of the comparator circuit. The first input terminal of the first comparator circuit is connected to the output terminal of the first amplifier circuit, the second input terminal of the first comparator circuit is connected to the output terminal of the second amplifier circuit, and the output terminal of the first comparator circuit is connected to the input terminal of the logic operation circuit; the first input terminal of the second comparator circuit is connected to the output terminal of the second amplifier circuit, the second input terminal of the second comparator circuit is connected to the output terminal of the first amplifier circuit, and the output terminal of the second comparator circuit is connected to the input terminal of the logic operation circuit.

2. The impedance detection circuit according to claim 1, characterized in that, The first amplifier circuit includes: The circuit comprises a first coupling capacitor, a first resistor, a second resistor, and a first operational amplifier; the first end of the first coupling capacitor serves as the first input terminal of the first amplifier circuit, the second end of the first coupling capacitor is connected to the first end of the first resistor, the second end of the first resistor is connected to the positive input terminal of the first operational amplifier and the first end of the second resistor, the negative input terminal of the first operational amplifier serves as the second input terminal of the first amplifier circuit, the output terminal of the first operational amplifier serves as the output terminal of the first amplifier circuit, and the second end of the second resistor is connected to the output terminal of the first operational amplifier.

3. The impedance detection circuit according to claim 1, characterized in that, The second amplifier circuit includes: The circuit comprises a second coupling capacitor, a third resistor, a fourth resistor, and a second operational amplifier; the first end of the second coupling capacitor serves as the first input terminal of the second amplifier circuit, the second end of the second coupling capacitor is connected to the first end of the third resistor, the second end of the third resistor is connected to the positive input terminal of the second operational amplifier and the first end of the fourth resistor, the negative input terminal of the second operational amplifier serves as the second input terminal of the second amplifier circuit, the output terminal of the second operational amplifier serves as the output terminal of the second amplifier circuit, and the second end of the fourth resistor is connected to the output terminal of the second operational amplifier.

4. The impedance detection circuit according to claim 1, characterized in that, The first comparator circuit includes: The system comprises a third operational amplifier, a first bias voltage supply circuit, a third coupling capacitor, and a fourth coupling capacitor. The first terminal of the third coupling capacitor serves as the first input terminal of the first comparator circuit, the second terminal of the third coupling capacitor is connected to the positive input terminal of the third operational amplifier, the first terminal of the fourth coupling capacitor serves as the second input terminal of the first comparator circuit, the second terminal of the fourth coupling capacitor is connected to the negative input terminal of the third operational amplifier, and the output terminal of the third operational amplifier serves as the output terminal of the first comparator circuit. The first bias voltage supply circuit is connected to both the positive and negative input terminals of the third operational amplifier. The first bias voltage providing circuit is used to output a first voltage to the positive input terminal of the third operational amplifier and output a second voltage to the negative input terminal of the third operational amplifier; the first voltage is less than the second voltage.

5. The impedance detection circuit according to claim 1, characterized in that, The second comparator circuit includes: The system comprises a fourth operational amplifier, a second bias voltage supply circuit, a fifth coupling capacitor, and a sixth coupling capacitor. The first terminal of the fifth coupling capacitor serves as the first input terminal of the second comparator circuit, and the second terminal of the fifth coupling capacitor is connected to the positive input terminal of the fourth operational amplifier. The first terminal of the sixth coupling capacitor serves as the second input terminal of the second comparator circuit, and the second terminal of the sixth coupling capacitor is connected to the negative input terminal of the fourth operational amplifier. The output terminal of the fourth operational amplifier serves as the output terminal of the second comparator circuit. The second bias voltage supply circuit is connected to both the positive and negative input terminals of the fourth operational amplifier. The second bias voltage providing circuit is used to output a third voltage to the positive input terminal of the fourth operational amplifier and to output a fourth voltage to the negative input terminal of the fourth operational amplifier; the third voltage is less than the fourth voltage.

6. The impedance detection circuit according to claim 1, characterized in that, The logic operation circuit includes: An OR gate; the first input of the OR gate is connected to the output of the first comparison circuit, and the second input of the OR gate is connected to the output of the second comparison circuit.

7. A method for detecting the contact status of a link, characterized in that, Applied to a host, the target transmit line and target receive line of the differential transceiver channel between the host and the device are connected to the impedance detection circuit as described in claim 1; Link contact status detection methods include: A first control signal is output to the impedance detection circuit to enable the switching circuit in the impedance detection circuit; A first signal sequence is sent to the device; wherein, the device simultaneously sends a second signal sequence to the host; the first signal sequence is the same as the second signal sequence; Detect the signal output from the output terminal of the impedance detection circuit; If the signal output by the impedance detection circuit is a first-level signal, then the differential transceiver channel link is abnormally contacted. If the signal output by the impedance detection circuit is a second-level signal, then the differential transceiver channel link is in normal contact.

8. The link contact status detection method according to claim 7, characterized in that, Also includes: Before sending the first signal sequence to the device, a first ordered set is sent to the device so that the device sends a second ordered set to the host and determines the time to send the second signal sequence based on the response end time; Record the end time of transmission; The transmission time of the first signal sequence is determined based on the transmission end time, so that the first signal sequence is transmitted to the device at the transmission time.

9. The link contact status detection method according to claim 8, characterized in that, Sending the first ordered set to the device includes: The device sends the first ordered set to the host a preset number of times, so that the device sends the second ordered set to the host a preset number of times.

10. The link contact status detection method according to claim 9, characterized in that, Determining the transmission time of the first signal sequence based on the transmission end time includes: The transmission end time and the predefined delay parameter are taken as the transmission time of the first signal sequence; the predefined delay parameter is equal to the sum of the maximum device processing delay, the time required for the first ordered set of transmission preset times, and the time margin.

11. The link contact status detection method according to claim 10, characterized in that, The time at which the device sends the second signal sequence is equal to the sum of the response end time and the time margin.

12. The link contact state detection method according to claim 7, characterized in that, Also includes: If a link connection anomaly is detected, the differential transceiver channel where the link contact anomaly occurred will be recorded in the system log.

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