Method and device for testing circuit based on test coverage rate optimization

Abstract

A method and apparatus for testing a circuit based on test coverage optimization are provided. The method includes: converting design data representing circuit components and circuit nodes of a circuit to be tested into graph data; generating a test coverage of the design data and influence data representing an influence of a circuit node for the test coverage based on graph data input into a graph neural network (GNN) model; a test point for test point insertion (TPI) is selected from the circuit nodes based on the impact data.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0063373, filed with the Korean Intellectual Property Office on May 14, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to methods and apparatus for testing circuits, and more particularly, to methods and apparatus for testing circuits based on test coverage optimization. Background Technology

[0004] In circuit testing technology, Design for Testability (DFT) refers to a design that is easy to test. For example, DFT can refer to design techniques used to more easily test electronic circuits or systems. DFT techniques can include, but are not limited to, scan chain, built-in self-test (BIST), or boundary scan. DFT of circuits or systems can help effectively identify and diagnose defects during the manufacturing process. Furthermore, DFT can play a significant role in improving product reliability, reducing manufacturing costs, and shortening time-to-market. Therefore, considering a DFT strategy from the initial stages of circuit design can be beneficial. Summary of the Invention

[0005] One or more embodiments may at least solve the above-described problems and / or disadvantages, as well as other disadvantages not described above. Furthermore, embodiments do not need to overcome the above-described disadvantages, and embodiments may not overcome any of the above-described problems.

[0006] According to one aspect of this disclosure, a method performed by an electronic device is provided, the method comprising: converting design data representing a plurality of circuit components and a plurality of circuit nodes of a circuit to be tested into graph data; generating test coverage data and impact data representing the influence of the plurality of circuit nodes based on the graph data input to a graph neural network (GNN) model; and selecting one or more test points from the plurality of circuit nodes for test point insertion (TPI) based on the impact data.

[0007] According to one aspect of this disclosure, a non-transitory computer-readable storage medium is provided that stores instructions which, when executed by a processor, cause the processor to perform a method comprising the steps of: converting design data representing a plurality of circuit components and a plurality of circuit nodes of a circuit to be tested into graph data; generating test coverage data and impact data representing the influence of the plurality of circuit nodes based on the graph data input to a graph neural network (GNN) model; and selecting one or more test points from the plurality of circuit nodes for test point insertion (TPI) based on the impact data.

[0008] According to one aspect of this disclosure, an electronic device is provided, comprising: a memory configured to store instructions; and one or more processors configured to execute the instructions to cause the electronic device to: convert design data representing a plurality of circuit components and a plurality of circuit nodes of a circuit to be tested into graph data; generate test coverage data and impact data representing the influence of the plurality of circuit nodes based on the graph data input to a graph neural network (GNN) model; and select one or more test points from the plurality of circuit nodes for test point insertion (TPI) based on the impact data. Attached Figure Description

[0009] The above and / or other aspects will become more apparent from the description of specific embodiments in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a diagram illustrating an example of a circuit to be tested according to an embodiment;

[0011] Figure 2A This is a diagram illustrating an example of Test Point Insertion (TPI) according to relevant technologies;

[0012] Figure 2B This is a diagram illustrating an example of Test Point Insertion (TPI) according to an embodiment;

[0013] Figure 3 This is a diagram illustrating an example of the data format conversion and test coverage prediction process according to an embodiment;

[0014] Figures 4A to 4C This is a diagram illustrating an example of data format conversion according to an embodiment;

[0015] Figure 5 This is a diagram illustrating an additional example of data format conversion according to an embodiment;

[0016] Figure 6 This is a diagram illustrating an example of the structure of a graph neural network (GNN) model according to an embodiment;

[0017] Figure 7 This is a diagram illustrating an example of impact data according to an embodiment;

[0018] Figure 8 This is a diagram illustrating an example of the training process of a GNN model according to an embodiment;

[0019] Figure 9 This is a flowchart illustrating an example of a circuit testing method based on test coverage optimization according to an embodiment; and

[0020] Figure 10 This is a diagram illustrating an example configuration of an electronic device according to an embodiment. Detailed Implementation

[0021] The detailed structural or functional descriptions below are provided only as examples, and various changes and modifications can be made to the embodiments. Accordingly, the embodiments should not be construed as being limited to this disclosure, but should be understood to include all changes, equivalents, and substitutions within the spirit and technical scope of this disclosure.

[0022] Although terms such as first and second are used to describe various components, these components are not limited to these terms. These terms should only be used to distinguish one component from another. For example, the first component may be referred to as the second component, or similarly, the second component may be referred to as the first component.

[0023] It should be noted that if a component is described as being “connected,” “coupled,” or “joined” to another component, a third component may be “connected,” “coupled,” or “joined” between the first and second components, although the first component may also be directly connected, coupled, or joined to the second component.

[0024] The singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context explicitly indicates otherwise. It will also be understood that the terms “comprising / containing” and / or “including / including” as used herein indicate the presence of the stated feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0025] As used in this article, each of "at least one of A and B", "at least one of A, B or C", etc., can include any one of the items listed together in the corresponding phrase, or all possible combinations thereof.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having a meaning that matches the contextual meaning in the relevant field, and shall not be interpreted as having an ideal or overly formal meaning, unless otherwise defined herein.

[0027] In the following description, embodiments will be illustrated with reference to the accompanying drawings. When describing embodiments with reference to the accompanying drawings, the same reference numerals refer to the same elements, and repeated descriptions related to them will be omitted.

[0028] Figure 1 This is a diagram illustrating an example of a circuit to be tested according to an embodiment. (Reference) Figure 1 The circuit 100 to be tested may include circuit component C and circuit node N. Figure 1The circuit 100 shown is for ease of description, but this disclosure is not limited thereto. Therefore, according to another embodiment, the number of circuit components and the number of circuit nodes are not limited to... Figure 1 The diagram is shown below. Furthermore, this disclosure is not limited to the arrangement of circuit components and circuit nodes. Circuit node N may differ from the diagram node described below.

[0029] According to an embodiment, the design data for circuit 100 can represent circuit component C and circuit node N. Circuit 100 and design data can have equivalent relationships. For example, the design data can include, but is not limited to, netlists. For example, circuit node N can be identified by a net name in the netlist. However, this disclosure is not limited to this, and therefore, circuit component C and circuit node N can be identified in other ways. For example, the design data can include other types of data to represent the relationship between circuit component C and circuit node N.

[0030] According to embodiments, circuit component C may include, but is not limited to, one or more components of register transfer level (RTL), one or more components of gate level, or a combination of RTL components and gate level components. For example, circuit component C may include, but is not limited to, logic gates, such as AND gates, OR gates, NOT gates, NAND gates, NOR gates, XOR gates, and XNOR gates.

[0031] According to an embodiment, defects in circuit 100 can be inspected through a testing process. During the testing process, various test modes can be used to evaluate whether circuit 100 meets functional requirements and performance targets. Test results can include test coverage as a result item. However, uncontrollable inputs / outputs (I / O) and / or unobservable I / O of circuit 100 may reduce test coverage. Uncontrollable I / O can refer to input or output signals that may not be controllable when using external testing equipment during the testing process. Unobservable I / O can refer to input or output signals that may not be observable when using external testing equipment during the testing process.

[0032] Design for Testability (DFT) refers to a design that is easy to test, and can refer to design techniques used to more easily test electronic circuits or systems. For example, Test Point Insertion (TPI) technology can be used in DFT. According to TPI technology, one or more test points can be selected from multiple circuit nodes N, and additional circuitry can be used to control or observe the signals at those test points. TPI technology can improve test coverage. However, due to the additional circuitry in TPI technology, design overhead may increase. High design overhead may reduce production efficiency. According to an embodiment, test points can be derived based on test coverage optimization using a Graph Neural Network (GNN) model.

[0033] Figure 2A This is a diagram illustrating an example of Test Point Insertion (TPI) according to relevant techniques, and Figure 2B This is a diagram illustrating an example of a TPI according to an embodiment. Reference Figure 2A In the related technical design 201, the circuit (e.g., Figure 1 The input signal i0 of part of circuit 210 of circuit 100 may be an uncontrollable input signal, and the output signal o0 may be an unobservable output signal.

[0034] refer to Figure 2B In design 202 according to an embodiment, a first test point tp1 and a second test point tp2 can be added. For example, the first test point tp1 and the second test point tp2 can be added to part of circuit 210 to measure the signals of the first test point tp1 and the second test point tp2. For example, the signals of the first test point tp1 and the second test point tp2 can be measured using a first scan flip-flop 221, a second scan flip-flop 223, and a multiplexer 222. For example, the first scan flip-flop 221, the second scan flip-flop 223, and the multiplexer 222 can correspond to additional circuitry for TPI. In design 202, the input signal i0 can be a controllable input signal, and the output signal o0 can be an observable output signal.

[0035] The first scan trigger 221 and the second scan trigger 223 can receive a data signal D, a scan input signal SI, a clock signal CLK, and a scan enable signal SE, and can output an output signal Q. According to an embodiment, the first scan trigger 221 can receive the data signal D, the scan input signal SI, the clock signal CLK, and the scan enable signal SE, and output the output signal Q to the multiplexer 222. The multiplexer 222 can output the input signal i0 or the output signal Q of the first scan trigger 221 based on the test mode control signal TM. For example, the multiplexer 222 can output the input signal i0 or the output signal Q of the first scan trigger 221 to the first test point tp1. According to an embodiment, the second scan trigger 223 can receive the data signal D, the scan input signal SI, the clock signal CLK, and the scan enable signal SE, and output the output signal Q. For example, the data signal D can be the output at the second test point tp2. According to an embodiment, the output signal of the second scan trigger 223 can represent the scan result. The first scan trigger 221 and the second scan trigger 223 can output data signal D or scan input signal SI based on the scan enable signal SE.

[0036] Figure 3 This is a diagram illustrating an example of the data format conversion and test coverage prediction process according to an embodiment. (Reference) Figure 3In the data format conversion stage 310, design data 311 can be converted into graph data 312. For example, design data 311 can be converted into graph data 312 having the format used in GNN model 321. However, this disclosure is not limited to this, and therefore, design data 311 can be converted into different formats. Design data 311 may represent circuit components and circuit nodes of the circuit to be tested.

[0037] For example, graph data 312 may include, but is not limited to, a graph node matrix and an edge matrix. The graph node matrix may represent the characteristics of circuit components, and the edge matrix may represent circuit nodes. For example, the characteristics of a circuit component may include, but are not limited to, component type, fan-in count, fan-out count, logic depth, masking information, or a combination thereof. At the gate level, component type may refer to the gate type. Fan-in count may refer to the number of inputs to each circuit component. Fan-out count may refer to the number of outputs to each circuit component. Logic depth may refer to the number of circuit components or circuit nodes present between the input nodes and output nodes of the circuit. According to an embodiment, when calculating the logic depth, feedback loops in the circuit may be temporarily removed. Masking information may indicate whether each circuit component is constrained or unconstrained.

[0038] According to an embodiment, in the test coverage prediction phase 320, test coverage 322 of design data 311 and impact data 323 representing the influence on each circuit node of test coverage 322 can be generated based on graph data 312. For example, graph data 312 can be used to generate test coverage 322 and impact data 323 by executing a GNN model 321.

[0039] Design data 311 may include test point candidates. For example, test point candidates may include one or more circuit nodes. For example, all circuit nodes of design data 311 may be test point candidates. However, this disclosure is not limited thereto, and therefore, according to embodiments, one or more circuit nodes of design data 311 may be test point candidates. Test point candidates of design data 311 can be used to predict test coverage 322.

[0040] GNN model 321 can generate a saliency map corresponding to the prediction of test coverage 322. The saliency map can represent the influence of each circuit node in the graph data 312 on the formation of test coverage 322. The saliency map can be generated in various ways. For example, gradient-based methods and / or perturbation-based methods can be used to generate the saliency map. However, this disclosure is not limited thereto, and therefore, according to other embodiments, other types of methods can be used to generate the saliency map. For example, masking information among the features of the graph nodes can be used to generate the saliency map. Influence data 323 can be generated from the saliency map.

[0041] According to an embodiment, test points for TPI can be selected from circuit nodes based on influence data 323. For example, test points can be selected according to the order of influence from the circuit nodes. For example, a first test point with a first influence level from the first circuit node can be selected before a second test point with a second influence level from the first circuit node. Here, the second influence level may be lower than the first influence level. For example, test points can be assigned a priority for selection based on the influence level from the circuit nodes. For example, test points can be selected according to priority order. For example, this order may be from higher priority to lower priority. However, this disclosure is not limited to this, and therefore, test points can be selected based on different criteria. Each circuit node can be a test point candidate. Influence data 323 can represent the influence of each circuit node. Circuit nodes can be sorted according to the influence of each circuit node, and the circuit nodes in the top group can be selected as test points for TPI.

[0042] Figures 4A-4C This is a diagram illustrating an example of data format conversion according to an embodiment. Figure 4A A first visual representation 410 is shown, representing circuit components 411-1, 411-2, 411-3, 411-4 and 411-5 and circuit nodes 412-1, 412-2, 412-3 and 412-4. Figure 4B A second visual representation 420 is shown, representing graph nodes 421-1, 421-2, 421-3, 421-4, and 421-5 corresponding to circuit components 411-1, 411-2, 411-3, 411-4, and 411-5, and graph edges 422-1, 422-2, 422-3, and 422-4 corresponding to circuit nodes 412-1, 412-2, 412-3, and 412-4. Figure 4C A third visual representation 430 is shown, in which component features such as component features 431-1, 431-2, 431-3, 431-4, and 431-5 are added to a second visual representation 420. A first visual representation 410 may represent design data, and a third visual representation 430 may represent graph data.

[0043] Figure 5 This is a diagram illustrating an additional example of data format conversion according to an embodiment. (Reference) Figure 5A simplified format design data 520 corresponding to the simplified format circuit 510 can be used. Original circuit components of the original format design data can be converted into replacement components of the simplified format design data 520. For example, the replacement components may have less diversity than the original circuit components. For example, in the simplified format design data 520, the replacement components may be limited to a specific type of component. For example, the type of replacement component can be predetermined. For example, the type of replacement component may be limited to AND gates, inverters, and latches. However, this disclosure is not limited to this, and therefore, a specific type of component may include other types of components. The type of original component is not limited. According to embodiments, the simplified format design data 520 can be used instead of the original format design data. For example, original circuit components can be converted into replacement components, and graph data 530 can be generated based on the replacement components. When using the simplified format design data 520, computational complexity can be reduced.

[0044] Graph data 530 may include a graph node matrix 531 and an edge matrix 532. The graph node matrix 531 may represent the characteristics of circuit components. For example, characteristics may include component type, fan-in number, fan-out number, logic depth, masking information, or a combination thereof.

[0045] Figure 6 This is a diagram illustrating an example of the structure of a GNN model according to an embodiment. (Reference) Figure 6 The GNN model 600 may include a first layer group 610 containing one or more graph convolutional layers 611, a second layer group 620 containing one or more pooling layers 621, and a third layer group 630 containing one or more multilayer perceptron (MLP) layers 631. Figure 6 The structure of the GNN model 600 shown is an example, and the GNN model 600 can have the same structure as... Figure 6 Different structures.

[0046] The GNN model 600 can receive graph data 601 as input, process the graph data 601 using first layer group 610 to third layer group 630, and generate test coverage 602 and influence data 603. Test coverage 602 can be referred to as test coverage data 602. Activation functions can be placed between one or more graph convolutional layers 611 of the first layer group 610. When executing one or more graph convolutional layers 611, features of all graph nodes can be normalized in mini-batch. The dimensionality of the output of the first layer group 610 can be reduced by one or more pooling layers 621. For example, the dimensionality can be reduced from the number of nodes multiplied by the number of features to 1 multiplied by the number of features. One or more MLP layers 631 can include activation functions.

[0047] Figure 7This is a diagram illustrating an example of impact data according to an embodiment. (Reference) Figure 7 Influence data 710 can represent the influence of each circuit node 711. Influence data 710 can be represented by sorting the circuit nodes 711 according to their influence. Test points TP for TPI can be selected from the circuit nodes 711 based on influence data 710. For example, one or more circuit nodes 711 can be selected as test points according to the order of influence from the circuit nodes 711. For example, circuit nodes 711 with higher influence levels can be selected first. For example, based on... Figure 7 As shown, circuit node i0 can be selected before circuit node i5. Figure 7 The format shown in the image is illustrative and not limited to this. For example, the impact data 710 can be represented as... Figure 7 Different types of diagrams or other forms besides this diagram.

[0048] Figure 8 This is a diagram illustrating an example of the training process of a GNN model according to an embodiment. (Reference) Figure 8 The GNN model 810 can be trained using sample design data 801 and the ground truth (GT) 820 as training data. The sample design data 801 can be converted into sample graph data 802. The GNN model 810 can then be executed using the sample graph data 802. Accordingly, the GNN model 810 can generate test coverage 812 and influence data 813. The GNN model 810 can be trained based on the difference between the test coverage 812 and the GT 820. The model parameters of the GNN model 810 can be updated through training.

[0049] The sample design data 801 can have random test points. GT 820 can be the actual test coverage measured for the random test points of the sample design data 801. That is, the GNN model 810 can be trained based on the sample design data 801 and the actual test coverage of the sample design data 801.

[0050] A GNN model 810 can be trained using large-scale training data. Various augmentation techniques can be used to obtain large-scale training data. For example, the design data for the training can be divided into hierarchical sub-blocks, and large-scale training data can be generated using the sub-blocks and their test coverage.

[0051] The GNN model 810 can be pre-trained before inference. The GNN model 810 can then be used for inference after training. For example, Figure 3 The GNN model 321 can correspond to Figure 8 The trained version of the GNN model 810 is now complete.

[0052] Figure 9This is a flowchart illustrating an example of a circuit testing method based on test coverage optimization according to an embodiment.

[0053] refer to Figure 9 In operation 910, the method may include converting design data of the circuit under test into graph data. For example, an electronic device may convert design data representing circuit components and / or circuit nodes of the circuit under test into graph data. For example, the design data may be converted into graph data having a format used in a GNN model.

[0054] According to an embodiment, the design data may include, but is not limited to, netlists. According to an embodiment, circuit nodes can be identified by netnames in the netlist.

[0055] According to embodiments, circuit components may include, but are not limited to, RTL components, gate-level components, or combinations thereof.

[0056] According to an embodiment, graph data may include a graph node matrix representing features of circuit components and an edge matrix representing circuit nodes.

[0057] According to embodiments, the features of a circuit component may include, but are not limited to, component type, number of fan-in, number of fan-out, logic depth, masking information, or a combination thereof.

[0058] According to an embodiment, the GNN model can generate a saliency plot illustrating the prediction of test coverage, and influence data can be generated from the saliency plot.

[0059] According to an embodiment, a GNN model can be trained based on sample design data and the actual test coverage of the sample design data.

[0060] According to an embodiment, a GNN model may include a first layer group containing one or more graph convolutional layers, a second layer group containing one or more pooling layers, and a third layer group containing one or more MLP layers.

[0061] In operation 920, the method may include generating test coverage data and impact data based on graph data. For example, an electronic device may use graph data to generate test coverage data for design data and impact data representing the effect on each circuit node for test coverage by executing a GNN model.

[0062] In operation 930, the method may include selecting test points based on influence data. For example, an electronic device may select test points for test point insertion (TPI) from multiple circuit nodes based on influence data.

[0063] According to an embodiment, in operation 930, the method may include: selecting test points in order of influence from circuit nodes.

[0064] According to an embodiment, in operation 910, the method may include: converting a circuit component into a replacement component that has less diversity than the circuit component, and generating graph data based on the replacement component.

[0065] According to an embodiment, the method may further include: testing the circuit based on selected test points.

[0066] Figure 10 This is a diagram illustrating an example configuration of an electronic device using a test coverage-based optimized circuit testing method according to an embodiment. (Reference) Figure 10 The electronic device 1000 may include one or more processors 1010, memory 1020, storage device 1030, input / output (I / O) device 1040, and network interface 1050. According to an embodiment, the one or more processors 1010, memory 1020, storage device 1030, I / O device 1040, and network interface 1050 may communicate with each other via a communication bus 1060. For example, the electronic device 1000 may be implemented as at least a part of a computing device such as a desktop computer or server.

[0067] One or more processors 1010 can execute instructions stored in memory 1020 or storage device 1030. When executed by one or more processors 1010, the instructions can cause electronic device 1000 to perform the above-mentioned... Figures 1 to 9 The described operations. Memory 1020 may include a non-transitory computer-readable storage medium or a non-transitory computer-readable storage device. Memory 1020 may store instructions executed by one or more processors 1010, and may store related information when the electronic device 1000 executes software and / or applications. According to an embodiment, memory 1020 may store a GNN model 1021. According to an embodiment, at least a portion of the GNN model 1021 may be stored in memory 1020, and referenced above... Figures 1 to 9 The described operation can be performed by electronic device 1000.

[0068] Storage device 1030 may include a non-transitory computer-readable storage medium or a non-transitory computer-readable storage device. Storage device 1030 may store a larger amount of information than memory 1020 and may store the information for a longer period of time. For example, storage device 1030 may include a magnetic hard disk, optical disk, flash memory, floppy disk, or other non-volatile memory known in the art.

[0069] I / O device 1040 can receive input from a user via input methods, including but not limited to keyboard, mouse, touch input (e.g., touchscreen), voice input (e.g., microphone), image input (e.g., image sensor or camera), or other devices that can detect input from the user and transmit the detected input to electronic device 1000. I / O device 1040 can provide output from electronic device 1000 to the user via a visual channel, auditory channel, or tactile channel. I / O device 1040 may include, for example, a display, touchscreen, speaker, vibration generator, or any other device that provides output to the user. Network interface 1050 can communicate with external devices via wired or wireless networks.

[0070] The embodiments described herein can be implemented using hardware components, software components, and / or combinations thereof. A processing device (e.g., one or more processors 1010) can be implemented using one or more general-purpose or special-purpose computers (e.g., processors, controllers, and arithmetic logic units (ALUs), DSPs, microcomputers, FPGAs, programmable logic units (PLUs), microprocessors, or any other device capable of responding to and executing instructions in a defined manner). The processing device can run an OS and one or more software applications running on the OS. The processing device can also access, store, manipulate, process, and create data in response to the execution of software. For simplicity, the description of the processing device is used as the singular; however, those skilled in the art will understand that a processing device can include multiple processing elements and / or various types of processing elements. For example, a processing device can include multiple processors, or a single processor and a single controller. Additionally, different processing configurations (e.g., parallel processors) are also possible.

[0071] Software can include computer programs, code segments, instructions, or some combination thereof, to independently or uniformly instruct or configure a processing device to operate on demand. Software and data can be stored in any type of machine, component, physical or virtual device, or computer storage medium or device capable of providing instructions or data to or being interpreted by the processing device. Software can also be distributed across network-coupled computer systems, enabling the software to be stored and executed in a distributed manner. Software and data can be stored on one or more non-transitory computer-readable recording media.

[0072] The methods according to the above embodiments can be recorded in a non-transitory computer-readable medium including program instructions to implement the various operations of the above embodiments. The medium may also include data files, data structures, etc., alone or in combination with program instructions. The program instructions recorded on the medium may be specifically designed and constructed for the purposes of the embodiments, or they may be program instructions well known and usable by those skilled in the art of computer software. Examples of non-transitory computer-readable media include: magnetic media, such as hard disks, floppy disks, and magnetic tapes; optical media, such as CD-ROMs and / or DVDs; magneto-optical media, such as optical discs; and hardware devices specifically configured to store and execute program instructions, such as read-only memory (ROM), random access memory (RAM), flash memory, etc. Examples of program instructions include machine code (e.g., generated by a compiler), and files containing high-level code that can be executed by a computer using an interpreter.

[0073] The aforementioned hardware device can be configured to act as one or more software modules to perform the operations of the above embodiments, and vice versa.

[0074] As described above, although embodiments have been described with reference to the limited accompanying drawings, those skilled in the art can apply various technical modifications and variations thereon. For example, suitable results can be achieved if the described techniques are performed in a different order, and / or if components in the described system, architecture, device, or circuit are combined in a different manner or replaced or supplemented with other components or their equivalents.

[0075] Therefore, other implementations are within the scope of the appended claims.

Claims

1. A method performed by an electronic device, the method comprising: The design data representing multiple circuit components and multiple circuit nodes of the circuit to be tested is converted into graph data; Based on the graph data input to the graph neural network (GNN) model, test coverage data and impact data representing the influence of the multiple circuit nodes are generated. as well as Based on the impact data, one or more test points are selected from the plurality of circuit nodes for test point insertion.

2. The method according to claim 1, wherein, The graph data includes a graph node matrix representing the features of the plurality of circuit components, and an edge matrix representing the plurality of circuit nodes.

3. The method according to claim 2, wherein, The characteristics of the plurality of circuit components include component type, number of fan-in, number of fan-out, logic depth, masking information, or a combination thereof.

4. The method according to claim 1, wherein The GNN model is configured to generate a saliency map corresponding to the predictions of the test coverage data, and The impact data is generated based on the saliency map.

5. The method according to claim 1, wherein, Selecting the one or more test points includes selecting the one or more test points based on the order of influence from the plurality of circuit nodes.

6. The method of claim 1, wherein converting the design data into the drawing data comprises: The plurality of circuit components are converted into a plurality of replacement components that have less diversity compared to the plurality of circuit components; as well as The graph data is generated based on the multiple replacement components.

7. The method according to claim 1, wherein The design data is a netlist, and The plurality of circuit nodes are identified by their net names in the netlist.

8. The method according to claim 1, wherein, The GNN model is trained based on the sample design data and the actual test coverage of the sample design data.

9. The method according to claim 1, wherein, The GNN model includes: The first layer group consists of one or more graph convolutional layers; The second layer group includes one or more pooling layers; and The third layer group includes one or more multi-layer perceptron layers.

10. The method according to claim 1, wherein, The plurality of circuit components include register transfer level components, gate level components, or combinations thereof.

11. A non-transitory computer-readable storage medium storing instructions, which, when executed by a processor, cause the processor to perform a method comprising the steps of: The design data representing multiple circuit components and multiple circuit nodes of the circuit to be tested is converted into graph data; Based on the graph data input to the graph neural network (GNN) model, test coverage data and impact data representing the influence of the multiple circuit nodes are generated; and Based on the impact data, one or more test points are selected from the plurality of circuit nodes for test point insertion.

12. An electronic device, comprising: The memory is configured to store instructions; as well as One or more processors are configured to execute the instructions to cause the electronic device to: The design data representing multiple circuit components and multiple circuit nodes of the circuit to be tested is converted into graph data; Based on the graph data input to the graph neural network (GNN) model, test coverage data and impact data representing the influence of the multiple circuit nodes are generated. as well as Based on the impact data, one or more test points are selected from the plurality of circuit nodes for test point insertion.

13. The electronic device according to claim 12, wherein, The graph data includes a graph node matrix representing the features of the plurality of circuit components, and an edge matrix representing the plurality of circuit nodes.

14. The electronic device according to claim 13, wherein, The characteristics of the plurality of circuit components include component type, number of fan-in, number of fan-out, logic depth, masking information, or a combination thereof.

15. The electronic device according to claim 12, wherein The GNN model is configured to generate a saliency map corresponding to the predictions of the test coverage data, and The impact data is generated based on the saliency map.

16. The electronic device according to claim 12, wherein, The one or more processors are also configured to select the one or more test points in order based on the influence from the plurality of circuit nodes.

17. The electronic device according to claim 12, wherein, The one or more processors are further configured to: The plurality of circuit components are converted into a plurality of replacement components with less diversity compared to the plurality of circuit components; and The graph data is generated based on the multiple replacement components.

18. The electronic device according to claim 12, wherein The design data is a netlist, and The plurality of circuit nodes are identified by their net names in the netlist.

19. The electronic device according to claim 12, wherein, The GNN model is trained based on the sample design data and the actual test coverage of the sample design data.

20. The electronic device according to claim 19, wherein, The GNN model includes: The first layer group consists of one or more graph convolutional layers; The second layer group includes one or more pooling layers; and The third layer group includes one or more multi-layer perceptron layers.

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