Verification document generation method and device of chip code, medium and computer equipment

Abstract

The invention discloses a verification document generation method and device for a chip code, a medium and computer equipment, and relates to the technical field of integrated circuit chip code design. And automatically generating a target verification document of the target code in combination with the target semantic text. The problems that the working efficiency and the working progress are affected and the probability of verification work error risks is increased due to the fact that verification engineers depend on verification of the verification documents of the chip codes are solved. Therefore, the time and energy required by verification personnel to understand the codes are reduced, new verification personnel can quickly master the code, the time for familiarity and code reconstruction is reduced, and the technical effect of improving the working efficiency and the working progress of target code verification is achieved. In addition, errors and risks possibly occurring when the code intention and logic are concluded are reduced, and the technical effect of ensuring the accuracy of the target verification document is achieved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit chip code design technology, and in particular to a method, apparatus, medium and computer equipment for generating verification documents for chip code. Background Technology

[0002] With the rapid development of integrated circuit technology, the scale and functional requirements of chips are constantly increasing, and their complexity is also growing exponentially. In system-on-a-chip (SoC) verification projects, chip verification is becoming increasingly important. Verification is not only a crucial step in ensuring the correctness of chip functionality, but also an important means of guaranteeing chip reliability and performance.

[0003] In related technologies, verification engineers typically rely on verification documentation to validate chips. However, different verification engineers have their own unique programming habits and coding styles. These differences can affect code readability and maintainability in collaborative projects or projects with multiple handovers. When any verification engineer needs to understand code written by other engineers, without detailed comments or accompanying verification documentation for reference, they often need to spend a significant amount of time and effort trying to decipher the code's intent and logic. Therefore, relying on verification documentation based on chip code verification engineers not only impacts work efficiency and progress but also increases the probability of errors in the verification process. Summary of the Invention

[0004] This application provides a method, apparatus, medium, and computer equipment for generating verification documents for chip code, in order to at least solve the problem in the related art that relying on verification engineers to verify chip code verification documents not only affects work efficiency and progress, but also increases the probability of errors in the verification work.

[0005] This application provides a method for generating verification documentation for chip code, including:

[0006] Obtain the target code of the target chip;

[0007] Extract target fusion features among multiple target attribute features corresponding to the target code. These multiple target attribute features include: target type features, target relationship features, and target parameter list.

[0008] The target fusion feature between multiple target attribute features is input into the code analysis model for prediction, and the target semantic text corresponding to the target code is obtained. The target semantic text includes: functional information, relational information, type information and parameter information of the target code.

[0009] Based on the target semantic text, a target verification document for the target code is generated using a document generation tool.

[0010] This application also provides a chip code verification document generation apparatus, the apparatus comprising:

[0011] The acquisition module is used to acquire the target code of the target chip;

[0012] The extraction module is used to extract target fusion features between multiple target attribute features corresponding to the target code. These multiple target attribute features include: target type features, target relationship features, and target parameter list.

[0013] The prediction module is used to input the target fusion features between multiple target attribute features into the code analysis model for prediction, and obtain the target semantic text corresponding to the target code. The target semantic text includes: functional information, relational information, type information and parameter information of the target code;

[0014] The generation module is used to generate target verification documents for the target code based on the target semantic text using a document generation tool.

[0015] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the step of generating a verification document for any of the above-described chip codes.

[0016] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the verification document generation method for any of the above-described chip codes.

[0017] This application addresses the problem of relying on verification engineers to verify chip code, which not only impacts work efficiency and schedule but also increases the probability of verification errors. By generating target semantic text corresponding to the target code based on a code analysis model and automatically generating target verification documents using this text, this application solves the issue of reliance on verification engineers to verify chip code documents. Therefore, this application not only reduces the time and effort required for verification personnel to understand the code but also facilitates new verification personnel to quickly get started, reducing the time spent familiarizing themselves with and refactoring the code, thus improving the efficiency and schedule of target code verification. Furthermore, this application reduces the errors and risks that may occur when interpreting code intent and logic, thus ensuring the accuracy of the target verification documents. Attached Figure Description

[0018] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating the chip code verification document generation method provided in this application embodiment;

[0020] Figure 2 A flowchart illustrating another chip code verification document generation method provided in this application embodiment;

[0021] Figure 3 A flowchart illustrating a method for generating verification documentation for chip code provided in an embodiment of this application;

[0022] Figure 4 A schematic diagram of the structure of the target verification document provided in the embodiments of this application;

[0023] Figure 5 A structural block diagram of the chip code verification document generation device provided in the embodiments of this application;

[0024] Figure 6 This is a schematic diagram of the hardware structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0026] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0027] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] The specific application environment architecture or specific hardware architecture on which the execution of the verification documentation generation method based on the chip code depends is described here.

[0029] With the rapid development of integrated circuit technology, the scale and functional requirements of chips are constantly increasing, and their complexity is also growing exponentially. In today's era of very large-scale integrated circuits, the integration level of chips is getting higher and higher, and the functional modules are becoming increasingly rich, which greatly increases the difficulty of chip design and verification. In system-on-a-chip verification projects, the importance of chip verification is becoming increasingly prominent. Verification work is not only a key link to ensure the correctness of chip functions, but also an important means to ensure chip reliability and performance. However, facing such complex design and verification tasks, it is far from enough to rely on the efforts of an individual; usually, a verification team is needed to collaborate and jointly develop and maintain the test environment.

[0030] In collaborative verification projects, the diversity of coding styles becomes a significant issue. Different verification engineers may come from diverse technical backgrounds, with their own unique programming habits and coding styles. This difference can severely compromise code readability and maintainability in multi-person collaborative projects. When verification personnel need to understand the code written by their colleagues, without detailed comments or accompanying verification documentation for reference, they often need to spend a considerable amount of time and effort trying to decipher the code's intent and logic. This not only reduces work efficiency but may also introduce new errors and risks.

[0031] Furthermore, in most module-level verification projects, the verification platform is typically developed iteratively based on the previous generation. While this development model, based on an existing platform, can inherit previous achievements to some extent, it also brings new challenges. Due to personnel changes and poor project handover, the original code comments often fail to meet the needs of new verification personnel for quick onboarding. Missing or incomplete comments make it difficult for new members to quickly understand the overall architecture of the verification platform, the functions of key modules, and the interactions between modules. In this situation, verification personnel need to spend a significant amount of time familiarizing themselves with and refactoring the code, which not only affects the progress of the verification project but may also increase the repetitiveness of verification work, further reducing overall work efficiency.

[0032] Therefore, the traditional method of relying on manual verification of chip code verification documents not only affects work efficiency and progress, but also increases the probability of errors in the verification process.

[0033] This embodiment provides a method for generating verification documents for chip code, which can be used in computer devices such as mobile phones, tablets, desktop computers, laptops, servers, etc. Figure 1 This is a flowchart of a chip code verification document generation method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0034] Step S101: Obtain the target code of the target chip.

[0035] Specifically, target chips include, but are not limited to, central processing unit (CPU) chips, system-on-chip (SoC) chips, and field-programmable gate array (FPGA) chips. Target code can be the source code for any programming project of the target chip.

[0036] For example, the following is a sample of target code.

[0037] class SemanticAnalyzer:

[0038] def__init__(self, model_path):

[0039] self.model=pipeline('text-generation',model=model_path)

[0040] self.cache = {}

[0041] def generate_documentation(self,code_block):

[0042] if code_block['hash']in self.cache:

[0043] return self.cache[code_block['hash']]

[0044] prompt=f"""Analyze the following SystemVerilog code according to the IEEE 1800 standard:

[0045] {code_block['content']}

[0046] Please reply in the following JSON format:

[0047]

[0048] Step S102: Extract the target fusion features between multiple target attribute features corresponding to the target code. The multiple target attribute features include: target type features, target relationship features, and target parameter list.

[0049] Specifically, target type features include: class name features, class variable features, and class function features; target relationship features include: parent class relationship features; and target parameter list includes: multiple parameter features.

[0050] For example, the target class feature is the Class of the target code in the example above, which includes information such as class name, variables, and functions. The target relationship feature is the parent class relationship, which means that the target code of each class has a link pointing to its parent class, and this link can be traced back to the top-level base class. The target parameter column includes: multiple parameter features, including but not limited to parameter type, parameter name, and optional parameters.

[0051] In some specific implementations, a dedicated code parsing tool is used to parse the target fusion features between multiple target attribute features corresponding to the target code.

[0052] For example, using the code parsing tool (ANother Tool for Language Recognition, ANTLR4), a parser generator widely used to read, process, execute, and translate structured text or binary files, it can generate a parser that can traverse the parse tree based on grammatical description rules. ANTLR4 is the fourth version of ANTLR.

[0053] The ANTLR4 code parsing tool uses a syntax tree listener pattern to capture multiple target attribute features in real time, including target type characteristics, target relationship characteristics, and target parameter lists. Based on this, ANTLR4 builds a class member method call graph to trace parameter passing paths. Further, at this stage, ANTLR4 performs code normalization, including standardizing indentation style, removing debugging statements, and expanding macro definitions, thereby obtaining the target fusion features among the multiple target attribute features corresponding to the target code.

[0054] In some preferred embodiments, a code attribute feature model is used to extract target fusion features among multiple target attribute features. The code attribute feature model includes: an embedding network, a convolutional network, a fully connected network, and a fusion network. The convolutional network includes: a first convolutional layer, a second convolutional layer, and a third convolutional layer. Extracting target fusion features among multiple target attribute features corresponding to the target code includes:

[0055] Step a1 involves cleaning the target code of the target chip.

[0056] In a specific example, cleaning the target code of the target chip includes, but is not limited to, deleting missing code and deleting abnormal code.

[0057] Due to programming redundancy or commented-out code blocks, the target code of the target chip may contain useless code. Useless code affects code readability. Therefore, before the target fusion feature between multiple target attribute features corresponding to the target code, the target code can be deleted to obtain the cleaned target code of the target chip.

[0058] For example, useless code can include both code and data. There are two conditions for identifying useless code:

[0059] (1) Execution fails, meaning the program's control flow cannot reach the code, or the data flow cannot reach the data;

[0060] (2) Untraceable, meaning that no system or software requirement can be traced from the code or data.

[0061] In this embodiment of the application, processing the target code of the target chip helps to improve the accuracy of extracting target fusion features between multiple target attribute features.

[0062] Step a2 involves using an embedded network to vectorize the cleaned target code to generate multiple code attribute vectors.

[0063] For example, in this embodiment, an embedded network is used to construct a vector matrix based on the historical code after cleaning. For example, if there are 100 historical codes and each code is to be converted into a 128-dimensional vector, then the shape of the constructed matrix is ​​100*128, and each input code corresponds to a vector in this matrix.

[0064] Step a3: Utilize the first convolutional layer to output the first convolutional information based on multiple code attribute vector information.

[0065] Step a4: Using the second convolutional layer, output the second convolutional information based on the first convolutional information.

[0066] Step a5: Using the third convolutional layer, output the third convolutional information based on the second convolutional information.

[0067] In the convolutional network consisting of the first, second, and third convolutional layers, the convolutional information output by each convolutional network serves as the input to the next convolutional network. In this embodiment, the convolutional network aims to capture local features of multiple code attribute information of the target code.

[0068] Step a6: Use a fully connected network to perform transformation processing based on the third convolution information to generate multiple target attribute features.

[0069] Specifically, the fully connected network integrates the local features extracted by the convolutional network into global features through weighted summation.

[0070] Step a7: Use a fusion network to fuse multiple historical attribute features to obtain historical fusion features among multiple historical attribute features.

[0071] Fusion networks can be multi-head attention modules that fuse multiple historical attribute features to obtain historical fusion features among multiple historical attribute features, thereby extracting target code feature information more accurately, which is ultimately beneficial for code analysis models to predict target semantic text.

[0072] Step S103: Input the target fusion feature between multiple target attribute features into the code analysis model for prediction to obtain the target semantic text corresponding to the target code. The target semantic text includes: functional information, relational information, type information and parameter information of the target code.

[0073] Step S104: Based on the target semantic text, use a document generation tool to generate a target verification document for the target code.

[0074] Specifically, the code analysis model can be a code suggestion model, also known as a prompt model. Through this model, a relatively accurate target semantic text corresponding to the target code is obtained. This target semantic text is structured code data with a specific code format. This structured code data includes: functional information, relational information, type information, and parameter information of the target code.

[0075] In traditional programming projects, while developers are advised to add code comments to aid understanding, significant differences in coding styles among verification engineers can reduce code readability and maintainability. When verification engineers need to understand code written by other colleagues, without detailed comments or accompanying verification documentation, they often spend considerable time and effort deciphering the code's intent and logic. This not only reduces efficiency but may also introduce new errors and risks. Furthermore, due to personnel changes and other factors, even if comments have been added to the original code, they often fail to meet the needs of new verification personnel for quick onboarding. Missing or incomplete comments make it difficult for new members to quickly understand the overall architecture of the verification platform, the functions of key modules, and the interactions between them. This forces new verification personnel to spend considerable time familiarizing themselves with and refactoring the code, impacting project progress, increasing the repetitiveness of verification work, and further reducing overall efficiency.

[0076] Therefore, this embodiment utilizes a pre-trained code analysis model to quickly and accurately predict the target semantic text corresponding to the target code, thereby facilitating the accurate and rapid generation of target verification documents for the target code.

[0077] Ultimately, this embodiment not only improves the efficiency and project schedule of verification work, ensuring its smooth progress, but also reduces the probability of errors in verification. Furthermore, this embodiment helps verification personnel quickly understand the code logic, reduces communication costs, and improves the maintainability and scalability of the code.

[0078] This embodiment provides a method for generating verification documents for chip code, which can be used in computer devices such as mobile phones, tablets, desktop computers, laptops, servers, etc. Figure 2 This is a flowchart of a chip code verification document generation method according to an embodiment of the present invention. The code analysis model is a pre-trained neural network model, and the training process of the code analysis model is as follows: Figure 2 As shown, the process includes the following steps:

[0079] Step S201: Obtain the historical code of the target chip.

[0080] Specifically, historical code serves as training sample code for the target chip. Similarly, target chips include, but are not limited to, Central Processing Unit (CPU) chips, System-on-Chips (SoC) chips, and Field-Programmable Gate Array (FPGA) chips. Historical code can be the source code for any programming project on the target chip.

[0081] Step S202: Extract the target fusion feature between multiple historical attribute features corresponding to the historical code. The multiple historical code attribute features include: historical type features, historical relationship features, and historical parameter list.

[0082] In some preferred embodiments, the target fusion feature is extracted among multiple historical attribute features corresponding to historical codes, including:

[0083] Step b1 involves cleaning up the historical code of the target chip.

[0084] In a specific example, cleaning up the historical code of the target chip includes, but is not limited to, deleting missing code and deleting abnormal code.

[0085] Due to programming redundancy or commented-out code blocks, the historical code of the target chip may contain useless code. Useless code affects code readability. Therefore, the historical code can be deleted before the target fusion feature between multiple historical attribute features corresponding to the historical code, resulting in the cleaned historical code of the target chip.

[0086] For example, useless code can include both code and data. There are two conditions for identifying useless code:

[0087] (1) Execution fails, meaning the program's control flow cannot reach the code, or the data flow cannot reach the data;

[0088] (2) Untraceable, meaning that no system or software requirement can be traced from the code or data.

[0089] In this embodiment of the application, processing the historical code of the target chip helps to improve the accuracy of extracting target fusion features between multiple target attribute features.

[0090] Step b2 involves using an embedded network to vectorize the historical code after cleaning, thereby generating multiple code attribute vector information.

[0091] For example, in this embodiment, an embedded network is used to construct a vector matrix based on the historical code after cleaning. For example, if there are 100 historical codes and each code is to be converted into a 128-dimensional vector, then the shape of the constructed matrix is ​​100*128, and each input code corresponds to a vector in this matrix.

[0092] Step b3: Utilize the first convolutional layer to output the first convolutional information based on multiple code attribute vector information.

[0093] Step b4: Using the second convolutional layer, output the second convolutional information based on the first convolutional information.

[0094] Step b5: Using the third convolutional layer, output the third convolutional information based on the second convolutional information.

[0095] In the convolutional network consisting of the first, second, and third convolutional layers, the convolutional information output by each convolutional network serves as the input to the next convolutional network. In this embodiment, the convolutional network aims to capture local features of multiple code attribute information from historical code.

[0096] Step b6: Use a fully connected network to perform transformation processing based on the third convolutional information to generate multiple historical attribute features.

[0097] Specifically, the fully connected network integrates the local features extracted by the convolutional network into global features through weighted summation.

[0098] Step b7: Use a fusion network to fuse multiple historical attribute features to obtain historical fusion features among multiple historical attribute features.

[0099] Fusion networks can be multi-head attention modules that fuse multiple historical attribute features to obtain historical fusion features among multiple historical attribute features, thereby extracting historical code feature information more accurately, which is ultimately beneficial for code analysis models to predict historical semantic text.

[0100] Step S203: Input multiple code attribute features corresponding to the historical code into the code analysis model for training to obtain the historical semantic text corresponding to the historical code, and the loss value between the historical semantic text and the historical code. The loss value is used to update the weight parameters of the code analysis model.

[0101] In a specific example, during the training of the code analysis model, when the loss value is greater than or equal to a preset threshold, the weight parameters of the code analysis model are repeatedly adjusted until the loss value is less than the preset threshold.

[0102] The preset threshold can be a value between 0 and 1, and can be flexibly set according to the actual application scenario.

[0103] Traditional methods rely on verification engineers to verify chip code documentation, which not only impacts work efficiency and schedule but also increases the probability of verification errors. Therefore, if the target chip's target code hasn't been trained using a code analysis model, directly generating target verification documentation through verification personnel or code parsing tools will inevitably lead to problems. Firstly, the diverse styles of the target code mean that the comments in the original code won't meet the needs of new verification personnel for quick onboarding. Secondly, the complexity of the original code, even with documentation generation tools, will affect the accuracy of the target code's verification text.

[0104] This embodiment utilizes machine learning to automatically learn the historical code of complex and diverse target chips, obtaining historical semantic text corresponding to the historical code, including historical type features, historical relationship features, and historical parameter lists. This enhances the accuracy of the code analysis model in predicting the target semantic text corresponding to the target code, thereby facilitating the accurate and rapid generation of target verification documents. Ultimately, this embodiment not only improves the efficiency and project schedule of verification work, ensuring its smooth progress, but also reduces the probability of verification errors. Furthermore, this embodiment helps verification personnel quickly understand the code logic, reduces communication costs, and improves the maintainability and scalability of the code.

[0105] Therefore, applying code analysis models to the code verification scenario of integrated circuit chips not only greatly improves the efficiency and progress of code verification work, but also ensures the accuracy of code verification work.

[0106] This embodiment provides a method for generating verification documents for chip code, which can be used in computer devices such as mobile phones, tablets, desktop computers, laptops, servers, etc. Figure 3 This is a flowchart of a chip code verification document generation method according to an embodiment of the present invention. The code analysis model is a pre-trained neural network model, and the training process of the code analysis model is as follows: Figure 3 As shown, step S104 above, which generates a target verification document for the target code using a document generation tool based on the target semantic text, includes:

[0107] Step S1041: Summarize the target code based on its functional information, relational information, type information, and parameter information to obtain the summary result.

[0108] Specifically, in this embodiment, the target code can be summarized into code data in a standard code format according to the data format of the target code's functional information, relational information, type information, and parameter information.

[0109] In some optional implementations, during the process of summarizing the target code based on its functional information, relational information, type information, and parameter information, target relation annotations are added to the summary results based on the relational information. For example, in the case of cross-class inheritance, an annotation "inherited from <parent class name>" will be added during the summarization process to help quickly locate the parent class of the target code.

[0110] Step S1042: Match the summary result and the target code to obtain the matching result of the summary result.

[0111] In some specific implementations, step S1042 above, matching the summary result and the target code to obtain the matching result of the summary result, includes:

[0112] Step c1: Obtain the first similarity between the summary function of the target code and the original function.

[0113] In a specific example, calculating the first similarity between the functional information of the target code and the target code includes:

[0114] Step c11: Obtain the summary function of the target code from the summary results, and obtain the original function of the target code from the target code.

[0115] Step c12: Extract the summary function feature vector corresponding to the summary function of the target code, and extract the original function feature vector corresponding to the original function of the target code.

[0116] Here, this embodiment can still use the feature extraction network in steps a1-a7 or steps b1-b7 above to extract the summary functional feature vector and extract the original functional feature vector. For the specific extraction process, please refer to steps a1-a7 or steps b1-b7 above, which will not be repeated here.

[0117] Step c13: Calculate the first similarity between the summarized function and the original function of the target code based on the summarized function feature vector and the original function feature vector.

[0118] In another specific example, the first similarity between the summary function of the target code and the original function is calculated using the following cosine similarity formula.

[0119]

[0120] Where cos(A1,B1) is the first similarity between the summary function and the original function of the target code, A1 is the feature vector of the summary function, B1 is the feature vector of the original function, ||A1|| is the length of the feature vector of the summary function, and ||B1|| is the length of the feature vector of the original function.

[0121] In another specific example, a pre-trained similarity matching model can be used to predict the first similarity between the aggregated and original functional features of the target code, by combining the aggregated feature vector and the original feature vector. The similarity matching model is trained in a supervised manner based on manually labeled samples, eliminating the need for unsupervised model mapping in the intermediate process, thus resulting in high accuracy.

[0122] Step c2: Obtain the second similarity between the summary relationship of the target code and the original relationship of the target code.

[0123] In a specific example, calculating the first similarity between the relational information of the target code and the target code includes:

[0124] Step c21: Obtain the summary relationship of the target code from the summary results, and obtain the original relationship of the target code from the target code.

[0125] Step c22: Extract the summary relation feature vector corresponding to the summary relation of the target code, and extract the original relation feature vector corresponding to the original relation of the target code.

[0126] Here, this embodiment can still use the feature extraction network in steps a1-a7 or steps b1-b7 above to extract the summary relation feature vector and extract the original relation feature vector. For the specific extraction process, please refer to steps a1-a7 or steps b1-b7 above, which will not be repeated here.

[0127] Step c23: Calculate the second similarity between the summary relation and the original relation of the target code based on the summary relation feature vector and the original relation feature vector.

[0128] In a specific example, the second similarity between the aggregate relation and the original relation of the target code is calculated using the following cosine similarity formula.

[0129]

[0130] Where cos(A2,B2) is the second similarity between the summary type and the original type of the target code, A2 is the feature vector of the summary type, B2 is the feature vector of the original type, ||A2|| is the length of the feature vector of the summary type, and ||B2|| is the length of the feature vector of the original type.

[0131] In another specific example, a pre-trained similarity matching model can be used to predict the first similarity between the summarized relation and the original relation in the target code, by combining the summarized relation feature vector and the original relation feature vector. The similarity matching model is trained in a supervised manner based on manually labeled samples, eliminating the need for unsupervised model mapping in the intermediate process; therefore, it achieves high accuracy.

[0132] Step c3: Obtain the third similarity between the aggregate type of the target code and the original type of the target code.

[0133] Step c31: Obtain the summary type of the target code from the summary results, and obtain the original type of the target code from the target code.

[0134] Step c32: Extract the summary type feature vector corresponding to the summary type of the target code, and extract the original type feature vector corresponding to the original type of the target code.

[0135] Here, this embodiment can still use the feature extraction network in steps a1-a7 or steps b1-b7 above to extract the summary type feature vector and extract the original type feature vector. For the specific extraction process, please refer to steps a1-a7 or steps b1-b7 above, which will not be repeated here.

[0136] Step c33: Calculate the third similarity between the summary type and the original type of the target code based on the summary type feature vector and the original type feature vector.

[0137] In another specific example, the third similarity between the aggregate type of the target code and the original type is calculated using the following cosine similarity formula.

[0138]

[0139] Where cos(A3,B3) is the third similarity between the summary type and the original type of the target code, A3 is the feature vector of the summary type, B3 is the feature vector of the original type, ||A3|| is the length of the feature vector of the summary type, and ||B3|| is the length of the feature vector of the original type.

[0140] In another specific example, a pre-trained similarity matching model can be used to predict the third similarity between the summary type and the original type of the target code, by combining the summary type feature vector and the original type feature vector. The similarity matching model is trained in a supervised manner based on manually labeled samples, eliminating the need for unsupervised model mapping in the intermediate process; therefore, it achieves high accuracy.

[0141] Step c4: Obtain the fourth similarity between the aggregated parameters of the target code and the original parameters of the target code.

[0142] Step c41: Obtain the summary parameters of the target code from the summary results, and obtain the original parameters of the target code from the target code.

[0143] Step c42: Extract the feature vector of the summary parameters corresponding to the summary parameters of the target code, and extract the feature vector of the original parameters corresponding to the original parameters of the target code.

[0144] Here, this embodiment can still use the feature extraction network in steps a1-a7 or steps b1-b7 above to extract the summary parameter feature vector and extract the original parameter feature vector. For the specific extraction process, please refer to steps a1-a7 or steps b1-b7 above, which will not be repeated here.

[0145] Step c43: Calculate the fourth similarity between the summarized parameters and the original parameters of the target code based on the summarized parameter feature vector and the original parameter feature vector.

[0146] In another specific example, the fourth similarity between the aggregate parameters of the target code and the original parameters is calculated using the following cosine similarity formula.

[0147]

[0148] Where cos(A4,B4) is the third similarity between the aggregated parameters and the original parameters of the target code, A4 is the feature vector of the aggregated parameters, B4 is the feature vector of the original parameters, ||A4|| is the length of the feature vector of the aggregated parameters, and ||B4|| is the length of the feature vector of the original parameters.

[0149] In another specific example, a pre-trained similarity matching model can be used to predict the fourth similarity between the aggregated parameters and the original parameters of the target code, combining the aggregated parameter feature vector and the original parameter feature vector. The similarity matching model is trained in a supervised manner based on manually labeled samples, eliminating the need for unsupervised model mapping in the intermediate process, thus resulting in high accuracy.

[0150] Step c5: Calculate the total similarity among the first similarity, second similarity, third similarity, and fourth similarity.

[0151] Step c6: When the total similarity is less than the preset threshold, it is determined that the summary result and the target code have matched successfully;

[0152] Step c7: When the total similarity is greater than or equal to the preset threshold, it is determined that the summary result and the target code have failed to match.

[0153] For example, based on the calculation of the first, second, third, and fourth similarities mentioned above, a weighted average is applied to these four similarities. If the first similarity is 0.42, the second is 0.35, the third is 0.43, and the fourth is 0.56, then the total similarity = 0.42 + 0.35 + 0.43 + 0.56 = 1.76. The preset threshold can be flexibly set, and when the preset threshold is 1.65, 1.76 > 1.65, indicating that the summarized result and the target code match successfully. If the first similarity is 0.12, the second is 0.15, the third is 0.41, and the fourth is 0.26, then the total similarity = 0.12 + 0.15 + 0.41 + 0.26 = 0.94. The preset threshold can also be flexibly set, and when the preset threshold is 1.65, 0.94 < 1.65, indicating that the summarized result and the target code do not match.

[0154] Step S1043: Based on the matching results of the summarized results, use the document generation tool to generate the target verification document of the target code according to the preset content.

[0155] Step d1: When the summary result and the target code match successfully, add a target validation comment to the target code at the matching and associated location.

[0156] Step d2: Update the line number information of the target code after adding the target verification comment;

[0157] Step d3: Based on the updated target verification comment line number information of the target code, use a document generation tool to generate a target verification document for the target code according to preset content.

[0158] For example, when the summary result and the target code match successfully, after determining the matching correlation position and adding a target validation comment at that position, the line numbers corresponding to subsequent code content will change. Therefore, fine-grained line number management is required to ensure that the line numbers of the target code are accurate after adding validation comments. The relevant code is as follows:

[0159]

[0160] The documentation generation tool could be Natural Docs, an open-source tool designed to automatically generate documentation from source code comments. It supports multiple programming languages ​​and emphasizes writing comments in a "natural language" style, making the documentation more readable and maintainable.

[0161] The document generation tool scans the target verification annotations and verifies the structure based on the standard verification method (Universal Verification Methodology, UVM). It automatically generates target verification documents in formats including but not limited to HTML and PDF, and includes features such as cross-references, indexes, and categories in the target verification documents.

[0162] The default content includes: The default content of the UVM validation structure includes four main components: env, Sequence, Virtual_sequence, and test. Figure 4 As shown, xx_verification is the project name of the programming project for the target chip.

[0163] Env is the core component of the UVM validation environment. It contains `config` for defining and passing environment configuration parameters, and `covergroup` and `reference_model` for collecting coverage data and providing expected results during the validation process. `env` also contains the connection methods and instantiation order of various components, which are crucial for ensuring the correctness and maintainability of the validation environment. `env` also includes: `env` parameters and `screboard` parameters.

[0164] Sequence: Contains the basic units used in UVM to generate test stimuli. It is a common basic sequence used by all test cases. These sequences can be reused to reduce code redundancy and improve verification efficiency. Adding comments to sequences can explain the types of test stimuli generated by the sequence and how they simulate real-world use cases, helping verification personnel understand the verification scenarios.

[0165] Virtual_sequence: A key component for constructing complex test cases using multiple base sequences. It allows validation engineers to create more complex test scenarios by combining and extending base sequences, thereby improving test coverage and effectiveness. Comments provide detailed explanations of the parameters and configurations used in virtual sequences to help other engineers understand and use them.

[0166] Test is the top-level component in the UVM verification environment, responsible for organizing and executing all test cases. Adding comments to tests can clarify the goals of the test cases and how they verify the functionality of the design.

[0167] Firstly, the chip code verification document generation method in this embodiment generates target semantic text corresponding to the target code based on a code analysis model, and automatically generates target verification documents for the target code by combining the target semantic text. Therefore, this embodiment not only reduces the time and effort required for verification personnel to understand the code, but also helps new verification personnel get started quickly, reducing the time spent familiarizing themselves with and refactoring the code, thus improving the efficiency and progress of target code verification.

[0168] Then, the chip code verification document generation method of this embodiment generates target semantic text corresponding to the target code based on the code analysis model, and automatically generates target verification document for the target code by combining the target semantic text. Therefore, this embodiment can add comments to the target verification document, thereby reducing the impact of differences in coding styles among different engineers and enhancing code readability. At the same time, standardized comments help maintenance personnel quickly understand the code logic and reduce maintenance costs.

[0169] Secondly, the chip code verification document generation method in this embodiment generates target semantic text corresponding to the target code based on a code analysis model, and automatically generates the target verification document of the target code by combining the target semantic text. Therefore, this embodiment reduces the errors and risks that may occur when trying to decipher the code's intent and logic, thus ensuring the accuracy of the target verification document.

[0170] Furthermore, the chip code verification document generation method in this embodiment generates target semantic text corresponding to the target code based on a code analysis model, and automatically generates target verification documents for the target code by combining the target semantic text. Therefore, it facilitates knowledge transfer during project handover, enabling new members to quickly understand the overall architecture and key module functions of the verification platform, thus improving project handover.

[0171] Finally, the chip code verification document generation method of this embodiment generates target semantic text corresponding to the target code based on the code analysis model, and automatically generates target verification documents for the target code by combining the target semantic text. Therefore, the automated process of automatically generating target verification documents in this embodiment reduces the workload of manually writing and maintaining documents.

[0172] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0173] Embodiments of this application also provide a chip code verification document generation apparatus, such as... Figure 5 As shown, the device includes:

[0174] Acquisition module 501 is used to acquire the target code of the target chip;

[0175] Extraction module 502 is used to extract target fusion features between multiple target attribute features corresponding to the target code. The multiple target attribute features include: target type features, target relationship features and target parameter list.

[0176] Prediction module 503 is used to input the target fusion features between multiple target attribute features into the code analysis model for prediction, and obtain the target semantic text corresponding to the target code. The target semantic text includes: functional information, relational information, type information and parameter information of the target code.

[0177] The generation module 504 is used to generate a target verification document for the target code based on the target semantic text using a document generation tool.

[0178] In some alternative implementations, the code analysis model is a pre-trained neural network model, the training module of which includes:

[0179] The acquisition submodule is used to acquire the historical code of the target chip;

[0180] The extraction submodule is used to extract the target fusion features between multiple historical attribute features corresponding to historical code. The multiple historical code attribute features include: historical type features, historical relationship features, and historical parameter list.

[0181] The training submodule is used to input multiple code attribute features corresponding to historical code into the code analysis model for training, to obtain the historical semantic text corresponding to the historical code, and the loss value between the historical semantic text and the historical code. The loss value is used to update the weight parameters of the code analysis model.

[0182] In some optional implementations, a code attribute feature model is used to extract target fusion features between multiple target attribute features corresponding to the target code. The code attribute feature model includes: an embedding network, a convolutional network, a fully connected network, and a fusion network. The convolutional network includes: a first convolutional layer, a second convolutional layer, and a third convolutional layer.

[0183] The extraction module includes:

[0184] The cleaning submodule is used to clean up the historical code of the target chip;

[0185] The vector processing submodule is used to vectorize the cleaned historical code using an embedded network to generate multiple code attribute vector information.

[0186] The first convolutional submodule is used to output the first convolutional information based on multiple code attribute vector information from the first convolutional layer;

[0187] The second convolutional submodule is used to output the second convolutional information based on the first convolutional information using the second convolutional layer;

[0188] The third convolutional submodule is used to output the third convolutional information based on the second convolutional information using the third convolutional layer;

[0189] The transformation processing submodule is used to perform transformation processing based on the third convolution information using a fully connected network to generate multiple historical attribute features;

[0190] By using a fusion network to fuse multiple historical attribute features, a historical fusion feature among the multiple historical attribute features is obtained.

[0191] In some optional implementations, during the training of the code analysis model, the training submodule repeatedly adjusts the weight parameters of the code analysis model multiple times when the loss value is greater than or equal to a preset threshold, until the loss value is less than the preset threshold.

[0192] In some alternative implementations, the generation module includes:

[0193] The summary submodule is used to summarize the target code based on its functional information, relational information, type information, and parameter information, and obtain the summary result.

[0194] The matching submodule is used to match the summary results and the target code to obtain the matching results of the summary results;

[0195] The generation submodule is used to generate target verification documents for the target code according to preset content using a document generation tool based on the matching results of the summary results.

[0196] In some alternative implementations, the generation module includes:

[0197] The annotation adds a submodule, which is used to add target validation comments to the target code at the matching correlation position when the summary results and target code match successfully;

[0198] The line number update submodule is used to update the line number information of the target code after adding target validation comments;

[0199] The document generation submodule is used to generate target verification documents for the target code based on the line number information of the target code after the updated target verification comments, using the document generation tool according to preset content.

[0200] In some alternative implementations, the matching submodule includes:

[0201] The first acquisition unit is used to acquire the first similarity between the summary function of the target code and the original function of the target code;

[0202] The second acquisition unit is used to acquire the second similarity between the summary relationship of the target code and the original relationship of the target code;

[0203] The third acquisition unit is used to acquire the third similarity between the summary type of the target code and the original type of the target code;

[0204] The fourth acquisition unit is used to acquire the fourth similarity between the summary parameters of the target code and the original parameters of the target code;

[0205] The similarity matching unit is used to calculate the total similarity between the first similarity, second similarity, third similarity, and fourth similarity.

[0206] The first determining unit is used to determine that the summary result and the target code are successfully matched when the total similarity is less than a preset threshold.

[0207] The second determining unit is used to determine that the summary result and the target code failed to match when the total similarity is greater than or equal to a preset threshold.

[0208] For a description of the features in the embodiment corresponding to the chip code verification document generation device, please refer to the relevant description in the embodiment corresponding to the chip code verification document generation method, which will not be repeated here.

[0209] Embodiments of this application also provide an electronic device, such as... Figure 6 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to perform the steps in any of the above-described chip code verification document generation method embodiments.

[0210] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in the embodiments of the chip code verification document generation method described above when running.

[0211] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0212] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0213] The present application provides a detailed description of a chip code verification document generation method. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for generating verification documentation for chip code, characterized in that, The method includes: Obtain the target code of the target chip; Extract target fusion features among multiple target attribute features corresponding to the target code, wherein the multiple target attribute features include: target type features, target relationship features, and target parameter list; The target fusion feature among the multiple target attribute features is input into the code analysis model for prediction to obtain the target semantic text corresponding to the target code. The target semantic text includes: the functional information, relational information, type information and parameter information of the target code. Based on the target semantic text, a target verification document for the target code is generated using a document generation tool.

2. The method according to claim 1, characterized in that, The code analysis model is a pre-trained neural network model, and the training process of the code analysis model includes: Obtain the historical code of the target chip; Extract the target fusion feature among multiple historical attribute features corresponding to the historical code. The multiple historical code attribute features include: historical type features, historical relationship features, and historical parameter list. Multiple code attribute features corresponding to the historical code are input into the code analysis model for training to obtain the historical semantic text corresponding to the historical code and the loss value between the historical semantic text and the historical code. The loss value is used to update the weight parameters of the code analysis model.

3. The method according to claim 2, characterized in that, The code attribute feature model is used to extract target fusion features among multiple target attribute features corresponding to the target code. The code attribute feature model includes: embedding network, convolutional network, fully connected network and fusion network. The convolutional network includes: first convolutional layer, second convolutional layer and third convolutional layer. Extract the target fusion features between multiple historical attribute features corresponding to historical codes, including: The historical code of the target chip is cleaned. The historical code after cleaning is vectorized using the embedded network to generate multiple code attribute vector information. The first convolutional layer outputs first convolutional information based on multiple code attribute vector information; The second convolutional layer outputs second convolutional information based on the first convolutional information; The third convolutional layer outputs third convolutional information based on the second convolutional information; The fully connected network is used to perform transformation processing based on the third convolutional information to generate the multiple historical attribute features; The fusion network is used to fuse the multiple historical attribute features to obtain historical fusion features among the multiple historical attribute features.

4. The method according to claim 2, characterized in that, During the training of the code analysis model, when the loss value is greater than or equal to a preset threshold, the weight parameters of the code analysis model are repeatedly adjusted until the loss value is less than the preset threshold.

5. The method according to claim 1, characterized in that, Based on the target semantic text, a target verification document for the target code is generated using a document generation tool, including: Based on the functional information, relational information, type information, and parameter information of the target code, the target code is summarized to obtain a summary result; Match the summary results with the target code to obtain the matching results of the summary results; Based on the matching results of the summarized results, the document generation tool is used to generate a target verification document for the target code according to preset content.

6. The method according to claim 5, characterized in that, Based on the matching results of the summarized results, the document generation tool is used to generate a target verification document for the target code according to preset content, including: When the summary result and the target code match successfully, add a target verification comment to the target code at the matching and associated location; Update the line number information of the target code after adding the target validation comment; Based on the line number information of the target code after the updated target verification comments, the document generation tool generates a target verification document for the target code according to preset content.

7. The method according to claim 5 or 6, characterized in that, Matching the summary result with the target code to obtain the matching result of the summary result includes: Obtain the first similarity between the summary function of the target code and the original function of the target code; Obtain the second similarity between the summarized relationship of the target code and the original relationship of the target code; Obtain the third similarity between the aggregate type of the target code and the original type of the target code; Obtain the fourth similarity between the aggregated parameters of the target code and the original parameters of the target code; Calculate the total similarity among the first similarity, the second similarity, the third similarity, and the fourth similarity; When the total similarity is less than a preset threshold, it is determined that the summary result and the target code are successfully matched; When the total similarity is greater than or equal to a preset threshold, it is determined that the summary result and the target code fail to match.

8. A chip code verification document generation device, characterized in that, The device includes: The acquisition module is used to acquire the target code of the target chip; The extraction module is used to extract target fusion features among multiple target attribute features corresponding to the target code, wherein the multiple target attribute features include: target type features, target relationship features, and target parameter list; The prediction module is used to input the target fusion features among the multiple target attribute features into the code analysis model for prediction, so as to obtain the target semantic text corresponding to the target code. The target semantic text includes: the functional information, relational information, type information and parameter information of the target code. The generation module is used to generate a target verification document for the target code based on the target semantic text using a document generation tool.

9. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the chip code verification document generation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to execute the chip code verification document generation method according to any one of claims 1 to 7.

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