Data processing apparatus and method, processor and chip

Abstract

This disclosure relates to a data processing apparatus and method, processor, and chip, belonging to the field of computer technology. The data processing apparatus includes an instruction fetching module and a processing module. The instruction fetching module caches at least one first instruction. The processing module splits the first instructions with different thread bundle specifications according to a preset value to obtain a splitting result. The splitting result includes one or more second instructions, a first identifier corresponding to the last second instruction in the one or more second instructions, and a second identifier corresponding to each second instruction. The second identifier is used to indicate the ranking of the second instruction in the first instruction. By setting the first identifier and the second identifier, the first instructions with different thread bundle specifications can be split, which is compatible with multiple thread bundle sizes. Since the number of threads in software code developed on different hardware platforms may be different, it has extremely high inclusiveness for software code developed on different hardware platforms.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to a data processing apparatus and method, processor and chip. Background Technology

[0002] Processor chips, such as Graphics Processing Units (GPUs), play an increasingly important role in graphics and general computing scenarios due to their highly parallel processing capabilities. Graphics processing in GPUs is typically handled in a fixed-function pipeline, while general-purpose processing is handled in a programmable pipeline. Load Store Units (LSUs), as the entry and exit points for accessing video memory, play a crucial role in the programmable pipeline. However, different GPUs often use different thread bundle sizes based on their architectural characteristics, and LSUs are often limited to a fixed thread bundle size, which presents limitations for scenarios with multiple thread bundle sizes. Summary of the Invention

[0003] This disclosure proposes a data processing technology solution.

[0004] According to one aspect of this disclosure, a data processing apparatus is provided, the data processing apparatus comprising: an instruction acquisition module and a processing module, the instruction acquisition module being connected to the processing module; the instruction acquisition module caching at least one first instruction; the processing module performing split processing on the first instructions with different thread bundle specifications according to a preset value to obtain a split result, the split result including one or more second instructions, a first identifier corresponding to the last ranked second instruction among the one or more second instructions, and a second identifier corresponding to each second instruction, the second identifier being used to indicate the ranking of the second instruction in the first instruction.

[0005] In one possible implementation, the data processing device further includes a driving module, which is connected to the instruction acquisition module and the processing module respectively. The driving module determines the processing result of each second instruction; according to the first identifier and the second identifier, it performs a packaging operation on the processing results of all second instructions split from the first instruction to obtain the packaging result of the first instruction, and generates a trigger signal representing the completion of the first instruction.

[0006] In one possible implementation, the processing module splits first instructions with different thread bundle specifications according to a preset value to obtain a splitting result, including: when the first instruction is a load instruction and the load target is a preset register, determining the size of the data loaded by the load instruction into the preset register based on the operands of the first instruction; performing an out-of-bounds check on the first instruction based on the size of the data loaded by the load instruction into the preset register to obtain a check result; and when the check result indicates that the first instruction passes the out-of-bounds check, the processing module splits the first instruction according to the preset value to obtain the splitting result.

[0007] In one possible implementation, the instruction acquisition module is further configured to cache the instruction number corresponding to each first instruction. The processing module includes an address preprocessing component and an address acquisition component. The address preprocessing component, in response to receiving the instruction number, performs splitting processing on the first instruction corresponding to the instruction number according to the preset value to obtain the splitting result. The address acquisition component, in response to receiving the instruction number and the second identifier, generates a second access request for obtaining address information in the second instruction corresponding to the instruction number and the second identifier.

[0008] In one possible implementation, the processing module further includes a parameter acquisition component and a data acquisition component, wherein the parameter acquisition component, in response to receiving the instruction number, acquires operands from a first instruction corresponding to the instruction number, or generates a first access request for acquiring operands in the first instruction corresponding to the instruction number; the data acquisition component, in response to receiving the instruction number and the second identifier, generates a third access request for acquiring data information in a second instruction corresponding to the instruction number and the second identifier.

[0009] In one possible implementation, the data processing device further includes an interface module, which collects at least one of the first access request from the parameter acquisition component, the second access request from the address acquisition component, and the third access request from the data acquisition component, and sends the operand returned by the first access request, the address information returned by the second access request, and the data information returned by the third access request to the driver module; the driver module determines the processing result of each second instruction by: the driver module determining the processing result of each second instruction based on the operand, the address information, and the data information.

[0010] In one possible implementation, the processing module splits first instructions with different thread bundle specifications according to a preset value to obtain a splitting result, including: the address preprocessing component, in response to the first instruction having a thread count greater than the preset value, obtains mask information of the first instruction, the mask information being used to indicate the validity of each thread in the first instruction; divides the mask information of the first instruction into multiple sub-segments grouped by a preset value; and splits the mask information of the first instruction according to the bitwise OR result of each group of sub-segments to obtain multiple second instructions, a first identifier corresponding to the last second instruction among the multiple second instructions, and a second identifier corresponding to each second instruction.

[0011] In one possible implementation, the data acquisition component, in response to receiving the instruction number and the second identifier, generates a third access request for acquiring data information in a second instruction corresponding to the instruction number and the second identifier, including: if the first instruction corresponding to the instruction number is a storage instruction, acquiring the operands and mask information corresponding to the second instruction based on the second identifier; and generating a third access request for acquiring data information in the second instruction corresponding to the instruction number and the second identifier based on the operands and mask information corresponding to the second instruction.

[0012] In one possible implementation, the driver module determines the processing result of each second instruction based on the operands, the address information, and the data information, including: the driver module determines the on-chip address and off-chip address corresponding to each second instruction based on the operands and the address information; when the second instruction is a load instruction, the processing result includes the driver module reading storage data from the off-chip address to the on-chip address; or, when the second instruction is a store instruction, the processing result includes the driver module writing the data information to the off-chip address.

[0013] According to one aspect of this disclosure, a method is provided applied to a data processing apparatus, the data processing apparatus comprising: an instruction acquisition module and a processing module, the instruction acquisition module being connected to the processing module; the method comprising: the instruction acquisition module caching at least one first instruction; the processing module splitting the first instructions with different thread bundle specifications according to a preset value to obtain a splitting result, the splitting result including one or more second instructions, a first identifier corresponding to the last ranked second instruction among the one or more second instructions, and a second identifier corresponding to each second instruction, the second identifier being used to indicate the ranking of the second instruction among the first instructions.

[0014] In one possible implementation, the data processing device further includes a driver module, which is connected to the instruction acquisition module and the processing module respectively. The method further includes: the driver module determining the processing result of each second instruction; performing a packaging operation on the processing results of all second instructions split from the first instruction according to the first identifier and the second identifier to obtain the packaging result of the first instruction, and generating a trigger signal representing the completion of the first instruction.

[0015] In one possible implementation, the processing module splits first instructions with different thread bundle specifications according to a preset value to obtain a splitting result, including: when the first instruction is a load instruction and the load target is a preset register, determining the size of the data loaded by the load instruction into the preset register based on the operands of the first instruction; performing an out-of-bounds check on the first instruction based on the size of the data loaded by the load instruction into the preset register to obtain a check result; and when the check result indicates that the first instruction passes the out-of-bounds check, the processing module splits the first instruction according to the preset value to obtain the splitting result.

[0016] In one possible implementation, the instruction acquisition module is further configured to cache the instruction number corresponding to each first instruction. The processing module includes an address preprocessing component and an address acquisition component. The processing module performs splitting processing on first instructions with different thread bundle specifications according to a preset value to obtain a splitting result. This includes: the address preprocessing component, in response to receiving the instruction number, performs splitting processing on the first instruction corresponding to the instruction number according to the preset value to obtain the splitting result; and the address acquisition component, in response to receiving the instruction number and the second identifier, generates a second access request for obtaining address information in the second instruction corresponding to the instruction number and the second identifier.

[0017] In one possible implementation, the processing module further includes a parameter acquisition component and a data acquisition component. The processing module splits first instructions with different thread bundle specifications according to preset values ​​to obtain a splitting result, including: the parameter acquisition component, in response to receiving the instruction number, obtains operands from the first instruction corresponding to the instruction number, or generates a first access request for obtaining operands in the first instruction corresponding to the instruction number; the data acquisition component, in response to receiving the instruction number and the second identifier, generates a third access request for obtaining data information in a second instruction corresponding to the instruction number and the second identifier.

[0018] In one possible implementation, the data processing device further includes an interface module, and the method further includes: the interface module collecting at least one of the first access request from the parameter acquisition component, the second access request from the address acquisition component, and the third access request from the data acquisition component, and sending the operand returned by the first access request, the address information returned by the second access request, and the data information returned by the third access request to the driver module; the driver module determining the processing result of each second instruction includes: the driver module determining the processing result of each second instruction based on the operand, the address information, and the data information.

[0019] In one possible implementation, the processing module splits first instructions with different thread bundle specifications according to a preset value to obtain a splitting result, including: the address preprocessing component, in response to the first instruction having a thread count greater than the preset value, obtains mask information of the first instruction, the mask information being used to indicate the validity of each thread in the first instruction; divides the mask information of the first instruction into multiple sub-segments grouped by a preset value; and splits the mask information of the first instruction according to the bitwise OR result of each group of sub-segments to obtain multiple second instructions, a first identifier corresponding to the last second instruction among the multiple second instructions, and a second identifier corresponding to each second instruction.

[0020] In one possible implementation, the data acquisition component, in response to receiving the instruction number and the second identifier, generates a third access request for acquiring data information in a second instruction corresponding to the instruction number and the second identifier, including: if the first instruction corresponding to the instruction number is a storage instruction, acquiring the operands and mask information corresponding to the second instruction based on the second identifier; and generating a third access request for acquiring data information in the second instruction corresponding to the instruction number and the second identifier based on the operands and mask information corresponding to the second instruction.

[0021] In one possible implementation, the driver module determines the processing result of each second instruction based on the operands, the address information, and the data information, including: the driver module determines the on-chip address and off-chip address corresponding to each second instruction based on the operands and the address information; when the second instruction is a load instruction, the processing result includes the driver module reading storage data from the off-chip address to the on-chip address; or, when the second instruction is a store instruction, the processing result includes the driver module writing the data information to the off-chip address.

[0022] According to one aspect of this disclosure, a processor is provided, the processor including the data processing means described above.

[0023] According to one aspect of this disclosure, a chip is provided that includes the processor described above.

[0024] In this embodiment, by setting a first identifier and a second identifier, first instructions with different thread bundle specifications can be split and processed, thus being compatible with multiple thread bundle sizes. Since the number of threads in software code developed on different hardware platforms may vary, this method has extremely high inclusiveness for software code developed on different hardware platforms. Simultaneously, it also provides the software with the ability to explore various thread bundle specifications in terms of performance tuning.

[0025] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0027] Figure 1 A schematic diagram of a data processing apparatus according to an embodiment of the present disclosure is shown.

[0028] Figure 2 Another schematic diagram of a data processing apparatus according to an embodiment of the present disclosure is shown.

[0029] Figure 3 Another schematic diagram of a data processing apparatus according to an embodiment of the present disclosure is shown.

[0030] Figure 4 A schematic diagram of an instruction acquisition module according to an embodiment of the present disclosure is shown.

[0031] Figure 5 A schematic diagram of a parameter acquisition component according to an embodiment of the present disclosure is shown.

[0032] Figure 6 A schematic diagram of an address preprocessing component according to an embodiment of the present disclosure is shown.

[0033] Figure 7 A schematic diagram of an address acquisition component according to an embodiment of the present disclosure is shown.

[0034] Figure 8 A schematic diagram of a data acquisition component according to an embodiment of the present disclosure is shown.

[0035] Figure 9 A schematic diagram of a driver module according to an embodiment of the present disclosure is shown.

[0036] Figure 10 A flowchart illustrating a data processing method according to an embodiment of the present disclosure is shown.

[0037] Figure 11 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0038] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0039] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0040] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0041] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0042] Figure 1 A schematic diagram of a data processing apparatus according to an embodiment of the present disclosure is shown, such as Figure 1 As shown, the data processing device includes: an instruction acquisition module 1 and a processing module 2, wherein the instruction acquisition module 1 is connected to the processing module 2; the instruction acquisition module 1 caches at least one first instruction; the processing module 2 splits the first instructions with different thread bundle specifications according to the preset value to obtain a splitting result, wherein the splitting result includes one or more second instructions, a first identifier corresponding to the last ranked second instruction among the one or more second instructions, and a second identifier corresponding to each second instruction, wherein the second identifier is used to indicate the ranking of the second instruction in the first instruction.

[0043] In one possible implementation, the data processing device may be located in a processor, which may be a newly designed processor or an improved version of an existing processor chip. The types of processor chips may include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), general-purpose graphics processing units (GPGPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs).

[0044] In this example, assuming the data processing unit is located within the graphics processor (GPU), it can provide loading functionality, loading data stored in the GPU's external video memory (VRAM) into memory locations within the GPU's programmable pipeline via various levels of cache. For instance, the data processing unit can load a segment of data from VRAM into a register. Alternatively, the data processing unit can also provide storage functionality, writing processed data from within the GPU's programmable pipeline to external VRAM via various levels of cache.

[0045] In one possible implementation, the instruction acquisition module 1 and the processing module 2 can be implemented using integrated circuits composed of general analog components, digital circuit components, etc. This disclosure does not limit the specific implementation method.

[0046] In one possible implementation, the instruction acquisition module 1 can cache at least one first instruction according to the order in which it receives the first instruction issued by the upstream module (e.g., the instruction issuing module of the graphics processor), and generate a corresponding instruction number for each first instruction. The instruction number is used to indicate the order in which the instruction acquisition module 1 receives the first instruction, so that when other modules execute the corresponding first instruction, they can extract instruction information from the instruction acquisition module 1 according to the number.

[0047] In one possible implementation, the first instruction can be encapsulated into a data packet according to a preset protocol format, which may include signals of multiple domain segments, such as: a first signal segment Valid, a second signal segment Enable, an identifier signal segment Wave id, a mode signal segment Wave mode, a mask information segment Active mask, and an accompanying information segment Sidebanddata.

[0048] The first signal field segment Valid can have a bit width of 1 bit, which is used to indicate the validity of the first instruction sent by the instruction issuing module of the graphics processor. 1 indicates that the first instruction sent by the instruction issuing module of the graphics processor is valid, and 0 indicates that the first instruction sent by the instruction issuing module of the graphics processor is invalid.

[0049] The bit width of the second signal field segment Enable can be 1 bit, which is used to indicate the validity of the first instruction received by the data processing device. 1 indicates that the first instruction received by the data processing device is valid, and 0 indicates that the first instruction received by the data processing device is invalid.

[0050] The width of the wave id identifier signal field can be 5 bits, used to distinguish the first instruction corresponding to different subtasks.

[0051] The width of the Wave mode signal segment can be 1 bit, used to indicate the number of threads corresponding to the first instruction. For example, Wave mode=0 corresponds to one type of thread count, and Wave mode=1 corresponds to another type of thread count. The embodiments of this disclosure do not limit the specific value of the thread count.

[0052] The active mask field has a bit width of 128 bits and is used to indicate the validity of each of the multiple threads carried by the first instruction.

[0053] The sideband data field can have a bit width of 202 and is used to describe the specific operational details or context of the first instruction, such as immediate values, mode flags, opcodes, address codes, and other additional information.

[0054] It should be understood that the embodiments of this disclosure do not limit the bit width of each field in the first instruction, and can be set according to the actual application scenario.

[0055] In one possible implementation, the instruction acquisition module 1 can send the instruction number of the first instruction received to the processing module 2. In response to receiving the instruction number from the instruction acquisition module 1, the processing module 2 reads the first instruction corresponding to the instruction number from the instruction acquisition module 1, and splits the first instruction corresponding to the instruction number according to a preset value to obtain one or more second instructions, as well as a first identifier corresponding to the last second instruction in the one or more second instructions, and a second identifier corresponding to each second instruction. The second identifier is used to indicate the ranking of the second instruction in the first instruction.

[0056] For example, assuming that the number of threads corresponding to the first instruction A is a preset value, the processing module 2 can split the first instruction A according to the preset value to obtain a second instruction and the first identifier corresponding to the second instruction.

[0057] For example, assuming the number of threads corresponding to the first instruction B is greater than a preset value, such as K times the preset value, the processing module 2 can split the first instruction B according to the preset value to obtain multiple second instructions, namely: second instruction 1 to second instruction K, and the first identifier corresponding to the last second instruction K among the K second instructions, and K second identifiers corresponding to the K second instructions. For example, the second identifier 1 corresponding to second instruction 1 is used to indicate that second instruction 1 is ranked first in first instruction B, the second identifier 2 corresponding to second instruction 2 is used to indicate that second instruction 2 is ranked second in first instruction B, and so on, the second identifier K corresponding to second instruction K is used to indicate that second instruction K is ranked Kth in first instruction B. It should be understood that the specific value of K is not limited in the embodiments of this disclosure.

[0058] By setting a first identifier and a second identifier, first instructions with different thread bundle specifications (e.g., first instructions with various numbers of threads) can be split and processed, ensuring compatibility with multiple thread bundle sizes. Since the number of threads in software code developed on different hardware platforms may vary, this feature offers high tolerance for software code developed on different hardware platforms. Furthermore, it provides software with the ability to explore various thread bundle specifications for performance tuning.

[0059] Figure 2 Another schematic diagram of a data processing apparatus according to an embodiment of the present disclosure is shown, such as Figure 2 As shown, the data processing device further includes a driving module 3, which is connected to the instruction acquisition module 1 and the processing module 2 respectively. The driving module 3 determines the processing result of each second instruction. The driving module 3 performs a packaging operation on the processing results of all second instructions split from the first instruction according to the first identifier and the second identifier to obtain the packaging result of the first instruction, and generates a trigger signal representing the completion of the first instruction.

[0060] The driver module 3 is unaware of the number of threads carried by the first instruction. Based on the splitting result of the front-end processing module 2, the driver module 3 can obtain the split second instruction and its corresponding identification information (such as the first identifier, the second identifier, etc.) each time. The driver module 3 can determine the processing result of each second instruction.

[0061] Since the second identifier is used to indicate the position of the second instruction in the first instruction, the driving module 3 can package the processing results of the second instruction split from the first instruction according to the sorting order indicated by the second identifier. Since the second instruction indicated by the first identifier is at the end of the sorting order, it can be determined whether the first instruction has been executed. If the second instruction has been executed, it means that the first instruction before the splitting of the second instruction has also been executed, indicating that the processing results of all the second instructions have been packaged. Therefore, if any second instruction has the first identifier, after obtaining the processing result of the second instruction and packaging the processing results of all the second instructions, a trigger signal indicating the completion of the first instruction can be generated.

[0062] The data processing apparatus of this disclosure, through a first identifier and a second identifier, packages the processing result of the second instruction, enabling compatibility with first instructions of various thread bundle sizes. For example, it can handle first instructions with a preset number of threads or a number greater than the preset number. Since the number of threads in software code developed on different hardware platforms may vary, it exhibits high versatility for software code developed on different hardware platforms. Furthermore, in terms of performance optimization, it provides software with the ability to explore various thread bundle specifications.

[0063] Figure 3 Another schematic diagram of a data processing apparatus according to an embodiment of the present disclosure is shown below. Figure 3 For example, the data processing apparatus of the present disclosure will be described by way of example.

[0064] In one possible implementation, such as Figure 3 As shown, in addition to the instruction acquisition module 1, processing module 2, and driver module 3, the data processing device may also include an interface module 4. When each module accesses an external register, the interface module 4 can collect the access requests in a unified manner, send the access requests according to the corresponding register interface format, and return the corresponding returned data to each module in order.

[0065] In one possible implementation, Figure 4 A schematic diagram of an instruction acquisition module according to an embodiment of the present disclosure is shown, such as... Figure 4As shown, the instruction acquisition module 1 is further configured to cache the instruction number corresponding to each first instruction. The instruction acquisition module 1 may include a management unit, a first queue, and a second queue. In response to receiving a first instruction, the management unit of the instruction acquisition module 1 is responsible for caching the accompanying information within each first instruction to the first queue, and for numbering each first instruction according to the order in which they were received, generating an instruction number corresponding to each first instruction. The management unit then sends the operation information (e.g., identification signal, mode signal, mask information) and instruction number of the first instruction to the second queue for caching. Thus, when other modules at each level execute a first instruction, they only need to send the corresponding instruction number to the instruction acquisition module 1, and the instruction acquisition module 1 can extract the corresponding operation information (e.g., identification signal, mode signal, mask information) and accompanying information of that first instruction and send them to the modules at each level.

[0066] In the example, the first queue may contain N+1 (e.g., 8) queue units, namely: queue unit 0 to queue unit N. Each queue unit can store the accompanying information of a first instruction. The first queue can store a maximum of N+1 first instructions. When the first queue reaches its maximum space, the data processing device will backpressure the front-end module (e.g., the instruction issuing module of the graphics processor) to stop receiving first instructions. When a first instruction is completed, the first instruction end signal is received from the driver module 3, and the space of the queue unit inside the instruction acquisition module 1 can be released.

[0067] In the example, for any number of threads, the first instruction is cached in the first queue of instruction retrieval module 1, along with its accompanying information. Operational information (such as identifier signals, pattern signals, and mask information) is cached in the second queue by passing it from one submodule to the next.

[0068] In one possible implementation, such as Figure 3 As shown, the processing module 2 includes a parameter acquisition component 21, an address preprocessing component 22, an address acquisition component 23, and a data acquisition component 24.

[0069] like Figure 3As shown, the parameter acquisition component 21 is connected to the instruction acquisition module 1, the interface module 4, and the address preprocessing component 22. In response to receiving the instruction number (e.g., an instruction number from the instruction acquisition module 1), the parameter acquisition component 21 acquires operands from the first instruction corresponding to the instruction number, or generates a first access request to acquire operands from the first instruction corresponding to the instruction number. The operands are included in the accompanying information field of the first instruction. The first instruction may carry one or more operands, which can be values, addresses, variables, registers, constants, etc., used to indicate the source of the operation data executed by the first instruction, or to indicate the operation object in the first instruction. The embodiments of this disclosure do not limit the type and number of operands carried by the first instruction.

[0070] Figure 5 A schematic diagram of a parameter acquisition component according to an embodiment of the present disclosure is shown, such as... Figure 5 As shown, in response to receiving an instruction number from the instruction acquisition module 1, the parameter acquisition component 21 can read the accompanying information of the first instruction corresponding to the instruction number from the instruction acquisition module 1, and determine the operand of the first instruction based on the accompanying information of the first instruction.

[0071] Since the first instruction can carry multiple operands, for example, the first instruction can carry at least one operand from the first operand to the fifth operand, the parameter acquisition component 21 will judge the parameters such as the first operand, the second operand, the third operand, the fourth operand, and the fifth operand respectively. When the operand corresponding to the first instruction is an immediate value, the corresponding operand state changes to the end state, which means that the operand carried by the accompanying information in the first instruction is an immediate value result. Otherwise, in order to access the corresponding register (such as the first register, the second register, and the third register) to obtain the return result, the interface module 4 can send a first access request to the corresponding register to obtain the operand.

[0072] The first and second operands can be used to control the number of loop jumps in the two-dimensional direction of multiple threads in the first instruction. For example, the first operand can control the number of loop jumps in the first dimension (e.g., the row direction), and the second operand can control the number of loop jumps in the second dimension (e.g., the column direction). The third operand can be an offset value used to adjust the offset of each loop jump in the execution of the first instruction. The fourth operand is an operand required for special instructions other than load and store instructions. The fifth operand can be used when performing out-of-bounds checks in subsequent components. It should be understood that the embodiments of this disclosure only use the first to fifth operands as examples, and there is no limitation on the type and number of operands carried by the first instruction.

[0073] Regardless of the number of threads in the current first instruction, the operands carried within the first instruction are valid only within that first instruction. Therefore, the processing logic of the parameter acquisition component 21 is the same for first instructions with various thread counts. The parameter acquisition component 21 can retrieve the operands in the first instruction; it retrieves operands regardless of the number of threads corresponding to the instruction.

[0074] like Figure 3 As shown, the address preprocessing component 22 is connected to the instruction acquisition module 1, the interface module 4, the parameter acquisition component 21, and the address acquisition component 23. In response to receiving the instruction number (e.g., the instruction number from the parameter acquisition component 21), the address preprocessing component 22 splits the first instruction corresponding to the instruction number according to the preset value to obtain the splitting result. The splitting result includes one or more second instructions, a first identifier corresponding to the last second instruction in the one or more second instructions, and a second identifier corresponding to each second instruction. The second identifier is used to indicate the position of the second instruction in the first instruction.

[0075] For example, assuming that the number of threads corresponding to the first instruction A is a preset value, the address preprocessing component 22 can split the first instruction A according to the preset value to obtain a second instruction, as well as a first identifier and a second identifier corresponding to the second instruction.

[0076] For example, if the number of threads corresponding to the first instruction B is greater than a preset value, such as K times the preset value, the address preprocessing component 22 can split the first instruction B according to the preset value to obtain multiple second instructions, namely: second instruction 1 to second instruction K, and the second identifier of each of the K second instructions, and the first identifier corresponding to the last second instruction K in the K second instructions.

[0077] The first identifier indicates that the corresponding second instruction is in the last position, and the second identifier indicates the order in which the corresponding second instruction is placed. It should be understood that the first and second identifiers can be combinations of numbers, letters, and special symbols. The embodiments of this disclosure do not limit the specific form of the first and second identifiers, and they can be set according to specific application scenarios.

[0078] In one possible implementation, the processing module 2 splits the first instruction corresponding to any instruction number according to the preset value to obtain one or more second instructions, and the first identifier corresponding to the last second instruction among the one or more second instructions. This includes: using the address preprocessing component 22 of the processing module 2 to split the first instruction corresponding to any instruction number according to the preset value to obtain one or more second instructions, and the first identifier corresponding to the last second instruction among the one or more second instructions.

[0079] The address preprocessing component 22 is configured to: when the first instruction is a load instruction and the load target is a preset register, determine the size of the data loaded into the preset register by the load instruction based on the operands of the first instruction; perform an out-of-bounds check on the first instruction based on the size of the data loaded into the preset register by the load instruction, and obtain a check result; when the check result indicates that the first instruction passes the out-of-bounds check, split the first instruction corresponding to any instruction number according to the preset value, and obtain the split result.

[0080] The out-of-bounds check checks whether the access operation of the first instruction will exceed the allocated range of the preset register. For example, if the data to be loaded by the first instruction is larger than the storage space of the preset register, the first instruction access will exceed the allocated range; if the data to be loaded by the first instruction is smaller than or equal to the storage space of the preset register, the first instruction access will not exceed the allocated range. It should be understood that the embodiments of this disclosure do not limit the size of the storage space of the preset register, and can be set according to the actual application scenario.

[0081] Figure 6 A schematic diagram of an address preprocessing component according to an embodiment of the present disclosure is shown, such as... Figure 6 As shown, in response to receiving the instruction number from the parameter acquisition component 21, the address preprocessing component 22 can read the accompanying information of the first instruction corresponding to the instruction number from the instruction acquisition module 1, and determine whether the current first instruction is a load instruction based on the accompanying information of the first instruction. If the current first instruction is not a load instruction, it means that the current first instruction is a storage instruction, and the current first instruction can be directly split and processed.

[0082] During the splitting process, the mode signal of the first instruction corresponding to the instruction number can be read from the instruction acquisition module 1. The number of threads of the current first instruction can be determined based on the mode signal. If the number of threads of the first instruction is the same as the preset value, the first instruction is split into a second instruction. Alternatively, if the number of threads of the first instruction is greater than the preset value, and the splitting reaches the last second instruction of the first instruction, a first identifier is set for the second instruction, and the address preprocessing component 22 ends. Otherwise, it will be executed cyclically according to the preset value granularity until the splitting reaches the last second instruction of the first instruction, at which point the address preprocessing component 22 ends.

[0083] Among them, the first instruction with a preset number of threads can be split into a second instruction, which is both the first second instruction and the last second instruction in the sequence.

[0084] If the current first instruction is a load instruction, and the load target is a preset register (e.g., the first register and the second register), then it will check whether the operand has been read back from the corresponding register (e.g., check whether the first operand and the second operand have been read back from the corresponding register). If it has been read back, the size of the loaded data will be calculated. At the same time, it will be determined whether the fifth operand has returned. If it has returned, then it will be checked for out-of-bounds error together with the result of the calculation of the size of the loaded data (e.g., the size of the space occupied by the loaded data).

[0085] If the loaded data of the current first instruction fails the out-of-bounds check, the first instruction is discarded and reported. If the loaded data of the current first instruction passes the out-of-bounds check, the current first instruction can be directly split. The specific splitting process can be found above and will not be repeated here.

[0086] In this way, the address preprocessing component 22 can perform out-of-bounds judgment for scenarios where the loading instruction is loaded and the loading target is a preset register. Regardless of the number of threads of the current first instruction, it will split the instruction according to the granularity of the preset value. When the number of threads of the first instruction is the preset value, the first instruction is split into a second instruction. Or, when the number of threads of the first instruction is greater than the preset value, the first instruction is split into a last second instruction. The address preprocessing component 22 then ends its workflow. In this way, by using the same workflow, it can be compatible with first instructions with the number of threads of the preset value and first instructions with the number of threads greater than the preset value.

[0087] In one possible implementation, the processing module 2 splits first instructions with different thread bundle specifications according to a preset value to obtain a splitting result, including: the address preprocessing component 22, in response to the first instruction having a thread count greater than the preset value, obtains mask information of the first instruction, the mask information being used to indicate the validity of each thread in the first instruction; divides the mask information of the first instruction into multiple sub-segments grouped by a preset value; and splits the mask information of the first instruction according to the bitwise OR result of each group of sub-segments to obtain multiple second instructions, a first identifier corresponding to the last second instruction among the multiple second instructions, and a second identifier corresponding to each second instruction.

[0088] For example, assuming the preset value is 32, and the number of threads is 32 and 128, the mask information Active mask for the first instruction of the 32-thread and 128-thread threads both have 128 bits. Specifically, for the first instruction of the 32-thread thread, the first 32 bits of the 128 bits of the mask information Activemask (i.e., Active mask [31:0]) are valid; for the first instruction of the 128-thread thread, all 128 bits of the mask information Activemask (i.e., Active mask [128:0]) are valid. It should be understood that the embodiments of this disclosure only use 32 and 128 threads as examples, and the specific values ​​of the number of threads and the preset value are not limited.

[0089] The address preprocessing component 22 will split the current first instruction according to the mode signal. When the mode signal indicates that the number of threads of the current first instruction is 32, the mask information Active mask[31:0] of the current first instruction is valid, and the mask information Active mask[127:32] is invalid. The split second instruction can be determined according to the mask information Active mask[31:0]. The address preprocessing component 22 will set a first identifier for the second instruction. For example, the first identifier of the second instruction can be set to 0, indicating that the split second instruction is the last ranked second instruction. The splitting of the first instruction with 32 threads is completed.

[0090] When the mode signal indicates that the number of threads for the current first instruction is 128, the number of threads corresponding to the first instruction, 128, is greater than the preset value of 32. The mask information Active mask[127:0] of the current first instruction is valid. The address preprocessing component 22 divides the mask information Active mask[127:0] of the first instruction into sub-segments of 32 bits each, namely: mask information Active mask[31:0], mask information Active mask[63:32], mask information Active mask[95:64], and mask information Active mask[127:96]. It then performs a bitwise OR operation on each sub-segment to split the mask information of the first instruction and obtain the splitting result.

[0091] For example, when the result of the bitwise OR operation of the mask information Active mask[31:0] signal is 1, the second flag is set to 0, and the first second instruction after splitting is determined according to the mask information Active mask[31:0].

[0092] When the result of the bitwise OR operation of the mask information Active mask[63:32] signal is 1, the second flag is set to 1, and the second second instruction after splitting is determined according to the mask information Active mask[63:32].

[0093] When the result of the bitwise OR operation of the mask information Active mask[95:64] signal is 1, the second identifier is set to 2, and the third second instruction after splitting is determined according to the mask information Active mask[95:64].

[0094] When the result of the bitwise OR operation of the mask information Active mask[127:96] signal is 1, the second flag is set to 3, and the fourth second instruction after splitting is determined according to the mask information Active mask[127:96]. The first flag is set for the second instruction. For example, the first flag of the second instruction can be set to 1, indicating that the fourth second instruction after splitting is the last second instruction. The splitting of the first instruction with 128 threads is completed.

[0095] If the result of the bitwise OR operation of the mask information Active mask[127:96] signal is 0, then when the second identifier is 2, the first identifier signal is set to 1, indicating that the third split second instruction is the last ranked second instruction, and the splitting of the first instruction with 128 threads is completed.

[0096] The second identifier is used to indicate the order of the second instruction. For example, if the second identifier corresponding to the second instruction is set to 0, it means that the second instruction is the first in order; if the second identifier corresponding to the second instruction is set to 1, it means that the second instruction is the second in order; if the second identifier corresponding to the second instruction is set to 2, it means that the second instruction is the third in order; and if the second identifier corresponding to the second instruction is set to 3, it means that the second instruction is the fourth in order.

[0097] By setting a first identifier and a second identifier, various instruction structures can be satisfied, such as a first instruction with a preset number of threads and a first instruction with a number of threads greater than the preset number. This helps to simplify the complexity of hardware design and improve the compatibility of the data processing device.

[0098] like Figure 3 As shown, the address acquisition component 23 is connected to the instruction acquisition module 1, the interface module 4, the address preprocessing component 22, and the data acquisition component 24. In response to receiving an instruction number (e.g., an instruction number from the address preprocessing component 22) and the second identifier, the address acquisition component 23 generates a second access request to obtain address information from a second instruction corresponding to the instruction number and the second identifier. The second identifier indicates the order of the second instruction, and the address information may include a base address and an offset address.

[0099] Figure 7 A schematic diagram of an address acquisition component according to an embodiment of the present disclosure is shown, such as... Figure 7 As shown, in response to receiving an instruction number from the address preprocessing component 22, the address acquisition component 23 can read the accompanying information of the first instruction before splitting corresponding to the instruction number from the instruction acquisition module 1, and determine the address information of the first instruction based on the accompanying information of the first instruction before splitting, such as the base address and offset address. Simultaneously, the address acquisition component 23 can read the mode signal corresponding to the instruction number from the instruction acquisition module 1, thereby determining the number of threads for the first instruction before splitting based on the mode signal.

[0100] Address acquisition component 23 can determine the address information (e.g., base address and offset address) carried in the first instruction before splitting the current second instruction. When the base address comes from the corresponding register (e.g., any one of the first register, second register, and third register), in order to obtain the base address, the second access request of the corresponding register can be sent to interface module 4. When the offset address during execution comes from the corresponding register (e.g., fourth register), address acquisition component 23 will send the second access request to obtain the base address first, and then send the second access request to obtain the offset address.

[0101] For the first instruction with a thread count that is a preset value or greater than the preset value, the first instruction will be split into multiple second instructions, namely segment0 / segment1 / segment2 / segment3, in the address preprocessing component 22 at the front end; when the address acquisition component 23 sends the second access request for the base address and offset address, it will determine whether the base address and offset address need to access the corresponding register.

[0102] If access to the corresponding register is required, the address acquisition component 23 will determine the mode signal of the first instruction before splitting the instruction number. If the mode signal indicates the first instruction with a thread number of a preset value, then based on the base address and offset address carried in the first instruction, a second access request will be directly generated and sent to the interface module 4. Then the interface module 4 will send the corresponding second access request to the corresponding register.

[0103] If the mode signal indicates a first instruction with a thread count greater than a preset value, a second access request will be generated based on the base address and offset address carried in the first instruction before splitting, and the second identifier of the second instruction after splitting. This ensures that the address information returned by the subsequent second access request is determined based on the base address, offset address, and second identifier. For example: the address information of the first second instruction segment0 obtained from splitting the first instruction will have the second identifier 0 added to it; the address information of the second second instruction segment1 obtained from splitting the first instruction will have the second identifier 1 added to it; the address information of the third second instruction segment2 obtained from splitting the first instruction will have the second identifier 2 added to it; and the address information of the fourth second instruction segment3 obtained from splitting the first instruction will have the second identifier 3 added to it.

[0104] To simplify the process, for scenarios where the base address and offset address originate from registers, if the number of threads for the first instruction is the same as the preset value, then sending a second access request is sufficient; if the number of threads for the first instruction is greater than the preset value, the second access request corresponding to the first second instruction segment0 obtained by splitting the first instruction can be used to obtain the address information of the first sorted second instruction. The address information of other sorted second instructions can be determined based on the address information of the first second instruction segment0, i.e., the second identifier corresponding to the other second instructions.

[0105] The address acquisition component 23 can obtain the address information of the first instruction before splitting, thereby determining the address information of each second instruction after splitting.

[0106] The data acquisition component 24 is connected to the instruction acquisition module 1, the interface module 4, the address acquisition component 23, and the driver module 3 respectively. In response to receiving the instruction number (e.g., the instruction number from the address acquisition component 23) and the second identifier, the data acquisition component 24 generates a third access request for acquiring data information in the second instruction corresponding to the instruction number and the second identifier.

[0107] In one possible implementation, the data acquisition component 24, in response to receiving the instruction number and the second identifier from the address acquisition component 23, generates a third access request for acquiring data information in a second instruction corresponding to the instruction number and the second identifier, including: if the first instruction corresponding to the instruction number is a storage instruction, acquiring the operands and mask information corresponding to the second instruction based on the second identifier; and generating a third access request for acquiring data information in a second instruction corresponding to the instruction number and the second identifier based on the operands and mask information corresponding to the second instruction.

[0108] Figure 8 A schematic diagram of a data acquisition component according to an embodiment of the present disclosure is shown, such as... Figure 8 As shown, in response to receiving the instruction number from the address acquisition component 23, the data acquisition component 24 can read the accompanying information of the first instruction before splitting corresponding to the instruction number from the instruction acquisition module 1. Based on the accompanying information of the first instruction before splitting, it can determine whether the first instruction is a storage instruction. If it is not a storage instruction, there is no need to acquire the data information to be stored. The data acquisition component 24 can directly end the process and send the instruction number to the next-level driver module 3.

[0109] If the first instruction matches the stored instruction, a two-dimensional iterative operation will be performed based on the operands corresponding to the second instruction (e.g., the first operand and the second operand), and the mask information fragment read from the instruction acquisition module 1 based on the instruction number and the second identifier. The first operand controls the number of loop jumps in the first dimension (e.g., the row direction), and the second operand controls the number of loop jumps in the second dimension (e.g., the column direction).

[0110] During the iterative operation in the two-dimensional direction, if the data information of a certain thread is in the corresponding register (e.g., the first register, the second register), a third access request to retrieve the data information can be sent to the corresponding register through the interface module 4. When the iterative operation in the two-dimensional direction is completed, the data acquisition component 24 can directly end the process and send the instruction number to the next-level driver module 3.

[0111] In both the first instruction scenario with a thread count of a preset value and the first instruction scenario with a thread count greater than the preset value, the workflow of the data acquisition component 24 can only end after all the second instructions obtained from the splitting of the first instruction are executed according to the splitting result of the pre-processing component 22.

[0112] Using the data acquisition component 24, the amount of data information can be calculated based on the first operand, the second operand, and the mask information, and a third access request for acquiring the data information can be generated, so that the subsequent driver module 3 can write the data information returned by the third access request to an external address.

[0113] In one possible implementation, the interface module 4 collects at least one of the following access requests: the first access request from the parameter acquisition component 21, the second access request from the address acquisition component 23, and the third access request from the data acquisition component 24. The interface module 4 then sends the operand returned by the first access request, the address information returned by the second access request, and the data information returned by the third access request to the driver module 3. The driver module 3 determines the processing result of each second instruction by: determining the processing result of each second instruction based on the operand, the address information, and the data information.

[0114] When modules at all levels need to access external registers, interface module 4 collects access requests in a unified manner, such as the first access request from parameter acquisition component 21, the second access request from address acquisition component 23, and the third access request from data acquisition component 24, and sends the access requests according to the corresponding register interface format, and returns the corresponding return data to modules at all levels in order.

[0115] In one possible implementation, the driver module 3 determines the processing result of each second instruction based on the operands, the address information, and the data information, including: the driver module 3 determines the on-chip address and off-chip address corresponding to each second instruction based on the operands and the address information; when the second instruction is a load instruction, the processing result includes the driver module 3 reading storage data from the off-chip address to the on-chip address; or, when the second instruction is a store instruction, the processing result includes the driver module 3 writing the data information to the off-chip address.

[0116] Figure 9 A schematic diagram of a driver module according to an embodiment of the present disclosure is shown, such as... Figure 9As shown, the driver module 3 can collect the corresponding operands and calculate the corresponding off-chip addresses according to the current second instruction, and perform a two-dimensional iterative operation. The processing results of the second instruction are then packaged and sent to the subsequent module.

[0117] In response to receiving an instruction number from the processing module 2 (e.g., the data acquisition component 24 in the processing module 2), the driving module 3 can read the accompanying information of the first instruction before splitting corresponding to the instruction number from the instruction acquisition module 1, and determine whether the second instruction is a loading instruction or a storage instruction based on the accompanying information. If the second instruction is neither a loading instruction nor a storage instruction, the driving module 3 can end the current process.

[0118] When the second instruction is a load instruction or a store instruction, before starting the two-dimensional loop iteration operation, the driver module 3 will first collect the data information and address information of the current second instruction. After completing the collection action, it will wait for whether the operand corresponding to the current second instruction (e.g., the fifth operand) is ready. When the above operation is completed, the instruction preparation signal will be set, indicating that the preparation work of the current second instruction is completed and the two-dimensional loop iteration operation can begin.

[0119] During the cyclic iteration operation in the two-dimensional direction, the control jump is performed based on the operands corresponding to the second instruction (e.g., the first operand and the second operand), the mask information fragments read from the instruction acquisition module 1 based on the instruction number and the second identifier. The iteration process is similar to that of the data acquisition component 24, and will not be described in detail here.

[0120] During the iterative operation in the two-dimensional direction, the off-chip address and on-chip address corresponding to the second instruction are calculated. The off-chip address is the address of the external video memory of the processor (e.g., the graphics processor), and the on-chip address is the address of the internal memory of the processor (e.g., the graphics processor).

[0121] In the example, the off-chip address = base address + offset address + off-chip jump address. The base address and offset address can be used to determine the starting address of each second instruction accessing the processor's external video memory, that is, the address of the first iteration accessing the processor's external video memory during the two-dimensional loop iteration operation. The off-chip jump address can be used to determine the offset between the address of the current iteration accessing the processor's external video memory and the starting address during the two-dimensional loop iteration operation. The off-chip jump address can be determined based on the number of loop iterations and the operands returned by the first access request (such as the second operand and the third operand). The embodiments of this disclosure do not limit the specific method of determining the off-chip jump address, and can be set according to the actual application scenario.

[0122] The on-chip address = target address + on-chip jump address. The target address (e.g., the address used to indicate the target register in the processor) is determined based on the accompanying information of the first instruction before the split corresponding to the second instruction. It can be used to determine the starting address of the processor's internal memory accessed by each second instruction, that is, the address of the processor's internal memory accessed in the first iteration during the two-dimensional cyclic iteration operation. The on-chip jump address can be used to determine the offset between the address of the processor's internal memory (e.g., a register) accessed in the current iteration and the target address during the two-dimensional cyclic iteration operation. The on-chip jump address can be determined based on the number of cyclic iterations and the operands returned by the first access request (e.g., the first operand and the second operand). The embodiments of this disclosure do not limit the specific method of determining the on-chip jump address and can be set according to the actual application scenario.

[0123] Based on the above calculations, the driver module 3 will process the load instruction and the store instruction differently. For example, for the load instruction, the driver module 3 will concatenate and send the off-chip addresses of 8 parallel threads at once; for the store instruction, the driver module 3 will concatenate the off-chip addresses of 4 parallel threads and the corresponding data information at once, thereby filling the corresponding bit fields.

[0124] Driver module 3 is unaware of the number of threads in the first instruction. Based on the splitting result of the pre-processing unit 22, driver module 3 always sees a sequence of instructions with a preset number of threads (e.g., any split second instruction). However, for the first instruction with a preset number of threads, a trigger signal indicating the completion of the first instruction is generated at the end of each second instruction. This trigger signal instructs the processor's flow control mechanism (fence mechanism) to execute other instructions in the next stage. However, for the first instruction with a number of threads greater than the preset number, the pre-processing unit 22 splits it into multiple second instructions, marking the last second instruction with a first identifier. When driver module 3 encounters a first identifier, it executes the second instruction corresponding to the current first identifier and then generates a trigger signal indicating the completion of the first instruction. This trigger signal instructs the processor's flow control mechanism (fence mechanism) to execute other instructions in the next stage. For other second instructions without a first identifier, no trigger signal is generated.

[0125] The driver module 3 can package the information obtained by the front-end model and send it to the back-end control module for merging processing. It is compatible with the first instruction with multiple thread bundle scales (such as the number of threads being a preset value, the number of threads being greater than a preset value, etc.).

[0126] In summary, in the data processing apparatus of this embodiment, the instruction acquisition module 1 caches at least one first instruction to be processed and the instruction number corresponding to each first instruction, wherein the number of threads corresponding to the first instruction is a preset value or greater than a preset value; the processing module 2 splits the first instruction corresponding to any instruction number according to the preset value to obtain one or more second instructions, and a first identifier corresponding to the last second instruction among the one or more second instructions; the driving module 3 determines the processing result of each second instruction and generates a trigger signal representing the completion of the first instruction according to the first identifier. Thus, the data processing apparatus of this embodiment is compatible with multiple thread bundle sizes, such as first instructions with a preset number of threads and first instructions with a number of threads greater than the preset value, exhibiting high inclusiveness for software code developed on different hardware platforms. Simultaneously, in terms of performance optimization, it also provides software with the ability to explore multiple thread bundle specifications.

[0127] It is understood that the various embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above-described solutions of specific implementation methods, the specific execution order of each module should be determined by its function and possible internal logic.

[0128] In addition, this disclosure also provides data processing methods, electronic devices, computer-readable storage media, programs, corresponding technical solutions and descriptions, and see the corresponding records in the method section, which will not be repeated here.

[0129] Figure 10 A flowchart illustrating a data processing method according to an embodiment of this disclosure is shown, such as... Figure 10 As shown, the method is applied to a data processing device, which includes: an instruction acquisition module and a processing module, wherein the instruction acquisition module is connected to the processing module; the method includes:

[0130] In step S11, the instruction acquisition module caches at least one first instruction;

[0131] In step S12, the processing module splits the first instructions with different thread bundle specifications according to a preset value to obtain a splitting result. The splitting result includes one or more second instructions, a first identifier corresponding to the last ranked second instruction among the one or more second instructions, and a second identifier corresponding to each second instruction. The second identifier is used to indicate the ranking of the second instruction in the first instruction.

[0132] In one possible implementation, the data processing device further includes a driver module, which is connected to the instruction acquisition module and the processing module respectively. The method further includes: the driver module determining the processing result of each second instruction; performing a packaging operation on the processing results of all second instructions split from the first instruction according to the first identifier and the second identifier to obtain the packaging result of the first instruction, and generating a trigger signal representing the completion of the first instruction.

[0133] In one possible implementation, step S12 may include: when the first instruction is a load instruction and the load target is a preset register, determining the size of the data loaded into the preset register by the load instruction based on the operands of the first instruction; performing an out-of-bounds check on the first instruction based on the size of the data loaded into the preset register by the load instruction, and obtaining a check result; when the check result indicates that the first instruction passes the out-of-bounds check, the processing module performs split processing on the first instruction based on the preset value, and obtains the split result.

[0134] In one possible implementation, the instruction acquisition module is further configured to cache the instruction number corresponding to each first instruction. The processing module includes an address preprocessing component and an address acquisition component. Step S12 may include: the address preprocessing component, in response to receiving the instruction number, splits the first instruction corresponding to the instruction number according to the preset value to obtain the splitting result; the address acquisition component, in response to receiving the instruction number and the second identifier, generates a second access request for obtaining address information in the second instruction corresponding to the instruction number and the second identifier.

[0135] In one possible implementation, the processing module further includes a parameter acquisition component and a data acquisition component. Step S12 may include: the parameter acquisition component, in response to receiving the instruction number, acquiring operands from a first instruction corresponding to the instruction number, or generating a first access request for acquiring operands in the first instruction corresponding to the instruction number; the data acquisition component, in response to receiving the instruction number and the second identifier, generating a third access request for acquiring data information in a second instruction corresponding to the instruction number and the second identifier.

[0136] In one possible implementation, the data processing device further includes an interface module, and the method further includes: the interface module collecting at least one of the first access request from the parameter acquisition component, the second access request from the address acquisition component, and the third access request from the data acquisition component, and sending the operand returned by the first access request, the address information returned by the second access request, and the data information returned by the third access request to the driver module; the driver module determining the processing result of each second instruction includes: the driver module determining the processing result of each second instruction based on the operand, the address information, and the data information.

[0137] In one possible implementation, step S12 may include: the address preprocessing component, in response to the number of threads corresponding to the first instruction being greater than the preset value, obtaining mask information of the first instruction, the mask information being used to indicate the validity of each thread in the first instruction; dividing the mask information of the first instruction into multiple sub-segments grouped by a preset number of bits; and performing splitting processing on the mask information of the first instruction according to the bitwise OR result of each group of sub-segments to obtain multiple second instructions, a first identifier corresponding to the last ranked second instruction among the multiple second instructions, and a second identifier corresponding to each second instruction.

[0138] In one possible implementation, the data acquisition component, in response to receiving the instruction number and the second identifier, generates a third access request for acquiring data information in a second instruction corresponding to the instruction number and the second identifier, including: if the first instruction corresponding to the instruction number is a storage instruction, acquiring the operands and mask information corresponding to the second instruction based on the second identifier; and generating a third access request for acquiring data information in the second instruction corresponding to the instruction number and the second identifier based on the operands and mask information corresponding to the second instruction.

[0139] In one possible implementation, the driver module determines the processing result of each second instruction based on the operands, the address information, and the data information, including: the driver module determines the on-chip address and off-chip address corresponding to each second instruction based on the operands and the address information; when the second instruction is a load instruction, the processing result includes the driver module reading storage data from the off-chip address to the on-chip address; or, when the second instruction is a store instruction, the processing result includes the driver module writing the data information to the off-chip address.

[0140] This method is specifically technically related to the internal structure of computer systems and can solve technical problems of how to improve hardware computing efficiency or execution performance (including reducing data storage, reducing data transmission, and increasing hardware processing speed), thereby achieving technical effects that improve the internal performance of computer systems in accordance with natural laws.

[0141] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0142] This disclosure also proposes a processor that includes the data processing apparatus described above.

[0143] This disclosure also proposes a chip that includes the processor described above.

[0144] This disclosure also proposes an electronic device that includes the processor described above.

[0145] Electronic devices can be provided as terminals, servers, or other forms of devices, such as user equipment (UE), mobile devices, user terminals, terminals, cellular phones, cordless phones, personal digital assistants (PDAs), handheld devices, computing devices, in-vehicle devices, wearable devices, etc.

[0146] Figure 11 A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. For example, the electronic device 1900 may be provided as a server or a terminal device. (Refer to...) Figure 11 The electronic device 1900 includes a processing component 1922, which further includes one or more processors (the processors are provided with, for example,...) Figure 1 The data processing apparatus shown, and memory resources represented by memory 1932, are used to store instructions, such as application programs, that can be executed by processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, processing component 1922 is configured to execute instructions to perform the methods described above.

[0147] Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input / output interface 1958. Electronic device 1900 can operate on an operating system stored in memory 1932, such as a Microsoft Server operating system (Windows Server). TM Apple's graphical user interface-based operating system (Mac OS X) TM ), a multi-user, multi-process computer operating system (Unix) TM Linux is a free and open-source Unix-like operating system. TM ), an open-source Unix-like operating system (FreeBSD) TM (or similar.)

[0148] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of an electronic device 1900 to perform the above-described method.

[0149] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0150] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, (but not limited to) electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0151] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0152] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0153] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0154] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0155] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0156] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0157] The computer program product can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0158] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0159] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0160] If the technical solution of this application involves personal information, the product using this technical solution has clearly informed the user of the personal information processing rules and obtained the user's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using this technical solution has obtained the user's separate consent before processing the sensitive personal information, and also meets the requirement of "express consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set up to inform users that they have entered the scope of personal information collection and that personal information will be collected. If an individual voluntarily enters the collection scope, it is deemed that they have agreed to the collection of their personal information; or on the personal information processing device, with clear signs / information informing users of the personal information processing rules, authorization is obtained from the individual through pop-up information or by asking the individual to upload their personal information; wherein, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the types of personal information processed.

[0161] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A data processing apparatus, characterized by, The data processing apparatus comprises an instruction obtaining module and a processing module, the instruction obtaining module is connected to the processing module; The instruction obtaining module caches at least one first instruction; The processing module splits the first instruction with different thread bundle specifications according to a preset value to obtain a splitting result, the splitting result comprises one or more second instructions, a first identifier corresponding to a last-ranked second instruction in the one or more second instructions, and a second identifier corresponding to each second instruction, the first identifier is used to indicate that the second instruction is the last-ranked, the second identifier is used to indicate the rank of the second instruction in the first instruction, the splitting is realized based on mask information of the first instruction, and the mask information is used to indicate the effectiveness of each thread in the first instruction.

2. The data processing apparatus according to claim 1, characterized by The data processing apparatus further comprises a driving module, the driving module is connected to the instruction obtaining module and the processing module, wherein, The driving module determines the processing result of each second instruction; According to the first identifier and the second identifier, the processing results of all second instructions split from the first instruction are packed to obtain a packed result of the first instruction, and a trigger signal representing completion of the first instruction is generated.

3. The data processing apparatus according to claim 1 or 2, characterized by, The processing module splits the first instruction with different thread bundle specifications according to a preset value to obtain a splitting result, comprising: In the case that the first instruction is a load instruction and the load target is a preset register, the size of the data loaded into the preset register by the load instruction is determined according to the operand of the first instruction; According to the size of the data loaded into the preset register by the load instruction, the first instruction is checked for overflow to obtain a checking result; In the case that the checking result indicates that the first instruction passes the overflow check, the processing module splits the first instruction according to the preset value to obtain the splitting result.

4. The data processing apparatus according to claim 1 or 2, characterized by The instruction obtaining module is further used to cache an instruction number corresponding to each first instruction, and the processing module comprises an address preprocessing component and an address obtaining component, wherein, The address preprocessing component splits the first instruction corresponding to the instruction number according to the preset value in response to receiving the instruction number to obtain the splitting result; The address obtaining component generates a second access request for obtaining address information in the second instruction corresponding to the instruction number and the second identifier in response to receiving the instruction number and the second identifier.

5. The data processing apparatus according to claim 4, characterized in that, The processing module further comprises a parameter obtaining component and a data obtaining component, wherein, The parameter obtaining component obtains an operand from the first instruction corresponding to the instruction number in response to receiving the instruction number, or generates a first access request for obtaining the operand in the first instruction corresponding to the instruction number; The data obtaining component generates a third access request for obtaining data information in the second instruction corresponding to the instruction number and the second identifier in response to receiving the instruction number and the second identifier.

6. The data processing apparatus according to claim 5, characterized in that, The data processing apparatus further comprises an interface module, which collects at least one of the first access request from the parameter acquisition component, the second access request from the address acquisition component, and the third access request from the data acquisition component, and sends the operand returned by the first access request, the address information returned by the second access request, and the data information returned by the third access request to a driving module; The driving module determines the processing result of each second instruction, including: The driving module determines the processing result of each second instruction according to the operand, the address information, and the data information.

7. The data processing apparatus according to claim 4, characterized by The processing module splits the first instructions with different thread bundle specifications according to a preset value to obtain a splitting result, including: The address preprocessing component acquires mask information of the first instruction in response to a case where the number of threads corresponding to the first instruction is greater than the preset value; The mask information of the first instruction is divided into a plurality of sub-segments each with a preset number of bits; According to the bit-by-bit OR result of each group of sub-segments, the mask information of the first instruction is split to obtain a plurality of second instructions, a first identifier corresponding to the last row of the second instruction in the plurality of second instructions, and a second identifier corresponding to each second instruction.

8. The data processing apparatus according to claim 5, characterized by The data acquisition component generates a third access request for acquiring data information in the second instruction corresponding to the instruction number and the second identifier in response to receiving the instruction number and the second identifier, including: In a case where the first instruction corresponding to the instruction number is a store instruction, the second identifier is acquired according to the second identifier; According to the operand and the mask information corresponding to the second instruction, a third access request for acquiring data information in the second instruction corresponding to the instruction number and the second identifier is generated.

9. The data processing apparatus according to claim 6, characterized by The driving module determines the processing result of each second instruction according to the operand, the address information, and the data information, including: The driving module determines the in-chip address and the off-chip address corresponding to each second instruction according to the operand and the address information; In a case where the second instruction is a load instruction, the processing result includes that the driving module reads the stored data from the off-chip address to the in-chip address; or In a case where the second instruction is a store instruction, the processing result includes that the driving module writes the data information to the off-chip address.

10. A data processing method, characterized by, The method is applied to a data processing apparatus, and the data processing apparatus comprises an instruction acquisition module and a processing module, the instruction acquisition module is connected to the processing module; The method comprises: The instruction acquisition module caches at least one first instruction; The processing module splits the first instruction with different thread bundle specifications according to a preset value to obtain a splitting result, the splitting result including one or more second instructions, a first identifier corresponding to a last-ranked second instruction in the one or more second instructions, and a second identifier corresponding to each second instruction, the first identifier being used to indicate that the second instruction is the last-ranked, and the second identifier being used to indicate a rank of the second instruction in the first instruction, the splitting being implemented based on mask information of the first instruction, the mask information being used to indicate an effectiveness of each thread in the first instruction.

11. A processor, comprising: The processor includes the data processing apparatus of any one of claims 1 to 9.

12. A chip, characterized by The chip includes the processor of claim 11.

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